Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278446	1		T1	2		T2	2		T3	2
all_values[1]	278446	1		T1	2		T2	2		T3	2
all_values[2]	278446	1		T1	2		T2	2		T3	2
all_values[3]	278446	1		T1	2		T2	2		T3	2
all_values[4]	278446	1		T1	2		T2	2		T3	2
all_values[5]	278446	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	563081	1		T1	12		T2	12		T3	12
auto[1]	1107595	1		T7	12952		T6	8072		T33	14256

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	813149	1		T1	7		T2	7		T3	7
auto[1]	857527	1		T1	5		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	278293	1		T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	153	1		T250	4		T333	5		T334	4
all_values[1]	auto[0]	auto[1]	278284	1		T1	2		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	162	1		T250	8		T333	1		T334	1
all_values[2]	auto[0]	auto[0]	1564	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	60	1		T250	2		T333	1		T334	1
all_values[2]	auto[1]	auto[0]	276766	1		T7	3238		T6	2018		T33	3564
all_values[2]	auto[1]	auto[1]	56	1		T250	1		T333	2		T334	1
all_values[3]	auto[0]	auto[0]	1571	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	56	1		T334	1		T335	2		T336	1
all_values[3]	auto[1]	auto[0]	79066	1		T7	1619		T6	1009		T33	73
all_values[3]	auto[1]	auto[1]	197753	1		T7	1619		T6	1009		T33	3491
all_values[4]	auto[0]	auto[0]	1112	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	515	1		T1	1		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	174785	1		T7	1619		T6	1009		T33	3033
all_values[4]	auto[1]	auto[1]	102034	1		T7	1619		T6	1009		T33	531
all_values[5]	auto[0]	auto[0]	1528	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	98	1		T34	1		T35	1		T36	1
all_values[5]	auto[1]	auto[0]	276757	1		T7	3238		T6	2018		T33	3564
all_values[5]	auto[1]	auto[1]	63	1		T333	2		T334	3		T335	2