Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	235369	1		T1	216		T2	26		T3	45
auto[FlashEraseBank]	265860	1		T2	18		T3	15		T4	8

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	249785	1		T1	11		T2	24		T3	60
auto[FlashOpProgram]	232468	1		T1	192		T2	17		T4	1
auto[FlashOpErase]	14976	1		T1	13		T2	3		T22	4
auto[FlashOpInvalid]	4000	1		T135	200		T260	200		T138	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	249785	1		T1	11		T2	24		T3	60
op[FlashOpProgram]	232468	1		T1	192		T2	17		T4	1
op[FlashOpErase]	14976	1		T1	13		T2	3		T22	4
read_erase_read	562	1		T1	1		T2	2		T22	2
read_prog_read	813	1		T2	7		T4	1		T19	4

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	362307	1		T2	24		T3	60		T4	4
auto[FlashPartInfo]	135193	1		T1	216		T2	13		T4	10
auto[FlashPartInfo1]	795	1		T2	5		T19	1		T6	17
auto[FlashPartInfo2]	2934	1		T2	2		T6	21		T51	5

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	179576	1		T2	12		T3	60		T4	4
auto[FlashPartData]	auto[FlashOpProgram]	175207	1		T2	11		T19	886		T39	1
auto[FlashPartData]	auto[FlashOpErase]	3620	1		T2	1		T22	4		T67	42
auto[FlashPartData]	auto[FlashOpInvalid]	3904	1		T135	198		T260	194		T138	192
auto[FlashPartInfo]	auto[FlashOpRead]	67675	1		T1	11		T2	7		T4	9
auto[FlashPartInfo]	auto[FlashOpProgram]	56111	1		T1	192		T2	6		T4	1
auto[FlashPartInfo]	auto[FlashOpErase]	11325	1		T1	13		T42	216		T116	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	82	1		T135	2		T260	6		T138	6
auto[FlashPartInfo1]	auto[FlashOpRead]	616	1		T2	5		T19	1		T6	17
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T63	32		T60	32		T138	1
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T138	1		T141	1		T430	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	8	1		T138	2		T141	2		T431	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1918	1		T6	21		T51	5		T63	64
auto[FlashPartInfo2]	auto[FlashOpProgram]	984	1		T118	4		T63	64		T103	2
auto[FlashPartInfo2]	auto[FlashOpErase]	26	1		T2	2		T67	1		T44	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T147	2		T432	2		T433	2