Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.86	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	3	29	90.62

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	3	29	90.62	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29304	1		T2	4		T22	32		T42	420
auto[1]	22	1		T37	1		T353	11		T354	1
auto[2]	45	1		T154	4		T354	2		T155	8
auto[3]	269	1		T4	1		T355	1		T197	9

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7413	1		T2	1		T22	8		T42	105
evic_idx[1]	7406	1		T2	1		T4	1		T22	8
evic_idx[2]	7418	1		T2	1		T22	8		T42	105
evic_idx[3]	7403	1		T2	1		T22	8		T42	105

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Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28833	1		T22	8		T42	420		T43	772
evic_op[2]	275	1		T4	1		T22	16		T53	4

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Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	3	29	90.62	3

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1] , evic_idx[2] , evic_idx[3]]	[evic_op[2]]	[auto[1]]	--	--	3

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7137	1		T22	2		T42	105		T43	193
evic_idx[0]	evic_op[1]	auto[1]	6	1		T353	3		T356	1		T357	2
evic_idx[0]	evic_op[1]	auto[2]	6	1		T354	1		T357	1		T358	4
evic_idx[0]	evic_op[1]	auto[3]	62	1		T197	1		T359	1		T360	3
evic_idx[0]	evic_op[2]	auto[0]	58	1		T22	4		T53	1		T206	1
evic_idx[0]	evic_op[2]	auto[1]	1	1		T37	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	1	1		T361	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	9	1		T362	1		T363	1		T364	1
evic_idx[1]	evic_op[1]	auto[0]	7137	1		T22	2		T42	105		T43	193
evic_idx[1]	evic_op[1]	auto[1]	6	1		T353	3		T354	1		T357	2
evic_idx[1]	evic_op[1]	auto[2]	6	1		T365	1		T366	1		T357	1
evic_idx[1]	evic_op[1]	auto[3]	57	1		T197	2		T359	1		T360	4
evic_idx[1]	evic_op[2]	auto[0]	56	1		T22	4		T53	1		T206	1
evic_idx[1]	evic_op[2]	auto[2]	3	1		T367	1		T368	1		T361	1
evic_idx[1]	evic_op[2]	auto[3]	8	1		T4	1		T355	1		T369	1
evic_idx[2]	evic_op[1]	auto[0]	7140	1		T22	2		T42	105		T43	193
evic_idx[2]	evic_op[1]	auto[1]	6	1		T353	3		T356	1		T357	2
evic_idx[2]	evic_op[1]	auto[2]	5	1		T354	1		T357	1		T358	3
evic_idx[2]	evic_op[1]	auto[3]	66	1		T197	3		T359	3		T360	5
evic_idx[2]	evic_op[2]	auto[0]	58	1		T22	4		T53	1		T206	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T367	1		T370	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	8	1		T371	1		T372	1		T373	1
evic_idx[3]	evic_op[1]	auto[0]	7137	1		T22	2		T42	105		T43	193
evic_idx[3]	evic_op[1]	auto[1]	3	1		T353	2		T357	1		-	-
evic_idx[3]	evic_op[1]	auto[2]	4	1		T357	1		T358	3		-	-
evic_idx[3]	evic_op[1]	auto[3]	55	1		T197	3		T359	3		T360	3
evic_idx[3]	evic_op[2]	auto[0]	61	1		T22	4		T53	1		T206	1
evic_idx[3]	evic_op[2]	auto[2]	6	1		T374	2		T367	2		T375	2
evic_idx[3]	evic_op[2]	auto[3]	4	1		T376	1		T377	1		T378	1