Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	11187	1		T342	8609		T343	2578		-	-
rd_lvl[2]	13257	1		T33	1364		T342	4722		T343	2195
rd_lvl[3]	15866	1		T33	573		T344	4375		T343	1153
rd_lvl[4]	42247	1		T33	113		T153	5049		T345	2871
rd_lvl[5]	15820	1		T33	380		T153	1543		T218	1076
rd_lvl[6]	19790	1		T33	366		T218	174		T295	128
rd_lvl[7]	10576	1		T131	1890		T295	18		T261	391
rd_lvl[8]	20760	1		T131	1468		T218	20		T295	1
rd_lvl[9]	7082	1		T6	381		T295	1		T264	282
rd_lvl[10]	4137	1		T6	608		T33	1		T266	9
rd_lvl[11]	5114	1		T33	1		T218	20		T346	157
rd_lvl[12]	3766	1		T6	20		T33	108		T347	166
rd_lvl[13]	3128	1		T33	108		T347	188		T348	227
rd_lvl[14]	6215	1		T7	1398		T31	257		T349	55
rd_lvl[15]	2246	1		T7	221		T31	154		T32	579