Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	278446	1		T1	2		T2	2		T3	2
all_pins[1]	278446	1		T1	2		T2	2		T3	2
all_pins[2]	278446	1		T1	2		T2	2		T3	2
all_pins[3]	278446	1		T1	2		T2	2		T3	2
all_pins[4]	278446	1		T1	2		T2	2		T3	2
all_pins[5]	278446	1		T1	2		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1373968	1		T1	12		T2	12		T3	12
values[0x1]	296708	1		T7	3238		T6	2018		T33	3569
transitions[0x0=>0x1]	263525	1		T7	3238		T6	2018		T33	3137
transitions[0x1=>0x0]	263508	1		T7	3238		T6	2018		T33	3137

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	278293	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	153	1		T250	4		T333	5		T334	4
all_pins[0]	transitions[0x0=>0x1]	76	1		T333	4		T334	3		T335	2
all_pins[0]	transitions[0x1=>0x0]	85	1		T250	4		T335	5		T336	1
all_pins[1]	values[0x0]	278284	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	162	1		T250	8		T333	1		T334	1
all_pins[1]	transitions[0x0=>0x1]	132	1		T250	7		T334	1		T335	4
all_pins[1]	transitions[0x1=>0x0]	2586	1		T31	156		T32	970		T298	1140
all_pins[2]	values[0x0]	275830	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	2616	1		T31	156		T32	970		T298	1140
all_pins[2]	transitions[0x0=>0x1]	43	1		T333	2		T334	1		T335	1
all_pins[2]	transitions[0x1=>0x0]	181369	1		T7	1619		T6	1009		T33	3014
all_pins[3]	values[0x0]	94504	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	183942	1		T7	1619		T6	1009		T33	3014
all_pins[3]	transitions[0x0=>0x1]	153486	1		T7	1619		T6	1009		T33	2582
all_pins[3]	transitions[0x1=>0x0]	79316	1		T7	1619		T6	1009		T33	123
all_pins[4]	values[0x0]	168674	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	109772	1		T7	1619		T6	1009		T33	555
all_pins[4]	transitions[0x0=>0x1]	109759	1		T7	1619		T6	1009		T33	555
all_pins[4]	transitions[0x1=>0x0]	50	1		T333	2		T334	3		T335	2
all_pins[5]	values[0x0]	278383	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	63	1		T333	2		T334	3		T335	2
all_pins[5]	transitions[0x0=>0x1]	29	1		T334	1		T335	1		T341	1
all_pins[5]	transitions[0x1=>0x0]	102	1		T250	3		T333	2		T334	1