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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.15 95.70 93.98 98.31 91.84 98.25 96.89 98.09


Total test records in report: 1246
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T375 /workspace/coverage/default/20.flash_ctrl_rw_evict.811546503 Aug 18 06:07:55 PM PDT 24 Aug 18 06:08:28 PM PDT 24 44228600 ps
T1077 /workspace/coverage/default/2.flash_ctrl_rw_serr.3154370955 Aug 18 06:04:11 PM PDT 24 Aug 18 06:07:42 PM PDT 24 1388218800 ps
T1078 /workspace/coverage/default/23.flash_ctrl_smoke.2240189083 Aug 18 06:08:10 PM PDT 24 Aug 18 06:11:03 PM PDT 24 31877900 ps
T1079 /workspace/coverage/default/6.flash_ctrl_otp_reset.3772572291 Aug 18 06:05:03 PM PDT 24 Aug 18 06:07:14 PM PDT 24 38943100 ps
T1080 /workspace/coverage/default/38.flash_ctrl_otp_reset.672766687 Aug 18 06:09:02 PM PDT 24 Aug 18 06:11:13 PM PDT 24 154575500 ps
T1081 /workspace/coverage/default/9.flash_ctrl_ro_derr.3073827399 Aug 18 06:06:08 PM PDT 24 Aug 18 06:08:47 PM PDT 24 1875119100 ps
T1082 /workspace/coverage/default/2.flash_ctrl_rw_derr.2843245619 Aug 18 06:04:08 PM PDT 24 Aug 18 06:07:57 PM PDT 24 1569225900 ps
T1083 /workspace/coverage/default/2.flash_ctrl_oversize_error.2153767905 Aug 18 06:04:07 PM PDT 24 Aug 18 06:07:05 PM PDT 24 4542400300 ps
T1084 /workspace/coverage/default/7.flash_ctrl_fetch_code.1094548367 Aug 18 06:05:12 PM PDT 24 Aug 18 06:05:47 PM PDT 24 8008570800 ps
T1085 /workspace/coverage/default/43.flash_ctrl_smoke.3253815209 Aug 18 06:09:20 PM PDT 24 Aug 18 06:12:12 PM PDT 24 73208000 ps
T1086 /workspace/coverage/default/15.flash_ctrl_wo.919486551 Aug 18 06:07:29 PM PDT 24 Aug 18 06:11:45 PM PDT 24 11366370500 ps
T1087 /workspace/coverage/default/3.flash_ctrl_sw_op.4288303765 Aug 18 06:04:13 PM PDT 24 Aug 18 06:04:40 PM PDT 24 22018300 ps
T1088 /workspace/coverage/default/30.flash_ctrl_otp_reset.1839540816 Aug 18 06:08:33 PM PDT 24 Aug 18 06:10:46 PM PDT 24 141234900 ps
T1089 /workspace/coverage/default/12.flash_ctrl_ro.1999462053 Aug 18 06:06:50 PM PDT 24 Aug 18 06:08:40 PM PDT 24 6236796000 ps
T1090 /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.955082794 Aug 18 06:04:25 PM PDT 24 Aug 18 06:04:48 PM PDT 24 18497400 ps
T1091 /workspace/coverage/default/18.flash_ctrl_wo.1028288587 Aug 18 06:07:55 PM PDT 24 Aug 18 06:10:58 PM PDT 24 2990149700 ps
T1092 /workspace/coverage/default/2.flash_ctrl_fs_sup.3752628159 Aug 18 06:04:14 PM PDT 24 Aug 18 06:04:50 PM PDT 24 846929000 ps
T1093 /workspace/coverage/default/16.flash_ctrl_phy_arb.3305166575 Aug 18 06:07:28 PM PDT 24 Aug 18 06:10:01 PM PDT 24 81499100 ps
T1094 /workspace/coverage/default/1.flash_ctrl_phy_arb.3073177311 Aug 18 06:03:42 PM PDT 24 Aug 18 06:12:21 PM PDT 24 773288700 ps
T191 /workspace/coverage/default/2.flash_ctrl_rd_intg.1269137925 Aug 18 06:04:13 PM PDT 24 Aug 18 06:04:43 PM PDT 24 110773600 ps
T1095 /workspace/coverage/default/0.flash_ctrl_host_addr_infection.1589561978 Aug 18 06:03:34 PM PDT 24 Aug 18 06:04:02 PM PDT 24 40167400 ps
T1096 /workspace/coverage/default/2.flash_ctrl_host_addr_infection.2813488375 Aug 18 06:04:19 PM PDT 24 Aug 18 06:04:50 PM PDT 24 27582500 ps
T421 /workspace/coverage/default/1.flash_ctrl_sec_info_access.2014913172 Aug 18 06:03:49 PM PDT 24 Aug 18 06:05:03 PM PDT 24 1525587700 ps
T1097 /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2256712587 Aug 18 06:04:50 PM PDT 24 Aug 18 06:05:52 PM PDT 24 10018401900 ps
T1098 /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.1431028804 Aug 18 06:03:58 PM PDT 24 Aug 18 06:05:40 PM PDT 24 55563900 ps
T1099 /workspace/coverage/default/0.flash_ctrl_serr_address.785928534 Aug 18 06:03:29 PM PDT 24 Aug 18 06:05:05 PM PDT 24 3341252300 ps
T1100 /workspace/coverage/default/52.flash_ctrl_connect.3046650782 Aug 18 06:09:45 PM PDT 24 Aug 18 06:10:01 PM PDT 24 17246900 ps
T1101 /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.224642542 Aug 18 06:06:20 PM PDT 24 Aug 18 06:07:26 PM PDT 24 1690020500 ps
T1102 /workspace/coverage/default/50.flash_ctrl_otp_reset.147858243 Aug 18 06:09:46 PM PDT 24 Aug 18 06:11:58 PM PDT 24 79047000 ps
T1103 /workspace/coverage/default/18.flash_ctrl_mp_regions.2641905455 Aug 18 06:07:49 PM PDT 24 Aug 18 06:09:59 PM PDT 24 5867611700 ps
T1104 /workspace/coverage/default/4.flash_ctrl_rand_ops.4159770139 Aug 18 06:04:35 PM PDT 24 Aug 18 06:27:59 PM PDT 24 171037000 ps
T64 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1971637259 Aug 18 06:40:11 PM PDT 24 Aug 18 06:40:28 PM PDT 24 34031600 ps
T65 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.112023857 Aug 18 06:40:04 PM PDT 24 Aug 18 06:40:23 PM PDT 24 88002000 ps
T250 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3936404456 Aug 18 06:40:16 PM PDT 24 Aug 18 06:40:30 PM PDT 24 141271400 ps
T66 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.4048086802 Aug 18 06:39:56 PM PDT 24 Aug 18 06:40:35 PM PDT 24 124736600 ps
T234 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2505175189 Aug 18 06:40:21 PM PDT 24 Aug 18 06:40:37 PM PDT 24 205294000 ps
T1105 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2895141110 Aug 18 06:39:52 PM PDT 24 Aug 18 06:40:08 PM PDT 24 11504300 ps
T104 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.302529052 Aug 18 06:40:04 PM PDT 24 Aug 18 06:40:22 PM PDT 24 102086200 ps
T1106 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.47684464 Aug 18 06:40:31 PM PDT 24 Aug 18 06:40:44 PM PDT 24 14032700 ps
T108 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2550080634 Aug 18 06:40:05 PM PDT 24 Aug 18 06:40:39 PM PDT 24 1083363000 ps
T105 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1182195027 Aug 18 06:40:05 PM PDT 24 Aug 18 06:40:23 PM PDT 24 61257700 ps
T106 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1079579505 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:31 PM PDT 24 85085800 ps
T1107 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2689501391 Aug 18 06:40:11 PM PDT 24 Aug 18 06:40:24 PM PDT 24 46208400 ps
T246 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1727845244 Aug 18 06:40:11 PM PDT 24 Aug 18 06:40:42 PM PDT 24 21303900 ps
T107 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1308659027 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:24 PM PDT 24 54668800 ps
T333 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.233016215 Aug 18 06:40:45 PM PDT 24 Aug 18 06:41:00 PM PDT 24 17072900 ps
T203 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2843795202 Aug 18 06:40:24 PM PDT 24 Aug 18 06:40:45 PM PDT 24 70912200 ps
T204 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3272179919 Aug 18 06:40:05 PM PDT 24 Aug 18 06:53:36 PM PDT 24 349280400 ps
T1108 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3032897369 Aug 18 06:40:04 PM PDT 24 Aug 18 06:40:20 PM PDT 24 37080900 ps
T235 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.366092584 Aug 18 06:39:58 PM PDT 24 Aug 18 06:40:16 PM PDT 24 297674500 ps
T334 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3194981435 Aug 18 06:40:18 PM PDT 24 Aug 18 06:40:32 PM PDT 24 34577300 ps
T335 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3188676491 Aug 18 06:40:12 PM PDT 24 Aug 18 06:40:26 PM PDT 24 29920100 ps
T247 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3161611818 Aug 18 06:39:57 PM PDT 24 Aug 18 06:40:28 PM PDT 24 63775100 ps
T236 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2225366818 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:30 PM PDT 24 2483720500 ps
T205 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1342368742 Aug 18 06:40:12 PM PDT 24 Aug 18 06:46:46 PM PDT 24 349971200 ps
T336 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4161777408 Aug 18 06:40:14 PM PDT 24 Aug 18 06:40:27 PM PDT 24 15457100 ps
T337 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.513981793 Aug 18 06:40:07 PM PDT 24 Aug 18 06:40:20 PM PDT 24 30882900 ps
T237 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3109162700 Aug 18 06:40:10 PM PDT 24 Aug 18 06:40:32 PM PDT 24 832596400 ps
T223 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1451106407 Aug 18 06:40:03 PM PDT 24 Aug 18 06:40:19 PM PDT 24 44079100 ps
T238 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.296945934 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:24 PM PDT 24 47245800 ps
T341 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1870980452 Aug 18 06:40:35 PM PDT 24 Aug 18 06:40:48 PM PDT 24 26118700 ps
T224 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1154543184 Aug 18 06:40:11 PM PDT 24 Aug 18 06:40:27 PM PDT 24 159498700 ps
T282 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.671437732 Aug 18 06:40:15 PM PDT 24 Aug 18 06:40:32 PM PDT 24 194407100 ps
T225 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.4232572173 Aug 18 06:40:30 PM PDT 24 Aug 18 06:40:49 PM PDT 24 293812400 ps
T239 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2192083508 Aug 18 06:39:58 PM PDT 24 Aug 18 06:40:16 PM PDT 24 26201800 ps
T240 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1153089536 Aug 18 06:40:18 PM PDT 24 Aug 18 06:40:33 PM PDT 24 72104500 ps
T1109 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2372606720 Aug 18 06:40:14 PM PDT 24 Aug 18 06:40:28 PM PDT 24 28644300 ps
T1110 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1449505315 Aug 18 06:40:02 PM PDT 24 Aug 18 06:40:18 PM PDT 24 99944800 ps
T338 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.4283146583 Aug 18 06:40:32 PM PDT 24 Aug 18 06:40:46 PM PDT 24 52453100 ps
T226 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.4112484441 Aug 18 06:40:10 PM PDT 24 Aug 18 06:40:30 PM PDT 24 241682500 ps
T227 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.977258793 Aug 18 06:40:10 PM PDT 24 Aug 18 06:40:28 PM PDT 24 110830500 ps
T389 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2671858557 Aug 18 06:40:01 PM PDT 24 Aug 18 06:41:19 PM PDT 24 2294909800 ps
T1111 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.85358372 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:25 PM PDT 24 14742900 ps
T1112 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1920724435 Aug 18 06:40:21 PM PDT 24 Aug 18 06:40:35 PM PDT 24 25579100 ps
T1113 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.293455687 Aug 18 06:40:12 PM PDT 24 Aug 18 06:40:26 PM PDT 24 15040100 ps
T1114 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2052208987 Aug 18 06:40:22 PM PDT 24 Aug 18 06:40:36 PM PDT 24 53486200 ps
T230 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.933953733 Aug 18 06:39:58 PM PDT 24 Aug 18 06:40:12 PM PDT 24 18875000 ps
T1115 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2502670927 Aug 18 06:40:06 PM PDT 24 Aug 18 06:40:22 PM PDT 24 44888100 ps
T1116 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3942533078 Aug 18 06:39:57 PM PDT 24 Aug 18 06:40:10 PM PDT 24 49492100 ps
T283 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.172682922 Aug 18 06:40:18 PM PDT 24 Aug 18 06:40:32 PM PDT 24 40205500 ps
T1117 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4129863188 Aug 18 06:40:14 PM PDT 24 Aug 18 06:40:27 PM PDT 24 58421400 ps
T1118 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2534564606 Aug 18 06:40:11 PM PDT 24 Aug 18 06:40:25 PM PDT 24 15055800 ps
T243 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1389770250 Aug 18 06:40:17 PM PDT 24 Aug 18 06:48:11 PM PDT 24 426447200 ps
T330 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3060464972 Aug 18 06:40:11 PM PDT 24 Aug 18 06:40:30 PM PDT 24 59710300 ps
T1119 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2361124571 Aug 18 06:40:02 PM PDT 24 Aug 18 06:40:38 PM PDT 24 1179926700 ps
T1120 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2826759005 Aug 18 06:40:31 PM PDT 24 Aug 18 06:40:44 PM PDT 24 27064900 ps
T339 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1765299806 Aug 18 06:40:27 PM PDT 24 Aug 18 06:40:41 PM PDT 24 66512400 ps
T1121 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1303701806 Aug 18 06:40:12 PM PDT 24 Aug 18 06:40:30 PM PDT 24 51625600 ps
T1122 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3869352217 Aug 18 06:39:54 PM PDT 24 Aug 18 06:40:30 PM PDT 24 684504000 ps
T257 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1943020262 Aug 18 06:40:09 PM PDT 24 Aug 18 06:56:06 PM PDT 24 663973500 ps
T278 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1974128150 Aug 18 06:40:05 PM PDT 24 Aug 18 06:40:27 PM PDT 24 882741600 ps
T1123 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1051626982 Aug 18 06:39:58 PM PDT 24 Aug 18 06:40:45 PM PDT 24 416599300 ps
T248 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1866776815 Aug 18 06:40:04 PM PDT 24 Aug 18 06:40:23 PM PDT 24 160312400 ps
T1124 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1381766711 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:30 PM PDT 24 121445700 ps
T1125 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3458745855 Aug 18 06:40:12 PM PDT 24 Aug 18 06:40:29 PM PDT 24 39788500 ps
T1126 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1039763776 Aug 18 06:40:08 PM PDT 24 Aug 18 06:40:23 PM PDT 24 13364200 ps
T1127 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.220080961 Aug 18 06:39:59 PM PDT 24 Aug 18 06:40:13 PM PDT 24 16403100 ps
T1128 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.483470064 Aug 18 06:40:10 PM PDT 24 Aug 18 06:40:23 PM PDT 24 15966100 ps
T1129 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1760727144 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:26 PM PDT 24 16797400 ps
T1130 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3250377463 Aug 18 06:40:04 PM PDT 24 Aug 18 06:40:21 PM PDT 24 17779700 ps
T1131 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2241478089 Aug 18 06:40:01 PM PDT 24 Aug 18 06:40:18 PM PDT 24 33547900 ps
T1132 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3259133901 Aug 18 06:40:15 PM PDT 24 Aug 18 06:40:29 PM PDT 24 31886100 ps
T1133 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2330050875 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:25 PM PDT 24 15447900 ps
T1134 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3227695821 Aug 18 06:40:04 PM PDT 24 Aug 18 06:41:08 PM PDT 24 2633039700 ps
T340 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.901701160 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:26 PM PDT 24 96277200 ps
T279 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.726817633 Aug 18 06:40:08 PM PDT 24 Aug 18 06:40:22 PM PDT 24 192676900 ps
T1135 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.758944283 Aug 18 06:40:04 PM PDT 24 Aug 18 06:40:19 PM PDT 24 31378300 ps
T1136 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.707528507 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:22 PM PDT 24 25023800 ps
T1137 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3504641865 Aug 18 06:40:11 PM PDT 24 Aug 18 06:40:24 PM PDT 24 31760200 ps
T1138 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1817090401 Aug 18 06:39:55 PM PDT 24 Aug 18 06:40:11 PM PDT 24 26059500 ps
T1139 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.824956517 Aug 18 06:39:57 PM PDT 24 Aug 18 06:40:16 PM PDT 24 89036000 ps
T280 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1189481881 Aug 18 06:40:01 PM PDT 24 Aug 18 06:56:17 PM PDT 24 7088353000 ps
T249 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3427006399 Aug 18 06:40:14 PM PDT 24 Aug 18 06:40:32 PM PDT 24 166180600 ps
T281 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4018757150 Aug 18 06:40:12 PM PDT 24 Aug 18 06:53:58 PM PDT 24 2299648100 ps
T231 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.4272436520 Aug 18 06:40:06 PM PDT 24 Aug 18 06:40:20 PM PDT 24 32293400 ps
T1140 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.281134557 Aug 18 06:40:17 PM PDT 24 Aug 18 06:40:30 PM PDT 24 49400100 ps
T1141 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.680181545 Aug 18 06:39:57 PM PDT 24 Aug 18 06:40:13 PM PDT 24 61064100 ps
T1142 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.173909256 Aug 18 06:40:07 PM PDT 24 Aug 18 06:40:22 PM PDT 24 22658200 ps
T1143 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1437442548 Aug 18 06:40:04 PM PDT 24 Aug 18 06:40:20 PM PDT 24 15386700 ps
T1144 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2750019193 Aug 18 06:40:12 PM PDT 24 Aug 18 06:40:26 PM PDT 24 53105500 ps
T384 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3288206382 Aug 18 06:40:09 PM PDT 24 Aug 18 06:56:35 PM PDT 24 3557102300 ps
T284 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3942914999 Aug 18 06:40:02 PM PDT 24 Aug 18 06:48:01 PM PDT 24 1725240000 ps
T1145 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3591742264 Aug 18 06:40:01 PM PDT 24 Aug 18 06:40:17 PM PDT 24 11351500 ps
T1146 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3841217304 Aug 18 06:40:25 PM PDT 24 Aug 18 06:40:45 PM PDT 24 164773200 ps
T1147 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3992267815 Aug 18 06:40:00 PM PDT 24 Aug 18 06:40:14 PM PDT 24 23411900 ps
T1148 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.907224648 Aug 18 06:40:12 PM PDT 24 Aug 18 06:40:29 PM PDT 24 76236700 ps
T256 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3284177674 Aug 18 06:40:22 PM PDT 24 Aug 18 06:40:38 PM PDT 24 40212300 ps
T1149 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1351061072 Aug 18 06:40:06 PM PDT 24 Aug 18 06:40:22 PM PDT 24 360628600 ps
T254 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1982886942 Aug 18 06:40:14 PM PDT 24 Aug 18 06:40:35 PM PDT 24 221817700 ps
T251 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3841470321 Aug 18 06:39:57 PM PDT 24 Aug 18 06:40:14 PM PDT 24 209429700 ps
T379 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3772307685 Aug 18 06:40:02 PM PDT 24 Aug 18 06:40:21 PM PDT 24 71216400 ps
T1150 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.93703924 Aug 18 06:40:30 PM PDT 24 Aug 18 06:40:47 PM PDT 24 63930200 ps
T232 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1838972950 Aug 18 06:40:05 PM PDT 24 Aug 18 06:40:19 PM PDT 24 60441200 ps
T1151 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3559613061 Aug 18 06:40:18 PM PDT 24 Aug 18 06:40:32 PM PDT 24 18216100 ps
T1152 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1474138896 Aug 18 06:40:01 PM PDT 24 Aug 18 06:40:15 PM PDT 24 28768200 ps
T1153 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3646933703 Aug 18 06:40:32 PM PDT 24 Aug 18 06:40:46 PM PDT 24 49294900 ps
T1154 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.984147801 Aug 18 06:40:04 PM PDT 24 Aug 18 06:40:20 PM PDT 24 35793100 ps
T1155 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2279884056 Aug 18 06:40:20 PM PDT 24 Aug 18 06:40:34 PM PDT 24 50282600 ps
T1156 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4028037216 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:31 PM PDT 24 30144900 ps
T1157 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2297408295 Aug 18 06:39:54 PM PDT 24 Aug 18 06:40:10 PM PDT 24 68763600 ps
T381 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1694920217 Aug 18 06:40:08 PM PDT 24 Aug 18 06:48:06 PM PDT 24 832017400 ps
T1158 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2277274599 Aug 18 06:40:11 PM PDT 24 Aug 18 06:40:24 PM PDT 24 50641000 ps
T383 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2485737908 Aug 18 06:40:19 PM PDT 24 Aug 18 06:48:18 PM PDT 24 298152600 ps
T285 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.55114686 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:31 PM PDT 24 418485800 ps
T286 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.408594729 Aug 18 06:40:03 PM PDT 24 Aug 18 06:40:41 PM PDT 24 101904300 ps
T1159 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.316822179 Aug 18 06:39:57 PM PDT 24 Aug 18 06:40:11 PM PDT 24 15937200 ps
T382 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3098085865 Aug 18 06:40:14 PM PDT 24 Aug 18 06:53:33 PM PDT 24 650586800 ps
T1160 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1599501167 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:43 PM PDT 24 121022700 ps
T1161 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1616485782 Aug 18 06:40:16 PM PDT 24 Aug 18 06:40:29 PM PDT 24 24995300 ps
T1162 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.405263847 Aug 18 06:40:02 PM PDT 24 Aug 18 06:40:17 PM PDT 24 49788300 ps
T1163 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.690347913 Aug 18 06:40:10 PM PDT 24 Aug 18 06:40:24 PM PDT 24 15364000 ps
T1164 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3055064865 Aug 18 06:40:06 PM PDT 24 Aug 18 06:40:21 PM PDT 24 414459200 ps
T1165 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2406024655 Aug 18 06:40:02 PM PDT 24 Aug 18 06:40:21 PM PDT 24 350708200 ps
T1166 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.4272919940 Aug 18 06:40:21 PM PDT 24 Aug 18 06:40:34 PM PDT 24 24511300 ps
T255 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3658691397 Aug 18 06:40:14 PM PDT 24 Aug 18 06:40:32 PM PDT 24 79624600 ps
T1167 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2732354070 Aug 18 06:40:25 PM PDT 24 Aug 18 06:40:39 PM PDT 24 21375300 ps
T1168 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.614823109 Aug 18 06:40:23 PM PDT 24 Aug 18 06:40:36 PM PDT 24 22930400 ps
T1169 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1714863304 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:25 PM PDT 24 44287300 ps
T253 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2271009199 Aug 18 06:40:11 PM PDT 24 Aug 18 06:40:31 PM PDT 24 230514900 ps
T1170 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4126300082 Aug 18 06:40:02 PM PDT 24 Aug 18 06:40:22 PM PDT 24 299734800 ps
T1171 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.193074794 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:28 PM PDT 24 77981300 ps
T1172 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3120978185 Aug 18 06:40:18 PM PDT 24 Aug 18 06:40:37 PM PDT 24 345957900 ps
T1173 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.38632738 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:26 PM PDT 24 67667400 ps
T1174 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2684930929 Aug 18 06:40:08 PM PDT 24 Aug 18 06:40:25 PM PDT 24 96069100 ps
T1175 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1186768717 Aug 18 06:40:00 PM PDT 24 Aug 18 06:40:18 PM PDT 24 94712300 ps
T1176 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.540052674 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:35 PM PDT 24 61533800 ps
T1177 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.827636248 Aug 18 06:40:26 PM PDT 24 Aug 18 06:40:40 PM PDT 24 25552900 ps
T1178 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2353104683 Aug 18 06:40:05 PM PDT 24 Aug 18 06:40:18 PM PDT 24 44927100 ps
T1179 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.139920953 Aug 18 06:40:11 PM PDT 24 Aug 18 06:40:25 PM PDT 24 37437600 ps
T1180 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4086402468 Aug 18 06:40:03 PM PDT 24 Aug 18 06:40:17 PM PDT 24 16752000 ps
T258 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2443136947 Aug 18 06:40:02 PM PDT 24 Aug 18 06:46:36 PM PDT 24 805919200 ps
T1181 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2369077123 Aug 18 06:40:09 PM PDT 24 Aug 18 06:48:01 PM PDT 24 675621400 ps
T1182 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2463603781 Aug 18 06:40:12 PM PDT 24 Aug 18 06:40:26 PM PDT 24 71508600 ps
T1183 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.782984960 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:29 PM PDT 24 33545000 ps
T1184 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3935905533 Aug 18 06:39:57 PM PDT 24 Aug 18 06:40:11 PM PDT 24 28537600 ps
T1185 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3933737126 Aug 18 06:40:15 PM PDT 24 Aug 18 06:40:33 PM PDT 24 146928500 ps
T1186 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4227975943 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:26 PM PDT 24 67018700 ps
T287 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3768963098 Aug 18 06:40:10 PM PDT 24 Aug 18 06:40:29 PM PDT 24 195006800 ps
T1187 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3870465459 Aug 18 06:40:08 PM PDT 24 Aug 18 06:40:25 PM PDT 24 85603700 ps
T1188 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1177854384 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:28 PM PDT 24 344354600 ps
T1189 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.111333891 Aug 18 06:40:03 PM PDT 24 Aug 18 06:40:19 PM PDT 24 13318700 ps
T1190 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.143069885 Aug 18 06:40:32 PM PDT 24 Aug 18 06:40:46 PM PDT 24 33618800 ps
T288 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1560446221 Aug 18 06:40:17 PM PDT 24 Aug 18 06:40:35 PM PDT 24 531700300 ps
T1191 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1840701970 Aug 18 06:40:10 PM PDT 24 Aug 18 06:40:28 PM PDT 24 211935100 ps
T1192 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.491064220 Aug 18 06:39:59 PM PDT 24 Aug 18 06:40:15 PM PDT 24 47107100 ps
T1193 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.264033509 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:51 PM PDT 24 1276729100 ps
T380 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.772781943 Aug 18 06:40:05 PM PDT 24 Aug 18 06:40:25 PM PDT 24 213762700 ps
T1194 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1597519305 Aug 18 06:40:11 PM PDT 24 Aug 18 06:40:30 PM PDT 24 939358600 ps
T1195 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1192438223 Aug 18 06:40:05 PM PDT 24 Aug 18 06:40:47 PM PDT 24 3421445400 ps
T1196 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.399549337 Aug 18 06:40:10 PM PDT 24 Aug 18 06:40:30 PM PDT 24 130456700 ps
T1197 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2069318089 Aug 18 06:40:00 PM PDT 24 Aug 18 06:41:00 PM PDT 24 1250502400 ps
T1198 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1619226434 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:26 PM PDT 24 30677300 ps
T1199 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.4034233793 Aug 18 06:40:15 PM PDT 24 Aug 18 06:40:29 PM PDT 24 17456300 ps
T1200 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.968893294 Aug 18 06:40:11 PM PDT 24 Aug 18 06:40:28 PM PDT 24 92888400 ps
T1201 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.492389770 Aug 18 06:40:35 PM PDT 24 Aug 18 06:40:48 PM PDT 24 34858200 ps
T1202 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.936046049 Aug 18 06:40:03 PM PDT 24 Aug 18 06:41:06 PM PDT 24 962598200 ps
T1203 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3340808707 Aug 18 06:40:08 PM PDT 24 Aug 18 06:40:26 PM PDT 24 137501500 ps
T1204 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.566585475 Aug 18 06:40:14 PM PDT 24 Aug 18 06:40:34 PM PDT 24 122952600 ps
T1205 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2655824281 Aug 18 06:40:03 PM PDT 24 Aug 18 06:40:16 PM PDT 24 20376100 ps
T1206 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1514600369 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:26 PM PDT 24 29381600 ps
T386 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2014692414 Aug 18 06:40:01 PM PDT 24 Aug 18 06:53:42 PM PDT 24 374890400 ps
T1207 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1912243592 Aug 18 06:40:19 PM PDT 24 Aug 18 06:40:39 PM PDT 24 382858300 ps
T385 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.959783485 Aug 18 06:40:02 PM PDT 24 Aug 18 06:48:01 PM PDT 24 1613478700 ps
T1208 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1063763533 Aug 18 06:39:58 PM PDT 24 Aug 18 06:40:36 PM PDT 24 2352564000 ps
T1209 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4241577102 Aug 18 06:40:14 PM PDT 24 Aug 18 06:48:09 PM PDT 24 369378600 ps
T1210 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3921572908 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:28 PM PDT 24 465742300 ps
T1211 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1001844619 Aug 18 06:40:10 PM PDT 24 Aug 18 06:40:24 PM PDT 24 23149700 ps
T1212 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.111166037 Aug 18 06:40:12 PM PDT 24 Aug 18 06:40:30 PM PDT 24 189085900 ps
T1213 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3425034721 Aug 18 06:40:15 PM PDT 24 Aug 18 06:40:34 PM PDT 24 125567100 ps
T1214 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1921980833 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:30 PM PDT 24 38909400 ps
T1215 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.4181102692 Aug 18 06:40:01 PM PDT 24 Aug 18 06:40:14 PM PDT 24 16233700 ps
T1216 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.34490780 Aug 18 06:40:03 PM PDT 24 Aug 18 06:40:19 PM PDT 24 99996100 ps
T1217 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3353813678 Aug 18 06:40:15 PM PDT 24 Aug 18 06:40:34 PM PDT 24 46000000 ps
T259 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.882266867 Aug 18 06:40:00 PM PDT 24 Aug 18 06:53:43 PM PDT 24 741375300 ps
T1218 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.680039009 Aug 18 06:39:53 PM PDT 24 Aug 18 06:40:09 PM PDT 24 30829100 ps
T1219 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1121277013 Aug 18 06:40:12 PM PDT 24 Aug 18 06:40:25 PM PDT 24 40029600 ps
T1220 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3866035837 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:27 PM PDT 24 16567200 ps
T233 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2319473439 Aug 18 06:40:12 PM PDT 24 Aug 18 06:40:25 PM PDT 24 183499400 ps
T1221 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1030848437 Aug 18 06:40:02 PM PDT 24 Aug 18 06:40:23 PM PDT 24 476215800 ps
T1222 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2573848982 Aug 18 06:40:04 PM PDT 24 Aug 18 06:40:23 PM PDT 24 149113000 ps
T1223 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.435410805 Aug 18 06:40:03 PM PDT 24 Aug 18 06:40:17 PM PDT 24 32342500 ps
T1224 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3133112179 Aug 18 06:40:16 PM PDT 24 Aug 18 06:40:30 PM PDT 24 23053600 ps
T1225 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3973887128 Aug 18 06:40:37 PM PDT 24 Aug 18 06:40:50 PM PDT 24 27610100 ps
T1226 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2691920963 Aug 18 06:40:01 PM PDT 24 Aug 18 06:40:18 PM PDT 24 17766800 ps
T1227 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.665508849 Aug 18 06:40:05 PM PDT 24 Aug 18 06:40:20 PM PDT 24 12195800 ps
T1228 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.328974691 Aug 18 06:40:06 PM PDT 24 Aug 18 06:40:20 PM PDT 24 55987200 ps
T1229 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.599985156 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:41 PM PDT 24 648189100 ps
T1230 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2549435912 Aug 18 06:40:32 PM PDT 24 Aug 18 06:40:45 PM PDT 24 217708700 ps
T387 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3515839530 Aug 18 06:40:08 PM PDT 24 Aug 18 06:56:05 PM PDT 24 3197017300 ps
T1231 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3890644617 Aug 18 06:40:02 PM PDT 24 Aug 18 06:40:20 PM PDT 24 1153587600 ps
T1232 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3759715362 Aug 18 06:39:59 PM PDT 24 Aug 18 06:40:16 PM PDT 24 71720200 ps
T1233 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1182289036 Aug 18 06:40:05 PM PDT 24 Aug 18 06:40:25 PM PDT 24 67909500 ps
T1234 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1795018475 Aug 18 06:40:09 PM PDT 24 Aug 18 06:40:24 PM PDT 24 107765900 ps
T1235 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.66279909 Aug 18 06:40:08 PM PDT 24 Aug 18 06:40:25 PM PDT 24 275114600 ps
T1236 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1983381893 Aug 18 06:40:14 PM PDT 24 Aug 18 06:48:10 PM PDT 24 1603489700 ps
T1237 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2754671859 Aug 18 06:40:04 PM PDT 24 Aug 18 06:40:18 PM PDT 24 30130900 ps
T1238 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1434957160 Aug 18 06:40:25 PM PDT 24 Aug 18 06:40:41 PM PDT 24 12989700 ps
T1239 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.285893142 Aug 18 06:40:07 PM PDT 24 Aug 18 06:41:10 PM PDT 24 3594591100 ps
T252 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2577199805 Aug 18 06:40:09 PM PDT 24 Aug 18 06:48:05 PM PDT 24 795776900 ps
T1240 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.245952332 Aug 18 06:40:11 PM PDT 24 Aug 18 06:40:26 PM PDT 24 67692700 ps
T1241 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2251228354 Aug 18 06:40:02 PM PDT 24 Aug 18 06:40:16 PM PDT 24 16603500 ps
T1242 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.927070527 Aug 18 06:40:14 PM PDT 24 Aug 18 06:40:30 PM PDT 24 41402600 ps
T1243 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3675084842 Aug 18 06:40:27 PM PDT 24 Aug 18 06:40:41 PM PDT 24 52901800 ps
T1244 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3723700794 Aug 18 06:40:02 PM PDT 24 Aug 18 06:40:19 PM PDT 24 168776500 ps
T1245 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1919042661 Aug 18 06:40:08 PM PDT 24 Aug 18 06:40:21 PM PDT 24 25433800 ps
T1246 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1948248173 Aug 18 06:40:13 PM PDT 24 Aug 18 06:40:29 PM PDT 24 12504100 ps

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.3456361815
Short name T19
Test name
Test status
Simulation time 2412562200 ps
CPU time 268.27 seconds
Started Aug 18 06:06:06 PM PDT 24
Finished Aug 18 06:10:34 PM PDT 24
Peak memory 285780 kb
Host smart-170b8195-735f-444a-90f6-ec0cca1c403a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456361815 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_derr.3456361815
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.1393125430
Short name T57
Test name
Test status
Simulation time 80139447500 ps
CPU time 849.54 seconds
Started Aug 18 06:07:17 PM PDT 24
Finished Aug 18 06:21:27 PM PDT 24
Peak memory 261392 kb
Host smart-b2ae1183-0eb6-4323-84d5-109e85c44d21
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393125430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.1393125430
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3272179919
Short name T204
Test name
Test status
Simulation time 349280400 ps
CPU time 810.38 seconds
Started Aug 18 06:40:05 PM PDT 24
Finished Aug 18 06:53:36 PM PDT 24
Peak memory 272368 kb
Host smart-0e52739a-82f7-4248-b4bd-8a61b1f209e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272179919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.3272179919
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.216429544
Short name T119
Test name
Test status
Simulation time 9051612900 ps
CPU time 217.12 seconds
Started Aug 18 06:06:30 PM PDT 24
Finished Aug 18 06:10:07 PM PDT 24
Peak memory 265736 kb
Host smart-bebd9cea-a54a-4fa8-9587-63285b577f2d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216429544 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.216429544
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.1457164528
Short name T13
Test name
Test status
Simulation time 40507800 ps
CPU time 109.88 seconds
Started Aug 18 06:09:29 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 261676 kb
Host smart-4ba7a7d1-5ac9-4e19-bd67-646c438d10ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457164528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.1457164528
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.2353675324
Short name T15
Test name
Test status
Simulation time 5368273800 ps
CPU time 5011.82 seconds
Started Aug 18 06:04:40 PM PDT 24
Finished Aug 18 07:28:12 PM PDT 24
Peak memory 290548 kb
Host smart-477c4df5-b56d-4c04-b3e8-3f2eab4dc8f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353675324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.2353675324
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1182195027
Short name T105
Test name
Test status
Simulation time 61257700 ps
CPU time 17.45 seconds
Started Aug 18 06:40:05 PM PDT 24
Finished Aug 18 06:40:23 PM PDT 24
Peak memory 272448 kb
Host smart-ddde8d30-028d-46b6-9474-9c480f04bee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182195027 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1182195027
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3886328131
Short name T7
Test name
Test status
Simulation time 23047076500 ps
CPU time 276.47 seconds
Started Aug 18 06:06:05 PM PDT 24
Finished Aug 18 06:10:42 PM PDT 24
Peak memory 291428 kb
Host smart-797890d1-f8a0-445e-a160-9d7817aa571d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886328131 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.3886328131
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.1084066054
Short name T89
Test name
Test status
Simulation time 3805570900 ps
CPU time 69.41 seconds
Started Aug 18 06:04:39 PM PDT 24
Finished Aug 18 06:05:48 PM PDT 24
Peak memory 260944 kb
Host smart-e6fa1981-2d48-482f-beb2-1d1568ceb121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084066054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.1084066054
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.2750293231
Short name T12
Test name
Test status
Simulation time 39718000 ps
CPU time 131.54 seconds
Started Aug 18 06:08:02 PM PDT 24
Finished Aug 18 06:10:13 PM PDT 24
Peak memory 264932 kb
Host smart-bc1ea87d-d675-46e0-b64b-6acdd3f0d4d6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750293231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.2750293231
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.920847069
Short name T67
Test name
Test status
Simulation time 10482863100 ps
CPU time 2570.33 seconds
Started Aug 18 06:04:49 PM PDT 24
Finished Aug 18 06:47:40 PM PDT 24
Peak memory 263400 kb
Host smart-bafec10c-5d52-4ccf-8705-4b7da319109b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=920847069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.920847069
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.1896125690
Short name T155
Test name
Test status
Simulation time 7856480300 ps
CPU time 434.53 seconds
Started Aug 18 06:04:22 PM PDT 24
Finished Aug 18 06:11:37 PM PDT 24
Peak memory 263924 kb
Host smart-9bb9416c-007d-4cf0-a955-41246f25bcd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1896125690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.1896125690
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.3997156776
Short name T6
Test name
Test status
Simulation time 4615303400 ps
CPU time 190.09 seconds
Started Aug 18 06:06:05 PM PDT 24
Finished Aug 18 06:09:16 PM PDT 24
Peak memory 293964 kb
Host smart-4f4f758b-3123-48b7-8cff-d1c85eaabcee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997156776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.3997156776
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.1832659106
Short name T14
Test name
Test status
Simulation time 15189100 ps
CPU time 14.01 seconds
Started Aug 18 06:04:15 PM PDT 24
Finished Aug 18 06:04:29 PM PDT 24
Peak memory 266140 kb
Host smart-45ce78cc-b973-4340-86b3-c9b509dc5a98
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832659106 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.1832659106
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3188676491
Short name T335
Test name
Test status
Simulation time 29920100 ps
CPU time 13.46 seconds
Started Aug 18 06:40:12 PM PDT 24
Finished Aug 18 06:40:26 PM PDT 24
Peak memory 261504 kb
Host smart-e10be3cc-c09f-422a-8c8f-67ec459df294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188676491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
3188676491
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.3134186180
Short name T174
Test name
Test status
Simulation time 177566900 ps
CPU time 113.37 seconds
Started Aug 18 06:08:08 PM PDT 24
Finished Aug 18 06:10:01 PM PDT 24
Peak memory 264692 kb
Host smart-6a1abaaa-6022-4192-bf6e-e0914c9e095c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134186180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.3134186180
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.766735359
Short name T70
Test name
Test status
Simulation time 75479700 ps
CPU time 131.41 seconds
Started Aug 18 06:08:25 PM PDT 24
Finished Aug 18 06:10:36 PM PDT 24
Peak memory 265000 kb
Host smart-579318a0-bb4c-40be-997f-ce26ded2eb58
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766735359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ot
p_reset.766735359
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.581742516
Short name T90
Test name
Test status
Simulation time 3641993100 ps
CPU time 73.15 seconds
Started Aug 18 06:04:23 PM PDT 24
Finished Aug 18 06:05:36 PM PDT 24
Peak memory 261160 kb
Host smart-6c984cfa-e456-4200-a389-70aafb48646e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581742516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.581742516
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.1042050490
Short name T75
Test name
Test status
Simulation time 163836367100 ps
CPU time 923.75 seconds
Started Aug 18 06:03:50 PM PDT 24
Finished Aug 18 06:19:13 PM PDT 24
Peak memory 261972 kb
Host smart-5fd1ecca-8bcc-467b-a609-00b809d454c2
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042050490 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.1042050490
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.914287187
Short name T522
Test name
Test status
Simulation time 10032919900 ps
CPU time 66.71 seconds
Started Aug 18 06:07:36 PM PDT 24
Finished Aug 18 06:08:43 PM PDT 24
Peak memory 294024 kb
Host smart-0337562c-87fb-4935-8d62-324672bf3145
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914287187 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.914287187
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1866776815
Short name T248
Test name
Test status
Simulation time 160312400 ps
CPU time 19.69 seconds
Started Aug 18 06:40:04 PM PDT 24
Finished Aug 18 06:40:23 PM PDT 24
Peak memory 264272 kb
Host smart-96504012-6bcb-4b16-b55c-9fb3bd850c65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866776815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.1
866776815
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.2767370243
Short name T8
Test name
Test status
Simulation time 81023300 ps
CPU time 15.43 seconds
Started Aug 18 06:04:16 PM PDT 24
Finished Aug 18 06:04:32 PM PDT 24
Peak memory 265496 kb
Host smart-0770d635-a2b0-4263-89a9-41dbfe7b331a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767370243 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.2767370243
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.415714644
Short name T207
Test name
Test status
Simulation time 2135633000 ps
CPU time 73.5 seconds
Started Aug 18 06:03:37 PM PDT 24
Finished Aug 18 06:04:50 PM PDT 24
Peak memory 264304 kb
Host smart-48b2537b-384c-464c-bbe7-853429edc57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415714644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.415714644
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.2554090117
Short name T178
Test name
Test status
Simulation time 331656526000 ps
CPU time 2560.72 seconds
Started Aug 18 06:04:22 PM PDT 24
Finished Aug 18 06:47:03 PM PDT 24
Peak memory 264576 kb
Host smart-bcc726be-59d4-4d0a-b3ad-ed1be4fec6d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554090117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.2554090117
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.1868102565
Short name T3
Test name
Test status
Simulation time 155452400 ps
CPU time 26.12 seconds
Started Aug 18 06:05:32 PM PDT 24
Finished Aug 18 06:05:58 PM PDT 24
Peak memory 264224 kb
Host smart-977a3eb5-a535-4eb2-8ac9-bae23efcf14c
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868102565 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_fetch_code.1868102565
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.610539949
Short name T123
Test name
Test status
Simulation time 158127097100 ps
CPU time 518.95 seconds
Started Aug 18 06:05:58 PM PDT 24
Finished Aug 18 06:14:37 PM PDT 24
Peak memory 275224 kb
Host smart-a58a2645-76b7-41b7-b964-da94ef335018
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610539949 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.610539949
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.811247270
Short name T91
Test name
Test status
Simulation time 9125730100 ps
CPU time 74.53 seconds
Started Aug 18 06:04:09 PM PDT 24
Finished Aug 18 06:05:24 PM PDT 24
Peak memory 261100 kb
Host smart-c844f4a8-fe6f-42cf-a3b7-27e42589fb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811247270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.811247270
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.3996186232
Short name T192
Test name
Test status
Simulation time 1909913500 ps
CPU time 181.07 seconds
Started Aug 18 06:05:06 PM PDT 24
Finished Aug 18 06:08:07 PM PDT 24
Peak memory 282324 kb
Host smart-1512e453-98eb-4a5d-9dbc-97ecf827949e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996186232 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.flash_ctrl_rw_serr.3996186232
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.2787160626
Short name T306
Test name
Test status
Simulation time 259182800 ps
CPU time 13.74 seconds
Started Aug 18 06:08:16 PM PDT 24
Finished Aug 18 06:08:30 PM PDT 24
Peak memory 258848 kb
Host smart-e8fc51a3-4938-4961-bfa0-cc3afa20e6b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787160626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
2787160626
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.1706898442
Short name T316
Test name
Test status
Simulation time 1931681700 ps
CPU time 160.04 seconds
Started Aug 18 06:06:29 PM PDT 24
Finished Aug 18 06:09:09 PM PDT 24
Peak memory 261452 kb
Host smart-c46ebf57-5491-4aaf-9fdf-b9e6bbd7a153
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706898442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.1706898442
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.1649625802
Short name T129
Test name
Test status
Simulation time 6305926900 ps
CPU time 99.51 seconds
Started Aug 18 06:05:34 PM PDT 24
Finished Aug 18 06:07:13 PM PDT 24
Peak memory 260632 kb
Host smart-beec0669-f06f-4195-a5ec-10f0439da9ce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649625802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.1649625802
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.1072611626
Short name T197
Test name
Test status
Simulation time 77537800 ps
CPU time 35.1 seconds
Started Aug 18 06:04:44 PM PDT 24
Finished Aug 18 06:05:19 PM PDT 24
Peak memory 276556 kb
Host smart-6345c7c3-2338-4c8e-9b41-e333370015e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072611626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.1072611626
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.1344612971
Short name T83
Test name
Test status
Simulation time 3461582700 ps
CPU time 2271.84 seconds
Started Aug 18 06:03:33 PM PDT 24
Finished Aug 18 06:41:25 PM PDT 24
Peak memory 265584 kb
Host smart-f5f191d1-f052-4b34-8c03-fa7995cf8d6b
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344612971 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.1344612971
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.3162365882
Short name T138
Test name
Test status
Simulation time 6496488700 ps
CPU time 68.92 seconds
Started Aug 18 06:04:07 PM PDT 24
Finished Aug 18 06:05:16 PM PDT 24
Peak memory 261020 kb
Host smart-467db388-3fcd-4888-849a-e5a3b97b172c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162365882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3162365882
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.2276456739
Short name T167
Test name
Test status
Simulation time 14860300 ps
CPU time 13.68 seconds
Started Aug 18 06:07:24 PM PDT 24
Finished Aug 18 06:07:38 PM PDT 24
Peak memory 265752 kb
Host smart-4a277e19-e9ce-46e8-a0a4-62f30fd61ba7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276456739 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.2276456739
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.4272436520
Short name T231
Test name
Test status
Simulation time 32293400 ps
CPU time 13.86 seconds
Started Aug 18 06:40:06 PM PDT 24
Finished Aug 18 06:40:20 PM PDT 24
Peak memory 263016 kb
Host smart-36504e6d-ce6c-419b-af97-10e5d75901d7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272436520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.4272436520
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.4270514581
Short name T343
Test name
Test status
Simulation time 6792693500 ps
CPU time 262.01 seconds
Started Aug 18 06:06:44 PM PDT 24
Finished Aug 18 06:11:06 PM PDT 24
Peak memory 285476 kb
Host smart-a01a033c-601b-4b2c-8ca7-c0fdda3a5dff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270514581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.4270514581
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.3906590662
Short name T357
Test name
Test status
Simulation time 222508300 ps
CPU time 32.26 seconds
Started Aug 18 06:06:58 PM PDT 24
Finished Aug 18 06:07:30 PM PDT 24
Peak memory 276560 kb
Host smart-beafd964-f14b-4176-8642-e5ae7396f38c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906590662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.3906590662
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.3262012992
Short name T293
Test name
Test status
Simulation time 24917200 ps
CPU time 13.3 seconds
Started Aug 18 06:03:38 PM PDT 24
Finished Aug 18 06:03:52 PM PDT 24
Peak memory 260684 kb
Host smart-8b02d6e7-a05f-45db-9d41-9e34e301c3dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262012992 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.3262012992
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4161777408
Short name T336
Test name
Test status
Simulation time 15457100 ps
CPU time 13.52 seconds
Started Aug 18 06:40:14 PM PDT 24
Finished Aug 18 06:40:27 PM PDT 24
Peak memory 261440 kb
Host smart-0c6992c0-c326-42c6-804f-1a241d236dc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161777408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
4161777408
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1943020262
Short name T257
Test name
Test status
Simulation time 663973500 ps
CPU time 956.12 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:56:06 PM PDT 24
Peak memory 264176 kb
Host smart-8034fb91-79a1-4978-89d4-1f567b7d14bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943020262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.1943020262
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3109162700
Short name T237
Test name
Test status
Simulation time 832596400 ps
CPU time 21.53 seconds
Started Aug 18 06:40:10 PM PDT 24
Finished Aug 18 06:40:32 PM PDT 24
Peak memory 262616 kb
Host smart-96affa70-5731-45ed-ba6b-2cb81552cb3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109162700 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.3109162700
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.4112484441
Short name T226
Test name
Test status
Simulation time 241682500 ps
CPU time 20.01 seconds
Started Aug 18 06:40:10 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 264296 kb
Host smart-6e164d88-7ccd-4910-a359-b506517fd9b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112484441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
4112484441
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4018757150
Short name T281
Test name
Test status
Simulation time 2299648100 ps
CPU time 825.09 seconds
Started Aug 18 06:40:12 PM PDT 24
Finished Aug 18 06:53:58 PM PDT 24
Peak memory 264144 kb
Host smart-85cef857-ef8e-4c67-9734-21541868f93e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018757150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.4018757150
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.2352368777
Short name T50
Test name
Test status
Simulation time 939504600 ps
CPU time 17.64 seconds
Started Aug 18 06:04:16 PM PDT 24
Finished Aug 18 06:04:34 PM PDT 24
Peak memory 266100 kb
Host smart-9d7fdefe-07d2-49f9-bffa-610551e3192a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352368777 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.2352368777
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.916650838
Short name T58
Test name
Test status
Simulation time 240215334500 ps
CPU time 837.89 seconds
Started Aug 18 06:07:28 PM PDT 24
Finished Aug 18 06:21:26 PM PDT 24
Peak memory 265160 kb
Host smart-d4f34439-a059-43d3-9359-a9c19797a4f4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916650838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.flash_ctrl_hw_rma_reset.916650838
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.1000897557
Short name T117
Test name
Test status
Simulation time 1285206100 ps
CPU time 4707.12 seconds
Started Aug 18 06:03:51 PM PDT 24
Finished Aug 18 07:22:19 PM PDT 24
Peak memory 286144 kb
Host smart-d029b71b-7f03-47c2-814d-6b419077d5c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000897557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.1000897557
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.1612005340
Short name T367
Test name
Test status
Simulation time 360310800 ps
CPU time 31.87 seconds
Started Aug 18 06:08:00 PM PDT 24
Finished Aug 18 06:08:32 PM PDT 24
Peak memory 274200 kb
Host smart-55065a11-5a45-4a49-839a-a19bdb9b26fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612005340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.1612005340
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.3047600570
Short name T206
Test name
Test status
Simulation time 1162775100 ps
CPU time 64.06 seconds
Started Aug 18 06:04:15 PM PDT 24
Finished Aug 18 06:05:20 PM PDT 24
Peak memory 264260 kb
Host smart-50c2769e-2c3e-446b-87c3-48af992123b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047600570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.3047600570
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.368832777
Short name T434
Test name
Test status
Simulation time 23530198000 ps
CPU time 271.83 seconds
Started Aug 18 06:08:40 PM PDT 24
Finished Aug 18 06:13:12 PM PDT 24
Peak memory 292740 kb
Host smart-641f5acd-9421-428d-9fb9-10980edcfa1f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368832777 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.368832777
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.2167544217
Short name T47
Test name
Test status
Simulation time 387060500 ps
CPU time 25.04 seconds
Started Aug 18 06:03:42 PM PDT 24
Finished Aug 18 06:04:07 PM PDT 24
Peak memory 262976 kb
Host smart-e4070079-3487-4851-b30b-f694ed857867
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167544217 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_fetch_code.2167544217
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.792265149
Short name T56
Test name
Test status
Simulation time 42358000 ps
CPU time 14.19 seconds
Started Aug 18 06:03:49 PM PDT 24
Finished Aug 18 06:04:03 PM PDT 24
Peak memory 277636 kb
Host smart-1d6dfdd5-fd95-472a-bfbb-c9d50f2d7563
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=792265149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.792265149
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.3852573923
Short name T950
Test name
Test status
Simulation time 26298600 ps
CPU time 13.42 seconds
Started Aug 18 06:07:34 PM PDT 24
Finished Aug 18 06:07:48 PM PDT 24
Peak memory 261620 kb
Host smart-5b8e7f3c-a1e4-49d3-ae30-18c2febcd190
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852573923 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.3852573923
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.2968760346
Short name T393
Test name
Test status
Simulation time 10600100 ps
CPU time 22.29 seconds
Started Aug 18 06:09:08 PM PDT 24
Finished Aug 18 06:09:31 PM PDT 24
Peak memory 267012 kb
Host smart-dae8727f-52c4-4eab-a5f0-1a05985ee079
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968760346 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.2968760346
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.3310155739
Short name T428
Test name
Test status
Simulation time 2867443100 ps
CPU time 236.53 seconds
Started Aug 18 06:08:08 PM PDT 24
Finished Aug 18 06:12:05 PM PDT 24
Peak memory 285684 kb
Host smart-b66c615b-067b-4ce6-aa77-c074bc6412c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310155739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.3310155739
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.545434751
Short name T294
Test name
Test status
Simulation time 1520613800 ps
CPU time 58.33 seconds
Started Aug 18 06:08:48 PM PDT 24
Finished Aug 18 06:09:47 PM PDT 24
Peak memory 263276 kb
Host smart-6abf1e32-d077-4d2d-a985-98fdb03baae7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545434751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_h
w_sec_otp.545434751
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.2892685214
Short name T113
Test name
Test status
Simulation time 42975000 ps
CPU time 15.81 seconds
Started Aug 18 06:07:34 PM PDT 24
Finished Aug 18 06:07:50 PM PDT 24
Peak memory 283576 kb
Host smart-41311748-98e7-42b2-a2c2-c418133a2d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892685214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.2892685214
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.3747640185
Short name T195
Test name
Test status
Simulation time 25232700 ps
CPU time 13.88 seconds
Started Aug 18 06:04:35 PM PDT 24
Finished Aug 18 06:04:49 PM PDT 24
Peak memory 265576 kb
Host smart-c05ef1d6-96b0-450b-9b42-774fd1133db9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747640185 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3747640185
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.1735354617
Short name T147
Test name
Test status
Simulation time 1014158400 ps
CPU time 88.71 seconds
Started Aug 18 06:07:36 PM PDT 24
Finished Aug 18 06:09:04 PM PDT 24
Peak memory 261220 kb
Host smart-2b5e2486-5d1b-4ec5-b2f4-5aa879ff3feb
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735354617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.1
735354617
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.2126078659
Short name T691
Test name
Test status
Simulation time 873222000 ps
CPU time 145.31 seconds
Started Aug 18 06:03:28 PM PDT 24
Finished Aug 18 06:05:53 PM PDT 24
Peak memory 282404 kb
Host smart-06a05de7-7d31-4398-bd56-5a17c94fc894
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126078659 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.2126078659
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.1269137925
Short name T191
Test name
Test status
Simulation time 110773600 ps
CPU time 29.6 seconds
Started Aug 18 06:04:13 PM PDT 24
Finished Aug 18 06:04:43 PM PDT 24
Peak memory 276192 kb
Host smart-b8b5ec5a-62e2-4e41-83cc-9ace1cf45e08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269137925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.1269137925
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.912405379
Short name T272
Test name
Test status
Simulation time 10034117100 ps
CPU time 51.85 seconds
Started Aug 18 06:07:26 PM PDT 24
Finished Aug 18 06:08:17 PM PDT 24
Peak memory 271572 kb
Host smart-fe0e03b0-6982-4554-8c72-860125e27684
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912405379 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.912405379
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.279752776
Short name T23
Test name
Test status
Simulation time 17952800 ps
CPU time 13.89 seconds
Started Aug 18 06:03:37 PM PDT 24
Finished Aug 18 06:03:51 PM PDT 24
Peak memory 266004 kb
Host smart-06b2fc03-7cdb-4dda-b07d-4fc7e18c1c2a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279752776 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.279752776
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.179681678
Short name T569
Test name
Test status
Simulation time 10033787700 ps
CPU time 112.92 seconds
Started Aug 18 06:06:29 PM PDT 24
Finished Aug 18 06:08:22 PM PDT 24
Peak memory 275956 kb
Host smart-9be69098-e854-4e3c-bdd8-91991b295cf5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179681678 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.179681678
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.432176442
Short name T958
Test name
Test status
Simulation time 25893000 ps
CPU time 13.32 seconds
Started Aug 18 06:06:29 PM PDT 24
Finished Aug 18 06:06:42 PM PDT 24
Peak memory 258872 kb
Host smart-00dfffde-3590-4d4f-9090-6176daa9e1f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432176442 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.432176442
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1342368742
Short name T205
Test name
Test status
Simulation time 349971200 ps
CPU time 393.54 seconds
Started Aug 18 06:40:12 PM PDT 24
Finished Aug 18 06:46:46 PM PDT 24
Peak memory 264176 kb
Host smart-4e304e62-fa8c-45b8-8fe3-3506dda2fc4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342368742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.1342368742
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.2085533623
Short name T423
Test name
Test status
Simulation time 919953000 ps
CPU time 56.45 seconds
Started Aug 18 06:07:16 PM PDT 24
Finished Aug 18 06:08:12 PM PDT 24
Peak memory 265652 kb
Host smart-20109874-8e6b-43da-b862-815bb7f08919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085533623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.2085533623
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.59560600
Short name T409
Test name
Test status
Simulation time 1058934500 ps
CPU time 70.03 seconds
Started Aug 18 06:07:36 PM PDT 24
Finished Aug 18 06:08:46 PM PDT 24
Peak memory 265252 kb
Host smart-61189077-b62c-40c9-900f-de0bd237c7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59560600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.59560600
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.1892086524
Short name T413
Test name
Test status
Simulation time 1956317600 ps
CPU time 72.57 seconds
Started Aug 18 06:08:47 PM PDT 24
Finished Aug 18 06:10:00 PM PDT 24
Peak memory 264408 kb
Host smart-a050e2d8-9c4d-433a-b02d-07309326603c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892086524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.1892086524
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2843795202
Short name T203
Test name
Test status
Simulation time 70912200 ps
CPU time 19.96 seconds
Started Aug 18 06:40:24 PM PDT 24
Finished Aug 18 06:40:45 PM PDT 24
Peak memory 264288 kb
Host smart-b3905b57-4cbd-4ae0-a09e-c9dfe34ddee4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843795202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
2843795202
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.4184085640
Short name T371
Test name
Test status
Simulation time 42031200 ps
CPU time 28.22 seconds
Started Aug 18 06:07:06 PM PDT 24
Finished Aug 18 06:07:34 PM PDT 24
Peak memory 275512 kb
Host smart-d378aa00-4ec6-4936-a10b-59af4feab643
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184085640 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.4184085640
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.1074675499
Short name T263
Test name
Test status
Simulation time 45333000 ps
CPU time 78.79 seconds
Started Aug 18 06:04:34 PM PDT 24
Finished Aug 18 06:05:53 PM PDT 24
Peak memory 263096 kb
Host smart-1b0f2b46-5cc7-41cf-9895-3c1b81857c2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074675499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.1074675499
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.272709205
Short name T149
Test name
Test status
Simulation time 877034000 ps
CPU time 18.28 seconds
Started Aug 18 06:03:49 PM PDT 24
Finished Aug 18 06:04:08 PM PDT 24
Peak memory 266012 kb
Host smart-29245e76-c583-47d2-81d9-2851fcf12808
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272709205 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.272709205
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.630008313
Short name T148
Test name
Test status
Simulation time 787028000 ps
CPU time 17.03 seconds
Started Aug 18 06:04:36 PM PDT 24
Finished Aug 18 06:04:54 PM PDT 24
Peak memory 262568 kb
Host smart-7083ec50-08aa-407a-98a6-26a2689611ba
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630008313 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.630008313
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.2114653853
Short name T165
Test name
Test status
Simulation time 38644800 ps
CPU time 20.88 seconds
Started Aug 18 06:03:38 PM PDT 24
Finished Aug 18 06:03:59 PM PDT 24
Peak memory 274124 kb
Host smart-bd6e93b6-234f-489e-ad53-5e478ca02bfc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114653853 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.2114653853
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2443136947
Short name T258
Test name
Test status
Simulation time 805919200 ps
CPU time 393.3 seconds
Started Aug 18 06:40:02 PM PDT 24
Finished Aug 18 06:46:36 PM PDT 24
Peak memory 264168 kb
Host smart-4d410976-0043-4f7e-94fd-5ada51476384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443136947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.2443136947
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.2487684843
Short name T245
Test name
Test status
Simulation time 23302600 ps
CPU time 14.2 seconds
Started Aug 18 06:03:48 PM PDT 24
Finished Aug 18 06:04:03 PM PDT 24
Peak memory 262184 kb
Host smart-b7d55127-2f0e-44e4-ad17-c263bf46c5d9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487684843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.2487684843
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.316822179
Short name T1159
Test name
Test status
Simulation time 15937200 ps
CPU time 13.55 seconds
Started Aug 18 06:39:57 PM PDT 24
Finished Aug 18 06:40:11 PM PDT 24
Peak memory 261520 kb
Host smart-b0b8d5c7-26fd-42cc-ae3c-29864890bdc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316822179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.316822179
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3098085865
Short name T382
Test name
Test status
Simulation time 650586800 ps
CPU time 798.63 seconds
Started Aug 18 06:40:14 PM PDT 24
Finished Aug 18 06:53:33 PM PDT 24
Peak memory 264180 kb
Host smart-9a8f453d-410d-4986-afb4-fbac664ae2d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098085865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.3098085865
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.3169804189
Short name T690
Test name
Test status
Simulation time 5265729600 ps
CPU time 133.54 seconds
Started Aug 18 06:03:34 PM PDT 24
Finished Aug 18 06:05:47 PM PDT 24
Peak memory 285980 kb
Host smart-12b8998d-fd2d-4706-9866-51a2cc40bed9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169804189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_intr_rd.3169804189
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.2357912788
Short name T402
Test name
Test status
Simulation time 106765800 ps
CPU time 22.44 seconds
Started Aug 18 06:03:28 PM PDT 24
Finished Aug 18 06:03:51 PM PDT 24
Peak memory 265600 kb
Host smart-cbc36cca-7d7b-473f-b445-34238704e7a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357912788 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.2357912788
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.2232940167
Short name T1020
Test name
Test status
Simulation time 34174800 ps
CPU time 31.7 seconds
Started Aug 18 06:03:36 PM PDT 24
Finished Aug 18 06:04:08 PM PDT 24
Peak memory 274240 kb
Host smart-b986bbac-1e63-4421-a28c-0409e2c465ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232940167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.2232940167
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.3312819933
Short name T99
Test name
Test status
Simulation time 10536100 ps
CPU time 21.69 seconds
Started Aug 18 06:03:52 PM PDT 24
Finished Aug 18 06:04:13 PM PDT 24
Peak memory 273804 kb
Host smart-8af75ea3-2ee9-4d37-84f7-90465dbdbf2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312819933 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.3312819933
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.2875349330
Short name T403
Test name
Test status
Simulation time 39698500 ps
CPU time 131.32 seconds
Started Aug 18 06:03:44 PM PDT 24
Finished Aug 18 06:05:55 PM PDT 24
Peak memory 265720 kb
Host smart-2a3be777-72f7-416c-a274-936fe2282b7c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875349330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.2875349330
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.4200484397
Short name T396
Test name
Test status
Simulation time 17408600 ps
CPU time 20.89 seconds
Started Aug 18 06:06:31 PM PDT 24
Finished Aug 18 06:06:52 PM PDT 24
Peak memory 273960 kb
Host smart-eed89d10-5d5b-4c29-ab78-439810d06f17
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200484397 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.4200484397
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.4222347563
Short name T908
Test name
Test status
Simulation time 38150300 ps
CPU time 131.89 seconds
Started Aug 18 06:06:21 PM PDT 24
Finished Aug 18 06:08:33 PM PDT 24
Peak memory 260436 kb
Host smart-d613bce0-9966-4b69-89fa-8b2a51922e79
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222347563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.4222347563
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.759239718
Short name T378
Test name
Test status
Simulation time 13382723800 ps
CPU time 468.93 seconds
Started Aug 18 06:06:21 PM PDT 24
Finished Aug 18 06:14:10 PM PDT 24
Peak memory 319708 kb
Host smart-5540dbd1-7036-4296-912c-b3a92c257e76
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759239718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.flash_ctrl_rw.759239718
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.3083396948
Short name T799
Test name
Test status
Simulation time 69612400 ps
CPU time 31.27 seconds
Started Aug 18 06:07:16 PM PDT 24
Finished Aug 18 06:07:48 PM PDT 24
Peak memory 276240 kb
Host smart-6daa3dfa-c144-4885-b4a1-6cd789d99b95
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083396948 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.3083396948
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.372132949
Short name T37
Test name
Test status
Simulation time 41415600 ps
CPU time 28.42 seconds
Started Aug 18 06:07:27 PM PDT 24
Finished Aug 18 06:07:56 PM PDT 24
Peak memory 276208 kb
Host smart-f43b8916-f00f-4d3f-8e60-fbb3882e26d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372132949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_rw_evict.372132949
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.2600298332
Short name T657
Test name
Test status
Simulation time 2965953400 ps
CPU time 70.62 seconds
Started Aug 18 06:07:50 PM PDT 24
Finished Aug 18 06:09:01 PM PDT 24
Peak memory 264160 kb
Host smart-1a3294c6-3953-43fe-97da-061931506aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600298332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.2600298332
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.2353481231
Short name T804
Test name
Test status
Simulation time 12803700 ps
CPU time 21.86 seconds
Started Aug 18 06:07:53 PM PDT 24
Finished Aug 18 06:08:15 PM PDT 24
Peak memory 274100 kb
Host smart-7a62e782-b58c-4264-a66d-dca71a75fa1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353481231 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.2353481231
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.1533601260
Short name T407
Test name
Test status
Simulation time 14107200 ps
CPU time 22.44 seconds
Started Aug 18 06:08:01 PM PDT 24
Finished Aug 18 06:08:23 PM PDT 24
Peak memory 274060 kb
Host smart-6cf1b654-b172-4650-8a22-5f58a9101353
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533601260 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.1533601260
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.3040955041
Short name T30
Test name
Test status
Simulation time 1678680200 ps
CPU time 61.21 seconds
Started Aug 18 06:08:28 PM PDT 24
Finished Aug 18 06:09:29 PM PDT 24
Peak memory 264124 kb
Host smart-60357420-48ac-4e80-aea6-cd96f915f415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040955041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.3040955041
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.2857931491
Short name T361
Test name
Test status
Simulation time 159959600 ps
CPU time 31.51 seconds
Started Aug 18 06:09:12 PM PDT 24
Finished Aug 18 06:09:43 PM PDT 24
Peak memory 276548 kb
Host smart-50830586-150f-464f-9f5f-28dbbe53e1ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857931491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.2857931491
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.1972205025
Short name T417
Test name
Test status
Simulation time 540383700 ps
CPU time 59.68 seconds
Started Aug 18 06:05:31 PM PDT 24
Finished Aug 18 06:06:30 PM PDT 24
Peak memory 264244 kb
Host smart-5902a6d4-fac6-48d7-a2a1-37a754fe0a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972205025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.1972205025
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1154543184
Short name T224
Test name
Test status
Simulation time 159498700 ps
CPU time 16.42 seconds
Started Aug 18 06:40:11 PM PDT 24
Finished Aug 18 06:40:27 PM PDT 24
Peak memory 264272 kb
Host smart-f5b59055-ffe5-4ae4-a5ba-be697940aaa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154543184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
1154543184
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.2007539291
Short name T28
Test name
Test status
Simulation time 51322562300 ps
CPU time 191.22 seconds
Started Aug 18 06:03:38 PM PDT 24
Finished Aug 18 06:06:49 PM PDT 24
Peak memory 260204 kb
Host smart-a511c08c-75f0-4bb7-97bc-441b3dcb25c4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200
7539291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.2007539291
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.1895648939
Short name T133
Test name
Test status
Simulation time 15445597300 ps
CPU time 538.96 seconds
Started Aug 18 06:05:05 PM PDT 24
Finished Aug 18 06:14:04 PM PDT 24
Peak memory 314996 kb
Host smart-2da25e12-21c2-487d-93f6-a6511d0a7bad
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895648939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.flash_ctrl_rw.1895648939
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.4018961300
Short name T54
Test name
Test status
Simulation time 82350700 ps
CPU time 14.66 seconds
Started Aug 18 06:03:37 PM PDT 24
Finished Aug 18 06:03:52 PM PDT 24
Peak memory 262172 kb
Host smart-60762506-292c-48e9-990f-647fcb1bbc1e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4018961300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.4018961300
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.982940534
Short name T86
Test name
Test status
Simulation time 4074938000 ps
CPU time 535.49 seconds
Started Aug 18 06:03:43 PM PDT 24
Finished Aug 18 06:12:38 PM PDT 24
Peak memory 318360 kb
Host smart-f7cac727-243b-43f5-9ae5-aba819df22a6
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982940534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.flash_ctrl_rw.982940534
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.3111203188
Short name T55
Test name
Test status
Simulation time 1592058100 ps
CPU time 4950.77 seconds
Started Aug 18 06:04:14 PM PDT 24
Finished Aug 18 07:26:45 PM PDT 24
Peak memory 291116 kb
Host smart-e53dfa52-8973-4ff9-bd6f-43818de12679
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111203188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.3111203188
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.2651197039
Short name T1069
Test name
Test status
Simulation time 2369222500 ps
CPU time 817.26 seconds
Started Aug 18 06:03:28 PM PDT 24
Finished Aug 18 06:17:05 PM PDT 24
Peak memory 274420 kb
Host smart-26bc561f-6e2d-45fa-a381-893f87b15fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651197039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.2651197039
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.2826841710
Short name T194
Test name
Test status
Simulation time 363244866000 ps
CPU time 2532.84 seconds
Started Aug 18 06:03:20 PM PDT 24
Finished Aug 18 06:45:33 PM PDT 24
Peak memory 265824 kb
Host smart-44000c51-d4c4-4691-96bb-0464708899b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826841710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.2826841710
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.3943643394
Short name T152
Test name
Test status
Simulation time 7738271000 ps
CPU time 135.05 seconds
Started Aug 18 06:03:28 PM PDT 24
Finished Aug 18 06:05:43 PM PDT 24
Peak memory 282396 kb
Host smart-33ce9db2-9367-40c7-b9b6-60bff5104311
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3943643394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.3943643394
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.764382837
Short name T110
Test name
Test status
Simulation time 272210716600 ps
CPU time 2803.58 seconds
Started Aug 18 06:03:47 PM PDT 24
Finished Aug 18 06:50:31 PM PDT 24
Peak memory 265864 kb
Host smart-c04413d4-baeb-4748-9b05-2ba45270fba3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764382837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.flash_ctrl_host_ctrl_arb.764382837
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.1867981958
Short name T327
Test name
Test status
Simulation time 4371830900 ps
CPU time 638.29 seconds
Started Aug 18 06:03:44 PM PDT 24
Finished Aug 18 06:14:22 PM PDT 24
Peak memory 315272 kb
Host smart-9877c9da-245e-4a0c-929f-333426c4ad65
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867981958 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.1867981958
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3464322201
Short name T170
Test name
Test status
Simulation time 40120688000 ps
CPU time 817.91 seconds
Started Aug 18 06:06:33 PM PDT 24
Finished Aug 18 06:20:12 PM PDT 24
Peak memory 264992 kb
Host smart-505d7c97-7836-4724-9374-77cef69a4b0c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464322201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3464322201
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.3577477939
Short name T208
Test name
Test status
Simulation time 76798900 ps
CPU time 132.06 seconds
Started Aug 18 06:07:17 PM PDT 24
Finished Aug 18 06:09:29 PM PDT 24
Peak memory 265592 kb
Host smart-c76544d1-e333-43ea-bf56-b1b7f0314131
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577477939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.3577477939
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.4218650239
Short name T35
Test name
Test status
Simulation time 575018400 ps
CPU time 143.14 seconds
Started Aug 18 06:04:09 PM PDT 24
Finished Aug 18 06:06:32 PM PDT 24
Peak memory 292632 kb
Host smart-fbd3252b-535f-4169-9f04-ca5e0a883523
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218650239 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.4218650239
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.3969537529
Short name T209
Test name
Test status
Simulation time 937913200 ps
CPU time 18.37 seconds
Started Aug 18 06:04:50 PM PDT 24
Finished Aug 18 06:05:08 PM PDT 24
Peak memory 263712 kb
Host smart-baef51ee-7efc-4986-b9df-7d4bd7a18f81
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969537529 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.3969537529
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2550080634
Short name T108
Test name
Test status
Simulation time 1083363000 ps
CPU time 34.26 seconds
Started Aug 18 06:40:05 PM PDT 24
Finished Aug 18 06:40:39 PM PDT 24
Peak memory 261720 kb
Host smart-fbc6e0a0-d0ea-4674-aff8-d838db833056
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550080634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.2550080634
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2671858557
Short name T389
Test name
Test status
Simulation time 2294909800 ps
CPU time 77.54 seconds
Started Aug 18 06:40:01 PM PDT 24
Finished Aug 18 06:41:19 PM PDT 24
Peak memory 261672 kb
Host smart-43bb7de4-b8b1-47e3-a42e-259cf5c1457a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671858557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.2671858557
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1051626982
Short name T1123
Test name
Test status
Simulation time 416599300 ps
CPU time 46.43 seconds
Started Aug 18 06:39:58 PM PDT 24
Finished Aug 18 06:40:45 PM PDT 24
Peak memory 263868 kb
Host smart-86fd810d-a901-462c-93d8-b70fc847cf23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051626982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.1051626982
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1079579505
Short name T106
Test name
Test status
Simulation time 85085800 ps
CPU time 18.06 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:31 PM PDT 24
Peak memory 271780 kb
Host smart-3a40e365-5aca-4343-aa44-e38fbe92c711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079579505 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.1079579505
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1186768717
Short name T1175
Test name
Test status
Simulation time 94712300 ps
CPU time 17.55 seconds
Started Aug 18 06:40:00 PM PDT 24
Finished Aug 18 06:40:18 PM PDT 24
Peak memory 264108 kb
Host smart-f092a82f-02c6-4b45-bb0e-31933ebcd8d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186768717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.1186768717
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.4181102692
Short name T1215
Test name
Test status
Simulation time 16233700 ps
CPU time 13.57 seconds
Started Aug 18 06:40:01 PM PDT 24
Finished Aug 18 06:40:14 PM PDT 24
Peak memory 261616 kb
Host smart-f9c343e5-f999-4113-aae6-1a83a32b7669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181102692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.4
181102692
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3992267815
Short name T1147
Test name
Test status
Simulation time 23411900 ps
CPU time 13.54 seconds
Started Aug 18 06:40:00 PM PDT 24
Finished Aug 18 06:40:14 PM PDT 24
Peak memory 261508 kb
Host smart-0aa46e79-4da3-4fbc-b0a1-57d8c63fc4c6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992267815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.3992267815
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2406024655
Short name T1165
Test name
Test status
Simulation time 350708200 ps
CPU time 18.52 seconds
Started Aug 18 06:40:02 PM PDT 24
Finished Aug 18 06:40:21 PM PDT 24
Peak memory 264156 kb
Host smart-0d85a244-bc77-46fa-a89d-ab7d52b44ca1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406024655 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.2406024655
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3759715362
Short name T1232
Test name
Test status
Simulation time 71720200 ps
CPU time 16.14 seconds
Started Aug 18 06:39:59 PM PDT 24
Finished Aug 18 06:40:16 PM PDT 24
Peak memory 253416 kb
Host smart-d8e6075f-42f5-4cbc-92a0-4ca567fbcf0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759715362 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.3759715362
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.328974691
Short name T1228
Test name
Test status
Simulation time 55987200 ps
CPU time 13.26 seconds
Started Aug 18 06:40:06 PM PDT 24
Finished Aug 18 06:40:20 PM PDT 24
Peak memory 253552 kb
Host smart-5db8836a-a248-428c-8792-9006f79e42ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328974691 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.328974691
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2271009199
Short name T253
Test name
Test status
Simulation time 230514900 ps
CPU time 19.89 seconds
Started Aug 18 06:40:11 PM PDT 24
Finished Aug 18 06:40:31 PM PDT 24
Peak memory 264256 kb
Host smart-7da19261-beb2-487e-8015-68c6102091d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271009199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.2
271009199
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.882266867
Short name T259
Test name
Test status
Simulation time 741375300 ps
CPU time 823 seconds
Started Aug 18 06:40:00 PM PDT 24
Finished Aug 18 06:53:43 PM PDT 24
Peak memory 264172 kb
Host smart-724c39b9-14ff-48cd-bf98-012ba14e7aee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882266867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_
tl_intg_err.882266867
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1063763533
Short name T1208
Test name
Test status
Simulation time 2352564000 ps
CPU time 38.01 seconds
Started Aug 18 06:39:58 PM PDT 24
Finished Aug 18 06:40:36 PM PDT 24
Peak memory 253576 kb
Host smart-5aa0b40b-a59e-45ad-963d-172cb0fd588e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063763533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.1063763533
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.936046049
Short name T1202
Test name
Test status
Simulation time 962598200 ps
CPU time 62.99 seconds
Started Aug 18 06:40:03 PM PDT 24
Finished Aug 18 06:41:06 PM PDT 24
Peak memory 261560 kb
Host smart-04f1a741-dc65-4ce0-9b0c-3db6dea6fb7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936046049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_bit_bash.936046049
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.4048086802
Short name T66
Test name
Test status
Simulation time 124736600 ps
CPU time 39.1 seconds
Started Aug 18 06:39:56 PM PDT 24
Finished Aug 18 06:40:35 PM PDT 24
Peak memory 263632 kb
Host smart-9a1f5c13-277d-407e-9d75-3a14ee90bfcf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048086802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.4048086802
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3772307685
Short name T379
Test name
Test status
Simulation time 71216400 ps
CPU time 18.99 seconds
Started Aug 18 06:40:02 PM PDT 24
Finished Aug 18 06:40:21 PM PDT 24
Peak memory 272460 kb
Host smart-b0a17cb4-b513-4906-a258-1537ae93133b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772307685 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3772307685
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2192083508
Short name T239
Test name
Test status
Simulation time 26201800 ps
CPU time 17.78 seconds
Started Aug 18 06:39:58 PM PDT 24
Finished Aug 18 06:40:16 PM PDT 24
Peak memory 264076 kb
Host smart-93b2ef8c-7f7a-4e83-a0f1-25b307b94848
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192083508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.2192083508
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2319473439
Short name T233
Test name
Test status
Simulation time 183499400 ps
CPU time 13.51 seconds
Started Aug 18 06:40:12 PM PDT 24
Finished Aug 18 06:40:25 PM PDT 24
Peak memory 262792 kb
Host smart-21721e45-259d-4995-ba93-190fcae4828c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319473439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.2319473439
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3935905533
Short name T1184
Test name
Test status
Simulation time 28537600 ps
CPU time 13.62 seconds
Started Aug 18 06:39:57 PM PDT 24
Finished Aug 18 06:40:11 PM PDT 24
Peak memory 261548 kb
Host smart-3fb6b1b1-e0d1-4ff2-8f3d-a4f3bb9da127
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935905533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.3935905533
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3869352217
Short name T1122
Test name
Test status
Simulation time 684504000 ps
CPU time 36.34 seconds
Started Aug 18 06:39:54 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 262972 kb
Host smart-84d604b3-b527-4f8f-ba3b-4945e410c168
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869352217 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.3869352217
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2655824281
Short name T1205
Test name
Test status
Simulation time 20376100 ps
CPU time 13.18 seconds
Started Aug 18 06:40:03 PM PDT 24
Finished Aug 18 06:40:16 PM PDT 24
Peak memory 253500 kb
Host smart-4a86b94a-38dd-456e-b54d-a43aafd7869b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655824281 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.2655824281
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.680181545
Short name T1141
Test name
Test status
Simulation time 61064100 ps
CPU time 16.15 seconds
Started Aug 18 06:39:57 PM PDT 24
Finished Aug 18 06:40:13 PM PDT 24
Peak memory 253548 kb
Host smart-6088b2e4-69eb-4c6e-9ea4-bafe35dc027a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680181545 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.680181545
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3841470321
Short name T251
Test name
Test status
Simulation time 209429700 ps
CPU time 16.52 seconds
Started Aug 18 06:39:57 PM PDT 24
Finished Aug 18 06:40:14 PM PDT 24
Peak memory 264292 kb
Host smart-f2da64b7-7158-42cb-9fe6-9324ea6e836d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841470321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3
841470321
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1189481881
Short name T280
Test name
Test status
Simulation time 7088353000 ps
CPU time 975.79 seconds
Started Aug 18 06:40:01 PM PDT 24
Finished Aug 18 06:56:17 PM PDT 24
Peak memory 264168 kb
Host smart-35de0acb-94ac-443d-a65c-ae2cba7599d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189481881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.1189481881
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3890644617
Short name T1231
Test name
Test status
Simulation time 1153587600 ps
CPU time 17.81 seconds
Started Aug 18 06:40:02 PM PDT 24
Finished Aug 18 06:40:20 PM PDT 24
Peak memory 278716 kb
Host smart-7fd3ce20-e234-4955-b251-a6fed520af45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890644617 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3890644617
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2691920963
Short name T1226
Test name
Test status
Simulation time 17766800 ps
CPU time 16.55 seconds
Started Aug 18 06:40:01 PM PDT 24
Finished Aug 18 06:40:18 PM PDT 24
Peak memory 264100 kb
Host smart-7bb0eee0-8835-4b59-a78d-c62c6f23c90f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691920963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.2691920963
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.513981793
Short name T337
Test name
Test status
Simulation time 30882900 ps
CPU time 13.51 seconds
Started Aug 18 06:40:07 PM PDT 24
Finished Aug 18 06:40:20 PM PDT 24
Peak memory 260756 kb
Host smart-4717ced2-020b-40e0-aac9-ab703ab87c9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513981793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.513981793
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3921572908
Short name T1210
Test name
Test status
Simulation time 465742300 ps
CPU time 18.44 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:28 PM PDT 24
Peak memory 263472 kb
Host smart-71cdda8c-9019-420f-b708-d1d6174ee66c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921572908 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.3921572908
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1948248173
Short name T1246
Test name
Test status
Simulation time 12504100 ps
CPU time 15.8 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:29 PM PDT 24
Peak memory 253508 kb
Host smart-533e6058-f7ec-4b49-84bb-a2e8b97ac68b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948248173 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.1948248173
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.984147801
Short name T1154
Test name
Test status
Simulation time 35793100 ps
CPU time 15.81 seconds
Started Aug 18 06:40:04 PM PDT 24
Finished Aug 18 06:40:20 PM PDT 24
Peak memory 253552 kb
Host smart-3503f3cc-4d14-4290-a136-ef400bd8397c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984147801 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.984147801
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.540052674
Short name T1176
Test name
Test status
Simulation time 61533800 ps
CPU time 21.81 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:35 PM PDT 24
Peak memory 263784 kb
Host smart-ea6903b9-0b14-47c5-b6b0-7362338bb0e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540052674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.540052674
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2369077123
Short name T1181
Test name
Test status
Simulation time 675621400 ps
CPU time 472.36 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:48:01 PM PDT 24
Peak memory 264172 kb
Host smart-3b268f86-6bcf-454b-9c21-1ac61c3bafb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369077123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.2369077123
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3427006399
Short name T249
Test name
Test status
Simulation time 166180600 ps
CPU time 17.63 seconds
Started Aug 18 06:40:14 PM PDT 24
Finished Aug 18 06:40:32 PM PDT 24
Peak memory 263760 kb
Host smart-120563f0-aef5-4082-945a-f04f138579d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427006399 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.3427006399
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.726817633
Short name T279
Test name
Test status
Simulation time 192676900 ps
CPU time 14 seconds
Started Aug 18 06:40:08 PM PDT 24
Finished Aug 18 06:40:22 PM PDT 24
Peak memory 264080 kb
Host smart-5ebb332a-11ad-49f7-8baa-5dbc324f2f58
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726817633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.flash_ctrl_csr_rw.726817633
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1619226434
Short name T1198
Test name
Test status
Simulation time 30677300 ps
CPU time 13.79 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:26 PM PDT 24
Peak memory 261744 kb
Host smart-0a3a0f49-7530-408e-a209-da4765bc8a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619226434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
1619226434
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3425034721
Short name T1213
Test name
Test status
Simulation time 125567100 ps
CPU time 19.63 seconds
Started Aug 18 06:40:15 PM PDT 24
Finished Aug 18 06:40:34 PM PDT 24
Peak memory 263052 kb
Host smart-0a846b63-62be-4c3a-863e-db0755ce2311
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425034721 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.3425034721
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1919042661
Short name T1245
Test name
Test status
Simulation time 25433800 ps
CPU time 13.46 seconds
Started Aug 18 06:40:08 PM PDT 24
Finished Aug 18 06:40:21 PM PDT 24
Peak memory 253464 kb
Host smart-d5d8b292-f09d-4d00-8040-5d73e9f9a9b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919042661 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.1919042661
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3259133901
Short name T1132
Test name
Test status
Simulation time 31886100 ps
CPU time 13.33 seconds
Started Aug 18 06:40:15 PM PDT 24
Finished Aug 18 06:40:29 PM PDT 24
Peak memory 253488 kb
Host smart-d0c16fba-c26f-4137-a925-ea98cfdaded8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259133901 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.3259133901
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.302529052
Short name T104
Test name
Test status
Simulation time 102086200 ps
CPU time 16.02 seconds
Started Aug 18 06:40:04 PM PDT 24
Finished Aug 18 06:40:22 PM PDT 24
Peak memory 263508 kb
Host smart-a403d48f-80ce-47a9-9495-ba249e13ef43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302529052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.302529052
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2577199805
Short name T252
Test name
Test status
Simulation time 795776900 ps
CPU time 475.7 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:48:05 PM PDT 24
Peak memory 264176 kb
Host smart-bae03e4b-0afe-4364-b402-6cc4699ff484
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577199805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.2577199805
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.566585475
Short name T1204
Test name
Test status
Simulation time 122952600 ps
CPU time 19.48 seconds
Started Aug 18 06:40:14 PM PDT 24
Finished Aug 18 06:40:34 PM PDT 24
Peak memory 272492 kb
Host smart-fd3a636a-13dc-4020-9390-ca9cbec2473f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566585475 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.566585475
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3458745855
Short name T1125
Test name
Test status
Simulation time 39788500 ps
CPU time 16.48 seconds
Started Aug 18 06:40:12 PM PDT 24
Finished Aug 18 06:40:29 PM PDT 24
Peak memory 264104 kb
Host smart-feeab28a-ac0e-46e1-979e-4903e6801082
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458745855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.3458745855
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2750019193
Short name T1144
Test name
Test status
Simulation time 53105500 ps
CPU time 13.86 seconds
Started Aug 18 06:40:12 PM PDT 24
Finished Aug 18 06:40:26 PM PDT 24
Peak memory 261756 kb
Host smart-200c5a12-7f1d-4193-a670-cfdba676b927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750019193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
2750019193
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1974128150
Short name T278
Test name
Test status
Simulation time 882741600 ps
CPU time 21.41 seconds
Started Aug 18 06:40:05 PM PDT 24
Finished Aug 18 06:40:27 PM PDT 24
Peak memory 262952 kb
Host smart-b7c970d3-a2db-49f5-b176-d239dafdc1ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974128150 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.1974128150
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3250377463
Short name T1130
Test name
Test status
Simulation time 17779700 ps
CPU time 15.48 seconds
Started Aug 18 06:40:04 PM PDT 24
Finished Aug 18 06:40:21 PM PDT 24
Peak memory 253516 kb
Host smart-20ffc53e-b101-4986-aff8-b3d5b76480e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250377463 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.3250377463
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.782984960
Short name T1183
Test name
Test status
Simulation time 33545000 ps
CPU time 15.57 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:29 PM PDT 24
Peak memory 253376 kb
Host smart-493d6c1d-3168-4cd3-b383-76045dc80a31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782984960 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.782984960
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.968893294
Short name T1200
Test name
Test status
Simulation time 92888400 ps
CPU time 17.19 seconds
Started Aug 18 06:40:11 PM PDT 24
Finished Aug 18 06:40:28 PM PDT 24
Peak memory 263508 kb
Host smart-aea03eef-a9f4-4405-a1d7-18338d503eab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968893294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.968893294
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3060464972
Short name T330
Test name
Test status
Simulation time 59710300 ps
CPU time 19.17 seconds
Started Aug 18 06:40:11 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 271812 kb
Host smart-eda6b6ee-10ec-4d5a-bc3e-476222a4ef98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060464972 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.3060464972
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.38632738
Short name T1173
Test name
Test status
Simulation time 67667400 ps
CPU time 16.31 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:26 PM PDT 24
Peak memory 264108 kb
Host smart-b21540c5-7521-4656-be1d-1362eebd3175
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38632738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 13.flash_ctrl_csr_rw.38632738
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.139920953
Short name T1179
Test name
Test status
Simulation time 37437600 ps
CPU time 13.42 seconds
Started Aug 18 06:40:11 PM PDT 24
Finished Aug 18 06:40:25 PM PDT 24
Peak memory 261736 kb
Host smart-c733cfe5-7244-483f-8ade-a770834e8466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139920953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.139920953
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1177854384
Short name T1188
Test name
Test status
Simulation time 344354600 ps
CPU time 18.42 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:28 PM PDT 24
Peak memory 261688 kb
Host smart-c0003fdb-7bf3-46f5-a9ec-79600d4ff262
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177854384 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.1177854384
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.665508849
Short name T1227
Test name
Test status
Simulation time 12195800 ps
CPU time 15.46 seconds
Started Aug 18 06:40:05 PM PDT 24
Finished Aug 18 06:40:20 PM PDT 24
Peak memory 253512 kb
Host smart-601d8d13-2542-4b3e-b00a-a2d2472453e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665508849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.665508849
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.173909256
Short name T1142
Test name
Test status
Simulation time 22658200 ps
CPU time 15.52 seconds
Started Aug 18 06:40:07 PM PDT 24
Finished Aug 18 06:40:22 PM PDT 24
Peak memory 253424 kb
Host smart-53e88470-e72e-4f5c-ad59-2f616ec13645
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173909256 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.173909256
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1912243592
Short name T1207
Test name
Test status
Simulation time 382858300 ps
CPU time 20.32 seconds
Started Aug 18 06:40:19 PM PDT 24
Finished Aug 18 06:40:39 PM PDT 24
Peak memory 278808 kb
Host smart-475ac2c0-cb6a-451f-b964-c696ac1275b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912243592 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.1912243592
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.172682922
Short name T283
Test name
Test status
Simulation time 40205500 ps
CPU time 14.2 seconds
Started Aug 18 06:40:18 PM PDT 24
Finished Aug 18 06:40:32 PM PDT 24
Peak memory 264080 kb
Host smart-b306cadc-ea37-42b5-907a-873393f43cb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172682922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.flash_ctrl_csr_rw.172682922
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3936404456
Short name T250
Test name
Test status
Simulation time 141271400 ps
CPU time 13.65 seconds
Started Aug 18 06:40:16 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 261680 kb
Host smart-a00197e1-bb1a-4a5a-b250-029496060a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936404456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
3936404456
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1599501167
Short name T1160
Test name
Test status
Simulation time 121022700 ps
CPU time 34.19 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:43 PM PDT 24
Peak memory 261736 kb
Host smart-cf83c36d-4509-413d-823e-8d30630587b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599501167 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.1599501167
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1039763776
Short name T1126
Test name
Test status
Simulation time 13364200 ps
CPU time 15.58 seconds
Started Aug 18 06:40:08 PM PDT 24
Finished Aug 18 06:40:23 PM PDT 24
Peak memory 253424 kb
Host smart-d6ceaa23-093d-4099-b448-775ac6270d0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039763776 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.1039763776
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.245952332
Short name T1240
Test name
Test status
Simulation time 67692700 ps
CPU time 15.5 seconds
Started Aug 18 06:40:11 PM PDT 24
Finished Aug 18 06:40:26 PM PDT 24
Peak memory 253368 kb
Host smart-14b4e76a-de72-42a6-a536-fdf1a8d869b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245952332 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.245952332
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3284177674
Short name T256
Test name
Test status
Simulation time 40212300 ps
CPU time 16.13 seconds
Started Aug 18 06:40:22 PM PDT 24
Finished Aug 18 06:40:38 PM PDT 24
Peak memory 264284 kb
Host smart-3bd93d7d-7cc7-40cc-b71f-1adaab22bf91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284177674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
3284177674
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1983381893
Short name T1236
Test name
Test status
Simulation time 1603489700 ps
CPU time 475 seconds
Started Aug 18 06:40:14 PM PDT 24
Finished Aug 18 06:48:10 PM PDT 24
Peak memory 264176 kb
Host smart-826764a9-364c-4604-aff5-f9ab2b6f8586
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983381893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.1983381893
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3841217304
Short name T1146
Test name
Test status
Simulation time 164773200 ps
CPU time 20.44 seconds
Started Aug 18 06:40:25 PM PDT 24
Finished Aug 18 06:40:45 PM PDT 24
Peak memory 271084 kb
Host smart-fc92b16a-25e7-43c2-95b6-c11f41a436b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841217304 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3841217304
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.671437732
Short name T282
Test name
Test status
Simulation time 194407100 ps
CPU time 17.22 seconds
Started Aug 18 06:40:15 PM PDT 24
Finished Aug 18 06:40:32 PM PDT 24
Peak memory 261700 kb
Host smart-e265cb6a-d630-449b-ae26-28bad55f6dd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671437732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.flash_ctrl_csr_rw.671437732
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3866035837
Short name T1220
Test name
Test status
Simulation time 16567200 ps
CPU time 13.38 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:27 PM PDT 24
Peak memory 261676 kb
Host smart-1ecbadab-8c12-469a-a758-0d760b4489d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866035837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
3866035837
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.193074794
Short name T1171
Test name
Test status
Simulation time 77981300 ps
CPU time 18.4 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:28 PM PDT 24
Peak memory 263248 kb
Host smart-eb0ace22-76c7-413f-b7ad-7b38cc60adc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193074794 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.193074794
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2689501391
Short name T1107
Test name
Test status
Simulation time 46208400 ps
CPU time 13.12 seconds
Started Aug 18 06:40:11 PM PDT 24
Finished Aug 18 06:40:24 PM PDT 24
Peak memory 253476 kb
Host smart-6207c700-4c8c-48bd-8c1c-a4b8dc1852a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689501391 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.2689501391
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1795018475
Short name T1234
Test name
Test status
Simulation time 107765900 ps
CPU time 15.63 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:24 PM PDT 24
Peak memory 253500 kb
Host smart-7ff54bd3-7f52-4a71-89a3-a4526b870b31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795018475 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.1795018475
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1982886942
Short name T254
Test name
Test status
Simulation time 221817700 ps
CPU time 20.49 seconds
Started Aug 18 06:40:14 PM PDT 24
Finished Aug 18 06:40:35 PM PDT 24
Peak memory 264268 kb
Host smart-ca17347d-d17b-4dea-8110-09d477bcaf01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982886942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
1982886942
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1308659027
Short name T107
Test name
Test status
Simulation time 54668800 ps
CPU time 14.69 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:24 PM PDT 24
Peak memory 275916 kb
Host smart-604ac382-e115-497a-b32c-70b45ba7087d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308659027 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.1308659027
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4028037216
Short name T1156
Test name
Test status
Simulation time 30144900 ps
CPU time 17.06 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:31 PM PDT 24
Peak memory 264112 kb
Host smart-abb183ad-9890-4924-baaa-d9bc753433d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028037216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.4028037216
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.707528507
Short name T1136
Test name
Test status
Simulation time 25023800 ps
CPU time 13.44 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:22 PM PDT 24
Peak memory 261616 kb
Host smart-5ac5e8bb-3d4e-4fb1-a144-d1db82ba860a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707528507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.707528507
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.55114686
Short name T285
Test name
Test status
Simulation time 418485800 ps
CPU time 18.37 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:31 PM PDT 24
Peak memory 263420 kb
Host smart-29e03074-74d0-4f95-88ed-c094515d4109
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55114686 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.55114686
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1714863304
Short name T1169
Test name
Test status
Simulation time 44287300 ps
CPU time 15.77 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:25 PM PDT 24
Peak memory 253404 kb
Host smart-9a92fad1-3d94-4c44-820e-89410d69f6db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714863304 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.1714863304
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2330050875
Short name T1133
Test name
Test status
Simulation time 15447900 ps
CPU time 15.72 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:25 PM PDT 24
Peak memory 253484 kb
Host smart-fbec283b-33ab-41f5-94af-84a2c4a64621
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330050875 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.2330050875
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.4232572173
Short name T225
Test name
Test status
Simulation time 293812400 ps
CPU time 19.03 seconds
Started Aug 18 06:40:30 PM PDT 24
Finished Aug 18 06:40:49 PM PDT 24
Peak memory 272488 kb
Host smart-b739c379-c5a8-43fa-8f99-50673c660ec4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232572173 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.4232572173
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3933737126
Short name T1185
Test name
Test status
Simulation time 146928500 ps
CPU time 17.56 seconds
Started Aug 18 06:40:15 PM PDT 24
Finished Aug 18 06:40:33 PM PDT 24
Peak memory 264092 kb
Host smart-a8d2e17d-cf9e-4dfc-89bc-6ab70a59f845
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933737126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.3933737126
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3504641865
Short name T1137
Test name
Test status
Simulation time 31760200 ps
CPU time 13.23 seconds
Started Aug 18 06:40:11 PM PDT 24
Finished Aug 18 06:40:24 PM PDT 24
Peak memory 261724 kb
Host smart-c36f2b2a-d185-4174-b6ea-733f52f941f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504641865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
3504641865
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2505175189
Short name T234
Test name
Test status
Simulation time 205294000 ps
CPU time 15.86 seconds
Started Aug 18 06:40:21 PM PDT 24
Finished Aug 18 06:40:37 PM PDT 24
Peak memory 261764 kb
Host smart-14e608f5-6549-4c57-aef7-ebda663ab1a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505175189 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.2505175189
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1001844619
Short name T1211
Test name
Test status
Simulation time 23149700 ps
CPU time 13.24 seconds
Started Aug 18 06:40:10 PM PDT 24
Finished Aug 18 06:40:24 PM PDT 24
Peak memory 253464 kb
Host smart-cc06f75a-154d-481b-93d4-46b3f4155a28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001844619 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.1001844619
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2502670927
Short name T1115
Test name
Test status
Simulation time 44888100 ps
CPU time 16.1 seconds
Started Aug 18 06:40:06 PM PDT 24
Finished Aug 18 06:40:22 PM PDT 24
Peak memory 253500 kb
Host smart-eb012c51-799f-4ce0-abf1-24678c545b8a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502670927 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.2502670927
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1182289036
Short name T1233
Test name
Test status
Simulation time 67909500 ps
CPU time 19.8 seconds
Started Aug 18 06:40:05 PM PDT 24
Finished Aug 18 06:40:25 PM PDT 24
Peak memory 264288 kb
Host smart-291846f5-b53a-4903-87a6-5505987bd979
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182289036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
1182289036
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1560446221
Short name T288
Test name
Test status
Simulation time 531700300 ps
CPU time 18.28 seconds
Started Aug 18 06:40:17 PM PDT 24
Finished Aug 18 06:40:35 PM PDT 24
Peak memory 277940 kb
Host smart-0712ebf2-066d-44bb-bef8-aa9216f6f2f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560446221 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1560446221
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.93703924
Short name T1150
Test name
Test status
Simulation time 63930200 ps
CPU time 16.99 seconds
Started Aug 18 06:40:30 PM PDT 24
Finished Aug 18 06:40:47 PM PDT 24
Peak memory 261496 kb
Host smart-726161ed-fa92-483b-90ff-f8520d915b67
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93703924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 18.flash_ctrl_csr_rw.93703924
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3559613061
Short name T1151
Test name
Test status
Simulation time 18216100 ps
CPU time 13.32 seconds
Started Aug 18 06:40:18 PM PDT 24
Finished Aug 18 06:40:32 PM PDT 24
Peak memory 261696 kb
Host smart-e37f6011-bdf9-42de-9a3d-15f42fe5469c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559613061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
3559613061
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1597519305
Short name T1194
Test name
Test status
Simulation time 939358600 ps
CPU time 18.16 seconds
Started Aug 18 06:40:11 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 261736 kb
Host smart-bb69c08a-313a-4514-810c-eb01d81b610e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597519305 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.1597519305
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.47684464
Short name T1106
Test name
Test status
Simulation time 14032700 ps
CPU time 13.05 seconds
Started Aug 18 06:40:31 PM PDT 24
Finished Aug 18 06:40:44 PM PDT 24
Peak memory 253304 kb
Host smart-24f9df4b-6870-4cef-b0ad-1f6d2bae087e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47684464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.47684464
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1434957160
Short name T1238
Test name
Test status
Simulation time 12989700 ps
CPU time 15.65 seconds
Started Aug 18 06:40:25 PM PDT 24
Finished Aug 18 06:40:41 PM PDT 24
Peak memory 253388 kb
Host smart-c51257d1-e232-412d-ab22-dbf0869a619b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434957160 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.1434957160
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3658691397
Short name T255
Test name
Test status
Simulation time 79624600 ps
CPU time 17.8 seconds
Started Aug 18 06:40:14 PM PDT 24
Finished Aug 18 06:40:32 PM PDT 24
Peak memory 264288 kb
Host smart-cb70718c-ec53-4dd5-828b-b84933d96bde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658691397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
3658691397
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4241577102
Short name T1209
Test name
Test status
Simulation time 369378600 ps
CPU time 474.79 seconds
Started Aug 18 06:40:14 PM PDT 24
Finished Aug 18 06:48:09 PM PDT 24
Peak memory 264052 kb
Host smart-e292888e-768f-4675-9f7f-0028af4d4534
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241577102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.4241577102
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3120978185
Short name T1172
Test name
Test status
Simulation time 345957900 ps
CPU time 19.02 seconds
Started Aug 18 06:40:18 PM PDT 24
Finished Aug 18 06:40:37 PM PDT 24
Peak memory 271732 kb
Host smart-00343e9e-c2fa-44c0-9988-f016e2e578f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120978185 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.3120978185
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1153089536
Short name T240
Test name
Test status
Simulation time 72104500 ps
CPU time 14.07 seconds
Started Aug 18 06:40:18 PM PDT 24
Finished Aug 18 06:40:33 PM PDT 24
Peak memory 261696 kb
Host smart-4d0c6845-8261-46ce-91cb-cd4fe3e3be24
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153089536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.1153089536
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.492389770
Short name T1201
Test name
Test status
Simulation time 34858200 ps
CPU time 13.41 seconds
Started Aug 18 06:40:35 PM PDT 24
Finished Aug 18 06:40:48 PM PDT 24
Peak memory 261512 kb
Host smart-d49fa36d-59f7-471d-8139-d345a3dea5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492389770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.492389770
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1971637259
Short name T64
Test name
Test status
Simulation time 34031600 ps
CPU time 17.78 seconds
Started Aug 18 06:40:11 PM PDT 24
Finished Aug 18 06:40:28 PM PDT 24
Peak memory 263120 kb
Host smart-24a90577-30b3-4247-9f50-1e4ebc11b357
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971637259 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.1971637259
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2732354070
Short name T1167
Test name
Test status
Simulation time 21375300 ps
CPU time 13.78 seconds
Started Aug 18 06:40:25 PM PDT 24
Finished Aug 18 06:40:39 PM PDT 24
Peak memory 253476 kb
Host smart-a4d1365f-aa1e-4292-9c22-a613078bffc2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732354070 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.2732354070
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.927070527
Short name T1242
Test name
Test status
Simulation time 41402600 ps
CPU time 15.84 seconds
Started Aug 18 06:40:14 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 253372 kb
Host smart-4acb3986-b530-49b6-8a29-db201db58bc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927070527 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.927070527
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2485737908
Short name T383
Test name
Test status
Simulation time 298152600 ps
CPU time 478.86 seconds
Started Aug 18 06:40:19 PM PDT 24
Finished Aug 18 06:48:18 PM PDT 24
Peak memory 264152 kb
Host smart-a1430cbb-7c90-4d40-b624-02f459c83d09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485737908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.2485737908
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2069318089
Short name T1197
Test name
Test status
Simulation time 1250502400 ps
CPU time 59.55 seconds
Started Aug 18 06:40:00 PM PDT 24
Finished Aug 18 06:41:00 PM PDT 24
Peak memory 261760 kb
Host smart-835d5005-7dea-4e6c-a5b0-a5d2a37b9a4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069318089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.2069318089
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3227695821
Short name T1134
Test name
Test status
Simulation time 2633039700 ps
CPU time 64.39 seconds
Started Aug 18 06:40:04 PM PDT 24
Finished Aug 18 06:41:08 PM PDT 24
Peak memory 261628 kb
Host smart-11785e45-2a98-4786-ab43-0249243f9dbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227695821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.3227695821
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3161611818
Short name T247
Test name
Test status
Simulation time 63775100 ps
CPU time 30.89 seconds
Started Aug 18 06:39:57 PM PDT 24
Finished Aug 18 06:40:28 PM PDT 24
Peak memory 261492 kb
Host smart-8433c375-60ad-458d-b59d-5f72e3068f3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161611818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.3161611818
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.824956517
Short name T1139
Test name
Test status
Simulation time 89036000 ps
CPU time 18.98 seconds
Started Aug 18 06:39:57 PM PDT 24
Finished Aug 18 06:40:16 PM PDT 24
Peak memory 272420 kb
Host smart-ecddcec3-c99b-4172-b5fd-592e9646b452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824956517 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.824956517
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3055064865
Short name T1164
Test name
Test status
Simulation time 414459200 ps
CPU time 15.15 seconds
Started Aug 18 06:40:06 PM PDT 24
Finished Aug 18 06:40:21 PM PDT 24
Peak memory 264028 kb
Host smart-fbfa0cfa-5ba7-4233-abf9-b47883b6a631
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055064865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.3055064865
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.220080961
Short name T1127
Test name
Test status
Simulation time 16403100 ps
CPU time 13.64 seconds
Started Aug 18 06:39:59 PM PDT 24
Finished Aug 18 06:40:13 PM PDT 24
Peak memory 261748 kb
Host smart-272c7fb0-465e-44a5-aff7-e7f62cd5950d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220080961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.220080961
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.933953733
Short name T230
Test name
Test status
Simulation time 18875000 ps
CPU time 13.63 seconds
Started Aug 18 06:39:58 PM PDT 24
Finished Aug 18 06:40:12 PM PDT 24
Peak memory 262656 kb
Host smart-0ed4bcd0-a636-4539-985b-4889fbe4b0f5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933953733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_mem_partial_access.933953733
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3942533078
Short name T1116
Test name
Test status
Simulation time 49492100 ps
CPU time 13.45 seconds
Started Aug 18 06:39:57 PM PDT 24
Finished Aug 18 06:40:10 PM PDT 24
Peak memory 261492 kb
Host smart-84e01afb-99c9-4268-b759-c7cad085579e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942533078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.3942533078
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.366092584
Short name T235
Test name
Test status
Simulation time 297674500 ps
CPU time 18.18 seconds
Started Aug 18 06:39:58 PM PDT 24
Finished Aug 18 06:40:16 PM PDT 24
Peak memory 261824 kb
Host smart-9afb8b0e-e363-49b7-8d7a-5c437fa9045e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366092584 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.366092584
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3032897369
Short name T1108
Test name
Test status
Simulation time 37080900 ps
CPU time 15.96 seconds
Started Aug 18 06:40:04 PM PDT 24
Finished Aug 18 06:40:20 PM PDT 24
Peak memory 253472 kb
Host smart-1df9ba7c-ff2d-477e-b1e8-a3d81ec016cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032897369 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.3032897369
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2895141110
Short name T1105
Test name
Test status
Simulation time 11504300 ps
CPU time 15.98 seconds
Started Aug 18 06:39:52 PM PDT 24
Finished Aug 18 06:40:08 PM PDT 24
Peak memory 253548 kb
Host smart-91317670-414a-435f-bb25-c5915752451b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895141110 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.2895141110
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2297408295
Short name T1157
Test name
Test status
Simulation time 68763600 ps
CPU time 16.51 seconds
Started Aug 18 06:39:54 PM PDT 24
Finished Aug 18 06:40:10 PM PDT 24
Peak memory 263552 kb
Host smart-3a1a3e94-d965-462e-a07d-8e413ea159bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297408295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.2
297408295
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3515839530
Short name T387
Test name
Test status
Simulation time 3197017300 ps
CPU time 956.95 seconds
Started Aug 18 06:40:08 PM PDT 24
Finished Aug 18 06:56:05 PM PDT 24
Peak memory 264232 kb
Host smart-2969d4db-d14a-4260-bbad-f8ab5343409c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515839530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.3515839530
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.827636248
Short name T1177
Test name
Test status
Simulation time 25552900 ps
CPU time 13.71 seconds
Started Aug 18 06:40:26 PM PDT 24
Finished Aug 18 06:40:40 PM PDT 24
Peak memory 261560 kb
Host smart-0c89b19a-fd64-45b4-a4d6-1e594d7541ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827636248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.827636248
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.4034233793
Short name T1199
Test name
Test status
Simulation time 17456300 ps
CPU time 13.42 seconds
Started Aug 18 06:40:15 PM PDT 24
Finished Aug 18 06:40:29 PM PDT 24
Peak memory 261656 kb
Host smart-922968c1-b118-4255-9bc0-3f219ae28e29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034233793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
4034233793
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.4283146583
Short name T338
Test name
Test status
Simulation time 52453100 ps
CPU time 13.73 seconds
Started Aug 18 06:40:32 PM PDT 24
Finished Aug 18 06:40:46 PM PDT 24
Peak memory 261668 kb
Host smart-3706de59-ab45-44e8-a8f9-eeeeb5145981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283146583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
4283146583
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4227975943
Short name T1186
Test name
Test status
Simulation time 67018700 ps
CPU time 13.51 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:26 PM PDT 24
Peak memory 261644 kb
Host smart-703fceb8-c06a-4b7c-8e66-e051075d04b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227975943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
4227975943
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2052208987
Short name T1114
Test name
Test status
Simulation time 53486200 ps
CPU time 13.33 seconds
Started Aug 18 06:40:22 PM PDT 24
Finished Aug 18 06:40:36 PM PDT 24
Peak memory 261528 kb
Host smart-e790c50f-74c7-43d5-a553-83372904c448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052208987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
2052208987
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1616485782
Short name T1161
Test name
Test status
Simulation time 24995300 ps
CPU time 13.38 seconds
Started Aug 18 06:40:16 PM PDT 24
Finished Aug 18 06:40:29 PM PDT 24
Peak memory 261736 kb
Host smart-8c52537e-96f3-4b63-949a-870503cc483e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616485782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
1616485782
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.233016215
Short name T333
Test name
Test status
Simulation time 17072900 ps
CPU time 13.71 seconds
Started Aug 18 06:40:45 PM PDT 24
Finished Aug 18 06:41:00 PM PDT 24
Peak memory 261744 kb
Host smart-0a9753e1-24ce-4f02-bd0e-424a1d937df3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233016215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.233016215
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1920724435
Short name T1112
Test name
Test status
Simulation time 25579100 ps
CPU time 13.73 seconds
Started Aug 18 06:40:21 PM PDT 24
Finished Aug 18 06:40:35 PM PDT 24
Peak memory 261680 kb
Host smart-dbf47498-044c-4cad-a768-1827fc48df3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920724435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
1920724435
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1760727144
Short name T1129
Test name
Test status
Simulation time 16797400 ps
CPU time 13.46 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:26 PM PDT 24
Peak memory 261564 kb
Host smart-06c5038b-8017-4f51-81b9-db0a4fcdfa1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760727144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
1760727144
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.285893142
Short name T1239
Test name
Test status
Simulation time 3594591100 ps
CPU time 62.34 seconds
Started Aug 18 06:40:07 PM PDT 24
Finished Aug 18 06:41:10 PM PDT 24
Peak memory 261784 kb
Host smart-d5461731-ca83-4f3e-8440-eddeb34c93c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285893142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_aliasing.285893142
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.599985156
Short name T1229
Test name
Test status
Simulation time 648189100 ps
CPU time 32.53 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:41 PM PDT 24
Peak memory 261784 kb
Host smart-bd3c87d0-164a-4c5a-bf93-56199dad3e5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599985156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_bit_bash.599985156
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1727845244
Short name T246
Test name
Test status
Simulation time 21303900 ps
CPU time 31.29 seconds
Started Aug 18 06:40:11 PM PDT 24
Finished Aug 18 06:40:42 PM PDT 24
Peak memory 261576 kb
Host smart-e9b713d5-6737-4ead-9cff-576d80924554
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727845244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.1727845244
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2684930929
Short name T1174
Test name
Test status
Simulation time 96069100 ps
CPU time 17.31 seconds
Started Aug 18 06:40:08 PM PDT 24
Finished Aug 18 06:40:25 PM PDT 24
Peak memory 272448 kb
Host smart-c06c68e2-d8f1-4054-bab3-d3122490d7f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684930929 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.2684930929
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3870465459
Short name T1187
Test name
Test status
Simulation time 85603700 ps
CPU time 16.81 seconds
Started Aug 18 06:40:08 PM PDT 24
Finished Aug 18 06:40:25 PM PDT 24
Peak memory 264104 kb
Host smart-ff312bf3-c5cf-4090-b955-a40e2ac2a61a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870465459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.3870465459
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2754671859
Short name T1237
Test name
Test status
Simulation time 30130900 ps
CPU time 13.48 seconds
Started Aug 18 06:40:04 PM PDT 24
Finished Aug 18 06:40:18 PM PDT 24
Peak memory 261528 kb
Host smart-35e739c5-1a23-4d44-a181-49ab919c04a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754671859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.2
754671859
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1838972950
Short name T232
Test name
Test status
Simulation time 60441200 ps
CPU time 13.55 seconds
Started Aug 18 06:40:05 PM PDT 24
Finished Aug 18 06:40:19 PM PDT 24
Peak memory 262492 kb
Host smart-91d93407-40e5-4145-9971-c3b393fa26ca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838972950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.1838972950
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1474138896
Short name T1152
Test name
Test status
Simulation time 28768200 ps
CPU time 13.4 seconds
Started Aug 18 06:40:01 PM PDT 24
Finished Aug 18 06:40:15 PM PDT 24
Peak memory 261456 kb
Host smart-73dc3f49-47ed-487d-b25f-a57637a5759f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474138896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.1474138896
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2361124571
Short name T1119
Test name
Test status
Simulation time 1179926700 ps
CPU time 35.63 seconds
Started Aug 18 06:40:02 PM PDT 24
Finished Aug 18 06:40:38 PM PDT 24
Peak memory 261732 kb
Host smart-9490eda4-5f9c-4b37-90da-7fb82b3fc088
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361124571 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.2361124571
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1817090401
Short name T1138
Test name
Test status
Simulation time 26059500 ps
CPU time 15.52 seconds
Started Aug 18 06:39:55 PM PDT 24
Finished Aug 18 06:40:11 PM PDT 24
Peak memory 253448 kb
Host smart-b1556d86-f33a-4860-ba84-94c77e6fedce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817090401 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.1817090401
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.680039009
Short name T1218
Test name
Test status
Simulation time 30829100 ps
CPU time 16.07 seconds
Started Aug 18 06:39:53 PM PDT 24
Finished Aug 18 06:40:09 PM PDT 24
Peak memory 253452 kb
Host smart-f4ea7476-9abb-40f8-8031-2b03fe93c4cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680039009 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.680039009
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1451106407
Short name T223
Test name
Test status
Simulation time 44079100 ps
CPU time 16.32 seconds
Started Aug 18 06:40:03 PM PDT 24
Finished Aug 18 06:40:19 PM PDT 24
Peak memory 264240 kb
Host smart-736072be-0164-4192-968a-d593767864f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451106407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1
451106407
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2014692414
Short name T386
Test name
Test status
Simulation time 374890400 ps
CPU time 820.38 seconds
Started Aug 18 06:40:01 PM PDT 24
Finished Aug 18 06:53:42 PM PDT 24
Peak memory 264056 kb
Host smart-2ec954a2-30ce-4335-a0da-efa2ae660afc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014692414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.2014692414
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2826759005
Short name T1120
Test name
Test status
Simulation time 27064900 ps
CPU time 13.31 seconds
Started Aug 18 06:40:31 PM PDT 24
Finished Aug 18 06:40:44 PM PDT 24
Peak memory 261732 kb
Host smart-a165f9e9-c665-436c-ae63-1d107f53a45c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826759005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
2826759005
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.281134557
Short name T1140
Test name
Test status
Simulation time 49400100 ps
CPU time 13.54 seconds
Started Aug 18 06:40:17 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 261692 kb
Host smart-09f48566-40d4-4ef5-89ae-81b25191e05f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281134557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.281134557
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3353813678
Short name T1217
Test name
Test status
Simulation time 46000000 ps
CPU time 13.42 seconds
Started Aug 18 06:40:15 PM PDT 24
Finished Aug 18 06:40:34 PM PDT 24
Peak memory 261536 kb
Host smart-8a060209-6f31-4381-9c89-56f90ade3403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353813678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
3353813678
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3973887128
Short name T1225
Test name
Test status
Simulation time 27610100 ps
CPU time 13.31 seconds
Started Aug 18 06:40:37 PM PDT 24
Finished Aug 18 06:40:50 PM PDT 24
Peak memory 261544 kb
Host smart-18eb39da-e950-4c31-8597-b316f9f869e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973887128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
3973887128
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2279884056
Short name T1155
Test name
Test status
Simulation time 50282600 ps
CPU time 13.44 seconds
Started Aug 18 06:40:20 PM PDT 24
Finished Aug 18 06:40:34 PM PDT 24
Peak memory 261740 kb
Host smart-db65da46-fe24-44c7-9974-3b1bf508d595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279884056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
2279884056
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1514600369
Short name T1206
Test name
Test status
Simulation time 29381600 ps
CPU time 13.68 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:26 PM PDT 24
Peak memory 261680 kb
Host smart-b1ce9dee-87fc-4794-a79e-0c4ba8a5c14e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514600369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
1514600369
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3133112179
Short name T1224
Test name
Test status
Simulation time 23053600 ps
CPU time 13.88 seconds
Started Aug 18 06:40:16 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 261744 kb
Host smart-e1c535cc-87ca-436e-88b2-5fb24610e747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133112179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
3133112179
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.614823109
Short name T1168
Test name
Test status
Simulation time 22930400 ps
CPU time 13.57 seconds
Started Aug 18 06:40:23 PM PDT 24
Finished Aug 18 06:40:36 PM PDT 24
Peak memory 261632 kb
Host smart-57289667-f9ca-425e-ab25-98632cf18a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614823109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.614823109
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1765299806
Short name T339
Test name
Test status
Simulation time 66512400 ps
CPU time 13.8 seconds
Started Aug 18 06:40:27 PM PDT 24
Finished Aug 18 06:40:41 PM PDT 24
Peak memory 261604 kb
Host smart-9a9d8c1f-0687-4b72-a611-a4634b1bbeed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765299806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
1765299806
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1870980452
Short name T341
Test name
Test status
Simulation time 26118700 ps
CPU time 13.54 seconds
Started Aug 18 06:40:35 PM PDT 24
Finished Aug 18 06:40:48 PM PDT 24
Peak memory 261708 kb
Host smart-bdf2a6c9-4552-4d79-b832-da1469223d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870980452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
1870980452
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1192438223
Short name T1195
Test name
Test status
Simulation time 3421445400 ps
CPU time 42.64 seconds
Started Aug 18 06:40:05 PM PDT 24
Finished Aug 18 06:40:47 PM PDT 24
Peak memory 261728 kb
Host smart-20af1800-7935-44c9-bdd7-d3f788964542
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192438223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.1192438223
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.264033509
Short name T1193
Test name
Test status
Simulation time 1276729100 ps
CPU time 37.84 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:51 PM PDT 24
Peak memory 261680 kb
Host smart-a2aadce6-3ba3-4763-bc67-dd8ae33e8f50
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264033509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_bit_bash.264033509
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.408594729
Short name T286
Test name
Test status
Simulation time 101904300 ps
CPU time 38.3 seconds
Started Aug 18 06:40:03 PM PDT 24
Finished Aug 18 06:40:41 PM PDT 24
Peak memory 263764 kb
Host smart-00fcdb81-3ed3-4517-87e8-55e166113f59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408594729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_hw_reset.408594729
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.296945934
Short name T238
Test name
Test status
Simulation time 47245800 ps
CPU time 14.5 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:24 PM PDT 24
Peak memory 264084 kb
Host smart-b7a40d36-a1a6-43aa-bdc1-d6631b40555a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296945934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_csr_rw.296945934
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.690347913
Short name T1163
Test name
Test status
Simulation time 15364000 ps
CPU time 13.52 seconds
Started Aug 18 06:40:10 PM PDT 24
Finished Aug 18 06:40:24 PM PDT 24
Peak memory 261688 kb
Host smart-8d3d9c15-c8c1-448a-bd06-b635704d86bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690347913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.690347913
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2353104683
Short name T1178
Test name
Test status
Simulation time 44927100 ps
CPU time 13.69 seconds
Started Aug 18 06:40:05 PM PDT 24
Finished Aug 18 06:40:18 PM PDT 24
Peak memory 262500 kb
Host smart-f4d1171f-265c-44ed-91f8-ce39d847582d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353104683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.2353104683
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2534564606
Short name T1118
Test name
Test status
Simulation time 15055800 ps
CPU time 13.57 seconds
Started Aug 18 06:40:11 PM PDT 24
Finished Aug 18 06:40:25 PM PDT 24
Peak memory 261456 kb
Host smart-6c395096-3fa7-48e2-8bf4-f890e609c7b3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534564606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.2534564606
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1303701806
Short name T1121
Test name
Test status
Simulation time 51625600 ps
CPU time 17.82 seconds
Started Aug 18 06:40:12 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 261624 kb
Host smart-1524ea81-8d57-4fee-b1d0-f37eaa20da3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303701806 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.1303701806
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.435410805
Short name T1223
Test name
Test status
Simulation time 32342500 ps
CPU time 13.9 seconds
Started Aug 18 06:40:03 PM PDT 24
Finished Aug 18 06:40:17 PM PDT 24
Peak memory 253472 kb
Host smart-e5ba9a73-6874-4471-8302-53de87fedb23
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435410805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.435410805
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1121277013
Short name T1219
Test name
Test status
Simulation time 40029600 ps
CPU time 13.27 seconds
Started Aug 18 06:40:12 PM PDT 24
Finished Aug 18 06:40:25 PM PDT 24
Peak memory 253540 kb
Host smart-5c92464c-6fa2-4cf5-8d5f-a2debcebd298
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121277013 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.1121277013
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1030848437
Short name T1221
Test name
Test status
Simulation time 476215800 ps
CPU time 21.12 seconds
Started Aug 18 06:40:02 PM PDT 24
Finished Aug 18 06:40:23 PM PDT 24
Peak memory 264228 kb
Host smart-034eb00d-de49-4361-b363-f572ed5a559d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030848437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.1
030848437
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.901701160
Short name T340
Test name
Test status
Simulation time 96277200 ps
CPU time 13.54 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:26 PM PDT 24
Peak memory 261580 kb
Host smart-cdbfd593-bac5-48a1-acfd-425893d3a6c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901701160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.901701160
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3646933703
Short name T1153
Test name
Test status
Simulation time 49294900 ps
CPU time 13.45 seconds
Started Aug 18 06:40:32 PM PDT 24
Finished Aug 18 06:40:46 PM PDT 24
Peak memory 261624 kb
Host smart-1da8cca8-5c69-4b37-b86e-59ada26936a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646933703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
3646933703
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2549435912
Short name T1230
Test name
Test status
Simulation time 217708700 ps
CPU time 13.68 seconds
Started Aug 18 06:40:32 PM PDT 24
Finished Aug 18 06:40:45 PM PDT 24
Peak memory 261736 kb
Host smart-d6d348bb-3d21-47f8-bb4a-54c1d41559ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549435912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
2549435912
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4129863188
Short name T1117
Test name
Test status
Simulation time 58421400 ps
CPU time 13.42 seconds
Started Aug 18 06:40:14 PM PDT 24
Finished Aug 18 06:40:27 PM PDT 24
Peak memory 261676 kb
Host smart-adb665ac-49f2-470c-8a1c-dbeb78a3553c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129863188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
4129863188
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2372606720
Short name T1109
Test name
Test status
Simulation time 28644300 ps
CPU time 13.27 seconds
Started Aug 18 06:40:14 PM PDT 24
Finished Aug 18 06:40:28 PM PDT 24
Peak memory 261620 kb
Host smart-d7532f79-6a10-4e51-bed7-265f37267994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372606720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
2372606720
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.4272919940
Short name T1166
Test name
Test status
Simulation time 24511300 ps
CPU time 13.42 seconds
Started Aug 18 06:40:21 PM PDT 24
Finished Aug 18 06:40:34 PM PDT 24
Peak memory 261604 kb
Host smart-758119ac-4c6c-47b3-b86e-2d991bb05934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272919940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
4272919940
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3194981435
Short name T334
Test name
Test status
Simulation time 34577300 ps
CPU time 13.59 seconds
Started Aug 18 06:40:18 PM PDT 24
Finished Aug 18 06:40:32 PM PDT 24
Peak memory 261708 kb
Host smart-40881285-9087-4b15-b479-9d352aaae668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194981435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
3194981435
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.143069885
Short name T1190
Test name
Test status
Simulation time 33618800 ps
CPU time 13.52 seconds
Started Aug 18 06:40:32 PM PDT 24
Finished Aug 18 06:40:46 PM PDT 24
Peak memory 261632 kb
Host smart-52c0e5e3-a5c6-4435-80c6-605c89dc88bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143069885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.143069885
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3675084842
Short name T1243
Test name
Test status
Simulation time 52901800 ps
CPU time 13.46 seconds
Started Aug 18 06:40:27 PM PDT 24
Finished Aug 18 06:40:41 PM PDT 24
Peak memory 261556 kb
Host smart-8bfbfa00-d8aa-432d-aad7-df3e5856ecaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675084842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
3675084842
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4126300082
Short name T1170
Test name
Test status
Simulation time 299734800 ps
CPU time 19.67 seconds
Started Aug 18 06:40:02 PM PDT 24
Finished Aug 18 06:40:22 PM PDT 24
Peak memory 272456 kb
Host smart-846762ba-e875-41b7-8821-c2ed4b17e002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126300082 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.4126300082
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.405263847
Short name T1162
Test name
Test status
Simulation time 49788300 ps
CPU time 14.63 seconds
Started Aug 18 06:40:02 PM PDT 24
Finished Aug 18 06:40:17 PM PDT 24
Peak memory 261580 kb
Host smart-e668f8ba-6197-4930-b8bf-4b3467b77b9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405263847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_csr_rw.405263847
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4086402468
Short name T1180
Test name
Test status
Simulation time 16752000 ps
CPU time 13.44 seconds
Started Aug 18 06:40:03 PM PDT 24
Finished Aug 18 06:40:17 PM PDT 24
Peak memory 261728 kb
Host smart-7a159ce0-bb34-4017-a3d8-7716e5cb2db6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086402468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.4
086402468
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1381766711
Short name T1124
Test name
Test status
Simulation time 121445700 ps
CPU time 17.5 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 263040 kb
Host smart-48bd84a8-fda9-4a4d-b562-35c430bd76a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381766711 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.1381766711
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3591742264
Short name T1145
Test name
Test status
Simulation time 11351500 ps
CPU time 15.85 seconds
Started Aug 18 06:40:01 PM PDT 24
Finished Aug 18 06:40:17 PM PDT 24
Peak memory 253412 kb
Host smart-cfdeef01-72ed-42a6-8871-cf270eb28fad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591742264 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.3591742264
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2463603781
Short name T1182
Test name
Test status
Simulation time 71508600 ps
CPU time 13.14 seconds
Started Aug 18 06:40:12 PM PDT 24
Finished Aug 18 06:40:26 PM PDT 24
Peak memory 253372 kb
Host smart-187c8f35-32da-49bd-b8e1-3a1bed9e7ec9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463603781 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.2463603781
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3340808707
Short name T1203
Test name
Test status
Simulation time 137501500 ps
CPU time 17.92 seconds
Started Aug 18 06:40:08 PM PDT 24
Finished Aug 18 06:40:26 PM PDT 24
Peak memory 264288 kb
Host smart-28ebcf16-4fbd-4e11-b7f6-e214ecfad3bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340808707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.3
340808707
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3288206382
Short name T384
Test name
Test status
Simulation time 3557102300 ps
CPU time 985.87 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:56:35 PM PDT 24
Peak memory 264168 kb
Host smart-90e3b415-2260-438d-a9a0-62b15469221e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288206382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.3288206382
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2573848982
Short name T1222
Test name
Test status
Simulation time 149113000 ps
CPU time 18.27 seconds
Started Aug 18 06:40:04 PM PDT 24
Finished Aug 18 06:40:23 PM PDT 24
Peak memory 272128 kb
Host smart-f50d56af-5978-457d-b3d7-3a6d9c21bc3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573848982 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.2573848982
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.907224648
Short name T1148
Test name
Test status
Simulation time 76236700 ps
CPU time 17.42 seconds
Started Aug 18 06:40:12 PM PDT 24
Finished Aug 18 06:40:29 PM PDT 24
Peak memory 264116 kb
Host smart-5d46c457-d5ea-4e4c-abf2-eaffd428e535
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907224648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_csr_rw.907224648
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2277274599
Short name T1158
Test name
Test status
Simulation time 50641000 ps
CPU time 13.58 seconds
Started Aug 18 06:40:11 PM PDT 24
Finished Aug 18 06:40:24 PM PDT 24
Peak memory 260760 kb
Host smart-cd6fa028-d068-4a2d-a9df-f09881dd29ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277274599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.2
277274599
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1351061072
Short name T1149
Test name
Test status
Simulation time 360628600 ps
CPU time 16.01 seconds
Started Aug 18 06:40:06 PM PDT 24
Finished Aug 18 06:40:22 PM PDT 24
Peak memory 263464 kb
Host smart-bdca3bb3-2308-42d4-830c-613947f5a0a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351061072 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.1351061072
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.85358372
Short name T1111
Test name
Test status
Simulation time 14742900 ps
CPU time 15.45 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:25 PM PDT 24
Peak memory 253448 kb
Host smart-4d409f64-c96f-4b61-9d73-20cdb9f7f18f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85358372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.85358372
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.34490780
Short name T1216
Test name
Test status
Simulation time 99996100 ps
CPU time 15.84 seconds
Started Aug 18 06:40:03 PM PDT 24
Finished Aug 18 06:40:19 PM PDT 24
Peak memory 253484 kb
Host smart-3c6a659b-554a-415e-a638-467c0aba6b67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34490780 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.34490780
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3723700794
Short name T1244
Test name
Test status
Simulation time 168776500 ps
CPU time 17.39 seconds
Started Aug 18 06:40:02 PM PDT 24
Finished Aug 18 06:40:19 PM PDT 24
Peak memory 264208 kb
Host smart-5cbaf0c0-e200-4b51-bdcb-0ad66d35268f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723700794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.3
723700794
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1694920217
Short name T381
Test name
Test status
Simulation time 832017400 ps
CPU time 477.27 seconds
Started Aug 18 06:40:08 PM PDT 24
Finished Aug 18 06:48:06 PM PDT 24
Peak memory 264176 kb
Host smart-f1eef26b-d88b-4185-876e-52a5b7347054
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694920217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.1694920217
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.977258793
Short name T227
Test name
Test status
Simulation time 110830500 ps
CPU time 18.02 seconds
Started Aug 18 06:40:10 PM PDT 24
Finished Aug 18 06:40:28 PM PDT 24
Peak memory 275392 kb
Host smart-e5ef6256-4fb7-46aa-878f-24af091fea2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977258793 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.977258793
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.112023857
Short name T65
Test name
Test status
Simulation time 88002000 ps
CPU time 17.16 seconds
Started Aug 18 06:40:04 PM PDT 24
Finished Aug 18 06:40:23 PM PDT 24
Peak memory 261696 kb
Host smart-5738ca7f-a56e-49a9-b281-1caa5286c427
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112023857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_csr_rw.112023857
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2251228354
Short name T1241
Test name
Test status
Simulation time 16603500 ps
CPU time 13.75 seconds
Started Aug 18 06:40:02 PM PDT 24
Finished Aug 18 06:40:16 PM PDT 24
Peak memory 261732 kb
Host smart-b4f56408-6c0e-4bbf-95e4-5b84ce071770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251228354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.2
251228354
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1840701970
Short name T1191
Test name
Test status
Simulation time 211935100 ps
CPU time 18.08 seconds
Started Aug 18 06:40:10 PM PDT 24
Finished Aug 18 06:40:28 PM PDT 24
Peak memory 260820 kb
Host smart-2eeedc4b-5f1d-44a7-a042-a0f60913f934
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840701970 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.1840701970
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.491064220
Short name T1192
Test name
Test status
Simulation time 47107100 ps
CPU time 16.31 seconds
Started Aug 18 06:39:59 PM PDT 24
Finished Aug 18 06:40:15 PM PDT 24
Peak memory 253436 kb
Host smart-ae9792d1-bebd-4173-8ee5-b174d263ed5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491064220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.491064220
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.111333891
Short name T1189
Test name
Test status
Simulation time 13318700 ps
CPU time 15.95 seconds
Started Aug 18 06:40:03 PM PDT 24
Finished Aug 18 06:40:19 PM PDT 24
Peak memory 253416 kb
Host smart-b4afcf5f-ce12-44ed-824f-404097fbacbd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111333891 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.111333891
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1389770250
Short name T243
Test name
Test status
Simulation time 426447200 ps
CPU time 474.3 seconds
Started Aug 18 06:40:17 PM PDT 24
Finished Aug 18 06:48:11 PM PDT 24
Peak memory 264152 kb
Host smart-2b18e8c0-ea66-4197-abba-a0e9b75f5e04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389770250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.1389770250
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.399549337
Short name T1196
Test name
Test status
Simulation time 130456700 ps
CPU time 19.9 seconds
Started Aug 18 06:40:10 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 279712 kb
Host smart-5e222eb5-0cee-4ba0-82c6-b674921a1830
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399549337 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.399549337
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2241478089
Short name T1131
Test name
Test status
Simulation time 33547900 ps
CPU time 16.87 seconds
Started Aug 18 06:40:01 PM PDT 24
Finished Aug 18 06:40:18 PM PDT 24
Peak memory 264084 kb
Host smart-c5ec421e-980c-4e9f-ab07-ae2b48f3cb31
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241478089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.2241478089
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.483470064
Short name T1128
Test name
Test status
Simulation time 15966100 ps
CPU time 13.69 seconds
Started Aug 18 06:40:10 PM PDT 24
Finished Aug 18 06:40:23 PM PDT 24
Peak memory 261748 kb
Host smart-f869c902-4f51-4b98-8181-2d5b3f975670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483470064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.483470064
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1921980833
Short name T1214
Test name
Test status
Simulation time 38909400 ps
CPU time 16.31 seconds
Started Aug 18 06:40:13 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 253500 kb
Host smart-503fae21-ed12-40a4-9a91-791389215c57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921980833 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.1921980833
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.758944283
Short name T1135
Test name
Test status
Simulation time 31378300 ps
CPU time 15.51 seconds
Started Aug 18 06:40:04 PM PDT 24
Finished Aug 18 06:40:19 PM PDT 24
Peak memory 253500 kb
Host smart-97f5c37b-c51d-45f8-bb7f-9957a1407a52
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758944283 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.758944283
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.772781943
Short name T380
Test name
Test status
Simulation time 213762700 ps
CPU time 19.74 seconds
Started Aug 18 06:40:05 PM PDT 24
Finished Aug 18 06:40:25 PM PDT 24
Peak memory 264248 kb
Host smart-8ac8c2f7-fac4-499e-9c9b-551fe7209895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772781943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.772781943
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3942914999
Short name T284
Test name
Test status
Simulation time 1725240000 ps
CPU time 478.45 seconds
Started Aug 18 06:40:02 PM PDT 24
Finished Aug 18 06:48:01 PM PDT 24
Peak memory 264172 kb
Host smart-3c0c15ad-3c54-428d-826c-1154051632c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942914999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.3942914999
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3768963098
Short name T287
Test name
Test status
Simulation time 195006800 ps
CPU time 18.99 seconds
Started Aug 18 06:40:10 PM PDT 24
Finished Aug 18 06:40:29 PM PDT 24
Peak memory 270988 kb
Host smart-d9bd642d-9343-445d-978a-58640f8754a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768963098 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.3768963098
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.66279909
Short name T1235
Test name
Test status
Simulation time 275114600 ps
CPU time 16.92 seconds
Started Aug 18 06:40:08 PM PDT 24
Finished Aug 18 06:40:25 PM PDT 24
Peak memory 264060 kb
Host smart-ce43cf91-fe82-4d59-853e-5113fab50dcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66279909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 9.flash_ctrl_csr_rw.66279909
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.293455687
Short name T1113
Test name
Test status
Simulation time 15040100 ps
CPU time 13.39 seconds
Started Aug 18 06:40:12 PM PDT 24
Finished Aug 18 06:40:26 PM PDT 24
Peak memory 261736 kb
Host smart-fbfd5ac6-57bd-4039-9925-568a4f5d0c09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293455687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.293455687
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2225366818
Short name T236
Test name
Test status
Simulation time 2483720500 ps
CPU time 20.85 seconds
Started Aug 18 06:40:09 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 261800 kb
Host smart-47801f04-3522-43e9-9600-7602f6497ff2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225366818 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.2225366818
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1449505315
Short name T1110
Test name
Test status
Simulation time 99944800 ps
CPU time 15.61 seconds
Started Aug 18 06:40:02 PM PDT 24
Finished Aug 18 06:40:18 PM PDT 24
Peak memory 253448 kb
Host smart-ea51fbf5-ffdb-4dce-833c-9080a0e882a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449505315 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.1449505315
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1437442548
Short name T1143
Test name
Test status
Simulation time 15386700 ps
CPU time 15.8 seconds
Started Aug 18 06:40:04 PM PDT 24
Finished Aug 18 06:40:20 PM PDT 24
Peak memory 253312 kb
Host smart-ad5b3e95-0c73-4ba9-90a7-367292cf89c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437442548 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.1437442548
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.111166037
Short name T1212
Test name
Test status
Simulation time 189085900 ps
CPU time 18.5 seconds
Started Aug 18 06:40:12 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 264292 kb
Host smart-8cad80a7-fdec-4244-8f00-d691ca753525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111166037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.111166037
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.959783485
Short name T385
Test name
Test status
Simulation time 1613478700 ps
CPU time 478.42 seconds
Started Aug 18 06:40:02 PM PDT 24
Finished Aug 18 06:48:01 PM PDT 24
Peak memory 261588 kb
Host smart-77c5be79-b024-4544-96eb-62a6e141fbc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959783485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_
tl_intg_err.959783485
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.810910932
Short name T543
Test name
Test status
Simulation time 214140200 ps
CPU time 13.51 seconds
Started Aug 18 06:03:39 PM PDT 24
Finished Aug 18 06:03:53 PM PDT 24
Peak memory 258828 kb
Host smart-0fdbcff1-9298-48d0-a443-a024d5c2e69b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810910932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.810910932
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.3681017640
Short name T1061
Test name
Test status
Simulation time 22216700 ps
CPU time 13.65 seconds
Started Aug 18 06:03:37 PM PDT 24
Finished Aug 18 06:03:51 PM PDT 24
Peak memory 265372 kb
Host smart-df932c8e-088a-4257-8257-dc434522cccb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681017640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.3681017640
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.1963077657
Short name T644
Test name
Test status
Simulation time 76800400 ps
CPU time 13.61 seconds
Started Aug 18 06:03:36 PM PDT 24
Finished Aug 18 06:03:50 PM PDT 24
Peak memory 283540 kb
Host smart-0905f20f-b2f4-4b9c-8dda-5cf0fd2781b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963077657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.1963077657
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.1463076486
Short name T1064
Test name
Test status
Simulation time 759095000 ps
CPU time 201.5 seconds
Started Aug 18 06:03:32 PM PDT 24
Finished Aug 18 06:06:54 PM PDT 24
Peak memory 277832 kb
Host smart-ea758452-8ca3-4486-a50f-4bf7f6b7d03f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463076486 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_derr_detect.1463076486
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.2414283556
Short name T154
Test name
Test status
Simulation time 5571118900 ps
CPU time 371.68 seconds
Started Aug 18 06:03:20 PM PDT 24
Finished Aug 18 06:09:32 PM PDT 24
Peak memory 263840 kb
Host smart-411cfc5e-4b2c-4d93-9fe4-1bc458d3e5a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414283556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.2414283556
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.898382990
Short name T841
Test name
Test status
Simulation time 19422425900 ps
CPU time 2223.09 seconds
Started Aug 18 06:03:26 PM PDT 24
Finished Aug 18 06:40:30 PM PDT 24
Peak memory 265360 kb
Host smart-135ead56-713c-457b-82ef-73fcc083cb3d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=898382990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.898382990
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.128797402
Short name T614
Test name
Test status
Simulation time 130366400 ps
CPU time 22.04 seconds
Started Aug 18 06:03:20 PM PDT 24
Finished Aug 18 06:03:42 PM PDT 24
Peak memory 263980 kb
Host smart-bbb6e9ed-bcd0-47a8-bdaf-b9405008786a
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128797402 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_fetch_code.128797402
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.1363901681
Short name T1032
Test name
Test status
Simulation time 876027900 ps
CPU time 37.52 seconds
Started Aug 18 06:03:38 PM PDT 24
Finished Aug 18 06:04:15 PM PDT 24
Peak memory 265884 kb
Host smart-d37a43ac-d500-402e-81a0-23a497011591
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363901681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.1363901681
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.2553842984
Short name T60
Test name
Test status
Simulation time 173627374600 ps
CPU time 2730.57 seconds
Started Aug 18 06:03:30 PM PDT 24
Finished Aug 18 06:49:00 PM PDT 24
Peak memory 263116 kb
Host smart-868fad62-2751-496a-800d-be92c8f50431
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553842984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.2553842984
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_addr_infection.1589561978
Short name T1095
Test name
Test status
Simulation time 40167400 ps
CPU time 27.66 seconds
Started Aug 18 06:03:34 PM PDT 24
Finished Aug 18 06:04:02 PM PDT 24
Peak memory 274104 kb
Host smart-36ea98bb-39e3-4d18-8815-fda46d5be8a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589561978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_host_addr_infection.1589561978
Directory /workspace/0.flash_ctrl_host_addr_infection/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.3980467441
Short name T487
Test name
Test status
Simulation time 44702900 ps
CPU time 35.07 seconds
Started Aug 18 06:03:20 PM PDT 24
Finished Aug 18 06:03:55 PM PDT 24
Peak memory 263112 kb
Host smart-02541006-aa15-4687-a31b-97f86948b47f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980467441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.3980467441
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3683112935
Short name T733
Test name
Test status
Simulation time 10032231200 ps
CPU time 55.15 seconds
Started Aug 18 06:03:37 PM PDT 24
Finished Aug 18 06:04:33 PM PDT 24
Peak memory 272548 kb
Host smart-07662951-edfc-4d82-8a86-fc4c0d917848
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683112935 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.3683112935
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.3942667053
Short name T974
Test name
Test status
Simulation time 169353260500 ps
CPU time 2000.21 seconds
Started Aug 18 06:03:18 PM PDT 24
Finished Aug 18 06:36:39 PM PDT 24
Peak memory 265060 kb
Host smart-fba4e586-5066-4d43-9698-bc5f86d71b8a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942667053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.3942667053
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.2351373566
Short name T1072
Test name
Test status
Simulation time 170183667600 ps
CPU time 849.77 seconds
Started Aug 18 06:03:21 PM PDT 24
Finished Aug 18 06:17:31 PM PDT 24
Peak memory 264472 kb
Host smart-a908e89b-678c-420d-a0ca-e0a0ab463a36
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351373566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.2351373566
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.404533979
Short name T1016
Test name
Test status
Simulation time 6015296800 ps
CPU time 120.09 seconds
Started Aug 18 06:03:17 PM PDT 24
Finished Aug 18 06:05:17 PM PDT 24
Peak memory 263644 kb
Host smart-36bacc98-f592-4cfb-8834-af229672365f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404533979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw
_sec_otp.404533979
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.2982137679
Short name T637
Test name
Test status
Simulation time 9687779900 ps
CPU time 717.81 seconds
Started Aug 18 06:03:28 PM PDT 24
Finished Aug 18 06:15:26 PM PDT 24
Peak memory 343632 kb
Host smart-cf2a4874-ff9e-4d3c-b0fe-a53077a40b3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982137679 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_integrity.2982137679
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.1889352685
Short name T699
Test name
Test status
Simulation time 94383885800 ps
CPU time 288.21 seconds
Started Aug 18 06:03:34 PM PDT 24
Finished Aug 18 06:08:22 PM PDT 24
Peak memory 285736 kb
Host smart-fde55904-949e-4693-831b-826135e3c408
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889352685 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.1889352685
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.274127090
Short name T801
Test name
Test status
Simulation time 10292173800 ps
CPU time 72.94 seconds
Started Aug 18 06:03:37 PM PDT 24
Finished Aug 18 06:04:51 PM PDT 24
Peak memory 265712 kb
Host smart-93912e2f-ca84-49d8-ab7a-b10cd64fceb1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274127090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_intr_wr.274127090
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.3122452329
Short name T431
Test name
Test status
Simulation time 3859579900 ps
CPU time 85.55 seconds
Started Aug 18 06:03:31 PM PDT 24
Finished Aug 18 06:04:57 PM PDT 24
Peak memory 263940 kb
Host smart-067dd15c-991e-4459-8d09-702b2d1b8bf3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122452329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.3122452329
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.1001223044
Short name T910
Test name
Test status
Simulation time 15635100 ps
CPU time 13.28 seconds
Started Aug 18 06:03:38 PM PDT 24
Finished Aug 18 06:03:51 PM PDT 24
Peak memory 265320 kb
Host smart-e7ae1643-8a07-4d15-a371-d2b410ffd6fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001223044 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.1001223044
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.3259433822
Short name T80
Test name
Test status
Simulation time 1344898100 ps
CPU time 69.61 seconds
Started Aug 18 06:03:28 PM PDT 24
Finished Aug 18 06:04:38 PM PDT 24
Peak memory 261148 kb
Host smart-4bec6789-fbbe-4de4-960f-ad4692906b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259433822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.3259433822
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.2811816422
Short name T567
Test name
Test status
Simulation time 14144667500 ps
CPU time 134.35 seconds
Started Aug 18 06:03:19 PM PDT 24
Finished Aug 18 06:05:33 PM PDT 24
Peak memory 265784 kb
Host smart-ea7616ea-41c0-41e1-af97-5020286c292c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811816422 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.2811816422
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.3383373389
Short name T986
Test name
Test status
Simulation time 76137000 ps
CPU time 131.19 seconds
Started Aug 18 06:03:21 PM PDT 24
Finished Aug 18 06:05:32 PM PDT 24
Peak memory 260632 kb
Host smart-4a1b2cad-b356-4af0-b0bc-33b89f0098ec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383373389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.3383373389
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.887593322
Short name T488
Test name
Test status
Simulation time 1728891900 ps
CPU time 367.58 seconds
Started Aug 18 06:03:22 PM PDT 24
Finished Aug 18 06:09:29 PM PDT 24
Peak memory 263760 kb
Host smart-7c496611-90fd-492c-8d9a-468eeac0d39f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887593322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.887593322
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.4065426405
Short name T150
Test name
Test status
Simulation time 876243600 ps
CPU time 16.46 seconds
Started Aug 18 06:03:38 PM PDT 24
Finished Aug 18 06:03:54 PM PDT 24
Peak memory 266144 kb
Host smart-8c57d39f-a5a4-4555-bb6f-e107381e5f4c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065426405 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.4065426405
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.1179216198
Short name T5
Test name
Test status
Simulation time 43618200 ps
CPU time 14.1 seconds
Started Aug 18 06:03:38 PM PDT 24
Finished Aug 18 06:03:52 PM PDT 24
Peak memory 262856 kb
Host smart-f9b54e0b-f3bd-4ea2-b1d4-f6a6f384d700
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179216198 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.1179216198
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.2720103992
Short name T620
Test name
Test status
Simulation time 61537600 ps
CPU time 13.51 seconds
Started Aug 18 06:03:39 PM PDT 24
Finished Aug 18 06:03:53 PM PDT 24
Peak memory 259608 kb
Host smart-363677d5-d780-4a80-87fc-0012c324c5dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720103992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.flash_ctrl_prog_reset.2720103992
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.509660903
Short name T44
Test name
Test status
Simulation time 8677399800 ps
CPU time 616.05 seconds
Started Aug 18 06:03:20 PM PDT 24
Finished Aug 18 06:13:37 PM PDT 24
Peak memory 286908 kb
Host smart-9b8d943f-45a1-4b79-8323-a2952e949dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509660903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.509660903
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.3299072665
Short name T22
Test name
Test status
Simulation time 5727707900 ps
CPU time 138.58 seconds
Started Aug 18 06:03:20 PM PDT 24
Finished Aug 18 06:05:38 PM PDT 24
Peak memory 263144 kb
Host smart-923a901b-7894-42d7-8615-06ee42cbe044
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3299072665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.3299072665
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.1334332851
Short name T610
Test name
Test status
Simulation time 64156700 ps
CPU time 31.93 seconds
Started Aug 18 06:03:37 PM PDT 24
Finished Aug 18 06:04:09 PM PDT 24
Peak memory 276208 kb
Host smart-d982c257-4629-44eb-95fe-893afe6f0693
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334332851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.1334332851
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.572658548
Short name T717
Test name
Test status
Simulation time 181353100 ps
CPU time 44.96 seconds
Started Aug 18 06:03:37 PM PDT 24
Finished Aug 18 06:04:23 PM PDT 24
Peak memory 276456 kb
Host smart-36a38380-d8d8-4de8-99e9-ca19871f994b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572658548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_rd_ooo.572658548
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.1166664194
Short name T354
Test name
Test status
Simulation time 57145400 ps
CPU time 33.5 seconds
Started Aug 18 06:03:36 PM PDT 24
Finished Aug 18 06:04:09 PM PDT 24
Peak memory 276164 kb
Host smart-afdc1c4f-07e9-41da-852f-1e6bfb8b421b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166664194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.1166664194
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.1696511579
Short name T696
Test name
Test status
Simulation time 45919500 ps
CPU time 14.16 seconds
Started Aug 18 06:03:29 PM PDT 24
Finished Aug 18 06:03:43 PM PDT 24
Peak memory 259360 kb
Host smart-6980e70d-74f1-4f8e-89c0-357b2799f4a2
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1696511579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.1696511579
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.2966539383
Short name T564
Test name
Test status
Simulation time 26775700 ps
CPU time 21.8 seconds
Started Aug 18 06:03:30 PM PDT 24
Finished Aug 18 06:03:51 PM PDT 24
Peak memory 265820 kb
Host smart-b9e46e72-b1b4-42c7-9b8c-8a791900f426
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966539383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.2966539383
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.2781616736
Short name T77
Test name
Test status
Simulation time 82222252200 ps
CPU time 907.29 seconds
Started Aug 18 06:03:37 PM PDT 24
Finished Aug 18 06:18:45 PM PDT 24
Peak memory 261856 kb
Host smart-f6f62b6c-11da-4129-87f3-f3fda236ac6e
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781616736 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.2781616736
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.4042782928
Short name T440
Test name
Test status
Simulation time 2085847300 ps
CPU time 112.99 seconds
Started Aug 18 06:03:28 PM PDT 24
Finished Aug 18 06:05:21 PM PDT 24
Peak memory 282276 kb
Host smart-505c0608-6041-4e78-a2ab-27d41f2b6155
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042782928 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.4042782928
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.2363687266
Short name T36
Test name
Test status
Simulation time 5892512800 ps
CPU time 129.86 seconds
Started Aug 18 06:03:33 PM PDT 24
Finished Aug 18 06:05:43 PM PDT 24
Peak memory 295788 kb
Host smart-8ad37d99-c37c-4bbd-a197-5020ab03d5e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363687266 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.2363687266
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.1287716334
Short name T609
Test name
Test status
Simulation time 6730650300 ps
CPU time 509.65 seconds
Started Aug 18 06:03:31 PM PDT 24
Finished Aug 18 06:12:01 PM PDT 24
Peak memory 318376 kb
Host smart-78fbc08f-5b46-4b23-9ebe-08c5c5b448f0
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287716334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.1287716334
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.2997663115
Short name T242
Test name
Test status
Simulation time 1267880600 ps
CPU time 190.82 seconds
Started Aug 18 06:03:32 PM PDT 24
Finished Aug 18 06:06:43 PM PDT 24
Peak memory 282460 kb
Host smart-0ea3978d-1e87-44d0-a5a1-63407a47586f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997663115 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_derr.2997663115
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.1169173133
Short name T854
Test name
Test status
Simulation time 1533182700 ps
CPU time 211.28 seconds
Started Aug 18 06:03:28 PM PDT 24
Finished Aug 18 06:07:00 PM PDT 24
Peak memory 282472 kb
Host smart-aab849f1-077e-4cb7-ae33-718a80f5e447
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169173133 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.flash_ctrl_rw_serr.1169173133
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.1085808121
Short name T17
Test name
Test status
Simulation time 2631281900 ps
CPU time 4913.68 seconds
Started Aug 18 06:03:38 PM PDT 24
Finished Aug 18 07:25:32 PM PDT 24
Peak memory 288968 kb
Host smart-3707c028-171a-4871-aa55-343d8b0c8596
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085808121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.1085808121
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.785928534
Short name T1099
Test name
Test status
Simulation time 3341252300 ps
CPU time 96.24 seconds
Started Aug 18 06:03:29 PM PDT 24
Finished Aug 18 06:05:05 PM PDT 24
Peak memory 274192 kb
Host smart-72384aa6-afc7-4cdb-a68d-2c03fa1e0fb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785928534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_serr_address.785928534
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.452683689
Short name T1025
Test name
Test status
Simulation time 3423328200 ps
CPU time 78.56 seconds
Started Aug 18 06:03:28 PM PDT 24
Finished Aug 18 06:04:47 PM PDT 24
Peak memory 277312 kb
Host smart-3b5eb34f-b825-442b-8e7d-ce2ed7381ca5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452683689 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_counter.452683689
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.2312381422
Short name T520
Test name
Test status
Simulation time 63669200 ps
CPU time 147.93 seconds
Started Aug 18 06:03:21 PM PDT 24
Finished Aug 18 06:05:49 PM PDT 24
Peak memory 277452 kb
Host smart-9051dd0b-c496-459b-92d0-709939c188d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312381422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2312381422
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.3128349793
Short name T1065
Test name
Test status
Simulation time 30935600 ps
CPU time 26.51 seconds
Started Aug 18 06:03:20 PM PDT 24
Finished Aug 18 06:03:47 PM PDT 24
Peak memory 260288 kb
Host smart-476e5d41-3ea3-4e81-8ddc-0c26343cf180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128349793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.3128349793
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.2716835937
Short name T61
Test name
Test status
Simulation time 436105000 ps
CPU time 490.27 seconds
Started Aug 18 06:03:36 PM PDT 24
Finished Aug 18 06:11:47 PM PDT 24
Peak memory 280904 kb
Host smart-b31402a9-456f-4e16-9f59-aa62b0f6ddf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716835937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.2716835937
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.39629607
Short name T529
Test name
Test status
Simulation time 26686700 ps
CPU time 26.58 seconds
Started Aug 18 06:03:22 PM PDT 24
Finished Aug 18 06:03:48 PM PDT 24
Peak memory 260312 kb
Host smart-892b62ad-1a09-439e-b06e-34dbb1fed4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39629607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.39629607
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.3231595754
Short name T977
Test name
Test status
Simulation time 1747768300 ps
CPU time 135.36 seconds
Started Aug 18 06:03:26 PM PDT 24
Finished Aug 18 06:05:42 PM PDT 24
Peak memory 260524 kb
Host smart-5fd82253-4be8-4f46-8872-119385372d8c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231595754 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_wo.3231595754
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.3371759782
Short name T217
Test name
Test status
Simulation time 439666800 ps
CPU time 14.71 seconds
Started Aug 18 06:03:34 PM PDT 24
Finished Aug 18 06:03:49 PM PDT 24
Peak memory 260916 kb
Host smart-fc44d282-60e2-4bef-93be-0c169de81815
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371759782 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.3371759782
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.953545366
Short name T312
Test name
Test status
Simulation time 598689800 ps
CPU time 15.36 seconds
Started Aug 18 06:03:28 PM PDT 24
Finished Aug 18 06:03:44 PM PDT 24
Peak memory 259072 kb
Host smart-23d7c269-2f52-44e0-88eb-2bf94506af2a
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=953545366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swee
p.953545366
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.2161704103
Short name T45
Test name
Test status
Simulation time 12634900 ps
CPU time 13.96 seconds
Started Aug 18 06:03:49 PM PDT 24
Finished Aug 18 06:04:04 PM PDT 24
Peak memory 265964 kb
Host smart-1f32149c-adb9-49c3-bebc-99c0f9cf165d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161704103 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.2161704103
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.2500204474
Short name T1047
Test name
Test status
Simulation time 82507700 ps
CPU time 14.25 seconds
Started Aug 18 06:03:59 PM PDT 24
Finished Aug 18 06:04:13 PM PDT 24
Peak memory 265764 kb
Host smart-2d27d9c0-f471-41a0-9be2-9088ec1772c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500204474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.2
500204474
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.1863568347
Short name T597
Test name
Test status
Simulation time 15636800 ps
CPU time 15.77 seconds
Started Aug 18 06:03:48 PM PDT 24
Finished Aug 18 06:04:04 PM PDT 24
Peak memory 284896 kb
Host smart-81574a78-3385-4f36-895b-5a3bf000cc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863568347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.1863568347
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.548783447
Short name T530
Test name
Test status
Simulation time 1473753500 ps
CPU time 206.08 seconds
Started Aug 18 06:03:46 PM PDT 24
Finished Aug 18 06:07:12 PM PDT 24
Peak memory 278776 kb
Host smart-1f6f7901-8e99-4f82-a446-722f987016ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548783447 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_derr_detect.548783447
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.1733799558
Short name T858
Test name
Test status
Simulation time 10791177800 ps
CPU time 445.63 seconds
Started Aug 18 06:03:43 PM PDT 24
Finished Aug 18 06:11:09 PM PDT 24
Peak memory 263940 kb
Host smart-6a19745d-516b-48c0-bac5-4102a46cbf15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1733799558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.1733799558
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.510612645
Short name T1053
Test name
Test status
Simulation time 27568060400 ps
CPU time 2331.81 seconds
Started Aug 18 06:03:43 PM PDT 24
Finished Aug 18 06:42:35 PM PDT 24
Peak memory 263288 kb
Host smart-c25f66a7-a460-4290-b739-5dc395ad2fe1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=510612645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.510612645
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.1742172279
Short name T790
Test name
Test status
Simulation time 4457635200 ps
CPU time 2207.65 seconds
Started Aug 18 06:03:41 PM PDT 24
Finished Aug 18 06:40:29 PM PDT 24
Peak memory 264260 kb
Host smart-a6a6bd42-5f2e-45cf-b424-38bf45746fad
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742172279 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.1742172279
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.2739046103
Short name T963
Test name
Test status
Simulation time 341908000 ps
CPU time 825.04 seconds
Started Aug 18 06:03:44 PM PDT 24
Finished Aug 18 06:17:29 PM PDT 24
Peak memory 273972 kb
Host smart-d7244848-51fb-42a6-be77-010e23b86dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739046103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2739046103
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.718037947
Short name T79
Test name
Test status
Simulation time 5181166700 ps
CPU time 40.17 seconds
Started Aug 18 06:03:51 PM PDT 24
Finished Aug 18 06:04:32 PM PDT 24
Peak memory 262876 kb
Host smart-b0e071f9-508d-4746-84e1-c5da410337bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718037947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_fs_sup.718037947
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.3048822931
Short name T63
Test name
Test status
Simulation time 101737786000 ps
CPU time 4450.72 seconds
Started Aug 18 06:03:44 PM PDT 24
Finished Aug 18 07:17:56 PM PDT 24
Peak memory 265644 kb
Host smart-89371f63-ed47-4abd-8efc-a6311fb0d7c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048822931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.3048822931
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_addr_infection.3689620430
Short name T503
Test name
Test status
Simulation time 48509800 ps
CPU time 28.03 seconds
Started Aug 18 06:04:03 PM PDT 24
Finished Aug 18 06:04:31 PM PDT 24
Peak memory 274020 kb
Host smart-b460a90b-0ab1-4e74-8486-bdf16a4ebff6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689620430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_host_addr_infection.3689620430
Directory /workspace/1.flash_ctrl_host_addr_infection/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.2276366434
Short name T265
Test name
Test status
Simulation time 61402400 ps
CPU time 101.69 seconds
Started Aug 18 06:03:43 PM PDT 24
Finished Aug 18 06:05:25 PM PDT 24
Peak memory 263192 kb
Host smart-54933c21-ca1c-4f76-a4ba-92f1e39a744a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2276366434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.2276366434
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2393049093
Short name T274
Test name
Test status
Simulation time 10012378100 ps
CPU time 116.47 seconds
Started Aug 18 06:03:57 PM PDT 24
Finished Aug 18 06:05:54 PM PDT 24
Peak memory 314628 kb
Host smart-50f6e62c-988d-4fc3-b0fb-daabb842b1a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393049093 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2393049093
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2208590942
Short name T160
Test name
Test status
Simulation time 15609000 ps
CPU time 13.37 seconds
Started Aug 18 06:03:52 PM PDT 24
Finished Aug 18 06:04:05 PM PDT 24
Peak memory 258588 kb
Host smart-b6532436-922f-4707-862c-40a44e7423fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208590942 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.2208590942
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.2675040771
Short name T791
Test name
Test status
Simulation time 169351996800 ps
CPU time 1876.99 seconds
Started Aug 18 06:03:43 PM PDT 24
Finished Aug 18 06:35:00 PM PDT 24
Peak memory 260496 kb
Host smart-e619a1ae-b0ff-4d0b-9e79-3ebc8db339b1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675040771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.2675040771
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.189253603
Short name T317
Test name
Test status
Simulation time 80138293500 ps
CPU time 834.65 seconds
Started Aug 18 06:03:47 PM PDT 24
Finished Aug 18 06:17:41 PM PDT 24
Peak memory 261564 kb
Host smart-db967b6c-599c-4189-9a33-b330d5889802
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189253603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_hw_rma_reset.189253603
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.2071412782
Short name T561
Test name
Test status
Simulation time 2830775100 ps
CPU time 48.94 seconds
Started Aug 18 06:03:42 PM PDT 24
Finished Aug 18 06:04:31 PM PDT 24
Peak memory 261136 kb
Host smart-f7adacdb-c69b-4987-8fb2-987ae2091629
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071412782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.2071412782
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.1782294466
Short name T639
Test name
Test status
Simulation time 11522983300 ps
CPU time 191.23 seconds
Started Aug 18 06:03:51 PM PDT 24
Finished Aug 18 06:07:03 PM PDT 24
Peak memory 291304 kb
Host smart-f65a54ce-3bb2-4f4f-9030-2c7fcc04bcf8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782294466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.1782294466
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2945537617
Short name T584
Test name
Test status
Simulation time 51181079400 ps
CPU time 335.47 seconds
Started Aug 18 06:03:49 PM PDT 24
Finished Aug 18 06:09:24 PM PDT 24
Peak memory 292596 kb
Host smart-3dd9c328-955e-44cb-adf8-fb486a015a33
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945537617 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.2945537617
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.2587682993
Short name T724
Test name
Test status
Simulation time 3482403700 ps
CPU time 60.08 seconds
Started Aug 18 06:03:47 PM PDT 24
Finished Aug 18 06:04:48 PM PDT 24
Peak memory 261132 kb
Host smart-d8868311-7e52-400f-97f5-532c4c1ae4fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587682993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.2587682993
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.857658085
Short name T27
Test name
Test status
Simulation time 24356965400 ps
CPU time 182 seconds
Started Aug 18 06:03:51 PM PDT 24
Finished Aug 18 06:06:53 PM PDT 24
Peak memory 260312 kb
Host smart-7591dd13-c3f9-49d7-89d3-85ded451d052
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857
658085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.857658085
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.585451281
Short name T583
Test name
Test status
Simulation time 3276263100 ps
CPU time 70.52 seconds
Started Aug 18 06:03:43 PM PDT 24
Finished Aug 18 06:04:54 PM PDT 24
Peak memory 264164 kb
Host smart-e7dd89d5-46ce-440e-8dab-d734e4e5f4db
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585451281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.585451281
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.57485282
Short name T115
Test name
Test status
Simulation time 15009700 ps
CPU time 13.59 seconds
Started Aug 18 06:03:52 PM PDT 24
Finished Aug 18 06:04:06 PM PDT 24
Peak memory 260732 kb
Host smart-9c69a079-5252-4fdd-acb9-ca0b35226c51
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57485282 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.57485282
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.2551939629
Short name T156
Test name
Test status
Simulation time 1154323600 ps
CPU time 70.43 seconds
Started Aug 18 06:03:44 PM PDT 24
Finished Aug 18 06:04:54 PM PDT 24
Peak memory 261040 kb
Host smart-934d5050-90c0-4c45-8119-9b6bd66f3006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551939629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.2551939629
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.3791814160
Short name T853
Test name
Test status
Simulation time 15008307300 ps
CPU time 148.21 seconds
Started Aug 18 06:03:44 PM PDT 24
Finished Aug 18 06:06:12 PM PDT 24
Peak memory 264480 kb
Host smart-5278b0a6-bcde-4ee9-8a0c-23b6543ee90a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791814160 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.3791814160
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.3672335935
Short name T187
Test name
Test status
Simulation time 1450269100 ps
CPU time 224.61 seconds
Started Aug 18 06:03:43 PM PDT 24
Finished Aug 18 06:07:27 PM PDT 24
Peak memory 282452 kb
Host smart-e8db351a-d79e-4387-85c8-6ac171eddd10
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672335935 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.3672335935
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.3073177311
Short name T1094
Test name
Test status
Simulation time 773288700 ps
CPU time 518.32 seconds
Started Aug 18 06:03:42 PM PDT 24
Finished Aug 18 06:12:21 PM PDT 24
Peak memory 263544 kb
Host smart-1081aee2-347c-4dce-904f-ddeb8a24ce81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3073177311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.3073177311
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.3542771371
Short name T196
Test name
Test status
Simulation time 93436700 ps
CPU time 13.96 seconds
Started Aug 18 06:03:49 PM PDT 24
Finished Aug 18 06:04:03 PM PDT 24
Peak memory 263360 kb
Host smart-a5e55828-61c5-4e44-b3a1-85c171bcaf77
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542771371 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3542771371
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.926921545
Short name T467
Test name
Test status
Simulation time 101344100 ps
CPU time 14 seconds
Started Aug 18 06:03:51 PM PDT 24
Finished Aug 18 06:04:05 PM PDT 24
Peak memory 260004 kb
Host smart-0b4c6f74-cf9c-453b-9603-8de57c7952e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926921545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_prog_reset.926921545
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.3040800802
Short name T596
Test name
Test status
Simulation time 182043400 ps
CPU time 615.71 seconds
Started Aug 18 06:03:37 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 284948 kb
Host smart-b4525ffe-2d32-487a-903f-18f8631bd166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040800802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.3040800802
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.3695020501
Short name T211
Test name
Test status
Simulation time 767786300 ps
CPU time 114.7 seconds
Started Aug 18 06:03:43 PM PDT 24
Finished Aug 18 06:05:38 PM PDT 24
Peak memory 263276 kb
Host smart-ea25baeb-2e0c-4915-a01a-2e22ae8f3ab0
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3695020501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.3695020501
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.3683976989
Short name T351
Test name
Test status
Simulation time 115578200 ps
CPU time 32.37 seconds
Started Aug 18 06:03:49 PM PDT 24
Finished Aug 18 06:04:22 PM PDT 24
Peak memory 280560 kb
Host smart-110c1c5e-2315-48c0-a5df-a55105f7bd7a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683976989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.3683976989
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.1252627232
Short name T756
Test name
Test status
Simulation time 76629000 ps
CPU time 35.48 seconds
Started Aug 18 06:03:50 PM PDT 24
Finished Aug 18 06:04:26 PM PDT 24
Peak memory 278364 kb
Host smart-294aed3d-6556-40b1-8b9b-302c66f44540
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252627232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.1252627232
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.699467161
Short name T450
Test name
Test status
Simulation time 18923600 ps
CPU time 22.82 seconds
Started Aug 18 06:03:42 PM PDT 24
Finished Aug 18 06:04:05 PM PDT 24
Peak memory 265924 kb
Host smart-d8b5abd6-4be1-4954-a836-6ed5cd13db9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699467161 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.699467161
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.454395181
Short name T143
Test name
Test status
Simulation time 163433900 ps
CPU time 22.51 seconds
Started Aug 18 06:03:45 PM PDT 24
Finished Aug 18 06:04:08 PM PDT 24
Peak memory 265920 kb
Host smart-2e8588d9-20bd-493c-be4a-7dc3020b0159
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454395181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_read_word_sweep_serr.454395181
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.3577168170
Short name T919
Test name
Test status
Simulation time 2104794700 ps
CPU time 108.06 seconds
Started Aug 18 06:03:42 PM PDT 24
Finished Aug 18 06:05:30 PM PDT 24
Peak memory 282404 kb
Host smart-498229b1-cba5-4e83-ab0f-f325b05dc814
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577168170 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_ro.3577168170
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.3621311996
Short name T151
Test name
Test status
Simulation time 677053700 ps
CPU time 154.83 seconds
Started Aug 18 06:03:45 PM PDT 24
Finished Aug 18 06:06:20 PM PDT 24
Peak memory 282336 kb
Host smart-44dcace9-3b32-4f89-8eb5-b97e520b16da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3621311996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.3621311996
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.2480177474
Short name T797
Test name
Test status
Simulation time 1580858500 ps
CPU time 112.06 seconds
Started Aug 18 06:03:43 PM PDT 24
Finished Aug 18 06:05:35 PM PDT 24
Peak memory 291144 kb
Host smart-b6d7e3d8-9285-45af-a7b7-d8a36743edfc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480177474 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2480177474
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_derr.3208168286
Short name T875
Test name
Test status
Simulation time 3296907200 ps
CPU time 210.89 seconds
Started Aug 18 06:03:44 PM PDT 24
Finished Aug 18 06:07:15 PM PDT 24
Peak memory 289968 kb
Host smart-00915270-01a3-4dc7-a737-ded627a851a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208168286 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_derr.3208168286
Directory /workspace/1.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.2882587118
Short name T331
Test name
Test status
Simulation time 1959042700 ps
CPU time 228.04 seconds
Started Aug 18 06:03:45 PM PDT 24
Finished Aug 18 06:07:33 PM PDT 24
Peak memory 282420 kb
Host smart-18ff6286-0faf-4c88-94e7-4240072db93e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882587118 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.flash_ctrl_rw_serr.2882587118
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.2014913172
Short name T421
Test name
Test status
Simulation time 1525587700 ps
CPU time 73.93 seconds
Started Aug 18 06:03:49 PM PDT 24
Finished Aug 18 06:05:03 PM PDT 24
Peak memory 264232 kb
Host smart-a4c9e791-c6d1-48b5-94b9-9b65ce43eede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014913172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.2014913172
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.1611173511
Short name T922
Test name
Test status
Simulation time 1371431000 ps
CPU time 83.93 seconds
Started Aug 18 06:03:46 PM PDT 24
Finished Aug 18 06:05:10 PM PDT 24
Peak memory 274108 kb
Host smart-4def6522-be33-4eae-8321-1b9a90da723b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611173511 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.1611173511
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.2930738812
Short name T681
Test name
Test status
Simulation time 11555465100 ps
CPU time 89.53 seconds
Started Aug 18 06:03:41 PM PDT 24
Finished Aug 18 06:05:10 PM PDT 24
Peak memory 275820 kb
Host smart-04fcc4d8-8f98-4ecd-97eb-d5190e8701d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930738812 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.2930738812
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.618000502
Short name T994
Test name
Test status
Simulation time 59418600 ps
CPU time 77.07 seconds
Started Aug 18 06:03:36 PM PDT 24
Finished Aug 18 06:04:53 PM PDT 24
Peak memory 277132 kb
Host smart-d7a6cb95-b22e-4de2-8b4c-6b95983d08d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618000502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.618000502
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.1278284472
Short name T715
Test name
Test status
Simulation time 37882200 ps
CPU time 26.07 seconds
Started Aug 18 06:03:37 PM PDT 24
Finished Aug 18 06:04:04 PM PDT 24
Peak memory 260112 kb
Host smart-6c9e1a17-c22f-416e-b531-3df2dc8cc36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278284472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.1278284472
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.434381687
Short name T445
Test name
Test status
Simulation time 224331200 ps
CPU time 345.54 seconds
Started Aug 18 06:03:50 PM PDT 24
Finished Aug 18 06:09:36 PM PDT 24
Peak memory 288680 kb
Host smart-709e7683-5dda-4d46-87f6-1de844576342
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434381687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress
_all.434381687
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.3144796966
Short name T940
Test name
Test status
Simulation time 25025800 ps
CPU time 23.81 seconds
Started Aug 18 06:03:44 PM PDT 24
Finished Aug 18 06:04:08 PM PDT 24
Peak memory 260208 kb
Host smart-c9528688-cff3-4ef6-b0fc-c6dd33757073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144796966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.3144796966
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.4240792495
Short name T118
Test name
Test status
Simulation time 1937142600 ps
CPU time 164.59 seconds
Started Aug 18 06:03:45 PM PDT 24
Finished Aug 18 06:06:30 PM PDT 24
Peak memory 265752 kb
Host smart-5a75b74e-5ed5-4640-a10e-cd4fc01332ae
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240792495 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_wo.4240792495
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.1436513239
Short name T9
Test name
Test status
Simulation time 75620600 ps
CPU time 15.06 seconds
Started Aug 18 06:03:48 PM PDT 24
Finished Aug 18 06:04:03 PM PDT 24
Peak memory 261152 kb
Host smart-0d2db71a-6454-49e4-9d8e-ec6bbe42cd5d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436513239 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.1436513239
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.280503766
Short name T647
Test name
Test status
Simulation time 44654100 ps
CPU time 13.76 seconds
Started Aug 18 06:06:31 PM PDT 24
Finished Aug 18 06:06:45 PM PDT 24
Peak memory 258816 kb
Host smart-69633533-c267-4cc9-a526-6335b69b0887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280503766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.280503766
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.1593159271
Short name T747
Test name
Test status
Simulation time 21705700 ps
CPU time 16.41 seconds
Started Aug 18 06:06:29 PM PDT 24
Finished Aug 18 06:06:46 PM PDT 24
Peak memory 283492 kb
Host smart-ff77c792-2afa-467d-9c75-6cdf261e2d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593159271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1593159271
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.239104651
Short name T526
Test name
Test status
Simulation time 40125169900 ps
CPU time 865.6 seconds
Started Aug 18 06:06:22 PM PDT 24
Finished Aug 18 06:20:48 PM PDT 24
Peak memory 261520 kb
Host smart-5c11d842-9dc7-44ba-8130-1aff8068aa8d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239104651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.flash_ctrl_hw_rma_reset.239104651
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.224642542
Short name T1101
Test name
Test status
Simulation time 1690020500 ps
CPU time 65.45 seconds
Started Aug 18 06:06:20 PM PDT 24
Finished Aug 18 06:07:26 PM PDT 24
Peak memory 263368 kb
Host smart-d03096d8-5f5f-4ecf-9da8-009eae1917ad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224642542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_h
w_sec_otp.224642542
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.2795524576
Short name T960
Test name
Test status
Simulation time 3197586100 ps
CPU time 259.39 seconds
Started Aug 18 06:06:22 PM PDT 24
Finished Aug 18 06:10:41 PM PDT 24
Peak memory 285648 kb
Host smart-88b39343-55ab-4f89-a9a5-b2478316965d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795524576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.2795524576
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.2036552349
Short name T863
Test name
Test status
Simulation time 7191940600 ps
CPU time 134.25 seconds
Started Aug 18 06:06:22 PM PDT 24
Finished Aug 18 06:08:37 PM PDT 24
Peak memory 293408 kb
Host smart-e8b1b71a-7561-4925-8e96-d1073c1e0bf2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036552349 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.2036552349
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.4004925034
Short name T675
Test name
Test status
Simulation time 3326991700 ps
CPU time 65.67 seconds
Started Aug 18 06:06:26 PM PDT 24
Finished Aug 18 06:07:31 PM PDT 24
Peak memory 263960 kb
Host smart-6238284d-8103-440d-9442-990816ddbc3f
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004925034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.4
004925034
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.3791365309
Short name T859
Test name
Test status
Simulation time 15464600 ps
CPU time 13.37 seconds
Started Aug 18 06:06:33 PM PDT 24
Finished Aug 18 06:06:47 PM PDT 24
Peak memory 260656 kb
Host smart-edb14fc5-12ad-488d-a00b-fd6e27c517c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791365309 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.3791365309
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.105275430
Short name T142
Test name
Test status
Simulation time 75265418400 ps
CPU time 419.57 seconds
Started Aug 18 06:06:26 PM PDT 24
Finished Aug 18 06:13:25 PM PDT 24
Peak memory 274936 kb
Host smart-48132a98-9643-4b9d-b957-403e19d43749
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105275430 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.105275430
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.3406841193
Short name T892
Test name
Test status
Simulation time 679848100 ps
CPU time 411.26 seconds
Started Aug 18 06:06:23 PM PDT 24
Finished Aug 18 06:13:14 PM PDT 24
Peak memory 263772 kb
Host smart-fe9fcdf4-09a4-4d7c-a763-bf669347a5ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3406841193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3406841193
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.3153775513
Short name T132
Test name
Test status
Simulation time 10225800100 ps
CPU time 180.21 seconds
Started Aug 18 06:06:23 PM PDT 24
Finished Aug 18 06:09:23 PM PDT 24
Peak memory 262224 kb
Host smart-2a3e4cd2-365f-4436-8f04-8e6574557fa4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153775513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.flash_ctrl_prog_reset.3153775513
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.1922535228
Short name T656
Test name
Test status
Simulation time 165210300 ps
CPU time 282.98 seconds
Started Aug 18 06:06:17 PM PDT 24
Finished Aug 18 06:11:00 PM PDT 24
Peak memory 278004 kb
Host smart-3091fe6f-af77-4604-8050-8d1465e9d4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922535228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.1922535228
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.3228851266
Short name T365
Test name
Test status
Simulation time 104590700 ps
CPU time 33.58 seconds
Started Aug 18 06:06:21 PM PDT 24
Finished Aug 18 06:06:55 PM PDT 24
Peak memory 275484 kb
Host smart-68061e12-4a15-4237-a754-44bc4d7d535c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228851266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.3228851266
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.2672736987
Short name T635
Test name
Test status
Simulation time 556962600 ps
CPU time 112.09 seconds
Started Aug 18 06:06:22 PM PDT 24
Finished Aug 18 06:08:14 PM PDT 24
Peak memory 281392 kb
Host smart-1193eba8-5241-49f1-a8bf-47ceeb18fd5a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672736987 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.flash_ctrl_ro.2672736987
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.3688711090
Short name T752
Test name
Test status
Simulation time 100382700 ps
CPU time 30.13 seconds
Started Aug 18 06:06:20 PM PDT 24
Finished Aug 18 06:06:50 PM PDT 24
Peak memory 274208 kb
Host smart-98aba0f9-9d8d-4bcb-8bef-d35f4de6be86
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688711090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_rw_evict.3688711090
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.1316154437
Short name T25
Test name
Test status
Simulation time 31131700 ps
CPU time 29 seconds
Started Aug 18 06:06:21 PM PDT 24
Finished Aug 18 06:06:51 PM PDT 24
Peak memory 275424 kb
Host smart-1acb868d-67c8-4c0d-a32a-bc8ab1a035a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316154437 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.1316154437
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.1124639240
Short name T419
Test name
Test status
Simulation time 6800710100 ps
CPU time 74.6 seconds
Started Aug 18 06:06:33 PM PDT 24
Finished Aug 18 06:07:48 PM PDT 24
Peak memory 265432 kb
Host smart-a2b0f2e3-5751-4f03-9dec-a5cd0302fc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124639240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.1124639240
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.1493489356
Short name T228
Test name
Test status
Simulation time 92612000 ps
CPU time 98.69 seconds
Started Aug 18 06:06:13 PM PDT 24
Finished Aug 18 06:07:52 PM PDT 24
Peak memory 278032 kb
Host smart-f583a2a9-4d5e-48cc-b14e-c6a6563fbfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493489356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.1493489356
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.1472916828
Short name T296
Test name
Test status
Simulation time 7184447700 ps
CPU time 161.1 seconds
Started Aug 18 06:06:22 PM PDT 24
Finished Aug 18 06:09:03 PM PDT 24
Peak memory 260516 kb
Host smart-f34c8dee-9a66-477a-a7bb-ae14e047b87e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472916828 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.flash_ctrl_wo.1472916828
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.2365010304
Short name T548
Test name
Test status
Simulation time 21898800 ps
CPU time 13.5 seconds
Started Aug 18 06:06:46 PM PDT 24
Finished Aug 18 06:07:00 PM PDT 24
Peak memory 258796 kb
Host smart-c84a7742-3385-4bc5-b37a-f304ea842aca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365010304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
2365010304
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.3651804375
Short name T491
Test name
Test status
Simulation time 16250800 ps
CPU time 15.78 seconds
Started Aug 18 06:06:42 PM PDT 24
Finished Aug 18 06:06:58 PM PDT 24
Peak memory 283372 kb
Host smart-25093240-a06e-43c3-9d48-13b04fb6fe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651804375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.3651804375
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.502463188
Short name T955
Test name
Test status
Simulation time 12606100 ps
CPU time 22.05 seconds
Started Aug 18 06:06:42 PM PDT 24
Finished Aug 18 06:07:04 PM PDT 24
Peak memory 274160 kb
Host smart-60a4317f-8b11-4038-bb59-7ea2058d4796
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502463188 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.502463188
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.597831908
Short name T745
Test name
Test status
Simulation time 10019546700 ps
CPU time 73.24 seconds
Started Aug 18 06:06:40 PM PDT 24
Finished Aug 18 06:07:54 PM PDT 24
Peak memory 285772 kb
Host smart-734d9020-bbdb-4936-8271-0d7988339e16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597831908 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.597831908
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.752623232
Short name T267
Test name
Test status
Simulation time 14776400 ps
CPU time 13.36 seconds
Started Aug 18 06:06:38 PM PDT 24
Finished Aug 18 06:06:51 PM PDT 24
Peak memory 258812 kb
Host smart-4d714dd8-0660-4f2e-be3e-b0b674fd59c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752623232 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.752623232
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.1647240320
Short name T131
Test name
Test status
Simulation time 24062208000 ps
CPU time 296.47 seconds
Started Aug 18 06:06:39 PM PDT 24
Finished Aug 18 06:11:36 PM PDT 24
Peak memory 292212 kb
Host smart-6d198d80-f6f3-4970-a11e-8e67e2cadd6d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647240320 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.1647240320
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.1426359303
Short name T1070
Test name
Test status
Simulation time 8652671600 ps
CPU time 79.28 seconds
Started Aug 18 06:06:39 PM PDT 24
Finished Aug 18 06:07:58 PM PDT 24
Peak memory 264492 kb
Host smart-396b4bf4-ab21-4155-99e2-956ebc7fc646
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426359303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.1
426359303
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.2651267577
Short name T1010
Test name
Test status
Simulation time 25059800 ps
CPU time 13.58 seconds
Started Aug 18 06:06:39 PM PDT 24
Finished Aug 18 06:06:53 PM PDT 24
Peak memory 260764 kb
Host smart-0b2ae466-fe1a-497f-9479-a130f0fc308b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651267577 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.2651267577
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.2800840307
Short name T458
Test name
Test status
Simulation time 46155000 ps
CPU time 133.67 seconds
Started Aug 18 06:06:29 PM PDT 24
Finished Aug 18 06:08:43 PM PDT 24
Peak memory 265492 kb
Host smart-518ed9f9-f2dd-4f65-937a-fc944a446c8f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800840307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.2800840307
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.538247213
Short name T653
Test name
Test status
Simulation time 202544700 ps
CPU time 238.6 seconds
Started Aug 18 06:06:29 PM PDT 24
Finished Aug 18 06:10:28 PM PDT 24
Peak memory 263724 kb
Host smart-65ef39d0-cccf-4d90-9a84-bf3e2b67b018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538247213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.538247213
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.2971090996
Short name T641
Test name
Test status
Simulation time 8032468400 ps
CPU time 181.95 seconds
Started Aug 18 06:06:43 PM PDT 24
Finished Aug 18 06:09:45 PM PDT 24
Peak memory 260704 kb
Host smart-e95e6d8b-5a77-4b28-9ab2-f7d49f611b6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971090996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.flash_ctrl_prog_reset.2971090996
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.3795998758
Short name T145
Test name
Test status
Simulation time 214350100 ps
CPU time 419.78 seconds
Started Aug 18 06:06:32 PM PDT 24
Finished Aug 18 06:13:32 PM PDT 24
Peak memory 282068 kb
Host smart-921cd5f2-02b4-41a8-85e7-ce9a567f07f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795998758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.3795998758
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.495863237
Short name T356
Test name
Test status
Simulation time 208312600 ps
CPU time 32.2 seconds
Started Aug 18 06:06:39 PM PDT 24
Finished Aug 18 06:07:12 PM PDT 24
Peak memory 276284 kb
Host smart-b493335c-dcfd-4d81-8b74-af372acc4e0b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495863237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_re_evict.495863237
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.4164625694
Short name T976
Test name
Test status
Simulation time 601839800 ps
CPU time 109.97 seconds
Started Aug 18 06:06:42 PM PDT 24
Finished Aug 18 06:08:32 PM PDT 24
Peak memory 282372 kb
Host smart-12484142-7786-4e1f-8afb-d14ff4b3fa08
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164625694 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.flash_ctrl_ro.4164625694
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.2401257711
Short name T87
Test name
Test status
Simulation time 15269108000 ps
CPU time 594.57 seconds
Started Aug 18 06:06:38 PM PDT 24
Finished Aug 18 06:16:33 PM PDT 24
Peak memory 319772 kb
Host smart-a3eb03ab-b1ec-4eff-a227-ad6c21e1a1f3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401257711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_rw.2401257711
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.1738956805
Short name T137
Test name
Test status
Simulation time 115570500 ps
CPU time 30.99 seconds
Started Aug 18 06:06:39 PM PDT 24
Finished Aug 18 06:07:10 PM PDT 24
Peak memory 275364 kb
Host smart-64edcb44-ad1c-40aa-bdf2-57ec658ab54f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738956805 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.1738956805
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.2979997975
Short name T425
Test name
Test status
Simulation time 13097373900 ps
CPU time 73.86 seconds
Started Aug 18 06:06:43 PM PDT 24
Finished Aug 18 06:07:57 PM PDT 24
Peak memory 264352 kb
Host smart-e7aff93f-d267-49d2-a25f-bdd8f4a5ceb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979997975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.2979997975
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.621341871
Short name T216
Test name
Test status
Simulation time 68635600 ps
CPU time 74.44 seconds
Started Aug 18 06:06:28 PM PDT 24
Finished Aug 18 06:07:43 PM PDT 24
Peak memory 275980 kb
Host smart-68028624-18ba-4568-b203-5467bf46c8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621341871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.621341871
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.3741773920
Short name T574
Test name
Test status
Simulation time 2449522700 ps
CPU time 176.42 seconds
Started Aug 18 06:06:39 PM PDT 24
Finished Aug 18 06:09:36 PM PDT 24
Peak memory 260620 kb
Host smart-bfcda9e5-b144-4a0a-bda3-45e462b3aa86
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741773920 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.flash_ctrl_wo.3741773920
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.2733982487
Short name T490
Test name
Test status
Simulation time 23603600 ps
CPU time 13.63 seconds
Started Aug 18 06:06:59 PM PDT 24
Finished Aug 18 06:07:13 PM PDT 24
Peak memory 258908 kb
Host smart-e1176778-d1fb-45c3-b114-3ff7460a5ffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733982487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
2733982487
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.4245069214
Short name T881
Test name
Test status
Simulation time 14986500 ps
CPU time 16.31 seconds
Started Aug 18 06:06:56 PM PDT 24
Finished Aug 18 06:07:12 PM PDT 24
Peak memory 284776 kb
Host smart-51281174-de2e-4d42-a95a-70332f425d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245069214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.4245069214
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.3205553311
Short name T392
Test name
Test status
Simulation time 12639100 ps
CPU time 22.08 seconds
Started Aug 18 06:06:56 PM PDT 24
Finished Aug 18 06:07:18 PM PDT 24
Peak memory 273984 kb
Host smart-155c6b1a-a0ee-4965-baf1-8cac87d07140
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205553311 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.3205553311
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.865108594
Short name T1074
Test name
Test status
Simulation time 10088052600 ps
CPU time 59.13 seconds
Started Aug 18 06:06:57 PM PDT 24
Finished Aug 18 06:07:56 PM PDT 24
Peak memory 265784 kb
Host smart-d3f173d3-b71b-4c89-9748-f8ae6aba2f25
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865108594 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.865108594
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.1174540879
Short name T350
Test name
Test status
Simulation time 14693500 ps
CPU time 13.47 seconds
Started Aug 18 06:06:57 PM PDT 24
Finished Aug 18 06:07:10 PM PDT 24
Peak memory 260596 kb
Host smart-6a371259-2820-4463-8124-59a37dd96aed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174540879 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1174540879
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.4197732696
Short name T182
Test name
Test status
Simulation time 50122824000 ps
CPU time 826.7 seconds
Started Aug 18 06:06:51 PM PDT 24
Finished Aug 18 06:20:38 PM PDT 24
Peak memory 264192 kb
Host smart-012f23f0-d713-4a8c-83d1-fe96535c86e1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197732696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.4197732696
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.2188539978
Short name T728
Test name
Test status
Simulation time 5705602200 ps
CPU time 237.46 seconds
Started Aug 18 06:06:48 PM PDT 24
Finished Aug 18 06:10:45 PM PDT 24
Peak memory 263712 kb
Host smart-03b482c1-5c1d-47bc-9569-247fd4310bda
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188539978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.2188539978
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.2814801005
Short name T513
Test name
Test status
Simulation time 6024294200 ps
CPU time 142.82 seconds
Started Aug 18 06:06:47 PM PDT 24
Finished Aug 18 06:09:10 PM PDT 24
Peak memory 291520 kb
Host smart-ee47ff4f-55c1-4ed5-a7d6-38b05f35677d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814801005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.2814801005
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3987859329
Short name T324
Test name
Test status
Simulation time 12648605600 ps
CPU time 265.05 seconds
Started Aug 18 06:06:46 PM PDT 24
Finished Aug 18 06:11:11 PM PDT 24
Peak memory 291468 kb
Host smart-d14a090f-8c18-42b7-a307-9325a596e20e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987859329 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.3987859329
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.2812597059
Short name T798
Test name
Test status
Simulation time 1009574100 ps
CPU time 93.47 seconds
Started Aug 18 06:06:47 PM PDT 24
Finished Aug 18 06:08:21 PM PDT 24
Peak memory 261216 kb
Host smart-b3ee5109-9eee-4c60-8019-8d13037bfc2a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812597059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.2
812597059
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.1977425312
Short name T642
Test name
Test status
Simulation time 62095700 ps
CPU time 13.58 seconds
Started Aug 18 06:06:58 PM PDT 24
Finished Aug 18 06:07:12 PM PDT 24
Peak memory 260784 kb
Host smart-67fa78a3-160d-4257-aa3d-2fbebb3528c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977425312 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.1977425312
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.1231742892
Short name T760
Test name
Test status
Simulation time 20007451300 ps
CPU time 181.71 seconds
Started Aug 18 06:06:50 PM PDT 24
Finished Aug 18 06:09:52 PM PDT 24
Peak memory 265680 kb
Host smart-cdd3a0f9-824b-4da1-b3a5-e3a08208bad8
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231742892 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.1231742892
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.2173768360
Short name T997
Test name
Test status
Simulation time 158177200 ps
CPU time 133.15 seconds
Started Aug 18 06:06:51 PM PDT 24
Finished Aug 18 06:09:04 PM PDT 24
Peak memory 261320 kb
Host smart-c1c04b24-9d40-4ba6-94b6-2ee39161da01
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173768360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.2173768360
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.507956946
Short name T478
Test name
Test status
Simulation time 63165000 ps
CPU time 142.4 seconds
Started Aug 18 06:06:49 PM PDT 24
Finished Aug 18 06:09:12 PM PDT 24
Peak memory 263628 kb
Host smart-609fd829-8bd8-4791-b777-86c4ccce12e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=507956946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.507956946
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.3856241796
Short name T311
Test name
Test status
Simulation time 20399400 ps
CPU time 13.55 seconds
Started Aug 18 06:06:56 PM PDT 24
Finished Aug 18 06:07:10 PM PDT 24
Peak memory 259524 kb
Host smart-efcb6096-6f04-4f1b-9c6f-4e9edaade455
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856241796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.flash_ctrl_prog_reset.3856241796
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.222963051
Short name T146
Test name
Test status
Simulation time 4937226200 ps
CPU time 620.72 seconds
Started Aug 18 06:06:49 PM PDT 24
Finished Aug 18 06:17:09 PM PDT 24
Peak memory 287068 kb
Host smart-a0ce1cd7-f646-4fb8-a592-e6163b7432d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222963051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.222963051
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.1999462053
Short name T1089
Test name
Test status
Simulation time 6236796000 ps
CPU time 109.77 seconds
Started Aug 18 06:06:50 PM PDT 24
Finished Aug 18 06:08:40 PM PDT 24
Peak memory 290656 kb
Host smart-b36a1cce-7528-4456-b849-9842fa310905
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999462053 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_ro.1999462053
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.558643444
Short name T1024
Test name
Test status
Simulation time 14041048500 ps
CPU time 562.71 seconds
Started Aug 18 06:06:49 PM PDT 24
Finished Aug 18 06:16:12 PM PDT 24
Peak memory 314844 kb
Host smart-24082976-e764-420b-a87b-309e51fdf2c2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558643444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.flash_ctrl_rw.558643444
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.1307387206
Short name T562
Test name
Test status
Simulation time 353373200 ps
CPU time 29.6 seconds
Started Aug 18 06:06:59 PM PDT 24
Finished Aug 18 06:07:28 PM PDT 24
Peak memory 276312 kb
Host smart-f68b9f5a-2b35-427b-aee6-6f53621d83d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307387206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_rw_evict.1307387206
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.3414101787
Short name T368
Test name
Test status
Simulation time 35296400 ps
CPU time 31.89 seconds
Started Aug 18 06:06:56 PM PDT 24
Finished Aug 18 06:07:28 PM PDT 24
Peak memory 275564 kb
Host smart-0bafa010-46b9-490f-b6d5-541834383ae5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414101787 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.3414101787
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.1155191592
Short name T410
Test name
Test status
Simulation time 3756840600 ps
CPU time 58.89 seconds
Started Aug 18 06:06:57 PM PDT 24
Finished Aug 18 06:07:56 PM PDT 24
Peak memory 263748 kb
Host smart-5b1cf2bb-3367-4a04-8d8f-8dbb8dfcb9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155191592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.1155191592
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.334411206
Short name T401
Test name
Test status
Simulation time 21344400 ps
CPU time 52.77 seconds
Started Aug 18 06:06:52 PM PDT 24
Finished Aug 18 06:07:45 PM PDT 24
Peak memory 271576 kb
Host smart-6485a138-6866-4330-bfb2-d48dd2b85659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334411206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.334411206
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.4125753368
Short name T990
Test name
Test status
Simulation time 14010832500 ps
CPU time 268 seconds
Started Aug 18 06:06:47 PM PDT 24
Finished Aug 18 06:11:15 PM PDT 24
Peak memory 265856 kb
Host smart-9538afb8-ec69-416e-8d79-aac9d59cef08
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125753368 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.flash_ctrl_wo.4125753368
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.1461628874
Short name T512
Test name
Test status
Simulation time 51374100 ps
CPU time 13.9 seconds
Started Aug 18 06:07:15 PM PDT 24
Finished Aug 18 06:07:29 PM PDT 24
Peak memory 258732 kb
Host smart-1a07ecdb-e974-492e-a734-f0c668e47671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461628874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
1461628874
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.1499540756
Short name T809
Test name
Test status
Simulation time 13672500 ps
CPU time 13.69 seconds
Started Aug 18 06:07:15 PM PDT 24
Finished Aug 18 06:07:29 PM PDT 24
Peak memory 283524 kb
Host smart-6cb27a8a-d274-4b2c-addd-c2a73bc8e284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499540756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.1499540756
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.2804331741
Short name T668
Test name
Test status
Simulation time 12373700 ps
CPU time 22.12 seconds
Started Aug 18 06:07:04 PM PDT 24
Finished Aug 18 06:07:26 PM PDT 24
Peak memory 274052 kb
Host smart-dd63ebb9-8456-47fa-98d5-d80c81b32b57
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804331741 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.2804331741
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.882104793
Short name T81
Test name
Test status
Simulation time 10012557600 ps
CPU time 318.21 seconds
Started Aug 18 06:07:15 PM PDT 24
Finished Aug 18 06:12:33 PM PDT 24
Peak memory 313052 kb
Host smart-6d21339f-6b68-445f-9e66-558065810c59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882104793 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.882104793
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.3659121291
Short name T268
Test name
Test status
Simulation time 46204300 ps
CPU time 13.45 seconds
Started Aug 18 06:07:17 PM PDT 24
Finished Aug 18 06:07:31 PM PDT 24
Peak memory 259024 kb
Host smart-d1e354d4-d8dc-4232-9949-745f25935a83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659121291 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3659121291
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.985496243
Short name T183
Test name
Test status
Simulation time 40124869300 ps
CPU time 853.66 seconds
Started Aug 18 06:06:57 PM PDT 24
Finished Aug 18 06:21:11 PM PDT 24
Peak memory 265400 kb
Host smart-6351167f-4314-4434-baca-9b09638ae5c4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985496243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.flash_ctrl_hw_rma_reset.985496243
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.78277914
Short name T646
Test name
Test status
Simulation time 11020706800 ps
CPU time 91.5 seconds
Started Aug 18 06:06:59 PM PDT 24
Finished Aug 18 06:08:30 PM PDT 24
Peak memory 263680 kb
Host smart-67ac1a81-ab71-46c7-8490-f0ad0bb57efb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78277914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw
_sec_otp.78277914
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.3229729963
Short name T776
Test name
Test status
Simulation time 1422215500 ps
CPU time 154.41 seconds
Started Aug 18 06:07:07 PM PDT 24
Finished Aug 18 06:09:41 PM PDT 24
Peak memory 285772 kb
Host smart-87f1a5ed-9b74-4168-8bb8-d11bacc4d559
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229729963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.3229729963
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.378998671
Short name T628
Test name
Test status
Simulation time 46600398700 ps
CPU time 283.73 seconds
Started Aug 18 06:07:06 PM PDT 24
Finished Aug 18 06:11:50 PM PDT 24
Peak memory 290408 kb
Host smart-5339680c-c808-4e49-85e5-e07ca49b2f0b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378998671 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.378998671
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.4219337665
Short name T432
Test name
Test status
Simulation time 3271757200 ps
CPU time 61.91 seconds
Started Aug 18 06:07:06 PM PDT 24
Finished Aug 18 06:08:08 PM PDT 24
Peak memory 263484 kb
Host smart-25fe5951-57d2-4d27-8677-64167cc055c2
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219337665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.4
219337665
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.437178640
Short name T959
Test name
Test status
Simulation time 26135900 ps
CPU time 13.67 seconds
Started Aug 18 06:07:16 PM PDT 24
Finished Aug 18 06:07:30 PM PDT 24
Peak memory 265308 kb
Host smart-6e54e1e3-35af-4f30-80c9-da0347faaffb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437178640 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.437178640
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.1558049711
Short name T465
Test name
Test status
Simulation time 7204128900 ps
CPU time 136.48 seconds
Started Aug 18 06:07:07 PM PDT 24
Finished Aug 18 06:09:24 PM PDT 24
Peak memory 264356 kb
Host smart-3f3de88e-5eda-49a5-be16-d3673ec48b9b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558049711 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.1558049711
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.728648312
Short name T175
Test name
Test status
Simulation time 44496600 ps
CPU time 109.06 seconds
Started Aug 18 06:07:06 PM PDT 24
Finished Aug 18 06:08:55 PM PDT 24
Peak memory 260476 kb
Host smart-95ffdcc2-ca9f-4af0-a683-c5ff57fdc150
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728648312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ot
p_reset.728648312
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.1945061768
Short name T1056
Test name
Test status
Simulation time 2998972800 ps
CPU time 378.14 seconds
Started Aug 18 06:06:56 PM PDT 24
Finished Aug 18 06:13:14 PM PDT 24
Peak memory 263688 kb
Host smart-688ddef1-a83e-4c04-bc09-d506c10389c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1945061768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.1945061768
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.2968088812
Short name T504
Test name
Test status
Simulation time 20291900 ps
CPU time 13.76 seconds
Started Aug 18 06:07:05 PM PDT 24
Finished Aug 18 06:07:19 PM PDT 24
Peak memory 259508 kb
Host smart-9f412f43-f0c8-47b0-bc62-b40e3fb84996
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968088812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.flash_ctrl_prog_reset.2968088812
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.1723809706
Short name T1034
Test name
Test status
Simulation time 541113300 ps
CPU time 733.04 seconds
Started Aug 18 06:06:57 PM PDT 24
Finished Aug 18 06:19:10 PM PDT 24
Peak memory 288160 kb
Host smart-e7cbb826-6fa2-4c9c-a45b-e2e2f4365f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723809706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.1723809706
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.671858023
Short name T1042
Test name
Test status
Simulation time 245764300 ps
CPU time 35.64 seconds
Started Aug 18 06:07:07 PM PDT 24
Finished Aug 18 06:07:43 PM PDT 24
Peak memory 277184 kb
Host smart-8b84737a-aba8-4786-956c-672711b27951
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671858023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_re_evict.671858023
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.4084974253
Short name T703
Test name
Test status
Simulation time 2081166500 ps
CPU time 123.83 seconds
Started Aug 18 06:07:07 PM PDT 24
Finished Aug 18 06:09:11 PM PDT 24
Peak memory 282456 kb
Host smart-599c0d01-b080-4c08-ae9f-f9d73e84f6f4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084974253 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.flash_ctrl_ro.4084974253
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.873572547
Short name T964
Test name
Test status
Simulation time 4608918800 ps
CPU time 619 seconds
Started Aug 18 06:07:07 PM PDT 24
Finished Aug 18 06:17:26 PM PDT 24
Peak memory 315208 kb
Host smart-9cf02a43-698f-4e79-b010-38652dd404ff
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873572547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.flash_ctrl_rw.873572547
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.335554085
Short name T616
Test name
Test status
Simulation time 70335200 ps
CPU time 31.14 seconds
Started Aug 18 06:07:04 PM PDT 24
Finished Aug 18 06:07:36 PM PDT 24
Peak memory 274016 kb
Host smart-a29b0db1-f6f0-4f2a-8c4d-0ee8a4356924
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335554085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_rw_evict.335554085
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.4151957707
Short name T507
Test name
Test status
Simulation time 948268400 ps
CPU time 66.27 seconds
Started Aug 18 06:07:06 PM PDT 24
Finished Aug 18 06:08:13 PM PDT 24
Peak memory 264216 kb
Host smart-edf49b61-cd35-485c-9d33-4f2ac5e5990b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151957707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.4151957707
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.1843719074
Short name T572
Test name
Test status
Simulation time 35364000 ps
CPU time 149.16 seconds
Started Aug 18 06:06:56 PM PDT 24
Finished Aug 18 06:09:26 PM PDT 24
Peak memory 277528 kb
Host smart-11afc006-d707-4339-acdb-49be5555dc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843719074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.1843719074
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.991620560
Short name T471
Test name
Test status
Simulation time 2281313400 ps
CPU time 163.8 seconds
Started Aug 18 06:07:06 PM PDT 24
Finished Aug 18 06:09:50 PM PDT 24
Peak memory 260608 kb
Host smart-e0f563ab-89f7-40c3-907d-6c85c7d4e61d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991620560 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.flash_ctrl_wo.991620560
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.3464608371
Short name T923
Test name
Test status
Simulation time 86425100 ps
CPU time 13.52 seconds
Started Aug 18 06:07:29 PM PDT 24
Finished Aug 18 06:07:43 PM PDT 24
Peak memory 258812 kb
Host smart-37b4ebee-88b3-4a86-83ae-2ac41c57785d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464608371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
3464608371
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.69221733
Short name T468
Test name
Test status
Simulation time 49415000 ps
CPU time 16.27 seconds
Started Aug 18 06:07:14 PM PDT 24
Finished Aug 18 06:07:30 PM PDT 24
Peak memory 284912 kb
Host smart-b50959cb-6707-4ae8-b3c9-43aaa4fe3310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69221733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.69221733
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.1635760775
Short name T116
Test name
Test status
Simulation time 13878600 ps
CPU time 22.16 seconds
Started Aug 18 06:07:16 PM PDT 24
Finished Aug 18 06:07:38 PM PDT 24
Peak memory 266804 kb
Host smart-beaa2350-bc6d-421e-8ec9-9cefcc0ace08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635760775 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.1635760775
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.3489239529
Short name T749
Test name
Test status
Simulation time 10015568800 ps
CPU time 95.05 seconds
Started Aug 18 06:07:18 PM PDT 24
Finished Aug 18 06:08:53 PM PDT 24
Peak memory 331404 kb
Host smart-7032bdbf-afa1-4483-a278-a1a18e6a77cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489239529 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.3489239529
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.1765596223
Short name T716
Test name
Test status
Simulation time 45838300 ps
CPU time 13.61 seconds
Started Aug 18 06:07:18 PM PDT 24
Finished Aug 18 06:07:32 PM PDT 24
Peak memory 258712 kb
Host smart-cc66b899-13e0-457d-ba77-be34f4c95b2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765596223 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.1765596223
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.2629531442
Short name T598
Test name
Test status
Simulation time 31680483000 ps
CPU time 108.6 seconds
Started Aug 18 06:07:19 PM PDT 24
Finished Aug 18 06:09:07 PM PDT 24
Peak memory 261028 kb
Host smart-c2adc14d-568a-4b2e-b719-f0495d04155c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629531442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.2629531442
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.1668413812
Short name T348
Test name
Test status
Simulation time 2835194300 ps
CPU time 135.22 seconds
Started Aug 18 06:07:18 PM PDT 24
Finished Aug 18 06:09:33 PM PDT 24
Peak memory 294752 kb
Host smart-4c6f89c1-70a8-411b-b8b3-6292cea64d0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668413812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.1668413812
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1476379140
Short name T850
Test name
Test status
Simulation time 23800955000 ps
CPU time 156.63 seconds
Started Aug 18 06:07:15 PM PDT 24
Finished Aug 18 06:09:52 PM PDT 24
Peak memory 294932 kb
Host smart-c0f31b3c-f754-4b17-8787-0bac97b3143e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476379140 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.1476379140
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.3973325725
Short name T630
Test name
Test status
Simulation time 4280624700 ps
CPU time 65.67 seconds
Started Aug 18 06:07:18 PM PDT 24
Finished Aug 18 06:08:23 PM PDT 24
Peak memory 264108 kb
Host smart-fc76686f-c3a1-4913-a984-4faefbeb2306
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973325725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.3
973325725
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2655622762
Short name T843
Test name
Test status
Simulation time 45242900 ps
CPU time 13.59 seconds
Started Aug 18 06:07:18 PM PDT 24
Finished Aug 18 06:07:31 PM PDT 24
Peak memory 260744 kb
Host smart-28ac23b0-c20c-4a67-8c3c-2d915d9eac4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655622762 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.2655622762
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.416291586
Short name T127
Test name
Test status
Simulation time 40209799300 ps
CPU time 650.59 seconds
Started Aug 18 06:07:16 PM PDT 24
Finished Aug 18 06:18:07 PM PDT 24
Peak memory 275272 kb
Host smart-212e3562-f9f0-4a2d-8eb0-ff87072f9ff6
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416291586 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.416291586
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.3292539234
Short name T466
Test name
Test status
Simulation time 260616400 ps
CPU time 280.99 seconds
Started Aug 18 06:07:16 PM PDT 24
Finished Aug 18 06:11:57 PM PDT 24
Peak memory 263672 kb
Host smart-afd7f68d-e77f-4fcc-a224-c37aecde1ed9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292539234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.3292539234
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.2815268430
Short name T289
Test name
Test status
Simulation time 3016700800 ps
CPU time 190.35 seconds
Started Aug 18 06:07:18 PM PDT 24
Finished Aug 18 06:10:29 PM PDT 24
Peak memory 261084 kb
Host smart-aa536627-793d-471f-8976-850bc6f338c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815268430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.flash_ctrl_prog_reset.2815268430
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.2895007950
Short name T130
Test name
Test status
Simulation time 884361800 ps
CPU time 913.82 seconds
Started Aug 18 06:07:15 PM PDT 24
Finished Aug 18 06:22:29 PM PDT 24
Peak memory 284816 kb
Host smart-abfaae6d-55f1-44fd-a9b3-accd3dcdcaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895007950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.2895007950
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.1925917468
Short name T550
Test name
Test status
Simulation time 102093400 ps
CPU time 36.09 seconds
Started Aug 18 06:07:17 PM PDT 24
Finished Aug 18 06:07:53 PM PDT 24
Peak memory 278332 kb
Host smart-6a8b7836-0ad7-41ed-bb25-5d00544eb622
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925917468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.1925917468
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.1183463500
Short name T1057
Test name
Test status
Simulation time 1506912800 ps
CPU time 123.15 seconds
Started Aug 18 06:07:15 PM PDT 24
Finished Aug 18 06:09:19 PM PDT 24
Peak memory 282492 kb
Host smart-aea01cb6-7c7f-4676-8e91-076bc48f3cf6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183463500 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.flash_ctrl_ro.1183463500
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.1999295008
Short name T485
Test name
Test status
Simulation time 8942747900 ps
CPU time 522.05 seconds
Started Aug 18 06:07:15 PM PDT 24
Finished Aug 18 06:15:57 PM PDT 24
Peak memory 315104 kb
Host smart-e6caf605-ca84-49d9-838d-e74016bab33c
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999295008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.1999295008
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.721473544
Short name T883
Test name
Test status
Simulation time 66503200 ps
CPU time 30.56 seconds
Started Aug 18 06:07:18 PM PDT 24
Finished Aug 18 06:07:49 PM PDT 24
Peak memory 276228 kb
Host smart-c4338f98-45d4-440b-843d-efda938f2d81
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721473544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_rw_evict.721473544
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.3483847043
Short name T943
Test name
Test status
Simulation time 300933500 ps
CPU time 121.89 seconds
Started Aug 18 06:07:18 PM PDT 24
Finished Aug 18 06:09:20 PM PDT 24
Peak memory 279396 kb
Host smart-6e91e157-ae33-4c06-b6ea-02c9ae27478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483847043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3483847043
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.2650712166
Short name T1026
Test name
Test status
Simulation time 1920996200 ps
CPU time 156.51 seconds
Started Aug 18 06:07:17 PM PDT 24
Finished Aug 18 06:09:54 PM PDT 24
Peak memory 259904 kb
Host smart-4728d79a-f323-4c8d-b288-f97973641850
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650712166 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.2650712166
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.3955813345
Short name T662
Test name
Test status
Simulation time 42678600 ps
CPU time 13.6 seconds
Started Aug 18 06:07:26 PM PDT 24
Finished Aug 18 06:07:40 PM PDT 24
Peak memory 258812 kb
Host smart-c7c1ed2a-c011-47cc-b54e-557102d94e3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955813345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
3955813345
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.3720813001
Short name T849
Test name
Test status
Simulation time 16385100 ps
CPU time 13.52 seconds
Started Aug 18 06:07:27 PM PDT 24
Finished Aug 18 06:07:41 PM PDT 24
Peak memory 284836 kb
Host smart-94cca4de-a30a-48c8-9233-22ae9e807de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720813001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.3720813001
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.248972613
Short name T914
Test name
Test status
Simulation time 13178600 ps
CPU time 20.96 seconds
Started Aug 18 06:07:24 PM PDT 24
Finished Aug 18 06:07:45 PM PDT 24
Peak memory 273928 kb
Host smart-60d91a2f-baba-47ab-9fa1-9638c4bfb3ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248972613 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.248972613
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.1039247182
Short name T870
Test name
Test status
Simulation time 33627900 ps
CPU time 13.79 seconds
Started Aug 18 06:07:28 PM PDT 24
Finished Aug 18 06:07:42 PM PDT 24
Peak memory 260568 kb
Host smart-4500f610-1744-4831-ad25-d12b17428b31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039247182 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.1039247182
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.2051023036
Short name T184
Test name
Test status
Simulation time 40129631800 ps
CPU time 846.58 seconds
Started Aug 18 06:07:27 PM PDT 24
Finished Aug 18 06:21:34 PM PDT 24
Peak memory 265120 kb
Host smart-224f793f-2247-4659-aab6-4a76e7388883
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051023036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.2051023036
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.975926872
Short name T965
Test name
Test status
Simulation time 9336416000 ps
CPU time 89.31 seconds
Started Aug 18 06:07:25 PM PDT 24
Finished Aug 18 06:08:54 PM PDT 24
Peak memory 261500 kb
Host smart-17399254-3623-425f-b5f3-386626e3645a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975926872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_h
w_sec_otp.975926872
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.355166468
Short name T218
Test name
Test status
Simulation time 2774961600 ps
CPU time 141.38 seconds
Started Aug 18 06:07:29 PM PDT 24
Finished Aug 18 06:09:50 PM PDT 24
Peak memory 294952 kb
Host smart-da31b572-9dec-4339-81c1-c12e79f2a589
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355166468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flas
h_ctrl_intr_rd.355166468
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.90256474
Short name T1033
Test name
Test status
Simulation time 24797500500 ps
CPU time 183.58 seconds
Started Aug 18 06:07:25 PM PDT 24
Finished Aug 18 06:10:29 PM PDT 24
Peak memory 293452 kb
Host smart-41b307b2-d5e2-4546-99cf-3fe28d64eafc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90256474 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.90256474
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.1398688689
Short name T300
Test name
Test status
Simulation time 1012901700 ps
CPU time 85.29 seconds
Started Aug 18 06:07:25 PM PDT 24
Finished Aug 18 06:08:50 PM PDT 24
Peak memory 261340 kb
Host smart-45d1b7f6-b99a-45b4-82ab-c0d5cd1aa0b4
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398688689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1
398688689
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.2561752450
Short name T140
Test name
Test status
Simulation time 79161230500 ps
CPU time 273.46 seconds
Started Aug 18 06:07:27 PM PDT 24
Finished Aug 18 06:12:01 PM PDT 24
Peak memory 275980 kb
Host smart-cb0fa90e-f182-48b4-bdf7-44a891f3ed6e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561752450 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.2561752450
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.2519333511
Short name T435
Test name
Test status
Simulation time 74456300 ps
CPU time 132.65 seconds
Started Aug 18 06:07:28 PM PDT 24
Finished Aug 18 06:09:41 PM PDT 24
Peak memory 261424 kb
Host smart-1b30b012-54cc-468b-996f-100a78a9ff58
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519333511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.2519333511
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.3970063994
Short name T470
Test name
Test status
Simulation time 217134400 ps
CPU time 196.16 seconds
Started Aug 18 06:07:28 PM PDT 24
Finished Aug 18 06:10:44 PM PDT 24
Peak memory 263772 kb
Host smart-a3356466-2af3-4213-92a3-245e8db389d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3970063994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.3970063994
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.2372740527
Short name T301
Test name
Test status
Simulation time 75199100 ps
CPU time 13.6 seconds
Started Aug 18 06:07:26 PM PDT 24
Finished Aug 18 06:07:40 PM PDT 24
Peak memory 259572 kb
Host smart-cf3b0366-7f24-4620-b726-4d50eaf9f1d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372740527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.flash_ctrl_prog_reset.2372740527
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.500495641
Short name T120
Test name
Test status
Simulation time 800859200 ps
CPU time 992.41 seconds
Started Aug 18 06:07:26 PM PDT 24
Finished Aug 18 06:23:58 PM PDT 24
Peak memory 287772 kb
Host smart-f9ef259b-5e35-4b06-bea9-8a6f16455a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500495641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.500495641
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.2005715801
Short name T514
Test name
Test status
Simulation time 76598300 ps
CPU time 34.71 seconds
Started Aug 18 06:07:25 PM PDT 24
Finished Aug 18 06:08:00 PM PDT 24
Peak memory 274204 kb
Host smart-979e87f1-2e68-4d7f-ba75-943007912e2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005715801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.2005715801
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.1119616212
Short name T702
Test name
Test status
Simulation time 1191583200 ps
CPU time 110.74 seconds
Started Aug 18 06:07:25 PM PDT 24
Finished Aug 18 06:09:15 PM PDT 24
Peak memory 281708 kb
Host smart-4c992a5a-003f-4244-a648-c65aa474cd00
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119616212 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_ro.1119616212
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.2895280411
Short name T370
Test name
Test status
Simulation time 50898824700 ps
CPU time 675.04 seconds
Started Aug 18 06:07:26 PM PDT 24
Finished Aug 18 06:18:41 PM PDT 24
Peak memory 310200 kb
Host smart-15211970-0565-465d-b26c-01cebb3cbc91
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895280411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_rw.2895280411
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.842861522
Short name T372
Test name
Test status
Simulation time 28800700 ps
CPU time 28.69 seconds
Started Aug 18 06:07:28 PM PDT 24
Finished Aug 18 06:07:57 PM PDT 24
Peak memory 276248 kb
Host smart-ec89163c-e13e-4a5a-8ba6-0e57d192016a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842861522 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.842861522
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.3623731175
Short name T418
Test name
Test status
Simulation time 2159035800 ps
CPU time 75.4 seconds
Started Aug 18 06:07:27 PM PDT 24
Finished Aug 18 06:08:43 PM PDT 24
Peak memory 264188 kb
Host smart-da3aee64-ac4b-46ca-9c3c-7b7dbdcd8eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623731175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3623731175
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.160752569
Short name T759
Test name
Test status
Simulation time 27586300 ps
CPU time 96.63 seconds
Started Aug 18 06:07:25 PM PDT 24
Finished Aug 18 06:09:02 PM PDT 24
Peak memory 276544 kb
Host smart-0ef6aa7e-1f9f-41df-91dd-18be98c2f42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160752569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.160752569
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.919486551
Short name T1086
Test name
Test status
Simulation time 11366370500 ps
CPU time 256.02 seconds
Started Aug 18 06:07:29 PM PDT 24
Finished Aug 18 06:11:45 PM PDT 24
Peak memory 265988 kb
Host smart-9edf3996-8b26-4f61-9353-4f87754ee4d6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919486551 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.flash_ctrl_wo.919486551
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.3821627987
Short name T613
Test name
Test status
Simulation time 66831400 ps
CPU time 13.38 seconds
Started Aug 18 06:07:51 PM PDT 24
Finished Aug 18 06:08:04 PM PDT 24
Peak memory 265668 kb
Host smart-7189c11e-b705-4416-92e0-2624eab01ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821627987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
3821627987
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.1358814190
Short name T394
Test name
Test status
Simulation time 12607200 ps
CPU time 21.24 seconds
Started Aug 18 06:07:35 PM PDT 24
Finished Aug 18 06:07:56 PM PDT 24
Peak memory 274016 kb
Host smart-257b3d84-8bfd-45d5-a306-ff220cef9b00
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358814190 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.1358814190
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.2462389498
Short name T731
Test name
Test status
Simulation time 15074400 ps
CPU time 13.95 seconds
Started Aug 18 06:07:36 PM PDT 24
Finished Aug 18 06:07:50 PM PDT 24
Peak memory 265172 kb
Host smart-f9ade685-054c-46c2-bd38-73cf044a86c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462389498 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.2462389498
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.3865788828
Short name T838
Test name
Test status
Simulation time 25293356000 ps
CPU time 160.73 seconds
Started Aug 18 06:07:27 PM PDT 24
Finished Aug 18 06:10:07 PM PDT 24
Peak memory 261516 kb
Host smart-10948b14-86ab-4d2a-bb27-e00098d6d3a6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865788828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.3865788828
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.4087472730
Short name T261
Test name
Test status
Simulation time 6449588500 ps
CPU time 213.57 seconds
Started Aug 18 06:07:37 PM PDT 24
Finished Aug 18 06:11:11 PM PDT 24
Peak memory 285720 kb
Host smart-172f10e6-a5a2-4498-9d0f-d9458e7b0f24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087472730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.4087472730
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3315321116
Short name T345
Test name
Test status
Simulation time 168257838400 ps
CPU time 224.13 seconds
Started Aug 18 06:07:35 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 291552 kb
Host smart-624b6d20-67a8-4879-ac19-4ea19ca5cc4e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315321116 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.3315321116
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.3582434064
Short name T260
Test name
Test status
Simulation time 1694900400 ps
CPU time 66.78 seconds
Started Aug 18 06:07:38 PM PDT 24
Finished Aug 18 06:08:45 PM PDT 24
Peak memory 263692 kb
Host smart-eea42cf6-4d6f-4c6c-b72a-acbf935ce61e
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582434064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3
582434064
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.1771977765
Short name T1011
Test name
Test status
Simulation time 35252993400 ps
CPU time 217.24 seconds
Started Aug 18 06:07:29 PM PDT 24
Finished Aug 18 06:11:06 PM PDT 24
Peak memory 275172 kb
Host smart-d27766f2-8c20-4178-a624-6093a3bec705
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771977765 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.1771977765
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.323575105
Short name T823
Test name
Test status
Simulation time 80107800 ps
CPU time 130.49 seconds
Started Aug 18 06:07:28 PM PDT 24
Finished Aug 18 06:09:38 PM PDT 24
Peak memory 261460 kb
Host smart-153a0ba1-2ef6-41c9-9864-c10af9666869
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323575105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ot
p_reset.323575105
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.3305166575
Short name T1093
Test name
Test status
Simulation time 81499100 ps
CPU time 152.65 seconds
Started Aug 18 06:07:28 PM PDT 24
Finished Aug 18 06:10:01 PM PDT 24
Peak memory 263752 kb
Host smart-48b08374-1cf2-4fde-9a77-1b1217fc3fcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3305166575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.3305166575
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.4137884301
Short name T438
Test name
Test status
Simulation time 21454800 ps
CPU time 13.62 seconds
Started Aug 18 06:07:38 PM PDT 24
Finished Aug 18 06:07:52 PM PDT 24
Peak memory 260004 kb
Host smart-a68ab670-ed40-4742-b46d-402004b1bb34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137884301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.flash_ctrl_prog_reset.4137884301
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.2036422421
Short name T845
Test name
Test status
Simulation time 5472529700 ps
CPU time 548.91 seconds
Started Aug 18 06:07:27 PM PDT 24
Finished Aug 18 06:16:36 PM PDT 24
Peak memory 285944 kb
Host smart-675f8abb-c4df-4499-88b2-43af12aca528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036422421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2036422421
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.2741802807
Short name T366
Test name
Test status
Simulation time 280716300 ps
CPU time 33.46 seconds
Started Aug 18 06:07:36 PM PDT 24
Finished Aug 18 06:08:10 PM PDT 24
Peak memory 276240 kb
Host smart-7f798799-2df3-4be1-9363-ce0b1ea0ef2a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741802807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.2741802807
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.2227877514
Short name T198
Test name
Test status
Simulation time 1707225200 ps
CPU time 129.55 seconds
Started Aug 18 06:07:34 PM PDT 24
Finished Aug 18 06:09:44 PM PDT 24
Peak memory 281692 kb
Host smart-146e1aaa-d013-47d7-96f6-d306a71ad0db
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227877514 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.2227877514
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.2996738380
Short name T200
Test name
Test status
Simulation time 21732371100 ps
CPU time 562.88 seconds
Started Aug 18 06:07:39 PM PDT 24
Finished Aug 18 06:17:02 PM PDT 24
Peak memory 310588 kb
Host smart-62f6fa7e-9fda-4e12-82b6-c252147b4d48
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996738380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_rw.2996738380
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.8226604
Short name T806
Test name
Test status
Simulation time 40142900 ps
CPU time 31.06 seconds
Started Aug 18 06:07:35 PM PDT 24
Finished Aug 18 06:08:06 PM PDT 24
Peak memory 274200 kb
Host smart-792e0238-e4c8-415a-ae7e-ff8a25f8707f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8226604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=
flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash
_ctrl_rw_evict.8226604
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.2637655759
Short name T4
Test name
Test status
Simulation time 108985700 ps
CPU time 30.8 seconds
Started Aug 18 06:07:38 PM PDT 24
Finished Aug 18 06:08:08 PM PDT 24
Peak memory 275540 kb
Host smart-89de32e1-baf9-4d98-a135-6b3f6feafb23
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637655759 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.2637655759
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.1637010148
Short name T926
Test name
Test status
Simulation time 1982641900 ps
CPU time 70.26 seconds
Started Aug 18 06:07:34 PM PDT 24
Finished Aug 18 06:08:44 PM PDT 24
Peak memory 265436 kb
Host smart-8d90dbf0-ab9f-4a66-940a-387236450ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637010148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.1637010148
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.498151511
Short name T835
Test name
Test status
Simulation time 99549600 ps
CPU time 192.74 seconds
Started Aug 18 06:07:27 PM PDT 24
Finished Aug 18 06:10:40 PM PDT 24
Peak memory 279560 kb
Host smart-35b383b0-fced-47c0-a254-c7d756bb6e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498151511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.498151511
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.2120109172
Short name T907
Test name
Test status
Simulation time 4104617800 ps
CPU time 177.16 seconds
Started Aug 18 06:07:36 PM PDT 24
Finished Aug 18 06:10:33 PM PDT 24
Peak memory 265848 kb
Host smart-918ef29b-5f98-47db-a0d9-bbb694baf395
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120109172 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.flash_ctrl_wo.2120109172
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.1801281438
Short name T605
Test name
Test status
Simulation time 100093600 ps
CPU time 14.33 seconds
Started Aug 18 06:07:50 PM PDT 24
Finished Aug 18 06:08:04 PM PDT 24
Peak memory 265716 kb
Host smart-989e9069-dd2f-42ef-b784-48e5f2fb0341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801281438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
1801281438
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.3044260545
Short name T112
Test name
Test status
Simulation time 22032000 ps
CPU time 15.91 seconds
Started Aug 18 06:07:38 PM PDT 24
Finished Aug 18 06:07:54 PM PDT 24
Peak memory 283504 kb
Host smart-0abd914f-99ce-4ee4-8d20-ae1c3eb87f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044260545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.3044260545
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.1342692242
Short name T96
Test name
Test status
Simulation time 27070900 ps
CPU time 22.15 seconds
Started Aug 18 06:07:34 PM PDT 24
Finished Aug 18 06:07:57 PM PDT 24
Peak memory 274144 kb
Host smart-5ba1d961-3f56-4db0-ad3b-5780f9aa2fd5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342692242 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.1342692242
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.765660222
Short name T171
Test name
Test status
Simulation time 10034086200 ps
CPU time 61.92 seconds
Started Aug 18 06:07:49 PM PDT 24
Finished Aug 18 06:08:51 PM PDT 24
Peak memory 293796 kb
Host smart-1bf9eefa-8c8b-4735-9d80-11c0338d5151
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765660222 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.765660222
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.1513564705
Short name T969
Test name
Test status
Simulation time 25395600 ps
CPU time 13.28 seconds
Started Aug 18 06:07:48 PM PDT 24
Finished Aug 18 06:08:02 PM PDT 24
Peak memory 258820 kb
Host smart-790d6c29-4fb3-4c56-ba27-843617be1b1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513564705 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.1513564705
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.4274847005
Short name T558
Test name
Test status
Simulation time 80138067400 ps
CPU time 830.99 seconds
Started Aug 18 06:07:35 PM PDT 24
Finished Aug 18 06:21:26 PM PDT 24
Peak memory 262408 kb
Host smart-da2268c6-b741-44fe-9b81-c5478bc46930
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274847005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.4274847005
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.3622732867
Short name T456
Test name
Test status
Simulation time 7647050700 ps
CPU time 113.4 seconds
Started Aug 18 06:07:38 PM PDT 24
Finished Aug 18 06:09:32 PM PDT 24
Peak memory 263380 kb
Host smart-7df66159-c5f7-46e9-939b-9ce79a60b9e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622732867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.3622732867
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.1470890942
Short name T586
Test name
Test status
Simulation time 2549952000 ps
CPU time 139.31 seconds
Started Aug 18 06:07:35 PM PDT 24
Finished Aug 18 06:09:55 PM PDT 24
Peak memory 294704 kb
Host smart-a7144554-0959-48a7-8164-3ddcac68d5c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470890942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.1470890942
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2870249778
Short name T834
Test name
Test status
Simulation time 5981400000 ps
CPU time 164.05 seconds
Started Aug 18 06:07:38 PM PDT 24
Finished Aug 18 06:10:22 PM PDT 24
Peak memory 285784 kb
Host smart-97f0b616-17a0-4902-9fe3-e6a69ede87c9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870249778 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.2870249778
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1966993872
Short name T981
Test name
Test status
Simulation time 49139700 ps
CPU time 13.64 seconds
Started Aug 18 06:07:49 PM PDT 24
Finished Aug 18 06:08:02 PM PDT 24
Peak memory 260592 kb
Host smart-4c067229-5bc0-4aab-8b35-9a2a8fbb880a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966993872 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.1966993872
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.1103705654
Short name T136
Test name
Test status
Simulation time 2420214400 ps
CPU time 105.42 seconds
Started Aug 18 06:07:35 PM PDT 24
Finished Aug 18 06:09:20 PM PDT 24
Peak memory 265772 kb
Host smart-4c56d017-012d-4f95-8553-07bd3fd77809
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103705654 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.1103705654
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.3960682869
Short name T901
Test name
Test status
Simulation time 70351700 ps
CPU time 132.51 seconds
Started Aug 18 06:07:34 PM PDT 24
Finished Aug 18 06:09:46 PM PDT 24
Peak memory 261608 kb
Host smart-4daaa807-9b6e-4f46-880c-9493066b7da2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960682869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.3960682869
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.1913987875
Short name T980
Test name
Test status
Simulation time 1370096500 ps
CPU time 275.22 seconds
Started Aug 18 06:07:38 PM PDT 24
Finished Aug 18 06:12:13 PM PDT 24
Peak memory 263856 kb
Host smart-42198f16-9b30-4f8b-9e32-c2c38df49b77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1913987875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1913987875
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.2032524307
Short name T615
Test name
Test status
Simulation time 2783355200 ps
CPU time 142.9 seconds
Started Aug 18 06:07:38 PM PDT 24
Finished Aug 18 06:10:01 PM PDT 24
Peak memory 261196 kb
Host smart-1671d6b9-49c4-4649-83ba-5b93005262ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032524307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.flash_ctrl_prog_reset.2032524307
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.1380769809
Short name T860
Test name
Test status
Simulation time 192583300 ps
CPU time 596.34 seconds
Started Aug 18 06:07:40 PM PDT 24
Finished Aug 18 06:17:36 PM PDT 24
Peak memory 283036 kb
Host smart-cb4d024c-a4d3-4940-9ed5-ea6a614739b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380769809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.1380769809
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.3713840821
Short name T993
Test name
Test status
Simulation time 159886400 ps
CPU time 36.2 seconds
Started Aug 18 06:07:34 PM PDT 24
Finished Aug 18 06:08:11 PM PDT 24
Peak memory 275500 kb
Host smart-9a23c9af-3749-444e-89c5-c509f2a3465d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713840821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.3713840821
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.800545467
Short name T229
Test name
Test status
Simulation time 559880200 ps
CPU time 110.76 seconds
Started Aug 18 06:07:38 PM PDT 24
Finished Aug 18 06:09:29 PM PDT 24
Peak memory 282352 kb
Host smart-265f3531-8f4e-4cbe-b3f1-6a23f294db11
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800545467 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.flash_ctrl_ro.800545467
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.1103628526
Short name T1048
Test name
Test status
Simulation time 3659248500 ps
CPU time 577.14 seconds
Started Aug 18 06:07:38 PM PDT 24
Finished Aug 18 06:17:16 PM PDT 24
Peak memory 314988 kb
Host smart-1d1fe3c4-9f99-4421-bb8d-ea414a133c80
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103628526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.flash_ctrl_rw.1103628526
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.3321057989
Short name T449
Test name
Test status
Simulation time 44650900 ps
CPU time 32.14 seconds
Started Aug 18 06:07:33 PM PDT 24
Finished Aug 18 06:08:06 PM PDT 24
Peak memory 276224 kb
Host smart-2b9ef3f6-ec3b-40d9-94c1-0d2902e6dcb1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321057989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_rw_evict.3321057989
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.4118339644
Short name T902
Test name
Test status
Simulation time 88990600 ps
CPU time 31.52 seconds
Started Aug 18 06:07:39 PM PDT 24
Finished Aug 18 06:08:10 PM PDT 24
Peak memory 275476 kb
Host smart-595542ac-0ef5-47f9-a8ab-f88e6e7f82ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118339644 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.4118339644
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.640789663
Short name T750
Test name
Test status
Simulation time 30623300 ps
CPU time 166.97 seconds
Started Aug 18 06:07:35 PM PDT 24
Finished Aug 18 06:10:22 PM PDT 24
Peak memory 269416 kb
Host smart-d78bf012-6275-4ee6-8ca7-e08ff3ea0f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640789663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.640789663
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.261882885
Short name T887
Test name
Test status
Simulation time 2754352300 ps
CPU time 148.37 seconds
Started Aug 18 06:07:33 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 260596 kb
Host smart-126d402a-19f2-4cd5-9244-0313a14c45a9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261882885 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.flash_ctrl_wo.261882885
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.2477823482
Short name T774
Test name
Test status
Simulation time 67032200 ps
CPU time 13.63 seconds
Started Aug 18 06:07:49 PM PDT 24
Finished Aug 18 06:08:03 PM PDT 24
Peak memory 265820 kb
Host smart-10d848f0-0f56-4cb9-afe1-0d416fc38a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477823482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
2477823482
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.2360050173
Short name T634
Test name
Test status
Simulation time 22433200 ps
CPU time 15.67 seconds
Started Aug 18 06:07:50 PM PDT 24
Finished Aug 18 06:08:05 PM PDT 24
Peak memory 284804 kb
Host smart-d41af5fe-4ba4-4c7b-8c73-0e42daaaade9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360050173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.2360050173
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.1680605244
Short name T905
Test name
Test status
Simulation time 23051600 ps
CPU time 21.21 seconds
Started Aug 18 06:07:49 PM PDT 24
Finished Aug 18 06:08:10 PM PDT 24
Peak memory 266936 kb
Host smart-d381185c-8a74-4a52-aeb4-9e21a8dae8fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680605244 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.1680605244
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.3107576923
Short name T718
Test name
Test status
Simulation time 10019317600 ps
CPU time 180.9 seconds
Started Aug 18 06:07:49 PM PDT 24
Finished Aug 18 06:10:50 PM PDT 24
Peak memory 297188 kb
Host smart-cf77e881-0e6e-45dc-951e-49013dc1ca6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107576923 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.3107576923
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.1931978138
Short name T159
Test name
Test status
Simulation time 15125700 ps
CPU time 13.52 seconds
Started Aug 18 06:07:48 PM PDT 24
Finished Aug 18 06:08:02 PM PDT 24
Peak memory 258952 kb
Host smart-ffd30d6c-9233-4850-9992-00361d59402b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931978138 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.1931978138
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.673715728
Short name T693
Test name
Test status
Simulation time 40125308200 ps
CPU time 852.82 seconds
Started Aug 18 06:07:47 PM PDT 24
Finished Aug 18 06:22:00 PM PDT 24
Peak memory 262744 kb
Host smart-26e6f393-9cfd-48a7-ad7a-c25486ecb273
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673715728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.flash_ctrl_hw_rma_reset.673715728
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.1860512400
Short name T738
Test name
Test status
Simulation time 5574500700 ps
CPU time 86.2 seconds
Started Aug 18 06:07:51 PM PDT 24
Finished Aug 18 06:09:17 PM PDT 24
Peak memory 261040 kb
Host smart-e5b4b81f-a88a-4ebf-9bbd-d5967ecdcf24
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860512400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.1860512400
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.427368892
Short name T701
Test name
Test status
Simulation time 1504774200 ps
CPU time 193 seconds
Started Aug 18 06:07:50 PM PDT 24
Finished Aug 18 06:11:03 PM PDT 24
Peak memory 292216 kb
Host smart-3ac96593-b59f-4a1c-bc46-77d1f6a032ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427368892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flas
h_ctrl_intr_rd.427368892
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.4190031968
Short name T748
Test name
Test status
Simulation time 5873636400 ps
CPU time 132.51 seconds
Started Aug 18 06:07:51 PM PDT 24
Finished Aug 18 06:10:03 PM PDT 24
Peak memory 293756 kb
Host smart-86cc472b-1ed9-4416-affe-fa5a14737c2d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190031968 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.4190031968
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.3433568818
Short name T1058
Test name
Test status
Simulation time 9616179000 ps
CPU time 76.43 seconds
Started Aug 18 06:07:48 PM PDT 24
Finished Aug 18 06:09:04 PM PDT 24
Peak memory 261220 kb
Host smart-37246b7f-4057-4d40-846c-153c85b6b909
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433568818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.3
433568818
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.135774490
Short name T275
Test name
Test status
Simulation time 25826400 ps
CPU time 13.36 seconds
Started Aug 18 06:07:49 PM PDT 24
Finished Aug 18 06:08:02 PM PDT 24
Peak memory 265412 kb
Host smart-5a53d7e3-33ca-41d1-8170-066b281e6e43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135774490 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.135774490
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.2641905455
Short name T1103
Test name
Test status
Simulation time 5867611700 ps
CPU time 129.71 seconds
Started Aug 18 06:07:49 PM PDT 24
Finished Aug 18 06:09:59 PM PDT 24
Peak memory 265672 kb
Host smart-7a89b332-924f-4056-a8ec-20e42209027b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641905455 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.2641905455
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.861717568
Short name T909
Test name
Test status
Simulation time 185950300 ps
CPU time 132.35 seconds
Started Aug 18 06:07:50 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 260536 kb
Host smart-40d150bb-542d-463c-8201-8f6ca406259a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861717568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ot
p_reset.861717568
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.1835598703
Short name T743
Test name
Test status
Simulation time 4960688600 ps
CPU time 246.64 seconds
Started Aug 18 06:07:50 PM PDT 24
Finished Aug 18 06:11:57 PM PDT 24
Peak memory 263704 kb
Host smart-8db531e4-ad1b-45ed-9b0c-0efa4e0f371d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835598703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1835598703
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.987714830
Short name T846
Test name
Test status
Simulation time 113597800 ps
CPU time 13.54 seconds
Started Aug 18 06:07:49 PM PDT 24
Finished Aug 18 06:08:03 PM PDT 24
Peak memory 259688 kb
Host smart-4ee16450-1b24-431f-aca0-5b0078ab83c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987714830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.flash_ctrl_prog_reset.987714830
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.3968250117
Short name T771
Test name
Test status
Simulation time 2957187900 ps
CPU time 966.79 seconds
Started Aug 18 06:07:48 PM PDT 24
Finished Aug 18 06:23:55 PM PDT 24
Peak memory 288064 kb
Host smart-890687cb-2ce3-4c64-84e1-c120945649ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968250117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.3968250117
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.2435672436
Short name T1067
Test name
Test status
Simulation time 222638100 ps
CPU time 35.01 seconds
Started Aug 18 06:07:51 PM PDT 24
Finished Aug 18 06:08:26 PM PDT 24
Peak memory 276604 kb
Host smart-51285168-7dd6-462a-9689-1e52c2534c06
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435672436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.2435672436
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.3848849689
Short name T779
Test name
Test status
Simulation time 832819200 ps
CPU time 117.19 seconds
Started Aug 18 06:07:51 PM PDT 24
Finished Aug 18 06:09:48 PM PDT 24
Peak memory 282364 kb
Host smart-ca25ea5f-5c42-4717-b6bd-c6160bf79f28
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848849689 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.3848849689
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.2898771849
Short name T202
Test name
Test status
Simulation time 4017556900 ps
CPU time 623.37 seconds
Started Aug 18 06:07:50 PM PDT 24
Finished Aug 18 06:18:14 PM PDT 24
Peak memory 314888 kb
Host smart-7dc638b9-9484-4992-8eaa-b3f8c967d898
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898771849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.flash_ctrl_rw.2898771849
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.2399504602
Short name T374
Test name
Test status
Simulation time 51494900 ps
CPU time 31.35 seconds
Started Aug 18 06:07:50 PM PDT 24
Finished Aug 18 06:08:21 PM PDT 24
Peak memory 276120 kb
Host smart-317593d1-6a5b-4c28-8c9d-8b0100e4a672
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399504602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_rw_evict.2399504602
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.2383817960
Short name T321
Test name
Test status
Simulation time 71689000 ps
CPU time 31.21 seconds
Started Aug 18 06:07:50 PM PDT 24
Finished Aug 18 06:08:21 PM PDT 24
Peak memory 275468 kb
Host smart-001cd47f-05b6-4809-8648-ab7e187073cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383817960 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.2383817960
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.1749785239
Short name T813
Test name
Test status
Simulation time 23385800 ps
CPU time 73.41 seconds
Started Aug 18 06:07:49 PM PDT 24
Finished Aug 18 06:09:02 PM PDT 24
Peak memory 276088 kb
Host smart-0836a037-d759-467d-98cf-b340de0d47ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749785239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.1749785239
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.1028288587
Short name T1091
Test name
Test status
Simulation time 2990149700 ps
CPU time 182.63 seconds
Started Aug 18 06:07:55 PM PDT 24
Finished Aug 18 06:10:58 PM PDT 24
Peak memory 265776 kb
Host smart-0714f696-1b2c-4095-8331-2420b8bc948c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028288587 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.1028288587
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.1370890786
Short name T541
Test name
Test status
Simulation time 35332700 ps
CPU time 13.87 seconds
Started Aug 18 06:07:53 PM PDT 24
Finished Aug 18 06:08:07 PM PDT 24
Peak memory 265692 kb
Host smart-2515773a-4c7d-4e0c-8298-152ff3667064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370890786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
1370890786
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.3618666655
Short name T679
Test name
Test status
Simulation time 13321800 ps
CPU time 16.47 seconds
Started Aug 18 06:07:55 PM PDT 24
Finished Aug 18 06:08:12 PM PDT 24
Peak memory 284808 kb
Host smart-795f8bcd-2be8-4faf-b492-456f6353ef9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618666655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.3618666655
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3532426900
Short name T82
Test name
Test status
Simulation time 10035420900 ps
CPU time 92.45 seconds
Started Aug 18 06:07:54 PM PDT 24
Finished Aug 18 06:09:27 PM PDT 24
Peak memory 265752 kb
Host smart-543edfc8-ee95-4894-a9a5-c66db58b67d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532426900 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.3532426900
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.2850018112
Short name T836
Test name
Test status
Simulation time 25612600 ps
CPU time 13.3 seconds
Started Aug 18 06:07:53 PM PDT 24
Finished Aug 18 06:08:06 PM PDT 24
Peak memory 265160 kb
Host smart-fedb026d-5c4b-4c62-bd2a-cc36a5b4123b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850018112 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.2850018112
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.149042373
Short name T185
Test name
Test status
Simulation time 80134306600 ps
CPU time 882.87 seconds
Started Aug 18 06:07:56 PM PDT 24
Finished Aug 18 06:22:39 PM PDT 24
Peak memory 261512 kb
Host smart-0a9143b2-57b3-40e1-bf51-9c7c6ba42dcb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149042373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.flash_ctrl_hw_rma_reset.149042373
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.3572208506
Short name T100
Test name
Test status
Simulation time 29250307500 ps
CPU time 79.92 seconds
Started Aug 18 06:07:54 PM PDT 24
Finished Aug 18 06:09:14 PM PDT 24
Peak memory 263740 kb
Host smart-9e7d31e3-8369-437a-ab04-e1690217b7c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572208506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.3572208506
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.4093267841
Short name T565
Test name
Test status
Simulation time 7137590600 ps
CPU time 192.98 seconds
Started Aug 18 06:07:55 PM PDT 24
Finished Aug 18 06:11:08 PM PDT 24
Peak memory 292156 kb
Host smart-c0d18715-7a99-469b-96da-0b6e1b61bfed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093267841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.4093267841
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.798635591
Short name T32
Test name
Test status
Simulation time 14205957000 ps
CPU time 297.6 seconds
Started Aug 18 06:07:52 PM PDT 24
Finished Aug 18 06:12:50 PM PDT 24
Peak memory 290320 kb
Host smart-88db89ba-e26a-4af2-9de1-24ef4e04ddf1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798635591 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.798635591
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.2360536645
Short name T773
Test name
Test status
Simulation time 1579251700 ps
CPU time 78.5 seconds
Started Aug 18 06:07:52 PM PDT 24
Finished Aug 18 06:09:11 PM PDT 24
Peak memory 263788 kb
Host smart-96bac194-46bc-4bed-b9b5-d2454249d7b7
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360536645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2
360536645
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.1751415183
Short name T292
Test name
Test status
Simulation time 26031600 ps
CPU time 13.42 seconds
Started Aug 18 06:07:53 PM PDT 24
Finished Aug 18 06:08:06 PM PDT 24
Peak memory 260608 kb
Host smart-088780ce-dec0-4f49-92ec-928365b10274
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751415183 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.1751415183
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.3459360765
Short name T1052
Test name
Test status
Simulation time 7354568500 ps
CPU time 563.47 seconds
Started Aug 18 06:07:52 PM PDT 24
Finished Aug 18 06:17:16 PM PDT 24
Peak memory 275756 kb
Host smart-6590b110-13d1-4a75-bce9-e6d0196df589
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459360765 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.3459360765
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.2705995361
Short name T772
Test name
Test status
Simulation time 37169300 ps
CPU time 131.94 seconds
Started Aug 18 06:07:52 PM PDT 24
Finished Aug 18 06:10:04 PM PDT 24
Peak memory 264348 kb
Host smart-4e589a66-9d68-4e07-bbe3-b84a6df10bc4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705995361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.2705995361
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.126970792
Short name T962
Test name
Test status
Simulation time 151781000 ps
CPU time 110.59 seconds
Started Aug 18 06:07:53 PM PDT 24
Finished Aug 18 06:09:44 PM PDT 24
Peak memory 263804 kb
Host smart-be48b624-df01-449e-bcf8-a14ce35c75f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126970792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.126970792
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.976143334
Short name T400
Test name
Test status
Simulation time 396646200 ps
CPU time 27.73 seconds
Started Aug 18 06:07:54 PM PDT 24
Finished Aug 18 06:08:22 PM PDT 24
Peak memory 265784 kb
Host smart-1b250fc0-58af-4268-bf32-c2093362b0d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976143334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.flash_ctrl_prog_reset.976143334
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.3341849165
Short name T508
Test name
Test status
Simulation time 69750000 ps
CPU time 273.78 seconds
Started Aug 18 06:07:55 PM PDT 24
Finished Aug 18 06:12:29 PM PDT 24
Peak memory 282008 kb
Host smart-6ae35e2c-2701-4b7c-bbe2-9fca8f285f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341849165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.3341849165
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.1392917318
Short name T658
Test name
Test status
Simulation time 226372000 ps
CPU time 34.61 seconds
Started Aug 18 06:07:52 PM PDT 24
Finished Aug 18 06:08:27 PM PDT 24
Peak memory 274196 kb
Host smart-0746a24f-ec02-41ea-a2f3-5cc06b463bfa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392917318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.1392917318
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.2467264552
Short name T1021
Test name
Test status
Simulation time 1092698700 ps
CPU time 114.23 seconds
Started Aug 18 06:07:55 PM PDT 24
Finished Aug 18 06:09:49 PM PDT 24
Peak memory 290664 kb
Host smart-4959ad2d-5858-44c4-a7b9-796f1357f2d4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467264552 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.flash_ctrl_ro.2467264552
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.2841760930
Short name T607
Test name
Test status
Simulation time 3789975100 ps
CPU time 589.89 seconds
Started Aug 18 06:07:52 PM PDT 24
Finished Aug 18 06:17:42 PM PDT 24
Peak memory 310176 kb
Host smart-38de0fa3-479e-4d9b-8748-b13994e33415
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841760930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.2841760930
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.384494244
Short name T369
Test name
Test status
Simulation time 28176000 ps
CPU time 31 seconds
Started Aug 18 06:07:56 PM PDT 24
Finished Aug 18 06:08:27 PM PDT 24
Peak memory 275248 kb
Host smart-f3b1707e-9685-44d0-a996-56a8c1082557
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384494244 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.384494244
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.2721802018
Short name T827
Test name
Test status
Simulation time 5772307200 ps
CPU time 70.13 seconds
Started Aug 18 06:07:55 PM PDT 24
Finished Aug 18 06:09:05 PM PDT 24
Peak memory 265632 kb
Host smart-fde8a074-4f49-4189-a430-24cb2e92aba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721802018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.2721802018
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.163768037
Short name T631
Test name
Test status
Simulation time 22756300 ps
CPU time 98.54 seconds
Started Aug 18 06:07:51 PM PDT 24
Finished Aug 18 06:09:30 PM PDT 24
Peak memory 276452 kb
Host smart-4f9e43f8-551b-47c8-9580-0d145fd67b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163768037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.163768037
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.1624277694
Short name T604
Test name
Test status
Simulation time 4180167000 ps
CPU time 150.07 seconds
Started Aug 18 06:07:55 PM PDT 24
Finished Aug 18 06:10:25 PM PDT 24
Peak memory 261544 kb
Host smart-ab1c0cb6-957d-4a9c-bcc1-de86b5398355
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624277694 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.flash_ctrl_wo.1624277694
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.1204120851
Short name T10
Test name
Test status
Simulation time 13597800 ps
CPU time 13.81 seconds
Started Aug 18 06:04:19 PM PDT 24
Finished Aug 18 06:04:33 PM PDT 24
Peak memory 265480 kb
Host smart-fe24983e-863d-43f0-abe3-03d80615e0dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204120851 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.1204120851
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.1204984356
Short name T448
Test name
Test status
Simulation time 26447200 ps
CPU time 13.65 seconds
Started Aug 18 06:04:12 PM PDT 24
Finished Aug 18 06:04:26 PM PDT 24
Peak memory 265676 kb
Host smart-b836f910-2808-4125-97ab-4d1c70ee6972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204984356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.1
204984356
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.3835856224
Short name T388
Test name
Test status
Simulation time 178619300 ps
CPU time 14.18 seconds
Started Aug 18 06:04:14 PM PDT 24
Finished Aug 18 06:04:28 PM PDT 24
Peak memory 262008 kb
Host smart-3a878642-c4f1-4704-833b-f7ebf84c928f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835856224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.3835856224
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.1013055989
Short name T595
Test name
Test status
Simulation time 28727000 ps
CPU time 13.53 seconds
Started Aug 18 06:04:15 PM PDT 24
Finished Aug 18 06:04:29 PM PDT 24
Peak memory 284836 kb
Host smart-c1e8ba92-9485-4d08-93a8-08b74fb5e2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013055989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.1013055989
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.451538996
Short name T52
Test name
Test status
Simulation time 3116953300 ps
CPU time 214.34 seconds
Started Aug 18 06:04:08 PM PDT 24
Finished Aug 18 06:07:42 PM PDT 24
Peak memory 280172 kb
Host smart-de38cfa6-e10b-42f1-a27d-aab1b2bc364e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451538996 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_derr_detect.451538996
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.873497065
Short name T404
Test name
Test status
Simulation time 116282100 ps
CPU time 21.99 seconds
Started Aug 18 06:04:12 PM PDT 24
Finished Aug 18 06:04:34 PM PDT 24
Peak memory 266292 kb
Host smart-082f4eea-ce2f-451e-b9f1-76f7cb6bf484
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873497065 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.873497065
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.3238637231
Short name T161
Test name
Test status
Simulation time 10539041300 ps
CPU time 309.1 seconds
Started Aug 18 06:04:03 PM PDT 24
Finished Aug 18 06:09:12 PM PDT 24
Peak memory 263980 kb
Host smart-1718d504-f05f-4b13-904c-7b355be35e09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238637231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.3238637231
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.2565728371
Short name T121
Test name
Test status
Simulation time 21066644200 ps
CPU time 2347.96 seconds
Started Aug 18 06:04:01 PM PDT 24
Finished Aug 18 06:43:10 PM PDT 24
Peak memory 265600 kb
Host smart-cbfbd8c6-2e3e-4efc-a134-800c9ce2c9f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2565728371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.2565728371
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.3523662372
Short name T84
Test name
Test status
Simulation time 591309600 ps
CPU time 2575 seconds
Started Aug 18 06:04:02 PM PDT 24
Finished Aug 18 06:46:58 PM PDT 24
Peak memory 265700 kb
Host smart-db555507-688f-4e52-8c38-2df4df4051e9
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523662372 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.3523662372
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.1695090053
Short name T592
Test name
Test status
Simulation time 647983200 ps
CPU time 859.95 seconds
Started Aug 18 06:04:03 PM PDT 24
Finished Aug 18 06:18:23 PM PDT 24
Peak memory 273960 kb
Host smart-dedff3a7-62ea-4eac-bebc-b265af6581b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695090053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.1695090053
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.182740336
Short name T48
Test name
Test status
Simulation time 1369851600 ps
CPU time 26.35 seconds
Started Aug 18 06:04:00 PM PDT 24
Finished Aug 18 06:04:26 PM PDT 24
Peak memory 263160 kb
Host smart-1bf68aca-239c-4ff9-9e12-aaec64ffa351
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182740336 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_fetch_code.182740336
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.3752628159
Short name T1092
Test name
Test status
Simulation time 846929000 ps
CPU time 36.06 seconds
Started Aug 18 06:04:14 PM PDT 24
Finished Aug 18 06:04:50 PM PDT 24
Peak memory 263552 kb
Host smart-ef5f8b2e-1b3a-4cc2-af05-0f5c6e1bfb96
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752628159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.3752628159
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.2398367687
Short name T891
Test name
Test status
Simulation time 104438685900 ps
CPU time 2697.84 seconds
Started Aug 18 06:03:58 PM PDT 24
Finished Aug 18 06:48:56 PM PDT 24
Peak memory 263392 kb
Host smart-cbc5e400-a7dc-4c5b-ba6d-7a2153e5cd7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398367687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.2398367687
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_addr_infection.2813488375
Short name T1096
Test name
Test status
Simulation time 27582500 ps
CPU time 30.17 seconds
Started Aug 18 06:04:19 PM PDT 24
Finished Aug 18 06:04:50 PM PDT 24
Peak memory 275968 kb
Host smart-0daea6fd-fc6e-4c76-a5b7-a81c2048ef19
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813488375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_host_addr_infection.2813488375
Directory /workspace/2.flash_ctrl_host_addr_infection/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3358262853
Short name T109
Test name
Test status
Simulation time 567317181000 ps
CPU time 2490.58 seconds
Started Aug 18 06:04:02 PM PDT 24
Finished Aug 18 06:45:33 PM PDT 24
Peak memory 264720 kb
Host smart-5d76305a-9031-43fe-84c5-c2b3a1306bf8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358262853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.3358262853
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.3141695334
Short name T262
Test name
Test status
Simulation time 55744500 ps
CPU time 48.51 seconds
Started Aug 18 06:03:58 PM PDT 24
Finished Aug 18 06:04:47 PM PDT 24
Peak memory 263172 kb
Host smart-39b42637-b718-4062-9f59-727a9dc58033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141695334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.3141695334
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.4047257019
Short name T928
Test name
Test status
Simulation time 10019359600 ps
CPU time 186.58 seconds
Started Aug 18 06:04:16 PM PDT 24
Finished Aug 18 06:07:23 PM PDT 24
Peak memory 298344 kb
Host smart-ffab0b51-b922-4545-95d8-02069c698f98
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047257019 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.4047257019
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.3679755261
Short name T608
Test name
Test status
Simulation time 46881500 ps
CPU time 13.58 seconds
Started Aug 18 06:04:18 PM PDT 24
Finished Aug 18 06:04:32 PM PDT 24
Peak memory 260720 kb
Host smart-c7e9bbbb-8cd6-45f1-a6e8-b33e58f3d5b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679755261 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.3679755261
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.2666473850
Short name T872
Test name
Test status
Simulation time 405501997300 ps
CPU time 2264.67 seconds
Started Aug 18 06:03:58 PM PDT 24
Finished Aug 18 06:41:43 PM PDT 24
Peak memory 261348 kb
Host smart-cd067dc7-fc55-42fd-8a5d-daaf1b56ed0f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666473850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.2666473850
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.492197609
Short name T181
Test name
Test status
Simulation time 80146237000 ps
CPU time 919.95 seconds
Started Aug 18 06:04:00 PM PDT 24
Finished Aug 18 06:19:20 PM PDT 24
Peak memory 264620 kb
Host smart-3f6b767f-ec90-430c-b2b9-7f436469ffbb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492197609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_hw_rma_reset.492197609
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.2143547368
Short name T313
Test name
Test status
Simulation time 18845025300 ps
CPU time 156.75 seconds
Started Aug 18 06:03:59 PM PDT 24
Finished Aug 18 06:06:36 PM PDT 24
Peak memory 263856 kb
Host smart-288f0813-5db3-4375-8578-7c21198d6df2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143547368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.2143547368
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.1549474889
Short name T672
Test name
Test status
Simulation time 36950146600 ps
CPU time 573.79 seconds
Started Aug 18 06:04:08 PM PDT 24
Finished Aug 18 06:13:42 PM PDT 24
Peak memory 326848 kb
Host smart-7aeb9cab-e52b-448f-84fe-50d0d3568c84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549474889 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.1549474889
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.1408738773
Short name T33
Test name
Test status
Simulation time 1411265100 ps
CPU time 154.96 seconds
Started Aug 18 06:04:09 PM PDT 24
Finished Aug 18 06:06:44 PM PDT 24
Peak memory 292212 kb
Host smart-868abb51-f75c-4969-9c14-67f772782197
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408738773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.1408738773
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.1013210404
Short name T298
Test name
Test status
Simulation time 34874114500 ps
CPU time 278.34 seconds
Started Aug 18 06:04:09 PM PDT 24
Finished Aug 18 06:08:47 PM PDT 24
Peak memory 291480 kb
Host smart-270b3f18-e0fd-4bb7-b296-ce01133b7aba
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013210404 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.1013210404
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.3382525881
Short name T24
Test name
Test status
Simulation time 10776275600 ps
CPU time 72.59 seconds
Started Aug 18 06:04:08 PM PDT 24
Finished Aug 18 06:05:21 PM PDT 24
Peak memory 261196 kb
Host smart-28ad8fa0-63b3-4727-a698-90541ed7824f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382525881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.3382525881
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1599609918
Short name T707
Test name
Test status
Simulation time 91129221800 ps
CPU time 248.61 seconds
Started Aug 18 06:04:13 PM PDT 24
Finished Aug 18 06:08:22 PM PDT 24
Peak memory 265840 kb
Host smart-2899d5c5-6236-4b6d-861c-12ed14245ec7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159
9609918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1599609918
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.3240799038
Short name T571
Test name
Test status
Simulation time 73182000 ps
CPU time 13.51 seconds
Started Aug 18 06:04:15 PM PDT 24
Finished Aug 18 06:04:29 PM PDT 24
Peak memory 265284 kb
Host smart-65cea12c-83e4-4db1-b950-e6ba2e921e98
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240799038 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.3240799038
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.2051943669
Short name T219
Test name
Test status
Simulation time 3759485900 ps
CPU time 128.37 seconds
Started Aug 18 06:04:00 PM PDT 24
Finished Aug 18 06:06:09 PM PDT 24
Peak memory 265728 kb
Host smart-ae2024ab-bb46-4713-8704-99cef7f45cf7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051943669 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.2051943669
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.3640855243
Short name T1005
Test name
Test status
Simulation time 80875300 ps
CPU time 131.98 seconds
Started Aug 18 06:04:00 PM PDT 24
Finished Aug 18 06:06:12 PM PDT 24
Peak memory 265660 kb
Host smart-d152cbba-a096-4c98-905e-b3773b2a889d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640855243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.3640855243
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.2153767905
Short name T1083
Test name
Test status
Simulation time 4542400300 ps
CPU time 178.46 seconds
Started Aug 18 06:04:07 PM PDT 24
Finished Aug 18 06:07:05 PM PDT 24
Peak memory 282432 kb
Host smart-146f39ad-a831-40eb-a682-149e4ef73429
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153767905 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.2153767905
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.579970375
Short name T212
Test name
Test status
Simulation time 29693800 ps
CPU time 13.88 seconds
Started Aug 18 06:04:15 PM PDT 24
Finished Aug 18 06:04:29 PM PDT 24
Peak memory 261672 kb
Host smart-4686965c-7035-45e4-978b-0d3a75d5863a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=579970375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.579970375
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.1675552019
Short name T580
Test name
Test status
Simulation time 738463500 ps
CPU time 367.86 seconds
Started Aug 18 06:03:59 PM PDT 24
Finished Aug 18 06:10:07 PM PDT 24
Peak memory 263680 kb
Host smart-bf258ded-08e5-44f4-98ed-2f45b3d27ec4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1675552019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.1675552019
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.49539935
Short name T874
Test name
Test status
Simulation time 47596200 ps
CPU time 13.25 seconds
Started Aug 18 06:04:07 PM PDT 24
Finished Aug 18 06:04:21 PM PDT 24
Peak memory 259556 kb
Host smart-884787ff-e948-43b3-9f90-790424cda2a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49539935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U
VM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_prog_reset.49539935
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.2799437897
Short name T2
Test name
Test status
Simulation time 1488096100 ps
CPU time 679.8 seconds
Started Aug 18 06:04:00 PM PDT 24
Finished Aug 18 06:15:20 PM PDT 24
Peak memory 285188 kb
Host smart-49bd74f4-487b-4d2f-a67a-c47479d07556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799437897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.2799437897
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.1431028804
Short name T1098
Test name
Test status
Simulation time 55563900 ps
CPU time 101.1 seconds
Started Aug 18 06:03:58 PM PDT 24
Finished Aug 18 06:05:40 PM PDT 24
Peak memory 263356 kb
Host smart-b9855bd4-5dd8-430d-8178-29d6f90dd6c4
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1431028804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1431028804
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.2910423045
Short name T985
Test name
Test status
Simulation time 151351900 ps
CPU time 35.51 seconds
Started Aug 18 06:04:07 PM PDT 24
Finished Aug 18 06:04:43 PM PDT 24
Peak memory 274092 kb
Host smart-65c63b3b-3bf8-4aca-810e-ae51cf4addd7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910423045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.2910423045
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.1265981911
Short name T924
Test name
Test status
Simulation time 57669600 ps
CPU time 22.67 seconds
Started Aug 18 06:04:09 PM PDT 24
Finished Aug 18 06:04:32 PM PDT 24
Peak memory 265492 kb
Host smart-b1e17f29-36fb-449e-9e9c-6fed42891499
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265981911 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.1265981911
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.2848278504
Short name T451
Test name
Test status
Simulation time 26048800 ps
CPU time 21.3 seconds
Started Aug 18 06:04:09 PM PDT 24
Finished Aug 18 06:04:30 PM PDT 24
Peak memory 265900 kb
Host smart-b0e16b25-acc7-440f-996a-ec34ef01afea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848278504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.2848278504
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.1094506674
Short name T179
Test name
Test status
Simulation time 105346451500 ps
CPU time 953.77 seconds
Started Aug 18 06:04:15 PM PDT 24
Finished Aug 18 06:20:09 PM PDT 24
Peak memory 261864 kb
Host smart-e05c2b33-2908-45c9-8913-7dc0132b2117
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094506674 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.1094506674
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.1203138857
Short name T201
Test name
Test status
Simulation time 546900000 ps
CPU time 103.4 seconds
Started Aug 18 06:04:07 PM PDT 24
Finished Aug 18 06:05:50 PM PDT 24
Peak memory 297988 kb
Host smart-8d412051-4089-4860-8b49-06e36b10964a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203138857 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_ro.1203138857
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.4216575804
Short name T983
Test name
Test status
Simulation time 506480800 ps
CPU time 109.39 seconds
Started Aug 18 06:04:08 PM PDT 24
Finished Aug 18 06:05:58 PM PDT 24
Peak memory 282432 kb
Host smart-2672a990-8d35-458f-9d4b-c729172894b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4216575804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.4216575804
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.3736294079
Short name T134
Test name
Test status
Simulation time 3782188300 ps
CPU time 577.42 seconds
Started Aug 18 06:04:09 PM PDT 24
Finished Aug 18 06:13:47 PM PDT 24
Peak memory 310796 kb
Host smart-3ab50f7f-67b1-46d6-bf4d-f31554b4d171
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736294079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_rw.3736294079
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.2843245619
Short name T1082
Test name
Test status
Simulation time 1569225900 ps
CPU time 228.74 seconds
Started Aug 18 06:04:08 PM PDT 24
Finished Aug 18 06:07:57 PM PDT 24
Peak memory 289172 kb
Host smart-bc3eeb88-a73b-4d29-b8dd-300bd08bb525
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843245619 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_derr.2843245619
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.1096836395
Short name T988
Test name
Test status
Simulation time 28493400 ps
CPU time 31.35 seconds
Started Aug 18 06:04:11 PM PDT 24
Finished Aug 18 06:04:43 PM PDT 24
Peak memory 275476 kb
Host smart-cb5bd76d-9e3e-4cc4-bac4-764081cd757b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096836395 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.1096836395
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.3154370955
Short name T1077
Test name
Test status
Simulation time 1388218800 ps
CPU time 210.65 seconds
Started Aug 18 06:04:11 PM PDT 24
Finished Aug 18 06:07:42 PM PDT 24
Peak memory 296148 kb
Host smart-9f19be2f-beb4-4cdb-a34a-d5d515fc94e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154370955 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.flash_ctrl_rw_serr.3154370955
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.2581743342
Short name T1045
Test name
Test status
Simulation time 3460503000 ps
CPU time 99.76 seconds
Started Aug 18 06:04:08 PM PDT 24
Finished Aug 18 06:05:48 PM PDT 24
Peak memory 265952 kb
Host smart-6597ba9d-6cac-47e4-b358-fdbc343fd2a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581743342 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.2581743342
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.3313423331
Short name T945
Test name
Test status
Simulation time 2135222000 ps
CPU time 62.45 seconds
Started Aug 18 06:04:09 PM PDT 24
Finished Aug 18 06:05:11 PM PDT 24
Peak memory 274528 kb
Host smart-42ad0788-0038-4e82-9aea-28ba2e89d34c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313423331 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.3313423331
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.887377067
Short name T938
Test name
Test status
Simulation time 27912100 ps
CPU time 50.53 seconds
Started Aug 18 06:03:58 PM PDT 24
Finished Aug 18 06:04:49 PM PDT 24
Peak memory 271676 kb
Host smart-eae1b3ca-2906-4c0e-ab26-d5fc688c913c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887377067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.887377067
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.4072715214
Short name T842
Test name
Test status
Simulation time 54139000 ps
CPU time 26.41 seconds
Started Aug 18 06:04:01 PM PDT 24
Finished Aug 18 06:04:27 PM PDT 24
Peak memory 260284 kb
Host smart-1cc3d215-ba16-42ba-9569-8f7b0823355d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072715214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.4072715214
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.731191971
Short name T1060
Test name
Test status
Simulation time 235718900 ps
CPU time 180.76 seconds
Started Aug 18 06:04:14 PM PDT 24
Finished Aug 18 06:07:15 PM PDT 24
Peak memory 271464 kb
Host smart-dac52ee7-7dd4-42c4-a1c1-c4a49b7a90d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731191971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress
_all.731191971
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.1467260227
Short name T536
Test name
Test status
Simulation time 55550600 ps
CPU time 26.43 seconds
Started Aug 18 06:04:01 PM PDT 24
Finished Aug 18 06:04:28 PM PDT 24
Peak memory 260324 kb
Host smart-b67e10a8-5a93-4b37-b78a-c0c56b5ebc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467260227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.1467260227
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.1573730726
Short name T643
Test name
Test status
Simulation time 4590918000 ps
CPU time 193.06 seconds
Started Aug 18 06:04:12 PM PDT 24
Finished Aug 18 06:07:25 PM PDT 24
Peak memory 260564 kb
Host smart-83900f54-5f9e-4121-8081-c20e75f8781f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573730726 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_wo.1573730726
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.1132716399
Short name T587
Test name
Test status
Simulation time 71648400 ps
CPU time 13.66 seconds
Started Aug 18 06:08:02 PM PDT 24
Finished Aug 18 06:08:16 PM PDT 24
Peak memory 265660 kb
Host smart-97074647-48b2-4899-b3ed-b970279a10ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132716399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
1132716399
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.4245096559
Short name T898
Test name
Test status
Simulation time 26349100 ps
CPU time 16.11 seconds
Started Aug 18 06:08:00 PM PDT 24
Finished Aug 18 06:08:16 PM PDT 24
Peak memory 283576 kb
Host smart-4a152d8c-29b5-4054-9220-f40be202dbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245096559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.4245096559
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.2243335626
Short name T76
Test name
Test status
Simulation time 15674900 ps
CPU time 21.76 seconds
Started Aug 18 06:07:56 PM PDT 24
Finished Aug 18 06:08:18 PM PDT 24
Peak memory 274152 kb
Host smart-16921f09-387a-41ba-af62-96a30045a803
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243335626 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.2243335626
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.3578453691
Short name T482
Test name
Test status
Simulation time 39159893800 ps
CPU time 231.76 seconds
Started Aug 18 06:07:55 PM PDT 24
Finished Aug 18 06:11:47 PM PDT 24
Peak memory 263824 kb
Host smart-488ddc66-81c4-4b96-9342-bdb82e58b836
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578453691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.3578453691
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.190642133
Short name T979
Test name
Test status
Simulation time 1498700600 ps
CPU time 147.2 seconds
Started Aug 18 06:07:56 PM PDT 24
Finished Aug 18 06:10:24 PM PDT 24
Peak memory 291736 kb
Host smart-1ac50e04-dc3d-4c0e-b08b-3ed40acc33b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190642133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flas
h_ctrl_intr_rd.190642133
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.3270932622
Short name T935
Test name
Test status
Simulation time 5863309000 ps
CPU time 133.54 seconds
Started Aug 18 06:07:53 PM PDT 24
Finished Aug 18 06:10:07 PM PDT 24
Peak memory 293496 kb
Host smart-c56d84ec-074c-4c73-9770-088eb3384a11
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270932622 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.3270932622
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.3955893872
Short name T765
Test name
Test status
Simulation time 44795600 ps
CPU time 131.81 seconds
Started Aug 18 06:07:54 PM PDT 24
Finished Aug 18 06:10:06 PM PDT 24
Peak memory 260392 kb
Host smart-602a0914-ccdd-46ad-92a6-d8e89bae642c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955893872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.3955893872
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.2449139327
Short name T525
Test name
Test status
Simulation time 4940946600 ps
CPU time 180.7 seconds
Started Aug 18 06:07:56 PM PDT 24
Finished Aug 18 06:10:57 PM PDT 24
Peak memory 260828 kb
Host smart-822c95e9-593e-458c-a15f-bcfa59eed031
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449139327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.flash_ctrl_prog_reset.2449139327
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.811546503
Short name T375
Test name
Test status
Simulation time 44228600 ps
CPU time 33.01 seconds
Started Aug 18 06:07:55 PM PDT 24
Finished Aug 18 06:08:28 PM PDT 24
Peak memory 279072 kb
Host smart-c1d94c26-044c-4655-a0dd-4ae8f937c57c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811546503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_rw_evict.811546503
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.798460746
Short name T412
Test name
Test status
Simulation time 542715800 ps
CPU time 63.94 seconds
Started Aug 18 06:08:03 PM PDT 24
Finished Aug 18 06:09:07 PM PDT 24
Peak memory 265480 kb
Host smart-e3f053f2-b44d-4af2-9128-497eb8ebbfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798460746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.798460746
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.2900846207
Short name T665
Test name
Test status
Simulation time 35046200 ps
CPU time 147.54 seconds
Started Aug 18 06:07:53 PM PDT 24
Finished Aug 18 06:10:21 PM PDT 24
Peak memory 277580 kb
Host smart-377998e3-44eb-4d97-805a-c8274bac2b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900846207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2900846207
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.836964267
Short name T825
Test name
Test status
Simulation time 38704500 ps
CPU time 13.91 seconds
Started Aug 18 06:08:00 PM PDT 24
Finished Aug 18 06:08:14 PM PDT 24
Peak memory 265796 kb
Host smart-d58b5a3a-6a8d-437e-a812-a84d2ef6df7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836964267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.836964267
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.4208090976
Short name T180
Test name
Test status
Simulation time 53656800 ps
CPU time 13.65 seconds
Started Aug 18 06:08:01 PM PDT 24
Finished Aug 18 06:08:15 PM PDT 24
Peak memory 284792 kb
Host smart-2d342f6e-e96b-4e9d-8880-28534f4ad62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208090976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.4208090976
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.1682780416
Short name T322
Test name
Test status
Simulation time 3060649100 ps
CPU time 125.31 seconds
Started Aug 18 06:08:00 PM PDT 24
Finished Aug 18 06:10:06 PM PDT 24
Peak memory 261208 kb
Host smart-961b75c9-c0ef-4420-8d99-9f4f5d8acdf6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682780416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.1682780416
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.998412623
Short name T443
Test name
Test status
Simulation time 31488314200 ps
CPU time 262.53 seconds
Started Aug 18 06:08:03 PM PDT 24
Finished Aug 18 06:12:25 PM PDT 24
Peak memory 285596 kb
Host smart-35b72bc7-d5b2-451f-af44-fa9f122084b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998412623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flas
h_ctrl_intr_rd.998412623
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.1704721404
Short name T88
Test name
Test status
Simulation time 12552743400 ps
CPU time 280.57 seconds
Started Aug 18 06:07:59 PM PDT 24
Finished Aug 18 06:12:40 PM PDT 24
Peak memory 293952 kb
Host smart-deb6049a-d21a-49c2-a833-9f30678cbd5d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704721404 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.1704721404
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.1248556823
Short name T436
Test name
Test status
Simulation time 20877200 ps
CPU time 13.54 seconds
Started Aug 18 06:08:01 PM PDT 24
Finished Aug 18 06:08:15 PM PDT 24
Peak memory 259524 kb
Host smart-9a211b70-7c07-40da-89fd-a7accda0a5db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248556823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.flash_ctrl_prog_reset.1248556823
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.3826314385
Short name T824
Test name
Test status
Simulation time 5124459500 ps
CPU time 70.49 seconds
Started Aug 18 06:08:02 PM PDT 24
Finished Aug 18 06:09:12 PM PDT 24
Peak memory 264196 kb
Host smart-57059611-91ec-47ad-9cca-772d2fc0f984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826314385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3826314385
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.2560300233
Short name T1049
Test name
Test status
Simulation time 52934000 ps
CPU time 123.58 seconds
Started Aug 18 06:08:02 PM PDT 24
Finished Aug 18 06:10:06 PM PDT 24
Peak memory 279908 kb
Host smart-90eeeb36-c1cf-4c98-a2e4-e1e237b8a870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560300233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2560300233
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.2568016903
Short name T439
Test name
Test status
Simulation time 60399900 ps
CPU time 13.84 seconds
Started Aug 18 06:08:07 PM PDT 24
Finished Aug 18 06:08:21 PM PDT 24
Peak memory 265716 kb
Host smart-38ad038f-c590-4f29-aee3-e88a3f453863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568016903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
2568016903
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.1370994597
Short name T730
Test name
Test status
Simulation time 17051700 ps
CPU time 13.32 seconds
Started Aug 18 06:08:09 PM PDT 24
Finished Aug 18 06:08:22 PM PDT 24
Peak memory 284756 kb
Host smart-a993358f-00bc-402f-8013-06d2c19ec90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370994597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.1370994597
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.1407609840
Short name T833
Test name
Test status
Simulation time 15797400 ps
CPU time 21.96 seconds
Started Aug 18 06:08:10 PM PDT 24
Finished Aug 18 06:08:32 PM PDT 24
Peak memory 274088 kb
Host smart-55be80dd-3119-4d0d-9984-24b6e02e42dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407609840 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.1407609840
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.4242109002
Short name T784
Test name
Test status
Simulation time 2068967000 ps
CPU time 46.74 seconds
Started Aug 18 06:08:02 PM PDT 24
Finished Aug 18 06:08:49 PM PDT 24
Peak memory 263776 kb
Host smart-52e30cc5-cdb5-4685-9837-0bd6c8143d24
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242109002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.4242109002
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.25675418
Short name T582
Test name
Test status
Simulation time 26607924300 ps
CPU time 318.99 seconds
Started Aug 18 06:08:03 PM PDT 24
Finished Aug 18 06:13:22 PM PDT 24
Peak memory 292132 kb
Host smart-71e98329-c339-405f-b9c1-a8ceba301d57
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25675418 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.25675418
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.3974840798
Short name T953
Test name
Test status
Simulation time 61533500 ps
CPU time 132.77 seconds
Started Aug 18 06:08:05 PM PDT 24
Finished Aug 18 06:10:18 PM PDT 24
Peak memory 260348 kb
Host smart-678fb9c2-e632-43bf-ab69-b0a6de7816c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974840798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.3974840798
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.1058355785
Short name T483
Test name
Test status
Simulation time 8877243900 ps
CPU time 185.43 seconds
Started Aug 18 06:08:00 PM PDT 24
Finished Aug 18 06:11:05 PM PDT 24
Peak memory 260608 kb
Host smart-af156cc4-d760-4995-bdf1-d2414cb13df9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058355785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.flash_ctrl_prog_reset.1058355785
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.3768319050
Short name T1014
Test name
Test status
Simulation time 2057699300 ps
CPU time 66.6 seconds
Started Aug 18 06:08:09 PM PDT 24
Finished Aug 18 06:09:16 PM PDT 24
Peak memory 264176 kb
Host smart-50ed21ff-6d12-4b82-b309-34dd3ca61662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768319050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.3768319050
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.3233891666
Short name T1015
Test name
Test status
Simulation time 62773600 ps
CPU time 52.55 seconds
Started Aug 18 06:08:04 PM PDT 24
Finished Aug 18 06:08:56 PM PDT 24
Peak memory 271840 kb
Host smart-46ab6c80-e1d0-4e11-9850-b11afaed2a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233891666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.3233891666
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.3265749655
Short name T869
Test name
Test status
Simulation time 50697400 ps
CPU time 13.78 seconds
Started Aug 18 06:08:09 PM PDT 24
Finished Aug 18 06:08:23 PM PDT 24
Peak memory 265716 kb
Host smart-f763a400-ddde-4b4e-9b9b-33ef64ce683b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265749655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
3265749655
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.485773986
Short name T566
Test name
Test status
Simulation time 23267100 ps
CPU time 15.75 seconds
Started Aug 18 06:08:11 PM PDT 24
Finished Aug 18 06:08:27 PM PDT 24
Peak memory 283628 kb
Host smart-67441498-218f-472e-b51a-868d9f5ab69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485773986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.485773986
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.170359115
Short name T475
Test name
Test status
Simulation time 21457100 ps
CPU time 20.89 seconds
Started Aug 18 06:08:08 PM PDT 24
Finished Aug 18 06:08:29 PM PDT 24
Peak memory 274036 kb
Host smart-d61b4c21-9a16-4099-9389-d25cc8628435
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170359115 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.170359115
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.1275795888
Short name T452
Test name
Test status
Simulation time 1806805600 ps
CPU time 39.35 seconds
Started Aug 18 06:08:07 PM PDT 24
Finished Aug 18 06:08:46 PM PDT 24
Peak memory 261164 kb
Host smart-97fe14a0-8e17-4118-be38-338c8c74442c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275795888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.1275795888
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2634018496
Short name T342
Test name
Test status
Simulation time 36564576200 ps
CPU time 351.59 seconds
Started Aug 18 06:08:08 PM PDT 24
Finished Aug 18 06:14:00 PM PDT 24
Peak memory 293880 kb
Host smart-97a70642-94e5-49e1-8612-9df839364a70
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634018496 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2634018496
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.711561127
Short name T677
Test name
Test status
Simulation time 277349400 ps
CPU time 14.05 seconds
Started Aug 18 06:08:08 PM PDT 24
Finished Aug 18 06:08:23 PM PDT 24
Peak memory 265636 kb
Host smart-ca844198-9128-445a-986c-c27e551cc191
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711561127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.flash_ctrl_prog_reset.711561127
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.359179859
Short name T570
Test name
Test status
Simulation time 265189000 ps
CPU time 31.13 seconds
Started Aug 18 06:08:07 PM PDT 24
Finished Aug 18 06:08:38 PM PDT 24
Peak memory 268284 kb
Host smart-7abc31d5-7d36-4bb5-b308-42a289f43cd9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359179859 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.359179859
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.2873679552
Short name T303
Test name
Test status
Simulation time 2408037300 ps
CPU time 82.69 seconds
Started Aug 18 06:08:08 PM PDT 24
Finished Aug 18 06:09:30 PM PDT 24
Peak memory 264288 kb
Host smart-4f4497e9-903b-44cd-a1a6-fdd4e4d39ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873679552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.2873679552
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.2240189083
Short name T1078
Test name
Test status
Simulation time 31877900 ps
CPU time 173.05 seconds
Started Aug 18 06:08:10 PM PDT 24
Finished Aug 18 06:11:03 PM PDT 24
Peak memory 277800 kb
Host smart-180e2139-e128-4dbe-93a9-c3107a7fc9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240189083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.2240189083
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.144214776
Short name T900
Test name
Test status
Simulation time 34335000 ps
CPU time 13.81 seconds
Started Aug 18 06:08:19 PM PDT 24
Finished Aug 18 06:08:33 PM PDT 24
Peak memory 258548 kb
Host smart-7c99143f-6786-41e1-afe8-d6787aa602cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144214776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.144214776
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.3558408248
Short name T949
Test name
Test status
Simulation time 34284100 ps
CPU time 15.69 seconds
Started Aug 18 06:08:19 PM PDT 24
Finished Aug 18 06:08:35 PM PDT 24
Peak memory 284536 kb
Host smart-3df7944d-9d49-45a8-b24d-c5e9783d0358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558408248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3558408248
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.2654352248
Short name T399
Test name
Test status
Simulation time 10524400 ps
CPU time 22.02 seconds
Started Aug 18 06:08:17 PM PDT 24
Finished Aug 18 06:08:39 PM PDT 24
Peak memory 275396 kb
Host smart-93725d93-8839-421b-8c8b-3f099a07fd21
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654352248 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.2654352248
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.808350867
Short name T766
Test name
Test status
Simulation time 2736578700 ps
CPU time 84.87 seconds
Started Aug 18 06:08:08 PM PDT 24
Finished Aug 18 06:09:33 PM PDT 24
Peak memory 263880 kb
Host smart-1c27216c-29a2-4eef-9fc0-90aca2059179
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808350867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_h
w_sec_otp.808350867
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.564230482
Short name T830
Test name
Test status
Simulation time 1228157800 ps
CPU time 186.56 seconds
Started Aug 18 06:08:07 PM PDT 24
Finished Aug 18 06:11:13 PM PDT 24
Peak memory 294780 kb
Host smart-85db810a-00ad-49cf-a127-8d6b1a02feaa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564230482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flas
h_ctrl_intr_rd.564230482
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.919549364
Short name T585
Test name
Test status
Simulation time 12722485000 ps
CPU time 130.22 seconds
Started Aug 18 06:08:10 PM PDT 24
Finished Aug 18 06:10:21 PM PDT 24
Peak memory 293496 kb
Host smart-b2e82e79-dd14-423a-a6aa-ef0bbe0dcbce
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919549364 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.919549364
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.1490879739
Short name T71
Test name
Test status
Simulation time 139938800 ps
CPU time 129.93 seconds
Started Aug 18 06:08:10 PM PDT 24
Finished Aug 18 06:10:20 PM PDT 24
Peak memory 265456 kb
Host smart-7c09eb2b-e500-453d-9765-026ca8aff999
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490879739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o
tp_reset.1490879739
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.2998175891
Short name T1018
Test name
Test status
Simulation time 36659700 ps
CPU time 13.52 seconds
Started Aug 18 06:08:07 PM PDT 24
Finished Aug 18 06:08:20 PM PDT 24
Peak memory 259488 kb
Host smart-f61bc4bb-85ba-4dd3-98a9-5bae0a1098e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998175891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.flash_ctrl_prog_reset.2998175891
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.2897309345
Short name T927
Test name
Test status
Simulation time 47253700 ps
CPU time 30.8 seconds
Started Aug 18 06:08:10 PM PDT 24
Finished Aug 18 06:08:40 PM PDT 24
Peak memory 276304 kb
Host smart-ceef16d7-df32-45c8-ad30-0775ffda3a66
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897309345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl
ash_ctrl_rw_evict.2897309345
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.2388262966
Short name T761
Test name
Test status
Simulation time 48962500 ps
CPU time 32.13 seconds
Started Aug 18 06:08:07 PM PDT 24
Finished Aug 18 06:08:40 PM PDT 24
Peak memory 275312 kb
Host smart-503776c9-7803-4ce3-a444-47a9978949f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388262966 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.2388262966
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.3174316539
Short name T1006
Test name
Test status
Simulation time 1328958900 ps
CPU time 58.68 seconds
Started Aug 18 06:08:17 PM PDT 24
Finished Aug 18 06:09:16 PM PDT 24
Peak memory 264380 kb
Host smart-7f627c21-b286-47a4-bfe7-fd8e056f0f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174316539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3174316539
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.2378164888
Short name T39
Test name
Test status
Simulation time 21365500 ps
CPU time 76.23 seconds
Started Aug 18 06:08:10 PM PDT 24
Finished Aug 18 06:09:26 PM PDT 24
Peak memory 277052 kb
Host smart-fd5ad53d-ecc6-4fd6-8c68-413e7357629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378164888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.2378164888
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.2389757372
Short name T930
Test name
Test status
Simulation time 20455500 ps
CPU time 16.14 seconds
Started Aug 18 06:08:16 PM PDT 24
Finished Aug 18 06:08:32 PM PDT 24
Peak memory 283536 kb
Host smart-113abe28-2988-438f-aece-6a6fc28f4fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389757372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.2389757372
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.1817107197
Short name T329
Test name
Test status
Simulation time 25685400 ps
CPU time 20.98 seconds
Started Aug 18 06:08:15 PM PDT 24
Finished Aug 18 06:08:36 PM PDT 24
Peak memory 274064 kb
Host smart-8cab5e81-868c-4252-9007-d653f7047287
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817107197 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.1817107197
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.3362182141
Short name T320
Test name
Test status
Simulation time 1742349900 ps
CPU time 33.72 seconds
Started Aug 18 06:08:16 PM PDT 24
Finished Aug 18 06:08:50 PM PDT 24
Peak memory 261116 kb
Host smart-3259f67e-5f9f-4227-843e-6adb6f02e1c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362182141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.3362182141
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.2685901413
Short name T1036
Test name
Test status
Simulation time 1602220200 ps
CPU time 145.66 seconds
Started Aug 18 06:08:16 PM PDT 24
Finished Aug 18 06:10:41 PM PDT 24
Peak memory 294836 kb
Host smart-79278291-aa35-4a90-bda9-18d0d0ffdf6b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685901413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla
sh_ctrl_intr_rd.2685901413
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.2530684064
Short name T349
Test name
Test status
Simulation time 6117482700 ps
CPU time 143.72 seconds
Started Aug 18 06:08:14 PM PDT 24
Finished Aug 18 06:10:38 PM PDT 24
Peak memory 286000 kb
Host smart-7b1618cc-d8ee-4e4b-b896-5a6257ffb317
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530684064 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.2530684064
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.1534100763
Short name T494
Test name
Test status
Simulation time 36816000 ps
CPU time 132.16 seconds
Started Aug 18 06:08:16 PM PDT 24
Finished Aug 18 06:10:29 PM PDT 24
Peak memory 265524 kb
Host smart-31a5ee88-2a72-4ad9-80af-a9f6d73478f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534100763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.1534100763
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.2695708445
Short name T695
Test name
Test status
Simulation time 33390600 ps
CPU time 13.47 seconds
Started Aug 18 06:08:15 PM PDT 24
Finished Aug 18 06:08:29 PM PDT 24
Peak memory 259604 kb
Host smart-16fcb1b0-2b14-43eb-bd6c-cbd2515f2c89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695708445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.flash_ctrl_prog_reset.2695708445
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.3340490500
Short name T862
Test name
Test status
Simulation time 644765000 ps
CPU time 67.26 seconds
Started Aug 18 06:08:15 PM PDT 24
Finished Aug 18 06:09:22 PM PDT 24
Peak memory 265408 kb
Host smart-7c157612-0ba8-419e-84db-da214e8006d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340490500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.3340490500
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.537572994
Short name T818
Test name
Test status
Simulation time 41588500 ps
CPU time 49.15 seconds
Started Aug 18 06:08:14 PM PDT 24
Finished Aug 18 06:09:03 PM PDT 24
Peak memory 271748 kb
Host smart-4f6e7f25-c875-456a-bdcf-85daa7737a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537572994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.537572994
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.2986193939
Short name T884
Test name
Test status
Simulation time 176315000 ps
CPU time 13.86 seconds
Started Aug 18 06:08:25 PM PDT 24
Finished Aug 18 06:08:39 PM PDT 24
Peak memory 258828 kb
Host smart-78897e9b-6d57-456f-a6e8-7de465e7bfde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986193939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
2986193939
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.61742656
Short name T1008
Test name
Test status
Simulation time 27024000 ps
CPU time 13.51 seconds
Started Aug 18 06:08:25 PM PDT 24
Finished Aug 18 06:08:38 PM PDT 24
Peak memory 284684 kb
Host smart-7389ac31-f15a-4300-b029-d307eb86c7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61742656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.61742656
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.1065950777
Short name T95
Test name
Test status
Simulation time 13871400 ps
CPU time 21.77 seconds
Started Aug 18 06:08:24 PM PDT 24
Finished Aug 18 06:08:46 PM PDT 24
Peak memory 275280 kb
Host smart-5e61bc95-f96b-42e5-942a-cceaa54b7b57
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065950777 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.1065950777
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.499141019
Short name T866
Test name
Test status
Simulation time 1523285400 ps
CPU time 138.17 seconds
Started Aug 18 06:08:15 PM PDT 24
Finished Aug 18 06:10:33 PM PDT 24
Peak memory 261576 kb
Host smart-59ab9334-f00a-40b0-b704-6a88efe8df9b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499141019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_h
w_sec_otp.499141019
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.3078615574
Short name T323
Test name
Test status
Simulation time 593148500 ps
CPU time 118.71 seconds
Started Aug 18 06:08:18 PM PDT 24
Finished Aug 18 06:10:17 PM PDT 24
Peak memory 294776 kb
Host smart-28e353d4-4557-4907-b7ca-d05df2634bd9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078615574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.3078615574
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.3675025349
Short name T638
Test name
Test status
Simulation time 14800009700 ps
CPU time 144.54 seconds
Started Aug 18 06:08:25 PM PDT 24
Finished Aug 18 06:10:49 PM PDT 24
Peak memory 293756 kb
Host smart-c5e4aa21-886b-4680-a0f9-4217c7871a2b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675025349 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.3675025349
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.4282599234
Short name T912
Test name
Test status
Simulation time 67421500 ps
CPU time 130.47 seconds
Started Aug 18 06:08:18 PM PDT 24
Finished Aug 18 06:10:28 PM PDT 24
Peak memory 260656 kb
Host smart-60a1f497-d505-4f14-a358-7b4165749022
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282599234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.4282599234
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.2291855009
Short name T725
Test name
Test status
Simulation time 67419000 ps
CPU time 14.13 seconds
Started Aug 18 06:08:24 PM PDT 24
Finished Aug 18 06:08:39 PM PDT 24
Peak memory 259760 kb
Host smart-1cf53577-a97c-4682-a82d-9dda013f514b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291855009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.flash_ctrl_prog_reset.2291855009
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.1958843065
Short name T376
Test name
Test status
Simulation time 28321700 ps
CPU time 31.26 seconds
Started Aug 18 06:08:25 PM PDT 24
Finished Aug 18 06:08:57 PM PDT 24
Peak memory 276248 kb
Host smart-74d72312-c764-43ab-8b82-bbde76b8c9dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958843065 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.1958843065
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.800577106
Short name T521
Test name
Test status
Simulation time 97811700 ps
CPU time 74.84 seconds
Started Aug 18 06:08:18 PM PDT 24
Finished Aug 18 06:09:33 PM PDT 24
Peak memory 276372 kb
Host smart-8bbde788-72ad-47a5-957f-736bce9169f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800577106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.800577106
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.1718403105
Short name T856
Test name
Test status
Simulation time 122613100 ps
CPU time 13.73 seconds
Started Aug 18 06:08:25 PM PDT 24
Finished Aug 18 06:08:38 PM PDT 24
Peak memory 265768 kb
Host smart-7517f2c5-01f4-4e33-a1de-11a9de72e1d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718403105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
1718403105
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.2093270322
Short name T758
Test name
Test status
Simulation time 13746900 ps
CPU time 13.69 seconds
Started Aug 18 06:08:25 PM PDT 24
Finished Aug 18 06:08:39 PM PDT 24
Peak memory 283560 kb
Host smart-11de0545-0084-489c-934e-6ed00a860b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093270322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.2093270322
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.3542194995
Short name T600
Test name
Test status
Simulation time 16638900 ps
CPU time 21.58 seconds
Started Aug 18 06:08:25 PM PDT 24
Finished Aug 18 06:08:47 PM PDT 24
Peak memory 266908 kb
Host smart-3c30d264-c7ad-492c-857c-f5ed80c91c29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542194995 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.3542194995
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.1258354328
Short name T855
Test name
Test status
Simulation time 7563020300 ps
CPU time 75 seconds
Started Aug 18 06:08:25 PM PDT 24
Finished Aug 18 06:09:40 PM PDT 24
Peak memory 261472 kb
Host smart-18d8fecf-1076-4dea-aa46-1d4e1ce16ed7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258354328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.1258354328
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.817958134
Short name T894
Test name
Test status
Simulation time 5410299900 ps
CPU time 252.83 seconds
Started Aug 18 06:08:26 PM PDT 24
Finished Aug 18 06:12:39 PM PDT 24
Peak memory 285624 kb
Host smart-5c219f6e-5a01-4b15-b15c-62ccd82a0265
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817958134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flas
h_ctrl_intr_rd.817958134
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1291470030
Short name T344
Test name
Test status
Simulation time 25019988400 ps
CPU time 313.79 seconds
Started Aug 18 06:08:28 PM PDT 24
Finished Aug 18 06:13:42 PM PDT 24
Peak memory 285508 kb
Host smart-a0d600e3-d350-40a5-aea0-3bf0f0e7288c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291470030 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1291470030
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.1989951725
Short name T166
Test name
Test status
Simulation time 39149300 ps
CPU time 131.45 seconds
Started Aug 18 06:08:24 PM PDT 24
Finished Aug 18 06:10:36 PM PDT 24
Peak memory 260708 kb
Host smart-c8605738-95ab-4bba-8fed-9b86185f0429
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989951725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.1989951725
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.2593802327
Short name T157
Test name
Test status
Simulation time 31808900 ps
CPU time 13.63 seconds
Started Aug 18 06:08:25 PM PDT 24
Finished Aug 18 06:08:38 PM PDT 24
Peak memory 259640 kb
Host smart-9ec422f1-c8f5-405e-ad59-3b5eeb37763e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593802327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.flash_ctrl_prog_reset.2593802327
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.3827792758
Short name T890
Test name
Test status
Simulation time 40239000 ps
CPU time 31.75 seconds
Started Aug 18 06:08:24 PM PDT 24
Finished Aug 18 06:08:55 PM PDT 24
Peak memory 275556 kb
Host smart-fecbba39-cad0-4a98-84fe-cf98b0dbb0c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827792758 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.3827792758
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.1107736396
Short name T588
Test name
Test status
Simulation time 3023105400 ps
CPU time 70.7 seconds
Started Aug 18 06:08:25 PM PDT 24
Finished Aug 18 06:09:36 PM PDT 24
Peak memory 264316 kb
Host smart-ad075018-59ea-42e7-b47c-9d326152b895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107736396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.1107736396
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.2290546904
Short name T721
Test name
Test status
Simulation time 41033500 ps
CPU time 75.92 seconds
Started Aug 18 06:08:23 PM PDT 24
Finished Aug 18 06:09:39 PM PDT 24
Peak memory 274312 kb
Host smart-438565c8-36d7-4d59-9a87-98f1d0b50fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290546904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.2290546904
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.1964094461
Short name T840
Test name
Test status
Simulation time 36697900 ps
CPU time 13.87 seconds
Started Aug 18 06:08:32 PM PDT 24
Finished Aug 18 06:08:46 PM PDT 24
Peak memory 258860 kb
Host smart-715af5ab-e433-44a3-914f-6ac2a5e78a08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964094461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
1964094461
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.1888136663
Short name T531
Test name
Test status
Simulation time 24849400 ps
CPU time 13.53 seconds
Started Aug 18 06:08:32 PM PDT 24
Finished Aug 18 06:08:46 PM PDT 24
Peak memory 284824 kb
Host smart-41649315-658a-420c-911d-917e2aca6c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888136663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1888136663
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.1301773628
Short name T627
Test name
Test status
Simulation time 30985700 ps
CPU time 21.85 seconds
Started Aug 18 06:08:32 PM PDT 24
Finished Aug 18 06:08:54 PM PDT 24
Peak memory 274184 kb
Host smart-1c3c88fc-0caa-4291-b219-6d6f88da206b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301773628 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.1301773628
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.3233806931
Short name T557
Test name
Test status
Simulation time 9966282000 ps
CPU time 142.54 seconds
Started Aug 18 06:08:26 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 261404 kb
Host smart-d966e669-8221-4a80-84be-7b42d0b33728
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233806931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.3233806931
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.948461271
Short name T622
Test name
Test status
Simulation time 1601792700 ps
CPU time 225.35 seconds
Started Aug 18 06:08:25 PM PDT 24
Finished Aug 18 06:12:10 PM PDT 24
Peak memory 294296 kb
Host smart-5ec2d9ea-6405-49dd-99ca-0e42a7d1795e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948461271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flas
h_ctrl_intr_rd.948461271
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.915386175
Short name T603
Test name
Test status
Simulation time 11826338600 ps
CPU time 333.32 seconds
Started Aug 18 06:08:32 PM PDT 24
Finished Aug 18 06:14:05 PM PDT 24
Peak memory 285856 kb
Host smart-897f80e7-33a1-448a-bce2-5b5225c5711b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915386175 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.915386175
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.3863830738
Short name T457
Test name
Test status
Simulation time 31687500 ps
CPU time 14.99 seconds
Started Aug 18 06:08:32 PM PDT 24
Finished Aug 18 06:08:47 PM PDT 24
Peak memory 265720 kb
Host smart-81cceac2-89f2-45ae-a540-59340b424078
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863830738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.flash_ctrl_prog_reset.3863830738
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.4115817549
Short name T364
Test name
Test status
Simulation time 64509700 ps
CPU time 31.18 seconds
Started Aug 18 06:08:33 PM PDT 24
Finished Aug 18 06:09:04 PM PDT 24
Peak memory 268064 kb
Host smart-2fadc7bb-e33d-4aba-939f-9e8b2e8712b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115817549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.4115817549
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1510227784
Short name T734
Test name
Test status
Simulation time 29145100 ps
CPU time 28.87 seconds
Started Aug 18 06:08:32 PM PDT 24
Finished Aug 18 06:09:01 PM PDT 24
Peak memory 275360 kb
Host smart-2d78f88c-fac3-44b3-afae-75f4ef5ee6f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510227784 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1510227784
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.4026081112
Short name T817
Test name
Test status
Simulation time 1465844500 ps
CPU time 57.89 seconds
Started Aug 18 06:08:31 PM PDT 24
Finished Aug 18 06:09:29 PM PDT 24
Peak memory 265096 kb
Host smart-97eb8cb5-d871-4dcb-8950-e668f3f1ef68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026081112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.4026081112
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.2467571907
Short name T975
Test name
Test status
Simulation time 215681800 ps
CPU time 220.08 seconds
Started Aug 18 06:08:24 PM PDT 24
Finished Aug 18 06:12:04 PM PDT 24
Peak memory 278180 kb
Host smart-a4942963-25cc-4e80-bb92-18a9bca2b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467571907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.2467571907
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.2170109976
Short name T828
Test name
Test status
Simulation time 36430800 ps
CPU time 13.58 seconds
Started Aug 18 06:08:33 PM PDT 24
Finished Aug 18 06:08:46 PM PDT 24
Peak memory 265764 kb
Host smart-12fdae86-1720-4e89-b635-db3ce3200f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170109976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
2170109976
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.4247204262
Short name T463
Test name
Test status
Simulation time 14506600 ps
CPU time 16.02 seconds
Started Aug 18 06:08:33 PM PDT 24
Finished Aug 18 06:08:49 PM PDT 24
Peak memory 284828 kb
Host smart-b5deafb0-101d-4328-a0a3-91e79bf9d723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247204262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.4247204262
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.616227024
Short name T41
Test name
Test status
Simulation time 36619800 ps
CPU time 21.9 seconds
Started Aug 18 06:08:31 PM PDT 24
Finished Aug 18 06:08:53 PM PDT 24
Peak memory 274116 kb
Host smart-3b0db7c6-3ce3-4cc9-89b0-aff1198053a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616227024 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.616227024
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.1333605582
Short name T847
Test name
Test status
Simulation time 1195504100 ps
CPU time 107.62 seconds
Started Aug 18 06:08:31 PM PDT 24
Finished Aug 18 06:10:19 PM PDT 24
Peak memory 263776 kb
Host smart-fa021725-c0f4-49c9-b63f-83865c9fd681
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333605582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.1333605582
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.2498681337
Short name T31
Test name
Test status
Simulation time 1526022300 ps
CPU time 149.53 seconds
Started Aug 18 06:08:32 PM PDT 24
Finished Aug 18 06:11:02 PM PDT 24
Peak memory 286108 kb
Host smart-c11f8fc5-0642-49be-a3b2-423933febb22
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498681337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.2498681337
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.3813479139
Short name T651
Test name
Test status
Simulation time 6705449200 ps
CPU time 129.55 seconds
Started Aug 18 06:08:34 PM PDT 24
Finished Aug 18 06:10:44 PM PDT 24
Peak memory 293592 kb
Host smart-2eaa5701-0b65-4219-ab34-2879548e827e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813479139 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.3813479139
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.863213334
Short name T326
Test name
Test status
Simulation time 74148900 ps
CPU time 131 seconds
Started Aug 18 06:08:32 PM PDT 24
Finished Aug 18 06:10:43 PM PDT 24
Peak memory 260552 kb
Host smart-b0b8fb31-214f-4157-a911-6b3123890e4d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863213334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ot
p_reset.863213334
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.1829979979
Short name T602
Test name
Test status
Simulation time 2140722400 ps
CPU time 181.63 seconds
Started Aug 18 06:08:32 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 260516 kb
Host smart-3806c333-0e42-4667-9a28-92d9707f5fe4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829979979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.flash_ctrl_prog_reset.1829979979
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.3993993727
Short name T377
Test name
Test status
Simulation time 72019700 ps
CPU time 31.51 seconds
Started Aug 18 06:08:32 PM PDT 24
Finished Aug 18 06:09:03 PM PDT 24
Peak memory 274224 kb
Host smart-cb0c324c-2fb1-4be1-87fc-0e58c82000d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993993727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.3993993727
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.2021060703
Short name T373
Test name
Test status
Simulation time 64248000 ps
CPU time 30.61 seconds
Started Aug 18 06:08:32 PM PDT 24
Finished Aug 18 06:09:02 PM PDT 24
Peak memory 274112 kb
Host smart-0128b321-7a47-4fdf-bfd6-d08b73462901
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021060703 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.2021060703
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.541667376
Short name T532
Test name
Test status
Simulation time 4522771400 ps
CPU time 71.76 seconds
Started Aug 18 06:08:35 PM PDT 24
Finished Aug 18 06:09:47 PM PDT 24
Peak memory 264340 kb
Host smart-5e0bd862-7540-4dbb-a274-4f670b676ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541667376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.541667376
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.2364755313
Short name T929
Test name
Test status
Simulation time 59119400 ps
CPU time 124.52 seconds
Started Aug 18 06:08:31 PM PDT 24
Finished Aug 18 06:10:36 PM PDT 24
Peak memory 277060 kb
Host smart-5a9c29b6-5561-4a05-ae90-524953f1bd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364755313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.2364755313
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.472037013
Short name T1029
Test name
Test status
Simulation time 64324300 ps
CPU time 13.57 seconds
Started Aug 18 06:04:34 PM PDT 24
Finished Aug 18 06:04:48 PM PDT 24
Peak memory 258852 kb
Host smart-b220ab9d-9533-4f8a-a00c-651aa27b0253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472037013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.472037013
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.1358874954
Short name T1055
Test name
Test status
Simulation time 19971700 ps
CPU time 14.09 seconds
Started Aug 18 06:04:33 PM PDT 24
Finished Aug 18 06:04:48 PM PDT 24
Peak memory 265232 kb
Host smart-6706e1c6-3136-4742-9455-3d615d332d1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358874954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.1358874954
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.3396349444
Short name T775
Test name
Test status
Simulation time 27334800 ps
CPU time 15.78 seconds
Started Aug 18 06:04:32 PM PDT 24
Finished Aug 18 06:04:48 PM PDT 24
Peak memory 284836 kb
Host smart-db22eac3-9632-4177-a0fc-5d38d765f84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396349444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.3396349444
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.220367152
Short name T241
Test name
Test status
Simulation time 2664321800 ps
CPU time 198.75 seconds
Started Aug 18 06:04:27 PM PDT 24
Finished Aug 18 06:07:46 PM PDT 24
Peak memory 282428 kb
Host smart-41a31a6b-dd88-407a-965e-2f42b002056c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220367152 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_derr_detect.220367152
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.2382691511
Short name T398
Test name
Test status
Simulation time 37447300 ps
CPU time 22.03 seconds
Started Aug 18 06:04:34 PM PDT 24
Finished Aug 18 06:04:56 PM PDT 24
Peak memory 274020 kb
Host smart-631bc923-bc77-4ef0-93b1-c838a819eee7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382691511 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.2382691511
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.4205116061
Short name T539
Test name
Test status
Simulation time 14312236000 ps
CPU time 2571.51 seconds
Started Aug 18 06:04:25 PM PDT 24
Finished Aug 18 06:47:17 PM PDT 24
Peak memory 263392 kb
Host smart-7790bdfb-9477-4c23-a241-4293e0811033
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4205116061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.4205116061
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.2725961640
Short name T722
Test name
Test status
Simulation time 1103066600 ps
CPU time 1794.46 seconds
Started Aug 18 06:04:22 PM PDT 24
Finished Aug 18 06:34:17 PM PDT 24
Peak memory 262940 kb
Host smart-34bbd82b-772e-4ea5-bd9d-657f3f167113
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725961640 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.2725961640
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.2948247976
Short name T189
Test name
Test status
Simulation time 772285900 ps
CPU time 936.17 seconds
Started Aug 18 06:04:22 PM PDT 24
Finished Aug 18 06:19:59 PM PDT 24
Peak memory 273712 kb
Host smart-4ba20c0a-4429-4001-9cea-0eed0dbca562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948247976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.2948247976
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.2147716087
Short name T49
Test name
Test status
Simulation time 3880405500 ps
CPU time 27.28 seconds
Started Aug 18 06:04:27 PM PDT 24
Finished Aug 18 06:04:55 PM PDT 24
Peak memory 263092 kb
Host smart-fdaad085-b1b9-4b95-9b49-706dfd9fe42b
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147716087 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_fetch_code.2147716087
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.2208083867
Short name T941
Test name
Test status
Simulation time 4213952900 ps
CPU time 40.65 seconds
Started Aug 18 06:04:34 PM PDT 24
Finished Aug 18 06:05:15 PM PDT 24
Peak memory 263568 kb
Host smart-e406f1db-f9df-4dad-a87f-41ad8443f38b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208083867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.2208083867
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.2066750656
Short name T126
Test name
Test status
Simulation time 241692952300 ps
CPU time 2705.46 seconds
Started Aug 18 06:04:22 PM PDT 24
Finished Aug 18 06:49:28 PM PDT 24
Peak memory 263116 kb
Host smart-5b59975f-d966-47d0-91ad-2bf07cbb61e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066750656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.2066750656
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.2630362047
Short name T53
Test name
Test status
Simulation time 69421400 ps
CPU time 26.45 seconds
Started Aug 18 06:04:15 PM PDT 24
Finished Aug 18 06:04:41 PM PDT 24
Peak memory 263244 kb
Host smart-9e3f72d4-cccb-40ce-9a1d-e70be9b4dabc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630362047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.2630362047
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1548025250
Short name T162
Test name
Test status
Simulation time 10012149300 ps
CPU time 312.97 seconds
Started Aug 18 06:04:35 PM PDT 24
Finished Aug 18 06:09:48 PM PDT 24
Peak memory 294120 kb
Host smart-7f877be9-11f2-4224-89de-093815a3afe6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548025250 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.1548025250
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.1445246971
Short name T876
Test name
Test status
Simulation time 25836300 ps
CPU time 13.43 seconds
Started Aug 18 06:04:35 PM PDT 24
Finished Aug 18 06:04:48 PM PDT 24
Peak memory 265200 kb
Host smart-a7b62d21-8c52-40a6-9a25-a92352dc0f42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445246971 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.1445246971
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.2009406276
Short name T991
Test name
Test status
Simulation time 80152144600 ps
CPU time 876.47 seconds
Started Aug 18 06:04:21 PM PDT 24
Finished Aug 18 06:18:58 PM PDT 24
Peak memory 264620 kb
Host smart-782e1d0a-5ca4-459e-983d-ee097c9af56d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009406276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_hw_rma_reset.2009406276
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.2921824848
Short name T661
Test name
Test status
Simulation time 5547509400 ps
CPU time 115.71 seconds
Started Aug 18 06:04:23 PM PDT 24
Finished Aug 18 06:06:19 PM PDT 24
Peak memory 261320 kb
Host smart-9a380340-d040-49aa-9630-7398b78c35f3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921824848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.2921824848
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.3915378046
Short name T427
Test name
Test status
Simulation time 6232937800 ps
CPU time 517.11 seconds
Started Aug 18 06:04:35 PM PDT 24
Finished Aug 18 06:13:13 PM PDT 24
Peak memory 329044 kb
Host smart-6d2450f5-8e9e-4ac3-ab38-8106e66dc186
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915378046 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_integrity.3915378046
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.448849523
Short name T879
Test name
Test status
Simulation time 24666331800 ps
CPU time 133.61 seconds
Started Aug 18 06:04:33 PM PDT 24
Finished Aug 18 06:06:46 PM PDT 24
Peak memory 293380 kb
Host smart-ea14d113-d823-41c1-9681-481ff71eac07
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448849523 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.448849523
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.3726461903
Short name T549
Test name
Test status
Simulation time 4469693100 ps
CPU time 73.63 seconds
Started Aug 18 06:04:35 PM PDT 24
Finished Aug 18 06:05:49 PM PDT 24
Peak memory 262240 kb
Host smart-e4660a09-d6c3-46d4-8728-e35e0be84a6f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726461903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.3726461903
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1359333408
Short name T956
Test name
Test status
Simulation time 24679527500 ps
CPU time 207.02 seconds
Started Aug 18 06:04:33 PM PDT 24
Finished Aug 18 06:08:00 PM PDT 24
Peak memory 260344 kb
Host smart-8a13e1c9-fc3d-498d-bb45-55308afba038
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135
9333408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.1359333408
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.678049439
Short name T934
Test name
Test status
Simulation time 1015203600 ps
CPU time 89.02 seconds
Started Aug 18 06:04:24 PM PDT 24
Finished Aug 18 06:05:53 PM PDT 24
Peak memory 261076 kb
Host smart-8358b378-fcdb-41ef-98d4-82551c3ddc60
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678049439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.678049439
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.3046153048
Short name T942
Test name
Test status
Simulation time 46133100 ps
CPU time 13.55 seconds
Started Aug 18 06:04:31 PM PDT 24
Finished Aug 18 06:04:45 PM PDT 24
Peak memory 265272 kb
Host smart-92466fe1-ff6a-4f02-8135-250feef357e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046153048 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.3046153048
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.256753652
Short name T122
Test name
Test status
Simulation time 12369454800 ps
CPU time 713.33 seconds
Started Aug 18 06:04:24 PM PDT 24
Finished Aug 18 06:16:17 PM PDT 24
Peak memory 275464 kb
Host smart-b25090a0-82e2-45bd-b901-e4ceb89b7391
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256753652 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.256753652
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.3718091898
Short name T172
Test name
Test status
Simulation time 174471000 ps
CPU time 132.95 seconds
Started Aug 18 06:04:24 PM PDT 24
Finished Aug 18 06:06:37 PM PDT 24
Peak memory 264904 kb
Host smart-279dc447-d9a0-44af-b15f-1bd463434c5e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718091898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.3718091898
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.2727487615
Short name T509
Test name
Test status
Simulation time 1708143800 ps
CPU time 220.6 seconds
Started Aug 18 06:04:23 PM PDT 24
Finished Aug 18 06:08:04 PM PDT 24
Peak memory 282364 kb
Host smart-fc97025f-62f4-423c-84aa-78a1e8410c6a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727487615 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.2727487615
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.3398398019
Short name T213
Test name
Test status
Simulation time 53067000 ps
CPU time 13.81 seconds
Started Aug 18 06:04:33 PM PDT 24
Finished Aug 18 06:04:47 PM PDT 24
Peak memory 265576 kb
Host smart-8c19d023-9b04-46e0-a8d5-7c6fb21840b5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3398398019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.3398398019
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.2678931603
Short name T559
Test name
Test status
Simulation time 62196000 ps
CPU time 316.03 seconds
Started Aug 18 06:04:16 PM PDT 24
Finished Aug 18 06:09:32 PM PDT 24
Peak memory 263704 kb
Host smart-dec90c06-cead-44a5-977c-34e5d15f50b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2678931603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.2678931603
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.3787517951
Short name T664
Test name
Test status
Simulation time 35617600 ps
CPU time 13.79 seconds
Started Aug 18 06:04:32 PM PDT 24
Finished Aug 18 06:04:46 PM PDT 24
Peak memory 265588 kb
Host smart-bc1b88da-38df-43af-8424-f64ecc35b4de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787517951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.flash_ctrl_prog_reset.3787517951
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.3251542933
Short name T680
Test name
Test status
Simulation time 640283500 ps
CPU time 528.29 seconds
Started Aug 18 06:04:16 PM PDT 24
Finished Aug 18 06:13:04 PM PDT 24
Peak memory 283088 kb
Host smart-2454372a-4fe0-4362-b599-c2ef6b59c17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251542933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.3251542933
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.3805847194
Short name T555
Test name
Test status
Simulation time 231150600 ps
CPU time 104.04 seconds
Started Aug 18 06:04:15 PM PDT 24
Finished Aug 18 06:05:59 PM PDT 24
Peak memory 263460 kb
Host smart-dafe67ee-130b-4abf-b438-7fe0edada54a
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3805847194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.3805847194
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.3207469595
Short name T353
Test name
Test status
Simulation time 113810000 ps
CPU time 32.48 seconds
Started Aug 18 06:04:36 PM PDT 24
Finished Aug 18 06:05:09 PM PDT 24
Peak memory 276576 kb
Host smart-6af5ba32-e172-4380-b210-0e0aa293116f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207469595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.3207469595
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.955082794
Short name T1090
Test name
Test status
Simulation time 18497400 ps
CPU time 23.02 seconds
Started Aug 18 06:04:25 PM PDT 24
Finished Aug 18 06:04:48 PM PDT 24
Peak memory 265932 kb
Host smart-bab87417-056a-4385-bb2b-c07ba05143d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955082794 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.955082794
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.787838468
Short name T1043
Test name
Test status
Simulation time 207139900 ps
CPU time 21.68 seconds
Started Aug 18 06:04:22 PM PDT 24
Finished Aug 18 06:04:44 PM PDT 24
Peak memory 265896 kb
Host smart-886a7117-3e55-4461-9a54-3d1765442ca4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787838468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_read_word_sweep_serr.787838468
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.2660695717
Short name T800
Test name
Test status
Simulation time 5090630100 ps
CPU time 116.51 seconds
Started Aug 18 06:04:27 PM PDT 24
Finished Aug 18 06:06:24 PM PDT 24
Peak memory 281732 kb
Host smart-b633b60c-ea3a-4280-828e-525358c6f9d3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660695717 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.2660695717
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.1027418207
Short name T652
Test name
Test status
Simulation time 1042239200 ps
CPU time 155.08 seconds
Started Aug 18 06:04:26 PM PDT 24
Finished Aug 18 06:07:01 PM PDT 24
Peak memory 282404 kb
Host smart-8c4c4d12-477f-459d-a54d-d12144114480
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1027418207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.1027418207
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.3951620528
Short name T700
Test name
Test status
Simulation time 902889100 ps
CPU time 169.8 seconds
Started Aug 18 06:04:26 PM PDT 24
Finished Aug 18 06:07:16 PM PDT 24
Peak memory 295872 kb
Host smart-b0a4f134-c3d5-41ed-9b45-0a5b4a3e6976
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951620528 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.3951620528
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.3906579466
Short name T742
Test name
Test status
Simulation time 3522223600 ps
CPU time 597.23 seconds
Started Aug 18 06:04:22 PM PDT 24
Finished Aug 18 06:14:20 PM PDT 24
Peak memory 319536 kb
Host smart-4ac6ba54-624a-4ea3-bdc1-2dfec0f6d138
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906579466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_rw.3906579466
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.2523862113
Short name T995
Test name
Test status
Simulation time 1231294100 ps
CPU time 157.69 seconds
Started Aug 18 06:04:24 PM PDT 24
Finished Aug 18 06:07:02 PM PDT 24
Peak memory 285960 kb
Host smart-a76e0560-c39f-4d01-9a7b-bacab56923d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523862113 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_derr.2523862113
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.2771732446
Short name T26
Test name
Test status
Simulation time 41230100 ps
CPU time 30.9 seconds
Started Aug 18 06:04:33 PM PDT 24
Finished Aug 18 06:05:04 PM PDT 24
Peak memory 274052 kb
Host smart-d953c4e7-9f88-4e6c-826a-39fb3127f989
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771732446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.2771732446
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.2694684378
Short name T363
Test name
Test status
Simulation time 80902500 ps
CPU time 31.13 seconds
Started Aug 18 06:04:34 PM PDT 24
Finished Aug 18 06:05:05 PM PDT 24
Peak memory 275504 kb
Host smart-297ce20c-370a-4232-b72d-c4eef689484a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694684378 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.2694684378
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.274761477
Short name T880
Test name
Test status
Simulation time 15413574400 ps
CPU time 229.01 seconds
Started Aug 18 06:04:22 PM PDT 24
Finished Aug 18 06:08:12 PM PDT 24
Peak memory 282448 kb
Host smart-e8b37789-888f-41b0-a817-43ec13958793
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274761477 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_rw_serr.274761477
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.4062182395
Short name T16
Test name
Test status
Simulation time 21770080200 ps
CPU time 4975.16 seconds
Started Aug 18 06:04:31 PM PDT 24
Finished Aug 18 07:27:27 PM PDT 24
Peak memory 290388 kb
Host smart-e744a2e2-3d30-465a-b6ff-8d5424a3a85f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062182395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.4062182395
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.2603272447
Short name T29
Test name
Test status
Simulation time 1285333400 ps
CPU time 62.09 seconds
Started Aug 18 06:04:33 PM PDT 24
Finished Aug 18 06:05:35 PM PDT 24
Peak memory 264284 kb
Host smart-1431ed48-5983-42b0-96ce-1cb3792192bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603272447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.2603272447
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.2860404399
Short name T453
Test name
Test status
Simulation time 1346056000 ps
CPU time 74.3 seconds
Started Aug 18 06:04:24 PM PDT 24
Finished Aug 18 06:05:39 PM PDT 24
Peak memory 265692 kb
Host smart-38641b61-2c4b-4b21-8121-cd7fb3efd039
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860404399 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.2860404399
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.3379481566
Short name T676
Test name
Test status
Simulation time 1927420200 ps
CPU time 95.01 seconds
Started Aug 18 06:04:23 PM PDT 24
Finished Aug 18 06:05:58 PM PDT 24
Peak memory 274036 kb
Host smart-3bd1169a-a64a-4969-a97b-173543f0c394
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379481566 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.3379481566
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.4059910636
Short name T290
Test name
Test status
Simulation time 39164700 ps
CPU time 76.33 seconds
Started Aug 18 06:04:15 PM PDT 24
Finished Aug 18 06:05:31 PM PDT 24
Peak memory 277412 kb
Host smart-6c501253-3395-4fc9-ab92-c3e9c309d9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059910636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.4059910636
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.3824318659
Short name T899
Test name
Test status
Simulation time 18181100 ps
CPU time 25.75 seconds
Started Aug 18 06:04:19 PM PDT 24
Finished Aug 18 06:04:45 PM PDT 24
Peak memory 260152 kb
Host smart-fd28ff62-7ec3-4b80-b630-f8947ce75342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824318659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.3824318659
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.1391600700
Short name T460
Test name
Test status
Simulation time 210286800 ps
CPU time 313.5 seconds
Started Aug 18 06:04:32 PM PDT 24
Finished Aug 18 06:09:46 PM PDT 24
Peak memory 277548 kb
Host smart-ea28debb-c145-4026-92bd-2f519e03c067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391600700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.1391600700
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.4288303765
Short name T1087
Test name
Test status
Simulation time 22018300 ps
CPU time 26.56 seconds
Started Aug 18 06:04:13 PM PDT 24
Finished Aug 18 06:04:40 PM PDT 24
Peak memory 262796 kb
Host smart-6810b009-d7b6-4a62-9591-f7823a9b80e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288303765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.4288303765
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.4182819360
Short name T496
Test name
Test status
Simulation time 19438808400 ps
CPU time 221.76 seconds
Started Aug 18 06:04:22 PM PDT 24
Finished Aug 18 06:08:03 PM PDT 24
Peak memory 265816 kb
Host smart-4e3bc715-38e9-4f7c-b41f-910f3091d8fe
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182819360 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_wo.4182819360
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.4179942158
Short name T706
Test name
Test status
Simulation time 53117600 ps
CPU time 14.09 seconds
Started Aug 18 06:08:38 PM PDT 24
Finished Aug 18 06:08:52 PM PDT 24
Peak memory 258780 kb
Host smart-cd712fd7-fce5-4c51-9ddc-05197041fb21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179942158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
4179942158
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.2293668962
Short name T670
Test name
Test status
Simulation time 13595300 ps
CPU time 16.08 seconds
Started Aug 18 06:08:40 PM PDT 24
Finished Aug 18 06:08:57 PM PDT 24
Peak memory 283540 kb
Host smart-01502efa-421c-4b86-ac60-7d99bfab7995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293668962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.2293668962
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.3348351319
Short name T11
Test name
Test status
Simulation time 13305800 ps
CPU time 21.04 seconds
Started Aug 18 06:08:39 PM PDT 24
Finished Aug 18 06:09:01 PM PDT 24
Peak memory 274156 kb
Host smart-726f40c3-6657-4915-ae44-081ec642ca57
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348351319 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.3348351319
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.3924384105
Short name T794
Test name
Test status
Simulation time 4273445200 ps
CPU time 72.93 seconds
Started Aug 18 06:08:34 PM PDT 24
Finished Aug 18 06:09:47 PM PDT 24
Peak memory 263788 kb
Host smart-6e2d913f-0388-4080-a1a4-a79665eef1c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924384105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.3924384105
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.3029150100
Short name T297
Test name
Test status
Simulation time 1772648000 ps
CPU time 213.93 seconds
Started Aug 18 06:08:39 PM PDT 24
Finished Aug 18 06:12:13 PM PDT 24
Peak memory 291384 kb
Host smart-d87da458-6809-4d09-85b9-ecb228c72c9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029150100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.3029150100
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3399611445
Short name T645
Test name
Test status
Simulation time 11501645500 ps
CPU time 164.58 seconds
Started Aug 18 06:08:38 PM PDT 24
Finished Aug 18 06:11:22 PM PDT 24
Peak memory 293496 kb
Host smart-7c62d05d-8c31-4c70-8559-d2bafc72079b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399611445 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.3399611445
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.1839540816
Short name T1088
Test name
Test status
Simulation time 141234900 ps
CPU time 132.96 seconds
Started Aug 18 06:08:33 PM PDT 24
Finished Aug 18 06:10:46 PM PDT 24
Peak memory 261476 kb
Host smart-3baf10d3-76c4-4ecd-a79f-1a60f5402955
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839540816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.1839540816
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.4006399518
Short name T1022
Test name
Test status
Simulation time 112858000 ps
CPU time 29.7 seconds
Started Aug 18 06:08:39 PM PDT 24
Finished Aug 18 06:09:09 PM PDT 24
Peak memory 275492 kb
Host smart-6e86a683-3bff-4017-b182-f05ea74421fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006399518 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.4006399518
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.2256571832
Short name T780
Test name
Test status
Simulation time 2588840200 ps
CPU time 63.09 seconds
Started Aug 18 06:08:40 PM PDT 24
Finished Aug 18 06:09:43 PM PDT 24
Peak memory 263616 kb
Host smart-ab984fae-62b1-42bd-8cb4-b711a8ce9b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256571832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.2256571832
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.571014815
Short name T454
Test name
Test status
Simulation time 103839100 ps
CPU time 73.74 seconds
Started Aug 18 06:08:32 PM PDT 24
Finished Aug 18 06:09:46 PM PDT 24
Peak memory 276016 kb
Host smart-20645edd-59d2-4df6-9465-e364c701f0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571014815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.571014815
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.2905495045
Short name T93
Test name
Test status
Simulation time 63185600 ps
CPU time 14.11 seconds
Started Aug 18 06:08:41 PM PDT 24
Finished Aug 18 06:08:55 PM PDT 24
Peak memory 258716 kb
Host smart-2ab0e267-69a8-4b7a-9478-e8f11ca1aebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905495045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
2905495045
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.2226589062
Short name T951
Test name
Test status
Simulation time 13468200 ps
CPU time 15.95 seconds
Started Aug 18 06:08:39 PM PDT 24
Finished Aug 18 06:08:55 PM PDT 24
Peak memory 283564 kb
Host smart-89a003b9-cc2d-4cd8-8d5c-09c6c4406534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226589062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.2226589062
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.1865167818
Short name T98
Test name
Test status
Simulation time 11020500 ps
CPU time 21.7 seconds
Started Aug 18 06:08:39 PM PDT 24
Finished Aug 18 06:09:01 PM PDT 24
Peak memory 266904 kb
Host smart-7a19e999-08d3-49cb-922a-8190c78d876c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865167818 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.1865167818
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.160143527
Short name T309
Test name
Test status
Simulation time 4684543400 ps
CPU time 67.95 seconds
Started Aug 18 06:08:39 PM PDT 24
Finished Aug 18 06:09:47 PM PDT 24
Peak memory 261208 kb
Host smart-da224974-f366-420d-8dd8-71bd9e981c00
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160143527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_h
w_sec_otp.160143527
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.1166451283
Short name T1012
Test name
Test status
Simulation time 2279989300 ps
CPU time 135.29 seconds
Started Aug 18 06:08:39 PM PDT 24
Finished Aug 18 06:10:54 PM PDT 24
Peak memory 286180 kb
Host smart-6e06600a-30bc-4a10-9081-9aeecda1cac4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166451283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.1166451283
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.256940761
Short name T711
Test name
Test status
Simulation time 67228300 ps
CPU time 131.22 seconds
Started Aug 18 06:08:40 PM PDT 24
Finished Aug 18 06:10:51 PM PDT 24
Peak memory 260536 kb
Host smart-7ab61082-14ed-4b9f-a9c8-f804144e5ea4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256940761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_ot
p_reset.256940761
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.72632337
Short name T362
Test name
Test status
Simulation time 135766200 ps
CPU time 28.25 seconds
Started Aug 18 06:08:38 PM PDT 24
Finished Aug 18 06:09:07 PM PDT 24
Peak memory 274216 kb
Host smart-e4b99c71-66c8-4a87-ad0d-d8ab5d016d68
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72632337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flas
h_ctrl_rw_evict.72632337
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.1791608026
Short name T390
Test name
Test status
Simulation time 466861100 ps
CPU time 61.15 seconds
Started Aug 18 06:08:40 PM PDT 24
Finished Aug 18 06:09:41 PM PDT 24
Peak memory 263748 kb
Host smart-b3b84939-00d1-4464-a706-65e7aaea20be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791608026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.1791608026
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.118931502
Short name T785
Test name
Test status
Simulation time 95993900 ps
CPU time 102.5 seconds
Started Aug 18 06:08:41 PM PDT 24
Finished Aug 18 06:10:24 PM PDT 24
Peak memory 278300 kb
Host smart-5348d947-7141-4858-95d7-baac044001a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118931502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.118931502
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.2969292815
Short name T92
Test name
Test status
Simulation time 47925200 ps
CPU time 14.27 seconds
Started Aug 18 06:08:51 PM PDT 24
Finished Aug 18 06:09:05 PM PDT 24
Peak memory 258832 kb
Host smart-38945e35-265b-482b-87b1-ca659c6998a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969292815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
2969292815
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.3668537028
Short name T18
Test name
Test status
Simulation time 21347700 ps
CPU time 15.66 seconds
Started Aug 18 06:08:46 PM PDT 24
Finished Aug 18 06:09:01 PM PDT 24
Peak memory 284796 kb
Host smart-257f9cc9-930d-43f5-ab2e-54075cfd94b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668537028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.3668537028
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.626150903
Short name T921
Test name
Test status
Simulation time 29953100 ps
CPU time 22.99 seconds
Started Aug 18 06:08:47 PM PDT 24
Finished Aug 18 06:09:10 PM PDT 24
Peak memory 266944 kb
Host smart-f88aa44f-38b7-4c2a-be09-81057f7ca807
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626150903 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.626150903
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.3417818627
Short name T624
Test name
Test status
Simulation time 4053303700 ps
CPU time 114.71 seconds
Started Aug 18 06:08:38 PM PDT 24
Finished Aug 18 06:10:33 PM PDT 24
Peak memory 261264 kb
Host smart-88a5b528-e4cf-4273-a160-f3d8ffe7d43f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417818627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.3417818627
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.2398574759
Short name T1002
Test name
Test status
Simulation time 995072800 ps
CPU time 130.47 seconds
Started Aug 18 06:08:40 PM PDT 24
Finished Aug 18 06:10:50 PM PDT 24
Peak memory 294916 kb
Host smart-3212ccd6-6359-4f78-ad18-ad44b92ec10a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398574759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.2398574759
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1782265875
Short name T429
Test name
Test status
Simulation time 12052289400 ps
CPU time 250.53 seconds
Started Aug 18 06:08:48 PM PDT 24
Finished Aug 18 06:12:58 PM PDT 24
Peak memory 291756 kb
Host smart-f4a48305-4469-45c5-8734-74b1e331bc47
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782265875 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.1782265875
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.374090510
Short name T173
Test name
Test status
Simulation time 52047300 ps
CPU time 132.46 seconds
Started Aug 18 06:08:41 PM PDT 24
Finished Aug 18 06:10:53 PM PDT 24
Peak memory 260496 kb
Host smart-a4c47e7d-db98-4a93-99d0-c01d7a3a3a6b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374090510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ot
p_reset.374090510
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.787653023
Short name T692
Test name
Test status
Simulation time 35955500 ps
CPU time 31.36 seconds
Started Aug 18 06:08:47 PM PDT 24
Finished Aug 18 06:09:19 PM PDT 24
Peak memory 274168 kb
Host smart-b29d0d90-720c-4428-84a0-1f89d5700418
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787653023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_rw_evict.787653023
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.3565804744
Short name T873
Test name
Test status
Simulation time 223337400 ps
CPU time 174.47 seconds
Started Aug 18 06:08:40 PM PDT 24
Finished Aug 18 06:11:35 PM PDT 24
Peak memory 277836 kb
Host smart-509ef064-698f-4a36-9f91-03bff0e7191e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565804744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.3565804744
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.1168771470
Short name T763
Test name
Test status
Simulation time 49745300 ps
CPU time 13.44 seconds
Started Aug 18 06:08:47 PM PDT 24
Finished Aug 18 06:09:01 PM PDT 24
Peak memory 258976 kb
Host smart-c442569f-aad6-40b3-9621-47ddf0f6f876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168771470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
1168771470
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.671489416
Short name T911
Test name
Test status
Simulation time 40337500 ps
CPU time 15.64 seconds
Started Aug 18 06:08:47 PM PDT 24
Finished Aug 18 06:09:03 PM PDT 24
Peak memory 283268 kb
Host smart-365db3e4-bc9a-464c-b85f-2e79570a674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671489416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.671489416
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.643755798
Short name T732
Test name
Test status
Simulation time 13046800 ps
CPU time 21.05 seconds
Started Aug 18 06:08:47 PM PDT 24
Finished Aug 18 06:09:09 PM PDT 24
Peak memory 274072 kb
Host smart-1d4d1ae8-4541-4ee9-8c31-31cfc28f5ac0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643755798 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.643755798
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.3201304754
Short name T347
Test name
Test status
Simulation time 1298306600 ps
CPU time 130.48 seconds
Started Aug 18 06:08:47 PM PDT 24
Finished Aug 18 06:10:57 PM PDT 24
Peak memory 291464 kb
Host smart-702ff29e-9feb-4a85-934b-d11d379869d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201304754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.3201304754
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.1451744500
Short name T476
Test name
Test status
Simulation time 95548785400 ps
CPU time 146.39 seconds
Started Aug 18 06:08:46 PM PDT 24
Finished Aug 18 06:11:13 PM PDT 24
Peak memory 293528 kb
Host smart-50eb0b8d-8310-4a13-8870-80a12e35962e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451744500 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.1451744500
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.1082894411
Short name T697
Test name
Test status
Simulation time 206782400 ps
CPU time 134.5 seconds
Started Aug 18 06:08:46 PM PDT 24
Finished Aug 18 06:11:01 PM PDT 24
Peak memory 260448 kb
Host smart-9f315c1c-4254-4e61-b8ff-3ee148d8ba51
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082894411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.1082894411
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.668378434
Short name T545
Test name
Test status
Simulation time 64137200 ps
CPU time 31.36 seconds
Started Aug 18 06:08:47 PM PDT 24
Finished Aug 18 06:09:18 PM PDT 24
Peak memory 276284 kb
Host smart-c27f1497-5d4a-48d2-911b-5d976d108a96
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668378434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_rw_evict.668378434
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.1852698629
Short name T674
Test name
Test status
Simulation time 1378026500 ps
CPU time 74.83 seconds
Started Aug 18 06:08:46 PM PDT 24
Finished Aug 18 06:10:01 PM PDT 24
Peak memory 264600 kb
Host smart-e9524b35-583b-4b24-a9f4-613a7c7019a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852698629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1852698629
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.1123284810
Short name T802
Test name
Test status
Simulation time 22733400 ps
CPU time 75.7 seconds
Started Aug 18 06:08:46 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 269256 kb
Host smart-54cf4ed1-c69c-43c6-8f24-6cacf289039b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123284810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.1123284810
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.2143821291
Short name T704
Test name
Test status
Simulation time 425978100 ps
CPU time 14.27 seconds
Started Aug 18 06:08:55 PM PDT 24
Finished Aug 18 06:09:09 PM PDT 24
Peak memory 258736 kb
Host smart-62184ec2-2518-4822-9ba8-103ecb3493ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143821291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
2143821291
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.1450974543
Short name T1066
Test name
Test status
Simulation time 28688400 ps
CPU time 13.36 seconds
Started Aug 18 06:08:54 PM PDT 24
Finished Aug 18 06:09:07 PM PDT 24
Peak memory 284776 kb
Host smart-58c36721-a6f0-46d0-8d1d-2ac2a18e8cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450974543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1450974543
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.1829303494
Short name T839
Test name
Test status
Simulation time 27962700 ps
CPU time 21.03 seconds
Started Aug 18 06:08:56 PM PDT 24
Finished Aug 18 06:09:17 PM PDT 24
Peak memory 274152 kb
Host smart-27f443cf-108c-4eed-843b-f6d9117dcea6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829303494 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.1829303494
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.2465072039
Short name T462
Test name
Test status
Simulation time 2284842900 ps
CPU time 76.39 seconds
Started Aug 18 06:08:51 PM PDT 24
Finished Aug 18 06:10:08 PM PDT 24
Peak memory 261124 kb
Host smart-00ff61d7-8384-478a-90fc-a6ce474652be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465072039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.2465072039
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.2734724707
Short name T1051
Test name
Test status
Simulation time 1454696300 ps
CPU time 169.17 seconds
Started Aug 18 06:08:46 PM PDT 24
Finished Aug 18 06:11:35 PM PDT 24
Peak memory 294824 kb
Host smart-6f525d4a-bb2b-4f5f-b88c-ed68a605f325
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734724707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.2734724707
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.309519860
Short name T811
Test name
Test status
Simulation time 42528525300 ps
CPU time 192.21 seconds
Started Aug 18 06:08:47 PM PDT 24
Finished Aug 18 06:12:00 PM PDT 24
Peak memory 293396 kb
Host smart-703157f1-573c-4ecf-824b-cf616fb55c1c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309519860 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.309519860
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.2086977122
Short name T878
Test name
Test status
Simulation time 41086200 ps
CPU time 132.57 seconds
Started Aug 18 06:08:49 PM PDT 24
Finished Aug 18 06:11:01 PM PDT 24
Peak memory 260960 kb
Host smart-2392dc0f-b6d6-4d2f-ad35-e1a84ce6c62d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086977122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.2086977122
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.4130070805
Short name T786
Test name
Test status
Simulation time 129501500 ps
CPU time 32.1 seconds
Started Aug 18 06:08:56 PM PDT 24
Finished Aug 18 06:09:29 PM PDT 24
Peak memory 276272 kb
Host smart-a24a5554-7244-43d0-a1cd-e86803ab0f0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130070805 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.4130070805
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.2677261577
Short name T1075
Test name
Test status
Simulation time 1194080000 ps
CPU time 65.1 seconds
Started Aug 18 06:08:55 PM PDT 24
Finished Aug 18 06:10:01 PM PDT 24
Peak memory 265448 kb
Host smart-49ff2100-1b62-4487-be79-ba00a275f37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677261577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.2677261577
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.1434107005
Short name T961
Test name
Test status
Simulation time 108409600 ps
CPU time 100.41 seconds
Started Aug 18 06:08:51 PM PDT 24
Finished Aug 18 06:10:32 PM PDT 24
Peak memory 276640 kb
Host smart-4a97e953-b2db-4923-8efd-faae8af29897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434107005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1434107005
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.2989053300
Short name T744
Test name
Test status
Simulation time 25526100 ps
CPU time 13.69 seconds
Started Aug 18 06:08:57 PM PDT 24
Finished Aug 18 06:09:11 PM PDT 24
Peak memory 258880 kb
Host smart-42c04e9b-f427-4672-ac50-baba2137e055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989053300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
2989053300
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.3307659353
Short name T464
Test name
Test status
Simulation time 13666900 ps
CPU time 15.99 seconds
Started Aug 18 06:08:55 PM PDT 24
Finished Aug 18 06:09:12 PM PDT 24
Peak memory 284868 kb
Host smart-3edadff6-e162-4235-8a82-ae720dd74be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307659353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.3307659353
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.44670774
Short name T1076
Test name
Test status
Simulation time 12802000 ps
CPU time 20.56 seconds
Started Aug 18 06:08:56 PM PDT 24
Finished Aug 18 06:09:17 PM PDT 24
Peak memory 273984 kb
Host smart-ba9339c0-53d9-40b0-aa7d-0ec5e054800b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44670774 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.flash_ctrl_disable.44670774
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.2822599933
Short name T315
Test name
Test status
Simulation time 2144820100 ps
CPU time 86.27 seconds
Started Aug 18 06:08:53 PM PDT 24
Finished Aug 18 06:10:20 PM PDT 24
Peak memory 263904 kb
Host smart-42bda1d8-7e16-4e9f-90d9-ab30fc7b387c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822599933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.2822599933
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.3529726873
Short name T906
Test name
Test status
Simulation time 6697673500 ps
CPU time 227.82 seconds
Started Aug 18 06:08:55 PM PDT 24
Finished Aug 18 06:12:43 PM PDT 24
Peak memory 285572 kb
Host smart-9a1401f8-e01c-4024-b7c9-f70d313a9793
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529726873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_intr_rd.3529726873
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3617850965
Short name T947
Test name
Test status
Simulation time 5794715000 ps
CPU time 133.93 seconds
Started Aug 18 06:08:55 PM PDT 24
Finished Aug 18 06:11:09 PM PDT 24
Peak memory 293492 kb
Host smart-20701b58-4a1f-4df7-9671-c38a4cd15548
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617850965 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.3617850965
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.1606364014
Short name T626
Test name
Test status
Simulation time 147062300 ps
CPU time 111.35 seconds
Started Aug 18 06:08:56 PM PDT 24
Finished Aug 18 06:10:47 PM PDT 24
Peak memory 260576 kb
Host smart-e8510876-f2bb-4223-8c70-7377a638ee76
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606364014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.1606364014
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.2939464111
Short name T414
Test name
Test status
Simulation time 1551732600 ps
CPU time 64.15 seconds
Started Aug 18 06:08:56 PM PDT 24
Finished Aug 18 06:10:01 PM PDT 24
Peak memory 263240 kb
Host smart-3030ddb4-1740-4d06-9852-eb8e5b63fbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939464111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.2939464111
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.654986255
Short name T762
Test name
Test status
Simulation time 257619400 ps
CPU time 100.25 seconds
Started Aug 18 06:08:56 PM PDT 24
Finished Aug 18 06:10:36 PM PDT 24
Peak memory 276444 kb
Host smart-eb1fea3b-bc5a-4855-b92e-7998f3065289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654986255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.654986255
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.315995196
Short name T705
Test name
Test status
Simulation time 68407600 ps
CPU time 13.77 seconds
Started Aug 18 06:09:03 PM PDT 24
Finished Aug 18 06:09:17 PM PDT 24
Peak memory 258720 kb
Host smart-7996d9ca-894e-48c1-b3c2-66eabf202cdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315995196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.315995196
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.3673392612
Short name T486
Test name
Test status
Simulation time 25363200 ps
CPU time 13.34 seconds
Started Aug 18 06:09:03 PM PDT 24
Finished Aug 18 06:09:16 PM PDT 24
Peak memory 283548 kb
Host smart-0186a601-5e71-463c-9713-188cc14d1338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673392612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3673392612
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.748005949
Short name T719
Test name
Test status
Simulation time 30906200 ps
CPU time 21.98 seconds
Started Aug 18 06:09:05 PM PDT 24
Finished Aug 18 06:09:27 PM PDT 24
Peak memory 274164 kb
Host smart-97fe0e15-e727-445e-b0bd-a7ac8feacd19
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748005949 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.748005949
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.630731461
Short name T314
Test name
Test status
Simulation time 8397486700 ps
CPU time 67.37 seconds
Started Aug 18 06:09:07 PM PDT 24
Finished Aug 18 06:10:14 PM PDT 24
Peak memory 263840 kb
Host smart-873e5081-7cd6-4360-9706-87db24ec1ce7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630731461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_h
w_sec_otp.630731461
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.980672871
Short name T554
Test name
Test status
Simulation time 1193360900 ps
CPU time 135.31 seconds
Started Aug 18 06:09:02 PM PDT 24
Finished Aug 18 06:11:18 PM PDT 24
Peak memory 292100 kb
Host smart-e23c4cff-3575-45aa-b769-107c093abd75
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980672871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flas
h_ctrl_intr_rd.980672871
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3761745892
Short name T735
Test name
Test status
Simulation time 22694844800 ps
CPU time 155.18 seconds
Started Aug 18 06:09:00 PM PDT 24
Finished Aug 18 06:11:36 PM PDT 24
Peak memory 293740 kb
Host smart-99f5220f-c359-410e-8b7a-097662f1d4a1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761745892 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.3761745892
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.1351558944
Short name T302
Test name
Test status
Simulation time 69732800 ps
CPU time 134.97 seconds
Started Aug 18 06:09:05 PM PDT 24
Finished Aug 18 06:11:20 PM PDT 24
Peak memory 264880 kb
Host smart-56c525d4-dd28-4a9c-bca4-d1633d8c20cc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351558944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.1351558944
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.3302089354
Short name T996
Test name
Test status
Simulation time 82529100 ps
CPU time 31.27 seconds
Started Aug 18 06:09:07 PM PDT 24
Finished Aug 18 06:09:38 PM PDT 24
Peak memory 274264 kb
Host smart-869750e1-8a6e-4f31-8f7b-7d4aaee5730e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302089354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.3302089354
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.2244292734
Short name T952
Test name
Test status
Simulation time 1039473800 ps
CPU time 65.65 seconds
Started Aug 18 06:09:02 PM PDT 24
Finished Aug 18 06:10:08 PM PDT 24
Peak memory 264288 kb
Host smart-16c86e80-1ee4-47e3-895e-174ff2d2bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244292734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.2244292734
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.3325862221
Short name T739
Test name
Test status
Simulation time 44980200 ps
CPU time 122.74 seconds
Started Aug 18 06:08:56 PM PDT 24
Finished Aug 18 06:10:59 PM PDT 24
Peak memory 278384 kb
Host smart-eaab350e-ee6e-41d5-b0bc-758b3dc24354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325862221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.3325862221
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.2376514727
Short name T882
Test name
Test status
Simulation time 123618700 ps
CPU time 13.88 seconds
Started Aug 18 06:09:02 PM PDT 24
Finished Aug 18 06:09:16 PM PDT 24
Peak memory 258704 kb
Host smart-720486b0-5d58-4804-99a0-401157687ace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376514727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
2376514727
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.2651289559
Short name T864
Test name
Test status
Simulation time 21611200 ps
CPU time 16.18 seconds
Started Aug 18 06:09:03 PM PDT 24
Finished Aug 18 06:09:20 PM PDT 24
Peak memory 284900 kb
Host smart-3d47ad77-0262-42d8-b919-e995de8d5ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651289559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.2651289559
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.178635459
Short name T395
Test name
Test status
Simulation time 108727800 ps
CPU time 22.23 seconds
Started Aug 18 06:09:02 PM PDT 24
Finished Aug 18 06:09:24 PM PDT 24
Peak memory 274004 kb
Host smart-077a1af7-d3af-4e57-a564-6b0afe7bde38
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178635459 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.178635459
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1163692047
Short name T318
Test name
Test status
Simulation time 507670100 ps
CPU time 51.7 seconds
Started Aug 18 06:09:05 PM PDT 24
Finished Aug 18 06:09:57 PM PDT 24
Peak memory 263332 kb
Host smart-1575f53a-d420-4fce-a690-ba5e5882fc04
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163692047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.1163692047
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.3808803221
Short name T573
Test name
Test status
Simulation time 802339800 ps
CPU time 140.59 seconds
Started Aug 18 06:09:02 PM PDT 24
Finished Aug 18 06:11:22 PM PDT 24
Peak memory 294972 kb
Host smart-7284cae4-8aeb-40f5-8bc8-75d3f6fef243
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808803221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.3808803221
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2617499742
Short name T590
Test name
Test status
Simulation time 5782788900 ps
CPU time 141.21 seconds
Started Aug 18 06:09:05 PM PDT 24
Finished Aug 18 06:11:26 PM PDT 24
Peak memory 293484 kb
Host smart-1adbce24-0273-4d62-ab68-eeedac743027
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617499742 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.2617499742
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.2748821779
Short name T73
Test name
Test status
Simulation time 196577500 ps
CPU time 109.76 seconds
Started Aug 18 06:09:07 PM PDT 24
Finished Aug 18 06:10:56 PM PDT 24
Peak memory 260920 kb
Host smart-b661129f-64bf-4d35-b7e6-303eb37398da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748821779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.2748821779
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.3874793805
Short name T578
Test name
Test status
Simulation time 29597500 ps
CPU time 32.34 seconds
Started Aug 18 06:09:02 PM PDT 24
Finished Aug 18 06:09:35 PM PDT 24
Peak memory 276208 kb
Host smart-84d99b71-e8e2-4949-a96e-9a91ba6b528a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874793805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.3874793805
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.568639641
Short name T1
Test name
Test status
Simulation time 667668900 ps
CPU time 54.99 seconds
Started Aug 18 06:09:02 PM PDT 24
Finished Aug 18 06:09:57 PM PDT 24
Peak memory 265132 kb
Host smart-ca466afc-df7d-4672-af4d-235b3289483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568639641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.568639641
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.2369311355
Short name T857
Test name
Test status
Simulation time 70974400 ps
CPU time 173.64 seconds
Started Aug 18 06:09:07 PM PDT 24
Finished Aug 18 06:12:00 PM PDT 24
Peak memory 279564 kb
Host smart-08d3285e-d30b-488a-90e4-b4d5e4f73f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369311355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.2369311355
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.2351459271
Short name T519
Test name
Test status
Simulation time 133737400 ps
CPU time 13.85 seconds
Started Aug 18 06:09:12 PM PDT 24
Finished Aug 18 06:09:26 PM PDT 24
Peak memory 258876 kb
Host smart-00cfb2b4-2f21-4a87-944b-97eae9cb8ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351459271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
2351459271
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.264467495
Short name T755
Test name
Test status
Simulation time 13131200 ps
CPU time 15.66 seconds
Started Aug 18 06:09:10 PM PDT 24
Finished Aug 18 06:09:26 PM PDT 24
Peak memory 284868 kb
Host smart-3486c6f3-ca32-4d5f-8204-09b27df39aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264467495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.264467495
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.3480135728
Short name T788
Test name
Test status
Simulation time 12946800 ps
CPU time 21.04 seconds
Started Aug 18 06:09:04 PM PDT 24
Finished Aug 18 06:09:25 PM PDT 24
Peak memory 274064 kb
Host smart-5b1e4359-4743-49ee-b93e-e0094275f8ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480135728 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.3480135728
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.1542067083
Short name T729
Test name
Test status
Simulation time 10693229000 ps
CPU time 139.91 seconds
Started Aug 18 06:09:01 PM PDT 24
Finished Aug 18 06:11:21 PM PDT 24
Peak memory 261032 kb
Host smart-f6967426-b98f-4873-8f3f-afb2ad9939bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542067083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.1542067083
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.2591322999
Short name T266
Test name
Test status
Simulation time 660023600 ps
CPU time 124.58 seconds
Started Aug 18 06:09:03 PM PDT 24
Finished Aug 18 06:11:08 PM PDT 24
Peak memory 293428 kb
Host smart-4c5605d1-3ece-49a0-b4c5-6c54294324e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591322999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.2591322999
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1201117147
Short name T682
Test name
Test status
Simulation time 23633771300 ps
CPU time 313.4 seconds
Started Aug 18 06:09:03 PM PDT 24
Finished Aug 18 06:14:16 PM PDT 24
Peak memory 285556 kb
Host smart-85aafd15-7fef-4dd8-a614-5c7a625e5665
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201117147 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.1201117147
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.672766687
Short name T1080
Test name
Test status
Simulation time 154575500 ps
CPU time 130.98 seconds
Started Aug 18 06:09:02 PM PDT 24
Finished Aug 18 06:11:13 PM PDT 24
Peak memory 261452 kb
Host smart-f77c1c2b-6138-46f3-8583-3f789647f376
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672766687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ot
p_reset.672766687
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.1625356987
Short name T649
Test name
Test status
Simulation time 75227300 ps
CPU time 31.17 seconds
Started Aug 18 06:09:02 PM PDT 24
Finished Aug 18 06:09:33 PM PDT 24
Peak memory 276204 kb
Host smart-3a9a9d5f-93a2-4783-afd3-a5d36f747933
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625356987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.1625356987
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.1388901618
Short name T1035
Test name
Test status
Simulation time 42640500 ps
CPU time 28.17 seconds
Started Aug 18 06:09:02 PM PDT 24
Finished Aug 18 06:09:31 PM PDT 24
Peak memory 275556 kb
Host smart-d7066dff-427f-4368-ad8e-619d4aed188a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388901618 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.1388901618
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.3143483407
Short name T611
Test name
Test status
Simulation time 5056956900 ps
CPU time 70.42 seconds
Started Aug 18 06:09:10 PM PDT 24
Finished Aug 18 06:10:21 PM PDT 24
Peak memory 265304 kb
Host smart-509b4945-8093-419c-8e9a-5fd8f16bc75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143483407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.3143483407
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.2823090339
Short name T751
Test name
Test status
Simulation time 72525100 ps
CPU time 195.74 seconds
Started Aug 18 06:09:05 PM PDT 24
Finished Aug 18 06:12:20 PM PDT 24
Peak memory 279088 kb
Host smart-e336e52f-ca05-441c-882d-03a5735de352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823090339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.2823090339
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.757415789
Short name T552
Test name
Test status
Simulation time 103443800 ps
CPU time 13.76 seconds
Started Aug 18 06:09:09 PM PDT 24
Finished Aug 18 06:09:23 PM PDT 24
Peak memory 258664 kb
Host smart-31fdb415-5bc3-4830-991a-3a2d158342f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757415789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.757415789
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.516188139
Short name T101
Test name
Test status
Simulation time 14802600 ps
CPU time 13.6 seconds
Started Aug 18 06:09:11 PM PDT 24
Finished Aug 18 06:09:24 PM PDT 24
Peak memory 284948 kb
Host smart-2079cab2-3250-426b-aa06-6ad19f857650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516188139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.516188139
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.4014178811
Short name T43
Test name
Test status
Simulation time 33285733100 ps
CPU time 154.29 seconds
Started Aug 18 06:09:09 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 263656 kb
Host smart-ed180538-d518-4d7d-8230-1e3ce9bfb57a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014178811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.4014178811
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.347776410
Short name T264
Test name
Test status
Simulation time 1812164300 ps
CPU time 209.2 seconds
Started Aug 18 06:09:10 PM PDT 24
Finished Aug 18 06:12:40 PM PDT 24
Peak memory 291440 kb
Host smart-4cfabdfd-a8f0-4cff-a42f-0d844691f591
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347776410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flas
h_ctrl_intr_rd.347776410
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3106559226
Short name T819
Test name
Test status
Simulation time 13545340500 ps
CPU time 267.71 seconds
Started Aug 18 06:09:10 PM PDT 24
Finished Aug 18 06:13:38 PM PDT 24
Peak memory 292796 kb
Host smart-66eac5f8-fb51-4a00-8932-e1c070b55afc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106559226 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.3106559226
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.3817488025
Short name T623
Test name
Test status
Simulation time 38596200 ps
CPU time 112.15 seconds
Started Aug 18 06:09:11 PM PDT 24
Finished Aug 18 06:11:03 PM PDT 24
Peak memory 260720 kb
Host smart-a108f0ce-7a00-483e-bd9e-d741b8baff86
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817488025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.3817488025
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.1778125790
Short name T408
Test name
Test status
Simulation time 2556594100 ps
CPU time 80.09 seconds
Started Aug 18 06:09:10 PM PDT 24
Finished Aug 18 06:10:30 PM PDT 24
Peak memory 264168 kb
Host smart-7fcfcf30-6b2b-4745-ae01-5f24a7f54a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778125790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1778125790
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.2501693905
Short name T688
Test name
Test status
Simulation time 66525300 ps
CPU time 75.85 seconds
Started Aug 18 06:09:11 PM PDT 24
Finished Aug 18 06:10:27 PM PDT 24
Peak memory 276076 kb
Host smart-56b335e6-f152-4384-ad47-b8be12a0a640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501693905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.2501693905
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.3172112835
Short name T500
Test name
Test status
Simulation time 68825100 ps
CPU time 13.88 seconds
Started Aug 18 06:04:47 PM PDT 24
Finished Aug 18 06:05:01 PM PDT 24
Peak memory 258868 kb
Host smart-5b7de377-2397-4fed-9965-9303d27962a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172112835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.3
172112835
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.706945362
Short name T244
Test name
Test status
Simulation time 23337100 ps
CPU time 14.05 seconds
Started Aug 18 06:04:49 PM PDT 24
Finished Aug 18 06:05:03 PM PDT 24
Peak memory 261992 kb
Host smart-e36c7d2e-125a-4801-b68a-2c22fa2835c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706945362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
flash_ctrl_config_regwen.706945362
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.2198666674
Short name T1007
Test name
Test status
Simulation time 15352400 ps
CPU time 13.26 seconds
Started Aug 18 06:04:48 PM PDT 24
Finished Aug 18 06:05:02 PM PDT 24
Peak memory 284728 kb
Host smart-2be9f998-1928-4f35-a473-bcc1726f4491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198666674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.2198666674
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.3543743625
Short name T163
Test name
Test status
Simulation time 759248400 ps
CPU time 195.32 seconds
Started Aug 18 06:04:39 PM PDT 24
Finished Aug 18 06:07:54 PM PDT 24
Peak memory 280944 kb
Host smart-96394f29-b211-4f68-83dc-c1e13d537e96
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543743625 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_derr_detect.3543743625
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.4142501266
Short name T805
Test name
Test status
Simulation time 15811400 ps
CPU time 20.91 seconds
Started Aug 18 06:04:41 PM PDT 24
Finished Aug 18 06:05:02 PM PDT 24
Peak memory 265952 kb
Host smart-99958ed8-283d-495a-9a24-eeee4a251f01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142501266 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.4142501266
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.1547716050
Short name T787
Test name
Test status
Simulation time 2786453400 ps
CPU time 368.69 seconds
Started Aug 18 06:04:32 PM PDT 24
Finished Aug 18 06:10:41 PM PDT 24
Peak memory 263948 kb
Host smart-d0f2bf8f-7be7-42c2-89da-3da952982526
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547716050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.1547716050
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.2888384294
Short name T713
Test name
Test status
Simulation time 7645047400 ps
CPU time 2330.78 seconds
Started Aug 18 06:04:38 PM PDT 24
Finished Aug 18 06:43:29 PM PDT 24
Peak memory 265376 kb
Host smart-583c9f48-8251-4a4f-a084-d578114a92d3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2888384294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.2888384294
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.1105338654
Short name T85
Test name
Test status
Simulation time 2282600500 ps
CPU time 1950.83 seconds
Started Aug 18 06:04:39 PM PDT 24
Finished Aug 18 06:37:10 PM PDT 24
Peak memory 262612 kb
Host smart-62c2a69e-c774-4942-9bb5-7e744fe49e5d
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105338654 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.1105338654
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.12640566
Short name T1059
Test name
Test status
Simulation time 362275000 ps
CPU time 917.02 seconds
Started Aug 18 06:04:39 PM PDT 24
Finished Aug 18 06:19:56 PM PDT 24
Peak memory 273716 kb
Host smart-eacf9992-4024-4842-b218-0058485ddc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12640566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.12640566
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.3201217021
Short name T59
Test name
Test status
Simulation time 4299250100 ps
CPU time 24.25 seconds
Started Aug 18 06:04:40 PM PDT 24
Finished Aug 18 06:05:05 PM PDT 24
Peak memory 263096 kb
Host smart-1ce03f4b-b73f-456e-9973-07b83b192baa
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201217021 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_fetch_code.3201217021
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.913003840
Short name T968
Test name
Test status
Simulation time 1263624800 ps
CPU time 42.21 seconds
Started Aug 18 06:04:48 PM PDT 24
Finished Aug 18 06:05:31 PM PDT 24
Peak memory 265488 kb
Host smart-c40acaf3-ffe7-4dd9-a876-d77d1a549033
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913003840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_fs_sup.913003840
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.3009347096
Short name T789
Test name
Test status
Simulation time 99781369100 ps
CPU time 3955.51 seconds
Started Aug 18 06:04:38 PM PDT 24
Finished Aug 18 07:10:34 PM PDT 24
Peak memory 265660 kb
Host smart-2629d29d-6cfa-4187-8640-31e6a3f3105e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009347096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.3009347096
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.1121152798
Short name T78
Test name
Test status
Simulation time 894244732900 ps
CPU time 2220.16 seconds
Started Aug 18 06:04:40 PM PDT 24
Finished Aug 18 06:41:41 PM PDT 24
Peak memory 264624 kb
Host smart-23b3960a-0bae-482b-81a2-27fd7e9fa24e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121152798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.1121152798
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2256712587
Short name T1097
Test name
Test status
Simulation time 10018401900 ps
CPU time 62.07 seconds
Started Aug 18 06:04:50 PM PDT 24
Finished Aug 18 06:05:52 PM PDT 24
Peak memory 269200 kb
Host smart-077f2e4c-e353-4a81-b72f-afb7aa9d49f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256712587 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.2256712587
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.2348525514
Short name T655
Test name
Test status
Simulation time 25905500 ps
CPU time 13.45 seconds
Started Aug 18 06:04:48 PM PDT 24
Finished Aug 18 06:05:02 PM PDT 24
Peak memory 260696 kb
Host smart-5b59a4a3-4b7c-4f94-9910-ed7dc7a91cd6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348525514 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.2348525514
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.2997965515
Short name T687
Test name
Test status
Simulation time 160179437200 ps
CPU time 919.72 seconds
Started Aug 18 06:04:36 PM PDT 24
Finished Aug 18 06:19:56 PM PDT 24
Peak memory 264944 kb
Host smart-4b924628-6d42-48a4-b716-9ff6e860848d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997965515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.2997965515
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.2698996747
Short name T563
Test name
Test status
Simulation time 6116593800 ps
CPU time 113.29 seconds
Started Aug 18 06:04:34 PM PDT 24
Finished Aug 18 06:06:28 PM PDT 24
Peak memory 263344 kb
Host smart-cdb9dfc3-f27c-483f-9f4d-3e82b04c003b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698996747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.2698996747
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.3406502591
Short name T153
Test name
Test status
Simulation time 24600882700 ps
CPU time 302.87 seconds
Started Aug 18 06:04:39 PM PDT 24
Finished Aug 18 06:09:42 PM PDT 24
Peak memory 285932 kb
Host smart-5cf522fd-7867-4e5f-98bb-775731cc4361
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406502591 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.3406502591
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.3533067223
Short name T867
Test name
Test status
Simulation time 8881859100 ps
CPU time 74.47 seconds
Started Aug 18 06:04:38 PM PDT 24
Finished Aug 18 06:05:53 PM PDT 24
Peak memory 261136 kb
Host smart-1d4001da-f3fb-4c75-9531-d9a6229618d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533067223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.3533067223
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3128735884
Short name T764
Test name
Test status
Simulation time 27278477000 ps
CPU time 207.38 seconds
Started Aug 18 06:04:40 PM PDT 24
Finished Aug 18 06:08:07 PM PDT 24
Peak memory 260916 kb
Host smart-68f0099b-66d2-4a05-bb5a-f779ddb87a31
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312
8735884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3128735884
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.2278418944
Short name T617
Test name
Test status
Simulation time 996809900 ps
CPU time 90.18 seconds
Started Aug 18 06:04:41 PM PDT 24
Finished Aug 18 06:06:12 PM PDT 24
Peak memory 261116 kb
Host smart-a1ef05ca-19ad-4672-b8ad-522ec84a1652
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278418944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.2278418944
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.542714085
Short name T650
Test name
Test status
Simulation time 26649600 ps
CPU time 13.52 seconds
Started Aug 18 06:04:47 PM PDT 24
Finished Aug 18 06:05:01 PM PDT 24
Peak memory 260776 kb
Host smart-8ab126b1-1e93-4579-930b-42f80dceca25
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542714085 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.542714085
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.1786171466
Short name T720
Test name
Test status
Simulation time 2722682000 ps
CPU time 115.42 seconds
Started Aug 18 06:04:41 PM PDT 24
Finished Aug 18 06:06:37 PM PDT 24
Peak memory 265744 kb
Host smart-064d1af2-d161-4e73-ad72-a0e962397e26
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786171466 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.1786171466
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.1607525369
Short name T920
Test name
Test status
Simulation time 160727500 ps
CPU time 133.78 seconds
Started Aug 18 06:04:38 PM PDT 24
Finished Aug 18 06:06:52 PM PDT 24
Peak memory 260692 kb
Host smart-25b1e60b-ba07-400f-8ec0-1d6fd3f79a66
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607525369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.1607525369
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.4142363553
Short name T663
Test name
Test status
Simulation time 6742242600 ps
CPU time 164.58 seconds
Started Aug 18 06:04:40 PM PDT 24
Finished Aug 18 06:07:25 PM PDT 24
Peak memory 290588 kb
Host smart-d04a05c8-e39d-478a-a218-10a814dd35e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142363553 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.4142363553
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.3457233691
Short name T62
Test name
Test status
Simulation time 21039500 ps
CPU time 14.09 seconds
Started Aug 18 06:04:48 PM PDT 24
Finished Aug 18 06:05:03 PM PDT 24
Peak memory 277620 kb
Host smart-1f19420b-9de3-4aea-a48b-9150d706cfe4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3457233691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.3457233691
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.1614735868
Short name T193
Test name
Test status
Simulation time 123544900 ps
CPU time 312.75 seconds
Started Aug 18 06:04:35 PM PDT 24
Finished Aug 18 06:09:48 PM PDT 24
Peak memory 263624 kb
Host smart-160dae80-2c13-4713-840d-a78b9838753b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1614735868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1614735868
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.2773589577
Short name T781
Test name
Test status
Simulation time 157842100 ps
CPU time 14 seconds
Started Aug 18 06:04:49 PM PDT 24
Finished Aug 18 06:05:03 PM PDT 24
Peak memory 265944 kb
Host smart-3ca683c0-6125-498a-b566-b5b2209d1c5d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773589577 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.2773589577
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.4287552413
Short name T593
Test name
Test status
Simulation time 28876500 ps
CPU time 13.82 seconds
Started Aug 18 06:04:44 PM PDT 24
Finished Aug 18 06:04:58 PM PDT 24
Peak memory 259540 kb
Host smart-42ae75dd-b525-4cef-ad7a-ea452d8964f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287552413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.flash_ctrl_prog_reset.4287552413
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.4159770139
Short name T1104
Test name
Test status
Simulation time 171037000 ps
CPU time 1404.01 seconds
Started Aug 18 06:04:35 PM PDT 24
Finished Aug 18 06:27:59 PM PDT 24
Peak memory 290068 kb
Host smart-9201280f-310e-4f2f-a35f-8558ed84bf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159770139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.4159770139
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.3005337539
Short name T633
Test name
Test status
Simulation time 84203300 ps
CPU time 99.47 seconds
Started Aug 18 06:04:32 PM PDT 24
Finished Aug 18 06:06:12 PM PDT 24
Peak memory 263344 kb
Host smart-34703a79-ca65-465a-bbb5-6f7dfa994741
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3005337539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.3005337539
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.1970306091
Short name T577
Test name
Test status
Simulation time 31864700 ps
CPU time 22.69 seconds
Started Aug 18 06:04:43 PM PDT 24
Finished Aug 18 06:05:06 PM PDT 24
Peak memory 265924 kb
Host smart-153338a4-83e7-42b9-86fc-33ca4ef4ff20
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970306091 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.1970306091
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.2902461927
Short name T992
Test name
Test status
Simulation time 45003200 ps
CPU time 23.07 seconds
Started Aug 18 06:04:39 PM PDT 24
Finished Aug 18 06:05:02 PM PDT 24
Peak memory 265456 kb
Host smart-2d7c1ec4-56c2-4f94-9879-02fa5d1ad237
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902461927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.2902461927
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.3697159023
Short name T304
Test name
Test status
Simulation time 558128900 ps
CPU time 135.86 seconds
Started Aug 18 06:04:43 PM PDT 24
Finished Aug 18 06:06:59 PM PDT 24
Peak memory 282304 kb
Host smart-cb37d544-b4a7-40c2-a353-a974c7182728
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697159023 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_ro.3697159023
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.3327625862
Short name T848
Test name
Test status
Simulation time 1050357400 ps
CPU time 173.61 seconds
Started Aug 18 06:04:40 PM PDT 24
Finished Aug 18 06:07:34 PM PDT 24
Peak memory 283652 kb
Host smart-288717f3-2d69-4a33-9d26-5acd9f208342
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3327625862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.3327625862
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.1163147947
Short name T459
Test name
Test status
Simulation time 473462600 ps
CPU time 133.84 seconds
Started Aug 18 06:04:38 PM PDT 24
Finished Aug 18 06:06:52 PM PDT 24
Peak memory 282432 kb
Host smart-655c335f-d2c7-4102-8b5d-86c1a05aa95d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163147947 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.1163147947
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.1185708157
Short name T861
Test name
Test status
Simulation time 24810129700 ps
CPU time 520.33 seconds
Started Aug 18 06:04:39 PM PDT 24
Finished Aug 18 06:13:20 PM PDT 24
Peak memory 310244 kb
Host smart-65b981c8-a4af-4e0f-bff8-6b8b485ad85f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185708157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_rw.1185708157
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_derr.2765581906
Short name T793
Test name
Test status
Simulation time 14237593900 ps
CPU time 244.65 seconds
Started Aug 18 06:04:41 PM PDT 24
Finished Aug 18 06:08:46 PM PDT 24
Peak memory 293300 kb
Host smart-9d70a285-6d4f-4659-8d62-92d8278eb1f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765581906 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_derr.2765581906
Directory /workspace/4.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.3231780248
Short name T1027
Test name
Test status
Simulation time 73592800 ps
CPU time 29.53 seconds
Started Aug 18 06:04:43 PM PDT 24
Finished Aug 18 06:05:13 PM PDT 24
Peak memory 268320 kb
Host smart-b19ab422-37cf-40e6-a9aa-712b634ad7e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231780248 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.3231780248
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.2878226401
Short name T712
Test name
Test status
Simulation time 9278716100 ps
CPU time 254.3 seconds
Started Aug 18 06:04:39 PM PDT 24
Finished Aug 18 06:08:54 PM PDT 24
Peak memory 282420 kb
Host smart-84470440-93e0-41fb-8143-40083779a2c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878226401 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.flash_ctrl_rw_serr.2878226401
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.2074595748
Short name T424
Test name
Test status
Simulation time 2176372700 ps
CPU time 66.15 seconds
Started Aug 18 06:04:41 PM PDT 24
Finished Aug 18 06:05:47 PM PDT 24
Peak memory 265140 kb
Host smart-a9c1fd47-cc89-48ec-8c31-2ee41dd3dcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074595748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2074595748
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.2472344278
Short name T844
Test name
Test status
Simulation time 731556400 ps
CPU time 73.75 seconds
Started Aug 18 06:04:38 PM PDT 24
Finished Aug 18 06:05:52 PM PDT 24
Peak memory 274184 kb
Host smart-710527ba-e14d-42e6-bbd2-56f2057b46da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472344278 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.2472344278
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.1790063099
Short name T816
Test name
Test status
Simulation time 1531578600 ps
CPU time 81.94 seconds
Started Aug 18 06:04:39 PM PDT 24
Finished Aug 18 06:06:01 PM PDT 24
Peak memory 274868 kb
Host smart-0db03c91-5095-496a-909d-d10426f957a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790063099 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_serr_counter.1790063099
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.3982673046
Short name T619
Test name
Test status
Simulation time 78668900 ps
CPU time 121.64 seconds
Started Aug 18 06:04:33 PM PDT 24
Finished Aug 18 06:06:35 PM PDT 24
Peak memory 277084 kb
Host smart-2bcca9cd-bf0a-44a7-ab3f-e073fb73f891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982673046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.3982673046
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.126990645
Short name T826
Test name
Test status
Simulation time 85285100 ps
CPU time 23.37 seconds
Started Aug 18 06:04:32 PM PDT 24
Finished Aug 18 06:04:55 PM PDT 24
Peak memory 260224 kb
Host smart-37d654ad-e26c-4d95-943a-21c2d314bc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126990645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.126990645
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.2470789307
Short name T210
Test name
Test status
Simulation time 5608763500 ps
CPU time 1571.04 seconds
Started Aug 18 06:04:44 PM PDT 24
Finished Aug 18 06:30:55 PM PDT 24
Peak memory 288756 kb
Host smart-99e80fe1-20d5-4d96-a467-74a258c76317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470789307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.2470789307
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.2019442174
Short name T925
Test name
Test status
Simulation time 84397400 ps
CPU time 26.55 seconds
Started Aug 18 06:04:32 PM PDT 24
Finished Aug 18 06:04:59 PM PDT 24
Peak memory 260248 kb
Host smart-7ecf6518-65a3-49b2-bb9a-99dcd3efaa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019442174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2019442174
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.3081349299
Short name T442
Test name
Test status
Simulation time 2013479700 ps
CPU time 170.13 seconds
Started Aug 18 06:04:39 PM PDT 24
Finished Aug 18 06:07:29 PM PDT 24
Peak memory 265824 kb
Host smart-29be8ac4-e358-4b71-8096-3138eab2c281
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081349299 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_wo.3081349299
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.1098663606
Short name T865
Test name
Test status
Simulation time 130057300 ps
CPU time 14.46 seconds
Started Aug 18 06:09:17 PM PDT 24
Finished Aug 18 06:09:32 PM PDT 24
Peak memory 258900 kb
Host smart-63bc814f-a213-4c6c-8333-41d8ba9582fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098663606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
1098663606
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.2267294319
Short name T1040
Test name
Test status
Simulation time 15009300 ps
CPU time 15.88 seconds
Started Aug 18 06:09:17 PM PDT 24
Finished Aug 18 06:09:33 PM PDT 24
Peak memory 283592 kb
Host smart-ee366bb0-97c6-4105-9548-7e8bb07c9df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267294319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.2267294319
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.515701679
Short name T97
Test name
Test status
Simulation time 22451800 ps
CPU time 21.83 seconds
Started Aug 18 06:09:10 PM PDT 24
Finished Aug 18 06:09:32 PM PDT 24
Peak memory 274056 kb
Host smart-bba6e560-02eb-4d03-a042-2dfd11be8bbe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515701679 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.515701679
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.1519652752
Short name T479
Test name
Test status
Simulation time 5262958400 ps
CPU time 65.38 seconds
Started Aug 18 06:09:11 PM PDT 24
Finished Aug 18 06:10:16 PM PDT 24
Peak memory 261200 kb
Host smart-351df7ea-70f9-421d-b86c-ac046d999256
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519652752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.1519652752
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.3142852335
Short name T177
Test name
Test status
Simulation time 70168200 ps
CPU time 132.8 seconds
Started Aug 18 06:09:11 PM PDT 24
Finished Aug 18 06:11:24 PM PDT 24
Peak memory 264784 kb
Host smart-1ada8bb5-9e81-4941-baac-546d8213f6d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142852335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.3142852335
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.3057457074
Short name T970
Test name
Test status
Simulation time 2150649400 ps
CPU time 60.52 seconds
Started Aug 18 06:09:09 PM PDT 24
Finished Aug 18 06:10:10 PM PDT 24
Peak memory 265464 kb
Host smart-1a226593-5d5e-4f23-a0dd-f97b82914f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057457074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.3057457074
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.3810312111
Short name T516
Test name
Test status
Simulation time 18298500 ps
CPU time 76.84 seconds
Started Aug 18 06:09:09 PM PDT 24
Finished Aug 18 06:10:26 PM PDT 24
Peak memory 277184 kb
Host smart-02469a34-2f50-4e45-851c-06c073e7fd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810312111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.3810312111
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.2567274023
Short name T889
Test name
Test status
Simulation time 39299000 ps
CPU time 13.58 seconds
Started Aug 18 06:09:19 PM PDT 24
Finished Aug 18 06:09:32 PM PDT 24
Peak memory 258720 kb
Host smart-02f79f81-c742-44ef-96aa-c0cc0cb37db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567274023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
2567274023
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.2547844431
Short name T1000
Test name
Test status
Simulation time 16837600 ps
CPU time 16.11 seconds
Started Aug 18 06:09:20 PM PDT 24
Finished Aug 18 06:09:37 PM PDT 24
Peak memory 284852 kb
Host smart-a23eae3d-6a78-4389-a8d2-92ad9477dac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547844431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2547844431
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.3427966440
Short name T689
Test name
Test status
Simulation time 15492200 ps
CPU time 22.02 seconds
Started Aug 18 06:09:20 PM PDT 24
Finished Aug 18 06:09:42 PM PDT 24
Peak memory 274084 kb
Host smart-8f66b7aa-8c48-4c78-8b2a-08a412d7c2cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427966440 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.3427966440
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.1099820395
Short name T594
Test name
Test status
Simulation time 6090503300 ps
CPU time 183.8 seconds
Started Aug 18 06:09:19 PM PDT 24
Finished Aug 18 06:12:23 PM PDT 24
Peak memory 261544 kb
Host smart-203b3259-a20e-47ba-b4fd-4e5607b972fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099820395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.1099820395
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.2927140785
Short name T405
Test name
Test status
Simulation time 43722000 ps
CPU time 131.4 seconds
Started Aug 18 06:09:19 PM PDT 24
Finished Aug 18 06:11:30 PM PDT 24
Peak memory 265492 kb
Host smart-248cdcf3-c1fb-466c-8aa8-d65e3dd2fccd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927140785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.2927140785
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.2601110353
Short name T416
Test name
Test status
Simulation time 1093300400 ps
CPU time 64.71 seconds
Started Aug 18 06:09:17 PM PDT 24
Finished Aug 18 06:10:22 PM PDT 24
Peak memory 265648 kb
Host smart-a457f9c3-ac52-40c9-9f89-c46253638eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601110353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2601110353
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.2247532962
Short name T767
Test name
Test status
Simulation time 30718500 ps
CPU time 77.73 seconds
Started Aug 18 06:09:19 PM PDT 24
Finished Aug 18 06:10:36 PM PDT 24
Peak memory 276152 kb
Host smart-d802fd80-b536-4409-b5d7-f56bce00bd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247532962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2247532962
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.118816303
Short name T540
Test name
Test status
Simulation time 115471000 ps
CPU time 13.77 seconds
Started Aug 18 06:09:20 PM PDT 24
Finished Aug 18 06:09:34 PM PDT 24
Peak memory 265732 kb
Host smart-a813d12c-5bda-4f07-ab5d-2be581014e63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118816303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.118816303
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.3778052230
Short name T807
Test name
Test status
Simulation time 15147700 ps
CPU time 13.62 seconds
Started Aug 18 06:09:20 PM PDT 24
Finished Aug 18 06:09:34 PM PDT 24
Peak memory 283552 kb
Host smart-a0bb0871-97bf-45a0-bde2-16fd64a43337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778052230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.3778052230
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.1659966434
Short name T967
Test name
Test status
Simulation time 10848300 ps
CPU time 20.7 seconds
Started Aug 18 06:09:19 PM PDT 24
Finished Aug 18 06:09:40 PM PDT 24
Peak memory 274124 kb
Host smart-3f37dd18-97ee-42d0-881c-469b3a546448
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659966434 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.1659966434
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.4081704439
Short name T319
Test name
Test status
Simulation time 3257461500 ps
CPU time 88.15 seconds
Started Aug 18 06:09:19 PM PDT 24
Finished Aug 18 06:10:47 PM PDT 24
Peak memory 263780 kb
Host smart-76d3d451-915e-4360-b032-96be209f37a2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081704439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.4081704439
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.2100422549
Short name T837
Test name
Test status
Simulation time 296836100 ps
CPU time 112.62 seconds
Started Aug 18 06:09:20 PM PDT 24
Finished Aug 18 06:11:12 PM PDT 24
Peak memory 262744 kb
Host smart-f435c377-9c93-40d5-8eb1-5019fa1d806d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100422549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.2100422549
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.3963681521
Short name T769
Test name
Test status
Simulation time 614793300 ps
CPU time 49.36 seconds
Started Aug 18 06:09:17 PM PDT 24
Finished Aug 18 06:10:07 PM PDT 24
Peak memory 263704 kb
Host smart-f5f70280-3684-4c09-97a6-3386e6dcacb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963681521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.3963681521
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.514819234
Short name T533
Test name
Test status
Simulation time 24012100 ps
CPU time 221.43 seconds
Started Aug 18 06:09:20 PM PDT 24
Finished Aug 18 06:13:02 PM PDT 24
Peak memory 279448 kb
Host smart-fd16b9c9-1bf3-4520-909c-5b9cb719e042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514819234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.514819234
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.77973444
Short name T544
Test name
Test status
Simulation time 130630100 ps
CPU time 13.85 seconds
Started Aug 18 06:09:20 PM PDT 24
Finished Aug 18 06:09:34 PM PDT 24
Peak memory 258704 kb
Host smart-dc73d7f2-e0db-4307-a754-00153805b546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77973444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.77973444
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.4160365898
Short name T944
Test name
Test status
Simulation time 16963000 ps
CPU time 15.74 seconds
Started Aug 18 06:09:19 PM PDT 24
Finished Aug 18 06:09:35 PM PDT 24
Peak memory 283500 kb
Host smart-ec59f0d5-ce23-4a53-bf16-c94bd7dfb461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160365898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.4160365898
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.3040973524
Short name T671
Test name
Test status
Simulation time 145729900 ps
CPU time 20.63 seconds
Started Aug 18 06:09:17 PM PDT 24
Finished Aug 18 06:09:38 PM PDT 24
Peak memory 274164 kb
Host smart-8a8363fc-bd36-4877-ac10-8c999d1ca1fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040973524 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.3040973524
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.3485686264
Short name T480
Test name
Test status
Simulation time 8737551800 ps
CPU time 128.06 seconds
Started Aug 18 06:09:20 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 263796 kb
Host smart-addcec38-5072-4bef-aace-d102131a6849
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485686264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.3485686264
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.1041749110
Short name T822
Test name
Test status
Simulation time 51745000 ps
CPU time 132.48 seconds
Started Aug 18 06:09:16 PM PDT 24
Finished Aug 18 06:11:29 PM PDT 24
Peak memory 260376 kb
Host smart-53aa0dbe-1fec-4e36-a50d-55b8a8c5e167
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041749110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.1041749110
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.752578342
Short name T982
Test name
Test status
Simulation time 41518347600 ps
CPU time 93.11 seconds
Started Aug 18 06:09:19 PM PDT 24
Finished Aug 18 06:10:52 PM PDT 24
Peak memory 264740 kb
Host smart-e4050174-5185-4da4-b554-db117ebbd1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752578342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.752578342
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.3253815209
Short name T1085
Test name
Test status
Simulation time 73208000 ps
CPU time 171.77 seconds
Started Aug 18 06:09:20 PM PDT 24
Finished Aug 18 06:12:12 PM PDT 24
Peak memory 269928 kb
Host smart-6e21cd76-f06a-4a46-abdb-1e13aab164dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253815209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.3253815209
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.3190695225
Short name T1044
Test name
Test status
Simulation time 44607400 ps
CPU time 13.96 seconds
Started Aug 18 06:09:29 PM PDT 24
Finished Aug 18 06:09:43 PM PDT 24
Peak memory 258764 kb
Host smart-967efbbf-a62d-4caf-b83e-cc0c619704d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190695225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
3190695225
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.4161260423
Short name T685
Test name
Test status
Simulation time 16173200 ps
CPU time 15.99 seconds
Started Aug 18 06:09:27 PM PDT 24
Finished Aug 18 06:09:43 PM PDT 24
Peak memory 283568 kb
Host smart-d1ae71e5-55e6-45d3-85ce-1fa52db4000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161260423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.4161260423
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.3086091653
Short name T885
Test name
Test status
Simulation time 10993100 ps
CPU time 21.8 seconds
Started Aug 18 06:09:25 PM PDT 24
Finished Aug 18 06:09:47 PM PDT 24
Peak memory 274008 kb
Host smart-b521fdc0-6889-4fd2-be03-2a67a039b480
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086091653 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.3086091653
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.2270119081
Short name T939
Test name
Test status
Simulation time 35584558600 ps
CPU time 124.57 seconds
Started Aug 18 06:09:25 PM PDT 24
Finished Aug 18 06:11:30 PM PDT 24
Peak memory 263416 kb
Host smart-a90500f6-bb49-4771-8e84-2e15704e3624
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270119081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.2270119081
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.3794642113
Short name T918
Test name
Test status
Simulation time 69971100 ps
CPU time 133.15 seconds
Started Aug 18 06:09:26 PM PDT 24
Finished Aug 18 06:11:39 PM PDT 24
Peak memory 265724 kb
Host smart-0ea16638-7e49-475c-816e-cfd06dff8c81
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794642113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.3794642113
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.136922333
Short name T1028
Test name
Test status
Simulation time 3549675300 ps
CPU time 79.59 seconds
Started Aug 18 06:09:27 PM PDT 24
Finished Aug 18 06:10:47 PM PDT 24
Peak memory 264120 kb
Host smart-baf05ea0-d746-4ed4-8312-dcd4fd662384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136922333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.136922333
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.760579471
Short name T215
Test name
Test status
Simulation time 26461100 ps
CPU time 95.86 seconds
Started Aug 18 06:09:20 PM PDT 24
Finished Aug 18 06:10:56 PM PDT 24
Peak memory 276264 kb
Host smart-34945e1f-19c1-4c4d-b6a7-848d4a0c276e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760579471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.760579471
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.3711185239
Short name T998
Test name
Test status
Simulation time 265950600 ps
CPU time 13.99 seconds
Started Aug 18 06:09:26 PM PDT 24
Finished Aug 18 06:09:40 PM PDT 24
Peak memory 265700 kb
Host smart-e31e37c6-dbf8-4ac1-86fb-b006eb08d726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711185239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
3711185239
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.1090864470
Short name T913
Test name
Test status
Simulation time 24937700 ps
CPU time 13.34 seconds
Started Aug 18 06:09:26 PM PDT 24
Finished Aug 18 06:09:40 PM PDT 24
Peak memory 284704 kb
Host smart-211521d2-8ffb-4959-a954-0a884d6b5255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090864470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.1090864470
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.2646643960
Short name T1063
Test name
Test status
Simulation time 35511400 ps
CPU time 21.76 seconds
Started Aug 18 06:09:25 PM PDT 24
Finished Aug 18 06:09:47 PM PDT 24
Peak memory 273940 kb
Host smart-8ca971d5-b505-4433-8f97-3a9c71eb58fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646643960 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.2646643960
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.3976410920
Short name T904
Test name
Test status
Simulation time 9155486000 ps
CPU time 95.62 seconds
Started Aug 18 06:09:24 PM PDT 24
Finished Aug 18 06:11:00 PM PDT 24
Peak memory 261188 kb
Host smart-0f6cd501-619b-4924-816f-ac0e5350c3e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976410920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.3976410920
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.3690120002
Short name T420
Test name
Test status
Simulation time 3500772200 ps
CPU time 70.87 seconds
Started Aug 18 06:09:30 PM PDT 24
Finished Aug 18 06:10:41 PM PDT 24
Peak memory 260412 kb
Host smart-8f924d7b-63e3-4ee9-95cb-be11aa0d2d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690120002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.3690120002
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.3074646805
Short name T726
Test name
Test status
Simulation time 31924000 ps
CPU time 124.17 seconds
Started Aug 18 06:09:27 PM PDT 24
Finished Aug 18 06:11:31 PM PDT 24
Peak memory 277044 kb
Host smart-6c28fd94-8c34-49b0-ab8d-b2a2cd36b974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074646805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.3074646805
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.1921400008
Short name T1068
Test name
Test status
Simulation time 19780900 ps
CPU time 13.5 seconds
Started Aug 18 06:09:28 PM PDT 24
Finished Aug 18 06:09:42 PM PDT 24
Peak memory 258900 kb
Host smart-1f099fb8-97ce-4cb8-8114-2c14bc8a49af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921400008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
1921400008
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.4215188164
Short name T489
Test name
Test status
Simulation time 88832000 ps
CPU time 15.99 seconds
Started Aug 18 06:09:27 PM PDT 24
Finished Aug 18 06:09:43 PM PDT 24
Peak memory 283524 kb
Host smart-0e3f43fb-3a4c-4279-9690-68970a3873e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215188164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.4215188164
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.3482701429
Short name T164
Test name
Test status
Simulation time 14946000 ps
CPU time 21.02 seconds
Started Aug 18 06:09:28 PM PDT 24
Finished Aug 18 06:09:49 PM PDT 24
Peak memory 274084 kb
Host smart-312c17bd-6e4b-49fc-92cb-2ca2051cf1b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482701429 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.3482701429
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.3086451212
Short name T310
Test name
Test status
Simulation time 11083181200 ps
CPU time 224.48 seconds
Started Aug 18 06:09:28 PM PDT 24
Finished Aug 18 06:13:12 PM PDT 24
Peak memory 261496 kb
Host smart-02ef3292-5b00-4290-83ea-320a6f38d642
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086451212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.3086451212
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.4270150078
Short name T176
Test name
Test status
Simulation time 35919100 ps
CPU time 134.77 seconds
Started Aug 18 06:09:25 PM PDT 24
Finished Aug 18 06:11:40 PM PDT 24
Peak memory 260584 kb
Host smart-8f244c8c-bd3c-4058-a74e-56e1b70f5ad2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270150078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.4270150078
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.2768030473
Short name T411
Test name
Test status
Simulation time 5918153100 ps
CPU time 66.38 seconds
Started Aug 18 06:09:24 PM PDT 24
Finished Aug 18 06:10:31 PM PDT 24
Peak memory 263720 kb
Host smart-039101f3-8a3d-4481-9805-2f0962e243e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768030473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.2768030473
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.2678552696
Short name T1013
Test name
Test status
Simulation time 172864100 ps
CPU time 125.24 seconds
Started Aug 18 06:09:27 PM PDT 24
Finished Aug 18 06:11:32 PM PDT 24
Peak memory 276872 kb
Host smart-ef0637bf-66d2-4908-965d-759541cc8a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678552696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.2678552696
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.1858071564
Short name T473
Test name
Test status
Simulation time 84520500 ps
CPU time 13.54 seconds
Started Aug 18 06:09:38 PM PDT 24
Finished Aug 18 06:09:51 PM PDT 24
Peak memory 258704 kb
Host smart-37199347-43f9-4330-8549-b7e0fa1d4620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858071564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
1858071564
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.207183811
Short name T777
Test name
Test status
Simulation time 233031300 ps
CPU time 16.02 seconds
Started Aug 18 06:09:36 PM PDT 24
Finished Aug 18 06:09:52 PM PDT 24
Peak memory 284900 kb
Host smart-3eaa112b-0f55-4840-833f-94d1466cb999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207183811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.207183811
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.698196397
Short name T812
Test name
Test status
Simulation time 34451300 ps
CPU time 20.64 seconds
Started Aug 18 06:09:37 PM PDT 24
Finished Aug 18 06:09:58 PM PDT 24
Peak memory 274084 kb
Host smart-f830f221-df4f-45e5-8a4a-d8aebeee00f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698196397 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.698196397
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.397453360
Short name T1062
Test name
Test status
Simulation time 1245149400 ps
CPU time 33.84 seconds
Started Aug 18 06:09:25 PM PDT 24
Finished Aug 18 06:09:59 PM PDT 24
Peak memory 261164 kb
Host smart-cb1f08fb-96c1-407c-afc0-e97e3b802d82
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397453360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_h
w_sec_otp.397453360
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.3895848536
Short name T654
Test name
Test status
Simulation time 35141400 ps
CPU time 111.65 seconds
Started Aug 18 06:09:39 PM PDT 24
Finished Aug 18 06:11:31 PM PDT 24
Peak memory 261472 kb
Host smart-700dd45b-b4c6-4728-ac33-36a02499c707
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895848536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.3895848536
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.821647708
Short name T1003
Test name
Test status
Simulation time 7371706400 ps
CPU time 68.37 seconds
Started Aug 18 06:09:39 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 263728 kb
Host smart-8f325373-3b39-4f4c-9b81-78c089fcbb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821647708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.821647708
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.2992489717
Short name T325
Test name
Test status
Simulation time 17791000 ps
CPU time 125.15 seconds
Started Aug 18 06:09:25 PM PDT 24
Finished Aug 18 06:11:31 PM PDT 24
Peak memory 277668 kb
Host smart-27d9041e-7524-4f1a-8490-53822ff476fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992489717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.2992489717
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.1148473395
Short name T447
Test name
Test status
Simulation time 81754100 ps
CPU time 13.93 seconds
Started Aug 18 06:09:36 PM PDT 24
Finished Aug 18 06:09:50 PM PDT 24
Peak memory 258792 kb
Host smart-773cd4ac-87cf-431f-bf49-a689dbffd8a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148473395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
1148473395
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.3743022309
Short name T808
Test name
Test status
Simulation time 29286500 ps
CPU time 13.68 seconds
Started Aug 18 06:09:39 PM PDT 24
Finished Aug 18 06:09:52 PM PDT 24
Peak memory 283420 kb
Host smart-273ebbc0-2732-4e9f-9e29-84af24f9785f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743022309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.3743022309
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.2516579557
Short name T40
Test name
Test status
Simulation time 28124500 ps
CPU time 20.96 seconds
Started Aug 18 06:09:38 PM PDT 24
Finished Aug 18 06:09:59 PM PDT 24
Peak memory 274100 kb
Host smart-f3846293-d482-4c63-984f-b5ed2de3d45d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516579557 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.2516579557
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.1457122415
Short name T1046
Test name
Test status
Simulation time 16550045700 ps
CPU time 86.92 seconds
Started Aug 18 06:09:36 PM PDT 24
Finished Aug 18 06:11:03 PM PDT 24
Peak memory 261112 kb
Host smart-a1984750-01ee-4544-8073-3fdb6c3a0bc0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457122415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.1457122415
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.2673027941
Short name T831
Test name
Test status
Simulation time 88041800 ps
CPU time 133.55 seconds
Started Aug 18 06:09:36 PM PDT 24
Finished Aug 18 06:11:50 PM PDT 24
Peak memory 260488 kb
Host smart-2941b4a4-3938-4e12-90a8-abdb2e864b3b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673027941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.2673027941
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.3681743361
Short name T871
Test name
Test status
Simulation time 2689143600 ps
CPU time 71.46 seconds
Started Aug 18 06:09:36 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 263848 kb
Host smart-e7a9d67a-1cb7-4deb-9e5d-14f953b72523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681743361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.3681743361
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.3676322010
Short name T444
Test name
Test status
Simulation time 22848900 ps
CPU time 52.22 seconds
Started Aug 18 06:09:36 PM PDT 24
Finished Aug 18 06:10:28 PM PDT 24
Peak memory 271676 kb
Host smart-909291f8-1c0a-4c38-84e4-6500ed8d9c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676322010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.3676322010
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.121169921
Short name T1009
Test name
Test status
Simulation time 99969000 ps
CPU time 13.64 seconds
Started Aug 18 06:09:38 PM PDT 24
Finished Aug 18 06:09:52 PM PDT 24
Peak memory 258852 kb
Host smart-0103d697-0e17-41de-ae81-4a7495362a03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121169921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.121169921
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.3220843987
Short name T524
Test name
Test status
Simulation time 16457000 ps
CPU time 13.66 seconds
Started Aug 18 06:09:37 PM PDT 24
Finished Aug 18 06:09:51 PM PDT 24
Peak memory 284824 kb
Host smart-507eb35a-88c6-4e0d-88c7-84c28c08ec6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220843987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.3220843987
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.3990387898
Short name T397
Test name
Test status
Simulation time 10271700 ps
CPU time 21.81 seconds
Started Aug 18 06:09:37 PM PDT 24
Finished Aug 18 06:09:59 PM PDT 24
Peak memory 274164 kb
Host smart-26915949-6d8c-403c-80dc-60430dafb0a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990387898 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.3990387898
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.3728232067
Short name T636
Test name
Test status
Simulation time 5928798400 ps
CPU time 124.06 seconds
Started Aug 18 06:09:38 PM PDT 24
Finished Aug 18 06:11:42 PM PDT 24
Peak memory 261008 kb
Host smart-58ecdf3d-04fd-4474-b28a-d5cf730b8bcb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728232067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.3728232067
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.2240189509
Short name T740
Test name
Test status
Simulation time 81459000 ps
CPU time 135 seconds
Started Aug 18 06:09:36 PM PDT 24
Finished Aug 18 06:11:51 PM PDT 24
Peak memory 265040 kb
Host smart-80d0cbac-630f-497e-9ae5-4c4be2fafa73
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240189509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.2240189509
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.2872120302
Short name T415
Test name
Test status
Simulation time 1112422400 ps
CPU time 65.41 seconds
Started Aug 18 06:09:36 PM PDT 24
Finished Aug 18 06:10:41 PM PDT 24
Peak memory 265168 kb
Host smart-d559ce74-b756-46f7-9c79-88536801f32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872120302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.2872120302
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.2830584485
Short name T21
Test name
Test status
Simulation time 33153000 ps
CPU time 123.16 seconds
Started Aug 18 06:09:37 PM PDT 24
Finished Aug 18 06:11:40 PM PDT 24
Peak memory 276968 kb
Host smart-1465e483-144d-4297-be93-3e51a3dfdd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830584485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.2830584485
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.413911854
Short name T659
Test name
Test status
Simulation time 43309000 ps
CPU time 13.62 seconds
Started Aug 18 06:04:56 PM PDT 24
Finished Aug 18 06:05:10 PM PDT 24
Peak memory 258832 kb
Host smart-c0733d24-5e32-40c4-9f2c-d5018d38b9b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413911854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.413911854
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.4223341903
Short name T1030
Test name
Test status
Simulation time 15146600 ps
CPU time 15.86 seconds
Started Aug 18 06:04:55 PM PDT 24
Finished Aug 18 06:05:10 PM PDT 24
Peak memory 284836 kb
Host smart-a28f4b39-8f15-4b0d-bec6-e61686a3d483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223341903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.4223341903
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.3042806986
Short name T74
Test name
Test status
Simulation time 10691500 ps
CPU time 21.97 seconds
Started Aug 18 06:04:55 PM PDT 24
Finished Aug 18 06:05:17 PM PDT 24
Peak memory 274092 kb
Host smart-87841521-b86f-4006-a4ec-5fa7624fcf40
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042806986 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.3042806986
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.3433851410
Short name T188
Test name
Test status
Simulation time 925419700 ps
CPU time 981.47 seconds
Started Aug 18 06:04:49 PM PDT 24
Finished Aug 18 06:21:10 PM PDT 24
Peak memory 273900 kb
Host smart-58e6baaf-0447-4e75-8615-b741fb068778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433851410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.3433851410
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.2322362616
Short name T948
Test name
Test status
Simulation time 854189800 ps
CPU time 19.16 seconds
Started Aug 18 06:04:47 PM PDT 24
Finished Aug 18 06:05:06 PM PDT 24
Peak memory 264104 kb
Host smart-96519690-265d-48d8-ba60-4af1daa472dc
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322362616 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.flash_ctrl_fetch_code.2322362616
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.166616057
Short name T273
Test name
Test status
Simulation time 10036113800 ps
CPU time 55.5 seconds
Started Aug 18 06:04:55 PM PDT 24
Finished Aug 18 06:05:51 PM PDT 24
Peak memory 269100 kb
Host smart-4c43d4b5-96ff-4731-a679-57c23857264c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166616057 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.166616057
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.1884483401
Short name T612
Test name
Test status
Simulation time 15270500 ps
CPU time 13.51 seconds
Started Aug 18 06:04:56 PM PDT 24
Finished Aug 18 06:05:09 PM PDT 24
Peak memory 265232 kb
Host smart-81ba8028-5f38-4598-9d32-c5b90431b0e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884483401 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.1884483401
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.71935302
Short name T736
Test name
Test status
Simulation time 40122732900 ps
CPU time 795.89 seconds
Started Aug 18 06:04:50 PM PDT 24
Finished Aug 18 06:18:06 PM PDT 24
Peak memory 264600 kb
Host smart-b7e1f820-c705-4aac-b2e3-df2f699c89d6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71935302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.flash_ctrl_hw_rma_reset.71935302
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.4097447606
Short name T308
Test name
Test status
Simulation time 1684691700 ps
CPU time 148.99 seconds
Started Aug 18 06:04:47 PM PDT 24
Finished Aug 18 06:07:16 PM PDT 24
Peak memory 261476 kb
Host smart-b388de21-4e83-4155-813a-831352b8feeb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097447606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.4097447606
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.177132905
Short name T973
Test name
Test status
Simulation time 3190882000 ps
CPU time 213.21 seconds
Started Aug 18 06:04:55 PM PDT 24
Finished Aug 18 06:08:28 PM PDT 24
Peak memory 291524 kb
Host smart-d97be16c-6e92-4ba4-9289-f3db9b90e7dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177132905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash
_ctrl_intr_rd.177132905
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.2498839571
Short name T625
Test name
Test status
Simulation time 22091042500 ps
CPU time 163.27 seconds
Started Aug 18 06:04:55 PM PDT 24
Finished Aug 18 06:07:39 PM PDT 24
Peak memory 293468 kb
Host smart-178856e7-2ebb-4ca1-af31-e282a724d0de
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498839571 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.2498839571
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.2699748978
Short name T498
Test name
Test status
Simulation time 8953575100 ps
CPU time 74.17 seconds
Started Aug 18 06:04:55 PM PDT 24
Finished Aug 18 06:06:09 PM PDT 24
Peak memory 265812 kb
Host smart-4aab2229-d293-4864-8a90-257e10cc1ce9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699748978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.2699748978
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3025504285
Short name T984
Test name
Test status
Simulation time 24064512500 ps
CPU time 188.26 seconds
Started Aug 18 06:04:57 PM PDT 24
Finished Aug 18 06:08:06 PM PDT 24
Peak memory 261124 kb
Host smart-52da38ef-1b66-4dbd-ba94-6610908381e9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302
5504285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.3025504285
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.2078223609
Short name T433
Test name
Test status
Simulation time 8710285800 ps
CPU time 73.04 seconds
Started Aug 18 06:04:48 PM PDT 24
Finished Aug 18 06:06:02 PM PDT 24
Peak memory 263832 kb
Host smart-e270b2a0-56b6-4b34-8997-f14820981302
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078223609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.2078223609
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.1943835
Short name T815
Test name
Test status
Simulation time 15702900 ps
CPU time 13.99 seconds
Started Aug 18 06:04:56 PM PDT 24
Finished Aug 18 06:05:10 PM PDT 24
Peak memory 265288 kb
Host smart-b61d8e67-1296-435a-854e-e4efe86568af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943835 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.1943835
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.402743660
Short name T430
Test name
Test status
Simulation time 9822766500 ps
CPU time 206.4 seconds
Started Aug 18 06:04:49 PM PDT 24
Finished Aug 18 06:08:15 PM PDT 24
Peak memory 265584 kb
Host smart-7154d461-3ddb-43cd-b7d0-4c0b6ec4d608
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402743660 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.402743660
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.3351632337
Short name T546
Test name
Test status
Simulation time 126027900 ps
CPU time 132.05 seconds
Started Aug 18 06:04:49 PM PDT 24
Finished Aug 18 06:07:01 PM PDT 24
Peak memory 260276 kb
Host smart-32b5741a-6bf9-4cc1-a524-59136df8d166
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351632337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.3351632337
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.771608040
Short name T868
Test name
Test status
Simulation time 3581201000 ps
CPU time 361.05 seconds
Started Aug 18 06:04:48 PM PDT 24
Finished Aug 18 06:10:49 PM PDT 24
Peak memory 263700 kb
Host smart-174a8276-6e90-45c4-bf5c-586728c505d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=771608040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.771608040
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.4028587566
Short name T792
Test name
Test status
Simulation time 39282900 ps
CPU time 13.59 seconds
Started Aug 18 06:04:55 PM PDT 24
Finished Aug 18 06:05:09 PM PDT 24
Peak memory 265704 kb
Host smart-8823cd96-0ed9-4922-bbf4-a21647a4ecdd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028587566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.flash_ctrl_prog_reset.4028587566
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.3931067565
Short name T222
Test name
Test status
Simulation time 2844652000 ps
CPU time 649.14 seconds
Started Aug 18 06:04:47 PM PDT 24
Finished Aug 18 06:15:36 PM PDT 24
Peak memory 283880 kb
Host smart-6f4ba2fe-7801-4c8c-82e0-2ffc1d9170a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931067565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.3931067565
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.2296927670
Short name T358
Test name
Test status
Simulation time 150786500 ps
CPU time 33.59 seconds
Started Aug 18 06:04:54 PM PDT 24
Finished Aug 18 06:05:28 PM PDT 24
Peak memory 274204 kb
Host smart-e1ba214a-880e-4170-a62d-2f7e8218bca0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296927670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.2296927670
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.774962030
Short name T895
Test name
Test status
Simulation time 3098942900 ps
CPU time 113.17 seconds
Started Aug 18 06:04:48 PM PDT 24
Finished Aug 18 06:06:42 PM PDT 24
Peak memory 282400 kb
Host smart-27d82f9e-e719-454b-b160-cd743b8b0c20
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774962030 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.flash_ctrl_ro.774962030
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.1322145319
Short name T621
Test name
Test status
Simulation time 664614500 ps
CPU time 168.37 seconds
Started Aug 18 06:04:57 PM PDT 24
Finished Aug 18 06:07:45 PM PDT 24
Peak memory 282436 kb
Host smart-4a8e8839-9cd5-4ec0-b0a1-c30ea979c503
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1322145319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.1322145319
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.3447945030
Short name T299
Test name
Test status
Simulation time 2573410400 ps
CPU time 128.57 seconds
Started Aug 18 06:04:48 PM PDT 24
Finished Aug 18 06:06:57 PM PDT 24
Peak memory 295864 kb
Host smart-0674a772-b2b6-4efa-9499-a774f6d87128
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447945030 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.3447945030
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.3267812636
Short name T727
Test name
Test status
Simulation time 56079493800 ps
CPU time 575.61 seconds
Started Aug 18 06:04:49 PM PDT 24
Finished Aug 18 06:14:25 PM PDT 24
Peak memory 314804 kb
Host smart-e2d0b17a-9543-4eca-800d-1c9c009338b5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267812636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.flash_ctrl_rw.3267812636
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.493699825
Short name T917
Test name
Test status
Simulation time 12398964500 ps
CPU time 242.18 seconds
Started Aug 18 06:04:57 PM PDT 24
Finished Aug 18 06:08:59 PM PDT 24
Peak memory 291216 kb
Host smart-436bb8d4-8e6b-433d-8ca1-df56380c605b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493699825 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_derr.493699825
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.370831813
Short name T568
Test name
Test status
Simulation time 9239604700 ps
CPU time 171.67 seconds
Started Aug 18 06:04:55 PM PDT 24
Finished Aug 18 06:07:46 PM PDT 24
Peak memory 295940 kb
Host smart-541ba20a-06e6-4873-81c4-206695fe3ac0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370831813 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.flash_ctrl_rw_serr.370831813
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.3133544142
Short name T606
Test name
Test status
Simulation time 1717327100 ps
CPU time 75.05 seconds
Started Aug 18 06:04:54 PM PDT 24
Finished Aug 18 06:06:09 PM PDT 24
Peak memory 264180 kb
Host smart-7895cc5f-be7d-4513-b6f0-7e0e53366c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133544142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3133544142
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.2923753915
Short name T795
Test name
Test status
Simulation time 25949900 ps
CPU time 191.99 seconds
Started Aug 18 06:04:50 PM PDT 24
Finished Aug 18 06:08:02 PM PDT 24
Peak memory 280168 kb
Host smart-e473837e-94d4-4024-8118-60fd1446cf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923753915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2923753915
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.2030925303
Short name T515
Test name
Test status
Simulation time 5425448800 ps
CPU time 220.07 seconds
Started Aug 18 06:04:47 PM PDT 24
Finished Aug 18 06:08:27 PM PDT 24
Peak memory 265744 kb
Host smart-f7a067c1-492c-4974-90cc-a968f53d23ad
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030925303 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.flash_ctrl_wo.2030925303
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.1675320344
Short name T517
Test name
Test status
Simulation time 22025500 ps
CPU time 15.61 seconds
Started Aug 18 06:09:52 PM PDT 24
Finished Aug 18 06:10:07 PM PDT 24
Peak memory 284936 kb
Host smart-6f854e7e-93a3-4d29-a77e-11179f7a756d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675320344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.1675320344
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.147858243
Short name T1102
Test name
Test status
Simulation time 79047000 ps
CPU time 132.2 seconds
Started Aug 18 06:09:46 PM PDT 24
Finished Aug 18 06:11:58 PM PDT 24
Peak memory 265380 kb
Host smart-806c7a38-9b3a-4cef-9130-91e3f40cdfa8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147858243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_ot
p_reset.147858243
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.3706683529
Short name T481
Test name
Test status
Simulation time 47099000 ps
CPU time 16.17 seconds
Started Aug 18 06:09:46 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 284836 kb
Host smart-26ea2c47-6c6e-42df-966f-273a39cc6c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706683529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.3706683529
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.3090100419
Short name T528
Test name
Test status
Simulation time 69728600 ps
CPU time 112.07 seconds
Started Aug 18 06:09:46 PM PDT 24
Finished Aug 18 06:11:38 PM PDT 24
Peak memory 260536 kb
Host smart-046d39ac-f650-44ba-b8b4-ccf7d63130d3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090100419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.3090100419
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.3046650782
Short name T1100
Test name
Test status
Simulation time 17246900 ps
CPU time 16.18 seconds
Started Aug 18 06:09:45 PM PDT 24
Finished Aug 18 06:10:01 PM PDT 24
Peak memory 284816 kb
Host smart-eda17cfa-141b-46f2-b122-84383a7f73b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046650782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.3046650782
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.3734741352
Short name T694
Test name
Test status
Simulation time 78765300 ps
CPU time 131.9 seconds
Started Aug 18 06:09:44 PM PDT 24
Finished Aug 18 06:11:56 PM PDT 24
Peak memory 261536 kb
Host smart-4e29c30e-9e29-4be9-bd27-d5a3b9fe2391
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734741352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.3734741352
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.1923310667
Short name T737
Test name
Test status
Simulation time 17219100 ps
CPU time 13.38 seconds
Started Aug 18 06:09:44 PM PDT 24
Finished Aug 18 06:09:57 PM PDT 24
Peak memory 284820 kb
Host smart-3f3e4faf-7656-449e-a4f4-25f453d3a800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923310667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1923310667
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.510196131
Short name T954
Test name
Test status
Simulation time 41215800 ps
CPU time 133.75 seconds
Started Aug 18 06:09:46 PM PDT 24
Finished Aug 18 06:12:00 PM PDT 24
Peak memory 260776 kb
Host smart-29f00f81-153d-41af-b1cd-2ae27815847e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510196131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_ot
p_reset.510196131
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.2694698889
Short name T660
Test name
Test status
Simulation time 26222900 ps
CPU time 13.34 seconds
Started Aug 18 06:09:50 PM PDT 24
Finished Aug 18 06:10:04 PM PDT 24
Peak memory 283264 kb
Host smart-411646a6-ded0-4111-9e27-70a5fbe2d081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694698889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.2694698889
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.2998395821
Short name T803
Test name
Test status
Simulation time 78593000 ps
CPU time 132.72 seconds
Started Aug 18 06:09:52 PM PDT 24
Finished Aug 18 06:12:05 PM PDT 24
Peak memory 260824 kb
Host smart-709a6a30-c6f5-48aa-849d-2e4673410eaa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998395821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.2998395821
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.1124746617
Short name T553
Test name
Test status
Simulation time 51495800 ps
CPU time 16.15 seconds
Started Aug 18 06:09:46 PM PDT 24
Finished Aug 18 06:10:03 PM PDT 24
Peak memory 284768 kb
Host smart-5bcf7e6a-7fa0-4842-87ce-f7fab906fa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124746617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.1124746617
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.99485862
Short name T472
Test name
Test status
Simulation time 694538300 ps
CPU time 112.47 seconds
Started Aug 18 06:09:42 PM PDT 24
Finished Aug 18 06:11:35 PM PDT 24
Peak memory 265836 kb
Host smart-560f8b1a-51f0-4c0a-8b64-4d1451224725
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99485862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_otp
_reset.99485862
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.4276812829
Short name T618
Test name
Test status
Simulation time 52860300 ps
CPU time 15.67 seconds
Started Aug 18 06:09:46 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 283416 kb
Host smart-6df99218-edd4-435c-96dc-e13d51557b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276812829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.4276812829
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.1537081285
Short name T505
Test name
Test status
Simulation time 300278900 ps
CPU time 133.63 seconds
Started Aug 18 06:09:44 PM PDT 24
Finished Aug 18 06:11:58 PM PDT 24
Peak memory 261556 kb
Host smart-983409f4-3305-404d-b1e8-39be6a780e5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537081285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.1537081285
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.2078793382
Short name T501
Test name
Test status
Simulation time 19596500 ps
CPU time 13.4 seconds
Started Aug 18 06:09:50 PM PDT 24
Finished Aug 18 06:10:03 PM PDT 24
Peak memory 284788 kb
Host smart-dc0c6694-305e-4fae-b595-1bc1b290c947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078793382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.2078793382
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.783404813
Short name T972
Test name
Test status
Simulation time 40187800 ps
CPU time 132.63 seconds
Started Aug 18 06:09:47 PM PDT 24
Finished Aug 18 06:12:00 PM PDT 24
Peak memory 260412 kb
Host smart-de1a86d0-dc46-4c33-8ada-fcbb7619511f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783404813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_ot
p_reset.783404813
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.4073767138
Short name T1054
Test name
Test status
Simulation time 12886000 ps
CPU time 15.49 seconds
Started Aug 18 06:09:45 PM PDT 24
Finished Aug 18 06:10:01 PM PDT 24
Peak memory 283180 kb
Host smart-0ae7d07b-ef83-48a9-984e-c37c0802ee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073767138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.4073767138
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.1292765667
Short name T511
Test name
Test status
Simulation time 135780900 ps
CPU time 131.13 seconds
Started Aug 18 06:09:45 PM PDT 24
Finished Aug 18 06:11:56 PM PDT 24
Peak memory 260280 kb
Host smart-af45ba2c-0f4c-4240-bea8-64200046bf19
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292765667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.1292765667
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.3771447285
Short name T821
Test name
Test status
Simulation time 131789000 ps
CPU time 15.93 seconds
Started Aug 18 06:09:48 PM PDT 24
Finished Aug 18 06:10:04 PM PDT 24
Peak memory 284792 kb
Host smart-13828dfb-862d-4109-9a59-2ed5eead8292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771447285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.3771447285
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.1516245490
Short name T495
Test name
Test status
Simulation time 42365600 ps
CPU time 131.5 seconds
Started Aug 18 06:09:44 PM PDT 24
Finished Aug 18 06:11:56 PM PDT 24
Peak memory 261480 kb
Host smart-20480543-02cb-42a9-bd16-fa6f87562398
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516245490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.1516245490
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.594662504
Short name T441
Test name
Test status
Simulation time 54335000 ps
CPU time 14.05 seconds
Started Aug 18 06:05:14 PM PDT 24
Finished Aug 18 06:05:28 PM PDT 24
Peak memory 265792 kb
Host smart-9d52859e-7c1c-4f63-95bd-6b34ce60fd1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594662504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.594662504
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.1321139367
Short name T601
Test name
Test status
Simulation time 26943900 ps
CPU time 15.77 seconds
Started Aug 18 06:05:14 PM PDT 24
Finished Aug 18 06:05:30 PM PDT 24
Peak memory 283612 kb
Host smart-da767bbd-f92d-4a28-9f71-38dae067e5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321139367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1321139367
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.3848911716
Short name T589
Test name
Test status
Simulation time 11388600 ps
CPU time 21.93 seconds
Started Aug 18 06:05:12 PM PDT 24
Finished Aug 18 06:05:34 PM PDT 24
Peak memory 274036 kb
Host smart-d954ad27-7f57-4190-90cf-860cf8e1420d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848911716 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.3848911716
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.3206752475
Short name T68
Test name
Test status
Simulation time 3382445400 ps
CPU time 2208.72 seconds
Started Aug 18 06:05:05 PM PDT 24
Finished Aug 18 06:41:54 PM PDT 24
Peak memory 265636 kb
Host smart-80454086-ff5f-4feb-ae35-aeea3df157f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3206752475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.3206752475
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.347994279
Short name T599
Test name
Test status
Simulation time 1065597600 ps
CPU time 915.59 seconds
Started Aug 18 06:05:04 PM PDT 24
Finished Aug 18 06:20:20 PM PDT 24
Peak memory 273320 kb
Host smart-11f85d89-ed05-40fb-a247-390425899598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347994279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.347994279
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.1098035061
Short name T989
Test name
Test status
Simulation time 822599700 ps
CPU time 28.64 seconds
Started Aug 18 06:05:04 PM PDT 24
Finished Aug 18 06:05:33 PM PDT 24
Peak memory 263120 kb
Host smart-fd00254c-3c55-4218-9baf-df9691f7ee80
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098035061 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_fetch_code.1098035061
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3171348606
Short name T271
Test name
Test status
Simulation time 10019140700 ps
CPU time 65.74 seconds
Started Aug 18 06:05:12 PM PDT 24
Finished Aug 18 06:06:18 PM PDT 24
Peak memory 286380 kb
Host smart-be9e111b-b1dd-4c5d-935d-e1fc7c8405f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171348606 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.3171348606
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.830749144
Short name T666
Test name
Test status
Simulation time 143232000 ps
CPU time 13.61 seconds
Started Aug 18 06:05:13 PM PDT 24
Finished Aug 18 06:05:27 PM PDT 24
Peak memory 258932 kb
Host smart-e8fdb751-f0f3-425a-9853-1882d4a53446
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830749144 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.830749144
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.267463842
Short name T186
Test name
Test status
Simulation time 210196462200 ps
CPU time 900.92 seconds
Started Aug 18 06:05:02 PM PDT 24
Finished Aug 18 06:20:04 PM PDT 24
Peak memory 264700 kb
Host smart-332d23b4-a863-48c7-9263-a11a34bac206
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267463842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.flash_ctrl_hw_rma_reset.267463842
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.1118507128
Short name T42
Test name
Test status
Simulation time 5688139400 ps
CPU time 83.88 seconds
Started Aug 18 06:05:03 PM PDT 24
Finished Aug 18 06:06:27 PM PDT 24
Peak memory 263872 kb
Host smart-af227534-33ba-4d27-a959-d7aaaf498d5c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118507128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.1118507128
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.974683331
Short name T346
Test name
Test status
Simulation time 2906262900 ps
CPU time 150.3 seconds
Started Aug 18 06:05:02 PM PDT 24
Finished Aug 18 06:07:33 PM PDT 24
Peak memory 294820 kb
Host smart-0964bea2-d470-4f17-b986-5b4be6fd064b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974683331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_intr_rd.974683331
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.1667316520
Short name T710
Test name
Test status
Simulation time 9478867300 ps
CPU time 243.67 seconds
Started Aug 18 06:05:05 PM PDT 24
Finished Aug 18 06:09:08 PM PDT 24
Peak memory 294992 kb
Host smart-80e8d116-4e8b-46d5-bfac-40edc10ead73
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667316520 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.1667316520
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.1041434925
Short name T814
Test name
Test status
Simulation time 2397173700 ps
CPU time 73.01 seconds
Started Aug 18 06:05:05 PM PDT 24
Finished Aug 18 06:06:19 PM PDT 24
Peak memory 261084 kb
Host smart-41fcfc26-8c69-4bfc-892b-e7f9166fa817
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041434925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.1041434925
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3657487054
Short name T893
Test name
Test status
Simulation time 19870678200 ps
CPU time 163.9 seconds
Started Aug 18 06:05:03 PM PDT 24
Finished Aug 18 06:07:47 PM PDT 24
Peak memory 260756 kb
Host smart-1f8532a5-4e5d-4a65-b6cc-c90eb0643915
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365
7487054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.3657487054
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.1347578146
Short name T581
Test name
Test status
Simulation time 3360309700 ps
CPU time 79.59 seconds
Started Aug 18 06:05:04 PM PDT 24
Finished Aug 18 06:06:23 PM PDT 24
Peak memory 261208 kb
Host smart-956686a0-eeaf-4e64-a259-93e727477941
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347578146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.1347578146
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.1069344400
Short name T168
Test name
Test status
Simulation time 44888800 ps
CPU time 14.11 seconds
Started Aug 18 06:05:12 PM PDT 24
Finished Aug 18 06:05:26 PM PDT 24
Peak memory 260700 kb
Host smart-25cd5994-135f-412a-b61e-a997988c5b55
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069344400 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.1069344400
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.3296436807
Short name T124
Test name
Test status
Simulation time 14513006800 ps
CPU time 145.04 seconds
Started Aug 18 06:05:04 PM PDT 24
Finished Aug 18 06:07:29 PM PDT 24
Peak memory 265772 kb
Host smart-316fd140-4a4f-466c-8b2a-656114122347
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296436807 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.3296436807
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.3772572291
Short name T1079
Test name
Test status
Simulation time 38943100 ps
CPU time 130.92 seconds
Started Aug 18 06:05:03 PM PDT 24
Finished Aug 18 06:07:14 PM PDT 24
Peak memory 264144 kb
Host smart-affd89a0-eded-4d60-9805-8b8ac866fec3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772572291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.3772572291
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.1480971383
Short name T946
Test name
Test status
Simulation time 10169887000 ps
CPU time 421.88 seconds
Started Aug 18 06:04:57 PM PDT 24
Finished Aug 18 06:11:59 PM PDT 24
Peak memory 263672 kb
Host smart-ed9e912d-54fb-41d5-b0f0-37593e264ad5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480971383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.1480971383
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.2854499141
Short name T591
Test name
Test status
Simulation time 22495700 ps
CPU time 13.87 seconds
Started Aug 18 06:05:14 PM PDT 24
Finished Aug 18 06:05:28 PM PDT 24
Peak memory 265836 kb
Host smart-b1ccb59f-da1e-4e4f-8cce-6ebbc81947f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854499141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.flash_ctrl_prog_reset.2854499141
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.373977839
Short name T783
Test name
Test status
Simulation time 1381572800 ps
CPU time 274.89 seconds
Started Aug 18 06:04:55 PM PDT 24
Finished Aug 18 06:09:30 PM PDT 24
Peak memory 282064 kb
Host smart-9c7f9702-9293-4752-ab07-4773ac21f6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373977839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.373977839
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.3470837772
Short name T360
Test name
Test status
Simulation time 300254300 ps
CPU time 34.47 seconds
Started Aug 18 06:05:14 PM PDT 24
Finished Aug 18 06:05:49 PM PDT 24
Peak memory 276192 kb
Host smart-84b06ffe-eb5b-4198-abf3-086f76a7fa42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470837772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.3470837772
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.780279795
Short name T497
Test name
Test status
Simulation time 529289800 ps
CPU time 118.51 seconds
Started Aug 18 06:05:03 PM PDT 24
Finished Aug 18 06:07:02 PM PDT 24
Peak memory 282404 kb
Host smart-3df42e59-3038-404c-9f8c-9ceb72d3f0bf
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780279795 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_ro.780279795
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.1169087005
Short name T708
Test name
Test status
Simulation time 9155943800 ps
CPU time 153.53 seconds
Started Aug 18 06:05:02 PM PDT 24
Finished Aug 18 06:07:35 PM PDT 24
Peak memory 282416 kb
Host smart-f6f7c8a4-7f6f-4876-9a41-12001ed5ef43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1169087005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.1169087005
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.4012236276
Short name T575
Test name
Test status
Simulation time 1218737500 ps
CPU time 122.62 seconds
Started Aug 18 06:05:03 PM PDT 24
Finished Aug 18 06:07:06 PM PDT 24
Peak memory 282236 kb
Host smart-3944624f-75aa-4eff-b025-94da212c1ba1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012236276 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.4012236276
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.110087228
Short name T560
Test name
Test status
Simulation time 7035619000 ps
CPU time 235.24 seconds
Started Aug 18 06:05:05 PM PDT 24
Finished Aug 18 06:09:00 PM PDT 24
Peak memory 292292 kb
Host smart-f1cd9e57-94fc-4a5e-a008-c196de4a6d1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110087228 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_derr.110087228
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.377977835
Short name T829
Test name
Test status
Simulation time 26586800 ps
CPU time 32.12 seconds
Started Aug 18 06:05:14 PM PDT 24
Finished Aug 18 06:05:47 PM PDT 24
Peak memory 268132 kb
Host smart-a6d064ab-6345-4469-b0b3-c64c59e65ae6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377977835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_rw_evict.377977835
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.1002208477
Short name T723
Test name
Test status
Simulation time 27233800 ps
CPU time 31.79 seconds
Started Aug 18 06:05:14 PM PDT 24
Finished Aug 18 06:05:46 PM PDT 24
Peak memory 276240 kb
Host smart-681b0688-ec95-4146-a88f-4f05fd3b5c90
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002208477 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.1002208477
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.4196618083
Short name T820
Test name
Test status
Simulation time 4469333700 ps
CPU time 64.57 seconds
Started Aug 18 06:05:14 PM PDT 24
Finished Aug 18 06:06:19 PM PDT 24
Peak memory 265072 kb
Host smart-64678fb1-f04e-433e-9335-011e42ac0bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196618083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.4196618083
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.1349955491
Short name T576
Test name
Test status
Simulation time 36551900 ps
CPU time 122.79 seconds
Started Aug 18 06:04:55 PM PDT 24
Finished Aug 18 06:06:58 PM PDT 24
Peak memory 277984 kb
Host smart-23c58376-5c81-4999-a75a-ee0e15a51207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349955491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.1349955491
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.3441526572
Short name T851
Test name
Test status
Simulation time 2029622200 ps
CPU time 141.18 seconds
Started Aug 18 06:05:03 PM PDT 24
Finished Aug 18 06:07:25 PM PDT 24
Peak memory 260452 kb
Host smart-4385047f-215f-4985-82ad-078259b48fbe
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441526572 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.flash_ctrl_wo.3441526572
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.2609591397
Short name T852
Test name
Test status
Simulation time 16684100 ps
CPU time 16.36 seconds
Started Aug 18 06:09:46 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 284848 kb
Host smart-a006bbb2-2ab0-4a3a-802c-f4ebfec4c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609591397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.2609591397
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.3760430041
Short name T632
Test name
Test status
Simulation time 40617600 ps
CPU time 110.42 seconds
Started Aug 18 06:09:44 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 260508 kb
Host smart-4393d029-8205-4cb7-a0eb-f0f2aa871594
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760430041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.3760430041
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.1019526947
Short name T1001
Test name
Test status
Simulation time 14073600 ps
CPU time 16 seconds
Started Aug 18 06:09:50 PM PDT 24
Finished Aug 18 06:10:06 PM PDT 24
Peak memory 283428 kb
Host smart-50ea5101-e26b-465a-a4e0-282d4befc451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019526947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.1019526947
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.2538061340
Short name T746
Test name
Test status
Simulation time 145221000 ps
CPU time 133.1 seconds
Started Aug 18 06:09:52 PM PDT 24
Finished Aug 18 06:12:05 PM PDT 24
Peak memory 260508 kb
Host smart-0e5b03e3-738b-4655-9064-ab61b5566455
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538061340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.2538061340
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.4051144823
Short name T328
Test name
Test status
Simulation time 27818400 ps
CPU time 13.5 seconds
Started Aug 18 06:09:45 PM PDT 24
Finished Aug 18 06:09:59 PM PDT 24
Peak memory 284748 kb
Host smart-0580962f-2d7f-45d0-9d70-d7772d3dacee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051144823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.4051144823
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.3745221208
Short name T678
Test name
Test status
Simulation time 37397300 ps
CPU time 111.35 seconds
Started Aug 18 06:09:50 PM PDT 24
Finished Aug 18 06:11:42 PM PDT 24
Peak memory 260128 kb
Host smart-1077ed30-b557-46e4-ba0d-d9d7f07c7539
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745221208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.3745221208
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.2240703899
Short name T897
Test name
Test status
Simulation time 206496200 ps
CPU time 15.73 seconds
Started Aug 18 06:09:52 PM PDT 24
Finished Aug 18 06:10:07 PM PDT 24
Peak memory 284892 kb
Host smart-fb4295f2-76a6-4471-8dde-e5ff0279c766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240703899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.2240703899
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.649302750
Short name T1071
Test name
Test status
Simulation time 133723600 ps
CPU time 133.41 seconds
Started Aug 18 06:09:45 PM PDT 24
Finished Aug 18 06:11:59 PM PDT 24
Peak memory 260540 kb
Host smart-6c3fc6c6-e001-406c-8ff5-39c5f9eb071f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649302750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_ot
p_reset.649302750
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.3084357310
Short name T932
Test name
Test status
Simulation time 75918900 ps
CPU time 13.44 seconds
Started Aug 18 06:09:48 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 283504 kb
Host smart-ccd880ff-2f7d-4dc1-b7c7-2fa913de8e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084357310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.3084357310
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.1574317658
Short name T502
Test name
Test status
Simulation time 47031500 ps
CPU time 112.1 seconds
Started Aug 18 06:09:46 PM PDT 24
Finished Aug 18 06:11:38 PM PDT 24
Peak memory 260612 kb
Host smart-b8033817-388d-49a0-9aac-64436f50d2a2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574317658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.1574317658
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.2658925375
Short name T667
Test name
Test status
Simulation time 19534500 ps
CPU time 15.73 seconds
Started Aug 18 06:09:47 PM PDT 24
Finished Aug 18 06:10:03 PM PDT 24
Peak memory 283460 kb
Host smart-3035098b-cc8c-4c5e-81d2-a355e9fceb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658925375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2658925375
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.54029570
Short name T144
Test name
Test status
Simulation time 46016100 ps
CPU time 131.11 seconds
Started Aug 18 06:09:48 PM PDT 24
Finished Aug 18 06:11:59 PM PDT 24
Peak memory 260352 kb
Host smart-87a9f251-ef5c-4735-9ba3-23b1362dc4cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54029570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp
_reset.54029570
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.1122661334
Short name T291
Test name
Test status
Simulation time 17396400 ps
CPU time 16.27 seconds
Started Aug 18 06:09:45 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 283548 kb
Host smart-7055f58b-3925-4e06-bfb9-a19542d9782b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122661334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.1122661334
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.2425089242
Short name T629
Test name
Test status
Simulation time 143314100 ps
CPU time 110.07 seconds
Started Aug 18 06:09:48 PM PDT 24
Finished Aug 18 06:11:38 PM PDT 24
Peak memory 261480 kb
Host smart-2ea3a515-3d23-41ca-a464-df578bd5d3c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425089242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.2425089242
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.141890766
Short name T499
Test name
Test status
Simulation time 93788100 ps
CPU time 15.64 seconds
Started Aug 18 06:09:46 PM PDT 24
Finished Aug 18 06:10:01 PM PDT 24
Peak memory 283468 kb
Host smart-e30ee00e-ca5f-47e7-9779-067bf89db5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141890766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.141890766
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.449438437
Short name T888
Test name
Test status
Simulation time 153842200 ps
CPU time 132.68 seconds
Started Aug 18 06:09:46 PM PDT 24
Finished Aug 18 06:11:59 PM PDT 24
Peak memory 260696 kb
Host smart-e78d6f0d-52af-4ea8-bfac-11a309915354
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449438437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_ot
p_reset.449438437
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.511372887
Short name T537
Test name
Test status
Simulation time 38973400 ps
CPU time 13.45 seconds
Started Aug 18 06:09:54 PM PDT 24
Finished Aug 18 06:10:08 PM PDT 24
Peak memory 284760 kb
Host smart-d17b75f7-f5a2-44db-94e2-209c703682d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511372887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.511372887
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.2006422236
Short name T469
Test name
Test status
Simulation time 155202100 ps
CPU time 112.8 seconds
Started Aug 18 06:09:45 PM PDT 24
Finished Aug 18 06:11:38 PM PDT 24
Peak memory 261392 kb
Host smart-e085319f-22a3-4e41-a534-2d9c1b1c4a3d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006422236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.2006422236
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.3457466319
Short name T38
Test name
Test status
Simulation time 15742300 ps
CPU time 13.71 seconds
Started Aug 18 06:09:53 PM PDT 24
Finished Aug 18 06:10:07 PM PDT 24
Peak memory 284928 kb
Host smart-99cd1c8e-7042-427d-ab53-4e86e1acfc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457466319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.3457466319
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.4022992220
Short name T169
Test name
Test status
Simulation time 691636900 ps
CPU time 112.45 seconds
Started Aug 18 06:09:53 PM PDT 24
Finished Aug 18 06:11:45 PM PDT 24
Peak memory 264708 kb
Host smart-fd8bc7ff-1aa4-4492-84e8-f662bec05522
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022992220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.4022992220
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.2739970180
Short name T709
Test name
Test status
Simulation time 118986300 ps
CPU time 13.74 seconds
Started Aug 18 06:05:33 PM PDT 24
Finished Aug 18 06:05:47 PM PDT 24
Peak memory 258880 kb
Host smart-2a51b544-780f-4b56-b743-b5fe2b1e881a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739970180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.2
739970180
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.558792805
Short name T782
Test name
Test status
Simulation time 38356100 ps
CPU time 13.25 seconds
Started Aug 18 06:05:34 PM PDT 24
Finished Aug 18 06:05:48 PM PDT 24
Peak memory 283588 kb
Host smart-cc5b72d9-22da-4f15-8885-8e83b66e83bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558792805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.558792805
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.4039099736
Short name T1038
Test name
Test status
Simulation time 56665200 ps
CPU time 22.09 seconds
Started Aug 18 06:05:31 PM PDT 24
Finished Aug 18 06:05:53 PM PDT 24
Peak memory 274116 kb
Host smart-1c3c036a-4ccf-4112-8c8b-5fd4ce0d5c0b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039099736 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.4039099736
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.2110807004
Short name T1041
Test name
Test status
Simulation time 18232005300 ps
CPU time 2609.63 seconds
Started Aug 18 06:05:17 PM PDT 24
Finished Aug 18 06:48:47 PM PDT 24
Peak memory 265772 kb
Host smart-4858c685-a0e1-4710-bd3f-77d84b8dc566
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2110807004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.2110807004
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.3776966222
Short name T741
Test name
Test status
Simulation time 548269500 ps
CPU time 720.5 seconds
Started Aug 18 06:05:14 PM PDT 24
Finished Aug 18 06:17:15 PM PDT 24
Peak memory 265472 kb
Host smart-32f2a925-aaf0-4e70-95df-544515d508f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776966222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3776966222
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.1094548367
Short name T1084
Test name
Test status
Simulation time 8008570800 ps
CPU time 34.86 seconds
Started Aug 18 06:05:12 PM PDT 24
Finished Aug 18 06:05:47 PM PDT 24
Peak memory 262988 kb
Host smart-3ba36601-7c49-4d9a-87b7-47e030465bec
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094548367 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.flash_ctrl_fetch_code.1094548367
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.1500491048
Short name T683
Test name
Test status
Simulation time 10037876300 ps
CPU time 112.39 seconds
Started Aug 18 06:05:32 PM PDT 24
Finished Aug 18 06:07:24 PM PDT 24
Peak memory 275728 kb
Host smart-f6401751-18f8-4399-9ca2-7bf78ff817b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500491048 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.1500491048
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.3291663216
Short name T352
Test name
Test status
Simulation time 85445000 ps
CPU time 13.73 seconds
Started Aug 18 06:05:33 PM PDT 24
Finished Aug 18 06:05:47 PM PDT 24
Peak memory 260616 kb
Host smart-129628df-c8ed-462e-af50-fbaa8bc247a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291663216 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.3291663216
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.1274831544
Short name T158
Test name
Test status
Simulation time 190213449200 ps
CPU time 884.39 seconds
Started Aug 18 06:05:14 PM PDT 24
Finished Aug 18 06:19:59 PM PDT 24
Peak memory 265464 kb
Host smart-bac3ade0-2ffa-4aec-a69a-2a1fb78d215b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274831544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.1274831544
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.725713427
Short name T1037
Test name
Test status
Simulation time 7457217500 ps
CPU time 52.83 seconds
Started Aug 18 06:05:12 PM PDT 24
Finished Aug 18 06:06:05 PM PDT 24
Peak memory 263552 kb
Host smart-24455b86-0740-4e2b-99b9-dccd73adb515
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725713427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw
_sec_otp.725713427
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.2584157106
Short name T1004
Test name
Test status
Simulation time 3070907400 ps
CPU time 185.57 seconds
Started Aug 18 06:05:23 PM PDT 24
Finished Aug 18 06:08:28 PM PDT 24
Peak memory 291528 kb
Host smart-f20c10ef-e2bd-4961-8de3-9d9fbea14f7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584157106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.2584157106
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.2231998791
Short name T1023
Test name
Test status
Simulation time 65626671100 ps
CPU time 286.88 seconds
Started Aug 18 06:05:25 PM PDT 24
Finished Aug 18 06:10:12 PM PDT 24
Peak memory 291508 kb
Host smart-45d02a5e-7cae-49cf-9760-f8198f6a81b4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231998791 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.2231998791
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.3297663678
Short name T937
Test name
Test status
Simulation time 2605224500 ps
CPU time 73.46 seconds
Started Aug 18 06:05:22 PM PDT 24
Finished Aug 18 06:06:36 PM PDT 24
Peak memory 260656 kb
Host smart-bb70b521-b0b8-4377-8f28-116dbb72faf1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297663678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.3297663678
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2935066179
Short name T506
Test name
Test status
Simulation time 22286788400 ps
CPU time 198.16 seconds
Started Aug 18 06:05:25 PM PDT 24
Finished Aug 18 06:08:43 PM PDT 24
Peak memory 265616 kb
Host smart-98e9d8cc-f95c-4ead-a037-c942dbfb1878
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293
5066179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.2935066179
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.1836851131
Short name T978
Test name
Test status
Simulation time 2754902300 ps
CPU time 63.6 seconds
Started Aug 18 06:05:13 PM PDT 24
Finished Aug 18 06:06:17 PM PDT 24
Peak memory 261348 kb
Host smart-9037a5de-7d86-4b8e-b309-2daf20bb57ec
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836851131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.1836851131
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.2484943245
Short name T276
Test name
Test status
Simulation time 15292100 ps
CPU time 13.44 seconds
Started Aug 18 06:05:32 PM PDT 24
Finished Aug 18 06:05:45 PM PDT 24
Peak memory 265356 kb
Host smart-5a5e9e9a-f9f0-4383-92ae-4a52f133d0e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484943245 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.2484943245
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.3183636988
Short name T916
Test name
Test status
Simulation time 4731312900 ps
CPU time 148.38 seconds
Started Aug 18 06:05:13 PM PDT 24
Finished Aug 18 06:07:41 PM PDT 24
Peak memory 265784 kb
Host smart-0216933a-4ebd-4fdb-8588-8826cfe3103e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183636988 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.3183636988
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.3084066064
Short name T754
Test name
Test status
Simulation time 143930100 ps
CPU time 110.55 seconds
Started Aug 18 06:05:12 PM PDT 24
Finished Aug 18 06:07:03 PM PDT 24
Peak memory 260512 kb
Host smart-e6704b26-1b50-4a9d-9743-c2f71cd884c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084066064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.3084066064
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.4050909762
Short name T757
Test name
Test status
Simulation time 72209200 ps
CPU time 300.54 seconds
Started Aug 18 06:05:14 PM PDT 24
Finished Aug 18 06:10:14 PM PDT 24
Peak memory 263820 kb
Host smart-447dbb90-3c7a-44b1-aa3e-cd6db5a79555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050909762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.4050909762
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.667384240
Short name T966
Test name
Test status
Simulation time 1952011100 ps
CPU time 166.58 seconds
Started Aug 18 06:05:25 PM PDT 24
Finished Aug 18 06:08:12 PM PDT 24
Peak memory 265724 kb
Host smart-e4e1f1dd-4097-48ae-8d99-afdd0de9ad9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667384240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.flash_ctrl_prog_reset.667384240
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.2512963616
Short name T139
Test name
Test status
Simulation time 1464566700 ps
CPU time 399.75 seconds
Started Aug 18 06:05:15 PM PDT 24
Finished Aug 18 06:11:54 PM PDT 24
Peak memory 283396 kb
Host smart-7081cefa-8c06-4b4a-8f0d-744c50582ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512963616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.2512963616
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.1434359642
Short name T359
Test name
Test status
Simulation time 226803700 ps
CPU time 35.29 seconds
Started Aug 18 06:05:32 PM PDT 24
Finished Aug 18 06:06:08 PM PDT 24
Peak memory 268160 kb
Host smart-7b9aba9a-a907-48fa-81af-c465d088db4f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434359642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.1434359642
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.1078525734
Short name T957
Test name
Test status
Simulation time 563418200 ps
CPU time 108.47 seconds
Started Aug 18 06:05:22 PM PDT 24
Finished Aug 18 06:07:11 PM PDT 24
Peak memory 289872 kb
Host smart-d3d57f48-af80-4044-b49a-a9022cc8f3d3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078525734 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.1078525734
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.973704314
Short name T190
Test name
Test status
Simulation time 1569751800 ps
CPU time 120.38 seconds
Started Aug 18 06:05:21 PM PDT 24
Finished Aug 18 06:07:21 PM PDT 24
Peak memory 282332 kb
Host smart-afa0a96e-53dd-4418-90b8-52f41d831fb2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
973704314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.973704314
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.205928659
Short name T34
Test name
Test status
Simulation time 967295800 ps
CPU time 138.5 seconds
Started Aug 18 06:05:22 PM PDT 24
Finished Aug 18 06:07:41 PM PDT 24
Peak memory 282384 kb
Host smart-96e65898-5e12-4b4c-928f-f90074a07a8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205928659 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.205928659
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.3138615677
Short name T832
Test name
Test status
Simulation time 3898799900 ps
CPU time 511.44 seconds
Started Aug 18 06:05:21 PM PDT 24
Finished Aug 18 06:13:53 PM PDT 24
Peak memory 319536 kb
Host smart-8ad717d6-8372-4a3e-a16c-b8b40e649d01
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138615677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.flash_ctrl_rw.3138615677
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_derr.4246958348
Short name T933
Test name
Test status
Simulation time 1389994600 ps
CPU time 242.29 seconds
Started Aug 18 06:05:24 PM PDT 24
Finished Aug 18 06:09:26 PM PDT 24
Peak memory 289124 kb
Host smart-9e440c6f-2e3f-49fe-9a8f-a911cc1e5436
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246958348 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_derr.4246958348
Directory /workspace/7.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.2065997312
Short name T796
Test name
Test status
Simulation time 46929700 ps
CPU time 31.7 seconds
Started Aug 18 06:05:22 PM PDT 24
Finished Aug 18 06:05:54 PM PDT 24
Peak memory 268484 kb
Host smart-0c661db7-0484-405c-a6ee-ec5a8ddb3bf4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065997312 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.2065997312
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.2712272237
Short name T999
Test name
Test status
Simulation time 1324308600 ps
CPU time 190.57 seconds
Started Aug 18 06:05:20 PM PDT 24
Finished Aug 18 06:08:30 PM PDT 24
Peak memory 295772 kb
Host smart-d1d543a0-af4c-41ff-8035-d37c39243273
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712272237 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.flash_ctrl_rw_serr.2712272237
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.2149232217
Short name T461
Test name
Test status
Simulation time 103128600 ps
CPU time 169.7 seconds
Started Aug 18 06:05:15 PM PDT 24
Finished Aug 18 06:08:05 PM PDT 24
Peak memory 280992 kb
Host smart-63632e74-ef0b-437c-9314-e931d7a60404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149232217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.2149232217
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.2951799506
Short name T510
Test name
Test status
Simulation time 4400084400 ps
CPU time 165.45 seconds
Started Aug 18 06:05:16 PM PDT 24
Finished Aug 18 06:08:01 PM PDT 24
Peak memory 260744 kb
Host smart-0e1ba882-e24b-42db-b3db-17fe85fca382
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951799506 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.flash_ctrl_wo.2951799506
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.937243173
Short name T332
Test name
Test status
Simulation time 27210000 ps
CPU time 13.52 seconds
Started Aug 18 06:09:52 PM PDT 24
Finished Aug 18 06:10:05 PM PDT 24
Peak memory 283408 kb
Host smart-5e3f72bd-f32c-4712-a8b8-4391da3e0b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937243173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.937243173
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.1342644629
Short name T971
Test name
Test status
Simulation time 39692600 ps
CPU time 131.8 seconds
Started Aug 18 06:09:52 PM PDT 24
Finished Aug 18 06:12:04 PM PDT 24
Peak memory 260552 kb
Host smart-ecea5aec-fb23-4957-8c0c-745395ca0696
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342644629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.1342644629
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.188823029
Short name T114
Test name
Test status
Simulation time 13912400 ps
CPU time 15.72 seconds
Started Aug 18 06:09:55 PM PDT 24
Finished Aug 18 06:10:11 PM PDT 24
Peak memory 283656 kb
Host smart-ded6975a-e4b6-4858-8237-3c5c2c4d5f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188823029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.188823029
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.1432499010
Short name T446
Test name
Test status
Simulation time 92564800 ps
CPU time 132.62 seconds
Started Aug 18 06:09:54 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 265528 kb
Host smart-fedc080a-1a64-44f1-8e2d-9fd4d93fc615
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432499010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.1432499010
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.2597930357
Short name T474
Test name
Test status
Simulation time 28176800 ps
CPU time 13.77 seconds
Started Aug 18 06:09:54 PM PDT 24
Finished Aug 18 06:10:08 PM PDT 24
Peak memory 283496 kb
Host smart-79e00a69-c509-4cef-84dc-be0a03c3cc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597930357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.2597930357
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.1143475317
Short name T492
Test name
Test status
Simulation time 153096900 ps
CPU time 111.4 seconds
Started Aug 18 06:09:52 PM PDT 24
Finished Aug 18 06:11:44 PM PDT 24
Peak memory 260704 kb
Host smart-c2e2a999-9781-4b29-a0ec-1c1fd8744738
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143475317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.1143475317
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.736262455
Short name T669
Test name
Test status
Simulation time 13272700 ps
CPU time 16.16 seconds
Started Aug 18 06:09:51 PM PDT 24
Finished Aug 18 06:10:07 PM PDT 24
Peak memory 275372 kb
Host smart-d8f8b20f-4400-4843-ab70-322263506c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736262455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.736262455
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.3486200513
Short name T551
Test name
Test status
Simulation time 76601500 ps
CPU time 132.06 seconds
Started Aug 18 06:09:52 PM PDT 24
Finished Aug 18 06:12:05 PM PDT 24
Peak memory 260488 kb
Host smart-03a1ff2f-3254-4e68-b0c2-98a6a7943755
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486200513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.3486200513
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.2916509726
Short name T886
Test name
Test status
Simulation time 41963200 ps
CPU time 13.35 seconds
Started Aug 18 06:09:52 PM PDT 24
Finished Aug 18 06:10:06 PM PDT 24
Peak memory 283396 kb
Host smart-edbc0cd6-78a8-49ee-91a9-4d136d1ac063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916509726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.2916509726
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.235954931
Short name T877
Test name
Test status
Simulation time 39720000 ps
CPU time 109.92 seconds
Started Aug 18 06:09:52 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 260388 kb
Host smart-9594088b-98bf-4e02-8db0-bb823eda36d1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235954931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_ot
p_reset.235954931
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.2251854208
Short name T931
Test name
Test status
Simulation time 22878100 ps
CPU time 15.81 seconds
Started Aug 18 06:09:52 PM PDT 24
Finished Aug 18 06:10:08 PM PDT 24
Peak memory 283544 kb
Host smart-fbc563fc-d659-40cb-aebb-427d95eab804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251854208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.2251854208
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.2740837698
Short name T69
Test name
Test status
Simulation time 71699400 ps
CPU time 111.17 seconds
Started Aug 18 06:09:54 PM PDT 24
Finished Aug 18 06:11:45 PM PDT 24
Peak memory 260528 kb
Host smart-aab7133e-50f7-4539-ac42-6a8be36398e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740837698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.2740837698
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.17655062
Short name T477
Test name
Test status
Simulation time 22441000 ps
CPU time 15.9 seconds
Started Aug 18 06:09:54 PM PDT 24
Finished Aug 18 06:10:10 PM PDT 24
Peak memory 283560 kb
Host smart-ba95b112-de06-42c8-854b-fb500b369d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17655062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.17655062
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.3572919487
Short name T270
Test name
Test status
Simulation time 41642000 ps
CPU time 110.17 seconds
Started Aug 18 06:09:50 PM PDT 24
Finished Aug 18 06:11:41 PM PDT 24
Peak memory 265248 kb
Host smart-9a7284f8-7576-4083-977f-2fbc6b328f49
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572919487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.3572919487
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.2063109100
Short name T556
Test name
Test status
Simulation time 76325500 ps
CPU time 15.99 seconds
Started Aug 18 06:09:53 PM PDT 24
Finished Aug 18 06:10:09 PM PDT 24
Peak memory 283504 kb
Host smart-76d7f3ec-d879-4d74-9795-505e5f507c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063109100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.2063109100
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.3905866653
Short name T72
Test name
Test status
Simulation time 70182200 ps
CPU time 134.9 seconds
Started Aug 18 06:09:51 PM PDT 24
Finished Aug 18 06:12:06 PM PDT 24
Peak memory 265568 kb
Host smart-9e97cb65-a875-4c5e-b55b-78058900f537
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905866653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.3905866653
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.424874206
Short name T535
Test name
Test status
Simulation time 65869200 ps
CPU time 15.74 seconds
Started Aug 18 06:09:54 PM PDT 24
Finished Aug 18 06:10:10 PM PDT 24
Peak memory 283496 kb
Host smart-3773f883-cfaf-42a0-ada0-e47601cc2e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424874206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.424874206
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.1572658168
Short name T640
Test name
Test status
Simulation time 73293000 ps
CPU time 135.11 seconds
Started Aug 18 06:09:52 PM PDT 24
Finished Aug 18 06:12:08 PM PDT 24
Peak memory 265624 kb
Host smart-3fc0979b-fc69-4ffd-a91b-6edfff974562
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572658168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.1572658168
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.2674358207
Short name T1050
Test name
Test status
Simulation time 25447700 ps
CPU time 15.88 seconds
Started Aug 18 06:09:53 PM PDT 24
Finished Aug 18 06:10:09 PM PDT 24
Peak memory 283456 kb
Host smart-457a1602-feb4-4776-91a9-ecd3493054eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674358207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.2674358207
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.2188071386
Short name T493
Test name
Test status
Simulation time 153147200 ps
CPU time 132.8 seconds
Started Aug 18 06:09:54 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 264540 kb
Host smart-f23a83aa-6a61-4869-be65-2eb3198f1d9f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188071386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.2188071386
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.2417675582
Short name T523
Test name
Test status
Simulation time 151954100 ps
CPU time 15.1 seconds
Started Aug 18 06:05:51 PM PDT 24
Finished Aug 18 06:06:06 PM PDT 24
Peak memory 259756 kb
Host smart-c5cf7077-0274-48db-b3b5-431147f1962e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417675582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.2
417675582
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.1001414053
Short name T455
Test name
Test status
Simulation time 13438600 ps
CPU time 16.68 seconds
Started Aug 18 06:05:51 PM PDT 24
Finished Aug 18 06:06:08 PM PDT 24
Peak memory 283648 kb
Host smart-f6915af6-fa76-438c-85f9-4e35612f497e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001414053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.1001414053
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.1515556664
Short name T391
Test name
Test status
Simulation time 25232600 ps
CPU time 20.7 seconds
Started Aug 18 06:05:55 PM PDT 24
Finished Aug 18 06:06:16 PM PDT 24
Peak memory 274212 kb
Host smart-365333f3-67c2-4689-b559-d8027eefe6c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515556664 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.1515556664
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.2165949296
Short name T221
Test name
Test status
Simulation time 4724886100 ps
CPU time 2192.93 seconds
Started Aug 18 06:05:40 PM PDT 24
Finished Aug 18 06:42:13 PM PDT 24
Peak memory 265636 kb
Host smart-d828051e-be3f-4daa-95fd-4dde709ae272
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2165949296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.2165949296
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.672139859
Short name T1073
Test name
Test status
Simulation time 2176219400 ps
CPU time 754.98 seconds
Started Aug 18 06:05:32 PM PDT 24
Finished Aug 18 06:18:08 PM PDT 24
Peak memory 273672 kb
Host smart-6b12316d-4da2-4bf9-b393-d087aba16afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672139859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.672139859
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3513303402
Short name T214
Test name
Test status
Simulation time 10030611600 ps
CPU time 64.86 seconds
Started Aug 18 06:05:50 PM PDT 24
Finished Aug 18 06:06:55 PM PDT 24
Peak memory 301600 kb
Host smart-4d88567b-ab4a-4715-9260-021a9aa0807c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513303402 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3513303402
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.1687776188
Short name T684
Test name
Test status
Simulation time 48995300 ps
CPU time 13.7 seconds
Started Aug 18 06:05:51 PM PDT 24
Finished Aug 18 06:06:04 PM PDT 24
Peak memory 265128 kb
Host smart-1f3a7755-f6af-4e8e-a7f5-693409fd9064
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687776188 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.1687776188
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.2303220354
Short name T673
Test name
Test status
Simulation time 240214008800 ps
CPU time 1036.37 seconds
Started Aug 18 06:05:30 PM PDT 24
Finished Aug 18 06:22:46 PM PDT 24
Peak memory 265136 kb
Host smart-64751b3e-afa6-4773-9836-36b9d40f6e30
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303220354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.2303220354
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.3246199020
Short name T753
Test name
Test status
Simulation time 1002360900 ps
CPU time 116.21 seconds
Started Aug 18 06:05:41 PM PDT 24
Finished Aug 18 06:07:37 PM PDT 24
Peak memory 294844 kb
Host smart-adc6b6ff-96e7-4946-bbe0-a79acb459425
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246199020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.3246199020
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1350172002
Short name T295
Test name
Test status
Simulation time 5701893500 ps
CPU time 137.96 seconds
Started Aug 18 06:05:40 PM PDT 24
Finished Aug 18 06:07:58 PM PDT 24
Peak memory 294364 kb
Host smart-33e2ad80-45a1-48a1-b2fc-7656d8256aff
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350172002 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.1350172002
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.2229761663
Short name T538
Test name
Test status
Simulation time 1958238500 ps
CPU time 69.9 seconds
Started Aug 18 06:05:41 PM PDT 24
Finished Aug 18 06:06:51 PM PDT 24
Peak memory 265736 kb
Host smart-3f01585a-8f48-40ea-87e2-9ce5a377c41e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229761663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.2229761663
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.3995804824
Short name T648
Test name
Test status
Simulation time 156545184000 ps
CPU time 224.54 seconds
Started Aug 18 06:05:49 PM PDT 24
Finished Aug 18 06:09:34 PM PDT 24
Peak memory 265768 kb
Host smart-51ba4b84-6680-4a53-8b37-49212f945e9d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399
5804824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.3995804824
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.4205306887
Short name T141
Test name
Test status
Simulation time 13532320800 ps
CPU time 77.73 seconds
Started Aug 18 06:05:38 PM PDT 24
Finished Aug 18 06:06:56 PM PDT 24
Peak memory 261236 kb
Host smart-58998fda-6590-4533-a481-dc30b0b7fc1c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205306887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.4205306887
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.4053026266
Short name T936
Test name
Test status
Simulation time 45581500 ps
CPU time 13.72 seconds
Started Aug 18 06:05:48 PM PDT 24
Finished Aug 18 06:06:02 PM PDT 24
Peak memory 260680 kb
Host smart-38482d24-969b-4d23-b709-c7e2407bae6f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053026266 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.4053026266
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.2481721455
Short name T125
Test name
Test status
Simulation time 63466049300 ps
CPU time 837.12 seconds
Started Aug 18 06:05:31 PM PDT 24
Finished Aug 18 06:19:29 PM PDT 24
Peak memory 275520 kb
Host smart-74c6bd01-6433-48fb-8cd3-d9b35141b517
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481721455 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.2481721455
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.3832356992
Short name T1019
Test name
Test status
Simulation time 42622500 ps
CPU time 110.82 seconds
Started Aug 18 06:05:32 PM PDT 24
Finished Aug 18 06:07:23 PM PDT 24
Peak memory 265640 kb
Host smart-adf3861f-55d0-4723-805f-7050d52ecb2e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832356992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.3832356992
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.789328264
Short name T220
Test name
Test status
Simulation time 4030019600 ps
CPU time 446.98 seconds
Started Aug 18 06:05:30 PM PDT 24
Finished Aug 18 06:12:58 PM PDT 24
Peak memory 263760 kb
Host smart-8b727b2c-3569-46b5-b1ae-ac0d667210e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789328264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.789328264
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.4076055672
Short name T103
Test name
Test status
Simulation time 25301800 ps
CPU time 14.37 seconds
Started Aug 18 06:05:47 PM PDT 24
Finished Aug 18 06:06:01 PM PDT 24
Peak memory 260000 kb
Host smart-0762d072-b9dc-44f9-8e5a-bdb332c2cc16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076055672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.flash_ctrl_prog_reset.4076055672
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.3165751575
Short name T128
Test name
Test status
Simulation time 8662725100 ps
CPU time 771.54 seconds
Started Aug 18 06:05:31 PM PDT 24
Finished Aug 18 06:18:23 PM PDT 24
Peak memory 284148 kb
Host smart-3d69da2e-6790-4d92-ad85-bca0d52ac5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165751575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3165751575
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.439658408
Short name T1031
Test name
Test status
Simulation time 109127400 ps
CPU time 36.08 seconds
Started Aug 18 06:05:49 PM PDT 24
Finished Aug 18 06:06:25 PM PDT 24
Peak memory 274116 kb
Host smart-5a0be588-d467-47c9-a9ba-271a9f31582c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439658408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_re_evict.439658408
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.4273042383
Short name T102
Test name
Test status
Simulation time 547375600 ps
CPU time 111.04 seconds
Started Aug 18 06:05:39 PM PDT 24
Finished Aug 18 06:07:31 PM PDT 24
Peak memory 290000 kb
Host smart-3d30b0f4-9939-483f-85ce-21e73f11d5df
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273042383 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_ro.4273042383
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.1933704418
Short name T768
Test name
Test status
Simulation time 1984018100 ps
CPU time 116.94 seconds
Started Aug 18 06:05:41 PM PDT 24
Finished Aug 18 06:07:38 PM PDT 24
Peak memory 282392 kb
Host smart-1139da8b-59a6-4e86-a165-8d1aa232b47b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1933704418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.1933704418
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.2040336337
Short name T547
Test name
Test status
Simulation time 4085446400 ps
CPU time 136.73 seconds
Started Aug 18 06:05:37 PM PDT 24
Finished Aug 18 06:07:54 PM PDT 24
Peak memory 295708 kb
Host smart-90a726c3-5a46-4e24-8563-32f8a5ba6bda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040336337 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.2040336337
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.4113221232
Short name T199
Test name
Test status
Simulation time 15792518300 ps
CPU time 608.16 seconds
Started Aug 18 06:05:40 PM PDT 24
Finished Aug 18 06:15:48 PM PDT 24
Peak memory 310372 kb
Host smart-9c45df2b-66ef-44df-9d1a-e3aaf8813db8
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113221232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.flash_ctrl_rw.4113221232
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.1072522510
Short name T51
Test name
Test status
Simulation time 1953146000 ps
CPU time 270.55 seconds
Started Aug 18 06:05:39 PM PDT 24
Finished Aug 18 06:10:10 PM PDT 24
Peak memory 289248 kb
Host smart-c5160a8f-fbb9-436b-a2fc-f4eab6a785f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072522510 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_derr.1072522510
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.2448344322
Short name T355
Test name
Test status
Simulation time 48261200 ps
CPU time 31.36 seconds
Started Aug 18 06:05:48 PM PDT 24
Finished Aug 18 06:06:20 PM PDT 24
Peak memory 274220 kb
Host smart-37f3bf29-09a4-4f8b-8a3e-063e400fed39
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448344322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.2448344322
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.376546195
Short name T896
Test name
Test status
Simulation time 35598700 ps
CPU time 30.55 seconds
Started Aug 18 06:05:48 PM PDT 24
Finished Aug 18 06:06:19 PM PDT 24
Peak memory 274160 kb
Host smart-0b51eb4a-d95e-4fc7-81ad-827b00e68763
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376546195 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.376546195
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.86181274
Short name T903
Test name
Test status
Simulation time 9137387400 ps
CPU time 212.75 seconds
Started Aug 18 06:05:39 PM PDT 24
Finished Aug 18 06:09:11 PM PDT 24
Peak memory 282384 kb
Host smart-76c3edee-2457-4cb7-b6bf-1a34a31f420e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86181274 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.flash_ctrl_rw_serr.86181274
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.1696586314
Short name T307
Test name
Test status
Simulation time 495590700 ps
CPU time 59.4 seconds
Started Aug 18 06:05:47 PM PDT 24
Finished Aug 18 06:06:47 PM PDT 24
Peak memory 264676 kb
Host smart-9b9fecad-84e2-4447-87f4-039d3c598719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696586314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1696586314
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.2451318900
Short name T305
Test name
Test status
Simulation time 64804700 ps
CPU time 99.68 seconds
Started Aug 18 06:05:31 PM PDT 24
Finished Aug 18 06:07:11 PM PDT 24
Peak memory 276516 kb
Host smart-f4539f60-d5ea-4c71-9e27-1ae470525eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451318900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.2451318900
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.2909246494
Short name T579
Test name
Test status
Simulation time 8802859800 ps
CPU time 176.2 seconds
Started Aug 18 06:05:38 PM PDT 24
Finished Aug 18 06:08:35 PM PDT 24
Peak memory 265920 kb
Host smart-8c15cf4c-1ccd-42b4-90ff-f18aefa9ae4d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909246494 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.flash_ctrl_wo.2909246494
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.974434557
Short name T94
Test name
Test status
Simulation time 446212900 ps
CPU time 13.62 seconds
Started Aug 18 06:06:12 PM PDT 24
Finished Aug 18 06:06:26 PM PDT 24
Peak memory 265728 kb
Host smart-7915b7d1-50b9-4b84-8b4e-71cf9515e20d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974434557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.974434557
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.2510284990
Short name T20
Test name
Test status
Simulation time 18638900 ps
CPU time 16.08 seconds
Started Aug 18 06:06:16 PM PDT 24
Finished Aug 18 06:06:32 PM PDT 24
Peak memory 284816 kb
Host smart-e60db96b-3f0b-4ef1-bebf-02c478a2ce83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510284990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.2510284990
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.655974168
Short name T406
Test name
Test status
Simulation time 58563800 ps
CPU time 20.98 seconds
Started Aug 18 06:06:16 PM PDT 24
Finished Aug 18 06:06:37 PM PDT 24
Peak memory 274000 kb
Host smart-0993bb91-bed0-4390-b92f-44b0e9246ffd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655974168 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.655974168
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.4140449445
Short name T987
Test name
Test status
Simulation time 2473963600 ps
CPU time 2281.28 seconds
Started Aug 18 06:05:58 PM PDT 24
Finished Aug 18 06:43:59 PM PDT 24
Peak memory 265380 kb
Host smart-86e81717-43bb-48cf-ba60-96bbf1a1ec62
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4140449445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.4140449445
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.1241139256
Short name T277
Test name
Test status
Simulation time 1292957000 ps
CPU time 743.15 seconds
Started Aug 18 06:05:56 PM PDT 24
Finished Aug 18 06:18:19 PM PDT 24
Peak memory 274304 kb
Host smart-594ceadc-78d0-4d04-9b02-1bf48e1b73d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241139256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.1241139256
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.3889214883
Short name T46
Test name
Test status
Simulation time 366123400 ps
CPU time 23.01 seconds
Started Aug 18 06:05:57 PM PDT 24
Finished Aug 18 06:06:20 PM PDT 24
Peak memory 263136 kb
Host smart-1889304a-1cb7-420a-b0d3-b4667149505e
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889214883 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_fetch_code.3889214883
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.3401652628
Short name T542
Test name
Test status
Simulation time 10019268900 ps
CPU time 70.46 seconds
Started Aug 18 06:06:14 PM PDT 24
Finished Aug 18 06:07:24 PM PDT 24
Peak memory 288172 kb
Host smart-738af007-9ce8-449f-a2b0-d01e6bf51706
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401652628 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.3401652628
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.3784198903
Short name T269
Test name
Test status
Simulation time 25691400 ps
CPU time 13.5 seconds
Started Aug 18 06:06:14 PM PDT 24
Finished Aug 18 06:06:27 PM PDT 24
Peak memory 258980 kb
Host smart-c292fe33-f6a6-4232-93e7-f3681b88f7af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784198903 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.3784198903
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.3017646514
Short name T111
Test name
Test status
Simulation time 80135938300 ps
CPU time 823.66 seconds
Started Aug 18 06:05:49 PM PDT 24
Finished Aug 18 06:19:33 PM PDT 24
Peak memory 265496 kb
Host smart-f8e7be69-9141-42dc-8c9e-0cb64f127548
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017646514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.3017646514
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.562254280
Short name T527
Test name
Test status
Simulation time 3924642300 ps
CPU time 96.49 seconds
Started Aug 18 06:05:48 PM PDT 24
Finished Aug 18 06:07:25 PM PDT 24
Peak memory 261484 kb
Host smart-36a78e5d-6ca9-4ad6-b99d-744b3c0dacb2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562254280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw
_sec_otp.562254280
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.2399915021
Short name T686
Test name
Test status
Simulation time 7092565800 ps
CPU time 62.94 seconds
Started Aug 18 06:06:06 PM PDT 24
Finished Aug 18 06:07:09 PM PDT 24
Peak memory 262252 kb
Host smart-ee7c21ae-7e32-4578-b42e-173250e1a33f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399915021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.2399915021
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.2813442543
Short name T1039
Test name
Test status
Simulation time 27810059900 ps
CPU time 151.61 seconds
Started Aug 18 06:06:06 PM PDT 24
Finished Aug 18 06:08:37 PM PDT 24
Peak memory 260804 kb
Host smart-242e75d9-6715-4501-a0e3-d97bc6bb3638
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281
3442543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.2813442543
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.3731242717
Short name T135
Test name
Test status
Simulation time 1066016800 ps
CPU time 92.13 seconds
Started Aug 18 06:05:57 PM PDT 24
Finished Aug 18 06:07:29 PM PDT 24
Peak memory 264088 kb
Host smart-4461cfe6-77bc-4430-bc3b-5b5711a18038
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731242717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.3731242717
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.654689359
Short name T698
Test name
Test status
Simulation time 17727100 ps
CPU time 13.5 seconds
Started Aug 18 06:06:13 PM PDT 24
Finished Aug 18 06:06:27 PM PDT 24
Peak memory 260748 kb
Host smart-736530b1-7402-4880-9654-dbab68162bdc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654689359 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.654689359
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.3015519051
Short name T778
Test name
Test status
Simulation time 41262600 ps
CPU time 131.25 seconds
Started Aug 18 06:05:58 PM PDT 24
Finished Aug 18 06:08:09 PM PDT 24
Peak memory 260716 kb
Host smart-d69b8e32-ab42-4702-9162-ee05e0dcd007
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015519051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.3015519051
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.2186649651
Short name T1017
Test name
Test status
Simulation time 241696500 ps
CPU time 153.08 seconds
Started Aug 18 06:05:48 PM PDT 24
Finished Aug 18 06:08:21 PM PDT 24
Peak memory 263640 kb
Host smart-acd1f5dd-baeb-44a4-826d-e338ba004915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2186649651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2186649651
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.4008940105
Short name T437
Test name
Test status
Simulation time 31029500 ps
CPU time 13.71 seconds
Started Aug 18 06:06:06 PM PDT 24
Finished Aug 18 06:06:20 PM PDT 24
Peak memory 259560 kb
Host smart-8514efa3-849a-4d7e-8259-b7554fb9097d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008940105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.flash_ctrl_prog_reset.4008940105
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.3808690682
Short name T426
Test name
Test status
Simulation time 28645500 ps
CPU time 52 seconds
Started Aug 18 06:05:49 PM PDT 24
Finished Aug 18 06:06:41 PM PDT 24
Peak memory 271840 kb
Host smart-ed0e5e23-f15f-46e0-8d70-f139617398d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808690682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.3808690682
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.3507756796
Short name T484
Test name
Test status
Simulation time 110483900 ps
CPU time 35 seconds
Started Aug 18 06:06:12 PM PDT 24
Finished Aug 18 06:06:47 PM PDT 24
Peak memory 276216 kb
Host smart-01a3c7bd-9571-4be1-9ad9-e02723f91749
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507756796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.3507756796
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.958859107
Short name T714
Test name
Test status
Simulation time 595581100 ps
CPU time 129.84 seconds
Started Aug 18 06:05:58 PM PDT 24
Finished Aug 18 06:08:08 PM PDT 24
Peak memory 282352 kb
Host smart-04013315-ab6f-4b69-bd01-c5692e789d9f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958859107 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.flash_ctrl_ro.958859107
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.3073827399
Short name T1081
Test name
Test status
Simulation time 1875119100 ps
CPU time 158.87 seconds
Started Aug 18 06:06:08 PM PDT 24
Finished Aug 18 06:08:47 PM PDT 24
Peak memory 282532 kb
Host smart-f9b9f020-5ae3-4e95-b25a-928bbfe74761
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3073827399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.3073827399
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.1719193772
Short name T810
Test name
Test status
Simulation time 1084950200 ps
CPU time 138.61 seconds
Started Aug 18 06:06:05 PM PDT 24
Finished Aug 18 06:08:23 PM PDT 24
Peak memory 282368 kb
Host smart-285681b5-d24b-47a1-9f31-797ce5cefda1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719193772 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.1719193772
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.925160216
Short name T915
Test name
Test status
Simulation time 16328952100 ps
CPU time 573.66 seconds
Started Aug 18 06:05:56 PM PDT 24
Finished Aug 18 06:15:30 PM PDT 24
Peak memory 310592 kb
Host smart-e528bf9a-f301-4106-aa3a-c58562c903aa
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925160216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.flash_ctrl_rw.925160216
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.3897131889
Short name T770
Test name
Test status
Simulation time 1841574000 ps
CPU time 205.77 seconds
Started Aug 18 06:06:06 PM PDT 24
Finished Aug 18 06:09:32 PM PDT 24
Peak memory 295408 kb
Host smart-294071e3-d258-4312-96f5-420cab23d5ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897131889 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.flash_ctrl_rw_serr.3897131889
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.1354352504
Short name T422
Test name
Test status
Simulation time 7777599300 ps
CPU time 85.53 seconds
Started Aug 18 06:06:13 PM PDT 24
Finished Aug 18 06:07:39 PM PDT 24
Peak memory 264256 kb
Host smart-0aad52b0-baa7-4a0b-b35d-bcc927466686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354352504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.1354352504
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.3130972705
Short name T534
Test name
Test status
Simulation time 112040800 ps
CPU time 146.99 seconds
Started Aug 18 06:05:50 PM PDT 24
Finished Aug 18 06:08:17 PM PDT 24
Peak memory 277604 kb
Host smart-75e75feb-1638-404a-a940-9adf74eed04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130972705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.3130972705
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.806408276
Short name T518
Test name
Test status
Simulation time 9338147000 ps
CPU time 201.17 seconds
Started Aug 18 06:05:59 PM PDT 24
Finished Aug 18 06:09:20 PM PDT 24
Peak memory 260572 kb
Host smart-29da4fef-3e4a-4257-a540-9d9d6ecef98d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806408276 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.flash_ctrl_wo.806408276
Directory /workspace/9.flash_ctrl_wo/latest
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