Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	438194	1		T1	1		T2	656		T3	1
all_values[1]	438194	1		T1	1		T2	656		T3	1
all_values[2]	438194	1		T1	1		T2	656		T3	1
all_values[3]	438194	1		T1	1		T2	656		T3	1
all_values[4]	438194	1		T1	1		T2	656		T3	1
all_values[5]	438194	1		T1	1		T2	656		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	882660	1		T1	6		T2	1316		T3	6
auto[1]	1746504	1		T2	2620		T6	25368		T34	13088

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1290348	1		T1	4		T2	1927		T3	4
auto[1]	1338816	1		T1	2		T2	2009		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	438066	1		T1	1		T2	656		T3	1
all_values[0]	auto[1]	auto[1]	128	1		T318	1		T319	7		T320	2
all_values[1]	auto[0]	auto[1]	438034	1		T1	1		T2	656		T3	1
all_values[1]	auto[1]	auto[1]	160	1		T257	5		T318	4		T319	7
all_values[2]	auto[0]	auto[0]	1606	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	79	1		T257	1		T258	1		T318	1
all_values[2]	auto[1]	auto[0]	436462	1		T2	655		T6	6342		T34	3272
all_values[2]	auto[1]	auto[1]	47	1		T257	1		T258	1		T320	3
all_values[3]	auto[0]	auto[0]	1562	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	59	1		T60	2		T257	1		T258	2
all_values[3]	auto[1]	auto[0]	78143	1		T2	36		T6	22		T34	1636
all_values[3]	auto[1]	auto[1]	358430	1		T2	619		T6	6320		T34	1636
all_values[4]	auto[0]	auto[0]	1090	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	528	1		T4	1		T18	1		T7	1
all_values[4]	auto[1]	auto[0]	333449	1		T2	577		T6	5810		T34	1636
all_values[4]	auto[1]	auto[1]	103127	1		T2	78		T6	532		T34	1636
all_values[5]	auto[0]	auto[0]	1542	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	94	1		T44	1		T46	1		T47	1
all_values[5]	auto[1]	auto[0]	436494	1		T2	655		T6	6342		T34	3272
all_values[5]	auto[1]	auto[1]	64	1		T257	3		T319	1		T320	4