Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	239408	1		T1	5		T2	49		T3	722
auto[FlashEraseBank]	265004	1		T1	10		T2	29		T3	909

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	249720	1		T1	10		T2	78		T16	8
auto[FlashOpProgram]	235816	1		T1	5		T3	1631		T16	1
auto[FlashOpErase]	14876	1		T31	18		T39	4		T40	15
auto[FlashOpInvalid]	4000	1		T93	200		T95	200		T292	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	249720	1		T1	10		T2	78		T16	8
op[FlashOpProgram]	235816	1		T1	5		T3	1631		T16	1
op[FlashOpErase]	14876	1		T31	18		T39	4		T40	15
read_erase_read	542	1		T31	15		T40	1		T41	5
read_prog_read	857	1		T1	1		T16	1		T7	8

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	368058	1		T1	9		T3	1404		T16	1
auto[FlashPartInfo]	132394	1		T1	6		T3	225		T16	7
auto[FlashPartInfo1]	1014	1		T2	36		T7	1		T69	1
auto[FlashPartInfo2]	2946	1		T2	42		T3	2		T16	1

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	183165	1		T1	5		T16	1		T7	992
auto[FlashPartData]	auto[FlashOpProgram]	177413	1		T1	4		T3	1404		T18	1
auto[FlashPartData]	auto[FlashOpErase]	3570	1		T31	10		T93	96		T95	99
auto[FlashPartData]	auto[FlashOpInvalid]	3910	1		T93	192		T95	198		T292	196
auto[FlashPartInfo]	auto[FlashOpRead]	63783	1		T1	5		T16	6		T6	532
auto[FlashPartInfo]	auto[FlashOpProgram]	57276	1		T1	1		T3	225		T16	1
auto[FlashPartInfo]	auto[FlashOpErase]	11269	1		T31	8		T39	4		T40	15
auto[FlashPartInfo]	auto[FlashOpInvalid]	66	1		T93	6		T95	2		T292	4
auto[FlashPartInfo1]	auto[FlashOpRead]	844	1		T2	36		T7	1		T69	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T84	32		T138	1		T157	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T179	1		T138	1		T386	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T138	2		T386	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1928	1		T2	42		T16	1		T7	8
auto[FlashPartInfo2]	auto[FlashOpProgram]	964	1		T3	2		T7	4		T33	11
auto[FlashPartInfo2]	auto[FlashOpErase]	34	1		T93	1		T30	1		T387	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	20	1		T93	2		T387	2		T388	4