Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29256	1		T40	4		T93	400		T95	400
auto[1]	45	1		T206	1		T219	5		T389	1
auto[2]	57	1		T1	2		T31	4		T151	1
auto[3]	244	1		T1	1		T31	6		T204	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7403	1		T31	2		T40	1		T93	100
evic_idx[1]	7403	1		T1	1		T31	4		T40	1
evic_idx[2]	7397	1		T1	1		T31	2		T40	1
evic_idx[3]	7399	1		T1	1		T31	2		T40	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28714	1		T31	10		T40	4		T93	400
evic_op[2]	320	1		T1	3		T151	1		T45	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7110	1		T40	1		T93	100		T95	100
evic_idx[0]	evic_op[1]	auto[1]	7	1		T219	1		T390	2		T391	1
evic_idx[0]	evic_op[1]	auto[2]	8	1		T392	2		T281	1		T393	3
evic_idx[0]	evic_op[1]	auto[3]	58	1		T31	2		T267	1		T219	4
evic_idx[0]	evic_op[2]	auto[0]	66	1		T222	10		T30	1		T374	1
evic_idx[0]	evic_op[2]	auto[1]	4	1		T394	1		T395	2		T396	1
evic_idx[0]	evic_op[2]	auto[2]	2	1		T151	1		T397	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	6	1		T398	1		T220	1		T399	1
evic_idx[1]	evic_op[1]	auto[0]	7109	1		T40	1		T93	100		T95	100
evic_idx[1]	evic_op[1]	auto[1]	9	1		T219	2		T390	2		T391	3
evic_idx[1]	evic_op[1]	auto[2]	7	1		T31	2		T392	1		T281	1
evic_idx[1]	evic_op[1]	auto[3]	54	1		T31	2		T219	1		T400	1
evic_idx[1]	evic_op[2]	auto[0]	66	1		T222	10		T30	1		T374	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T389	1		T401	1		T395	2
evic_idx[1]	evic_op[2]	auto[2]	1	1		T1	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	11	1		T202	1		T402	1		T403	1
evic_idx[2]	evic_op[1]	auto[0]	7109	1		T40	1		T93	100		T95	100
evic_idx[2]	evic_op[1]	auto[1]	6	1		T219	1		T390	2		T391	2
evic_idx[2]	evic_op[1]	auto[2]	9	1		T31	1		T392	3		T281	1
evic_idx[2]	evic_op[1]	auto[3]	49	1		T31	1		T267	2		T219	1
evic_idx[2]	evic_op[2]	auto[0]	68	1		T222	10		T30	1		T307	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T401	1		T395	1		T404	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T1	1		T352	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	8	1		T204	1		T205	1		T144	1
evic_idx[3]	evic_op[1]	auto[0]	7112	1		T40	1		T93	100		T95	100
evic_idx[3]	evic_op[1]	auto[1]	6	1		T219	1		T390	2		T391	2
evic_idx[3]	evic_op[1]	auto[2]	9	1		T31	1		T392	4		T281	1
evic_idx[3]	evic_op[1]	auto[3]	52	1		T31	1		T267	2		T219	2
evic_idx[3]	evic_op[2]	auto[0]	64	1		T222	10		T30	1		T352	1
evic_idx[3]	evic_op[2]	auto[1]	5	1		T206	1		T401	1		T404	1
evic_idx[3]	evic_op[2]	auto[2]	3	1		T45	1		T405	1		T406	1
evic_idx[3]	evic_op[2]	auto[3]	6	1		T1	1		T407	1		T408	1