Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
5226 | 
1 | 
 | 
T54 | 
122 | 
 | 
T55 | 
120 | 
 | 
T56 | 
160 | 
| instr_types[0] | 
6452 | 
1 | 
 | 
T54 | 
247 | 
 | 
T55 | 
264 | 
 | 
T56 | 
199 | 
| instr_types[1] | 
4089511 | 
1 | 
 | 
T1 | 
16 | 
 | 
T2 | 
16347 | 
 | 
T16 | 
4 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4098874 | 
1 | 
 | 
T1 | 
16 | 
 | 
T2 | 
16347 | 
 | 
T16 | 
4 | 
| auto[1] | 
2315 | 
1 | 
 | 
T54 | 
305 | 
 | 
T55 | 
246 | 
 | 
T56 | 
183 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
4738 | 
1 | 
 | 
T54 | 
22 | 
 | 
T55 | 
88 | 
 | 
T56 | 
120 | 
| auto[0] | 
instr_types[0] | 
5586 | 
1 | 
 | 
T54 | 
115 | 
 | 
T55 | 
184 | 
 | 
T56 | 
151 | 
| auto[0] | 
instr_types[1] | 
4088550 | 
1 | 
 | 
T1 | 
16 | 
 | 
T2 | 
16347 | 
 | 
T16 | 
4 | 
| auto[1] | 
others | 
488 | 
1 | 
 | 
T54 | 
100 | 
 | 
T55 | 
32 | 
 | 
T56 | 
40 | 
| auto[1] | 
instr_types[0] | 
866 | 
1 | 
 | 
T54 | 
132 | 
 | 
T55 | 
80 | 
 | 
T56 | 
48 | 
| auto[1] | 
instr_types[1] | 
961 | 
1 | 
 | 
T54 | 
73 | 
 | 
T55 | 
134 | 
 | 
T56 | 
95 |