Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	79243	1		T6	2145		T85	8186		T324	2319
rd_lvl[2]	66503	1		T2	541		T6	1216		T22	1137
rd_lvl[3]	16910	1		T2	37		T6	579		T22	537
rd_lvl[4]	35096	1		T2	2		T6	468		T22	84
rd_lvl[5]	16483	1		T6	214		T22	486		T62	323
rd_lvl[6]	14262	1		T2	1		T6	39		T22	334
rd_lvl[7]	6661	1		T6	160		T62	14		T324	632
rd_lvl[8]	9521	1		T6	144		T22	2		T62	26
rd_lvl[9]	6637	1		T2	1		T6	232		T23	442
rd_lvl[10]	7559	1		T6	54		T22	1		T23	1172
rd_lvl[11]	6092	1		T6	103		T22	1		T231	425
rd_lvl[12]	8283	1		T6	1		T22	219		T231	1259
rd_lvl[13]	4606	1		T22	219		T271	1204		T43	413
rd_lvl[14]	7434	1		T6	104		T43	634		T325	59
rd_lvl[15]	1044	1		T34	448		T325	17		T326	150