Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	438194	1		T1	1		T2	656		T3	1
all_pins[1]	438194	1		T1	1		T2	656		T3	1
all_pins[2]	438194	1		T1	1		T2	656		T3	1
all_pins[3]	438194	1		T1	1		T2	656		T3	1
all_pins[4]	438194	1		T1	1		T2	656		T3	1
all_pins[5]	438194	1		T1	1		T2	656		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2226887	1		T1	6		T2	3276		T3	6
values[0x1]	402277	1		T2	660		T6	6036		T34	5648
transitions[0x0=>0x1]	366371	1		T2	618		T6	5481		T34	3272
transitions[0x1=>0x0]	366361	1		T2	618		T6	5481		T34	3272

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	438066	1		T1	1		T2	656		T3	1
all_pins[0]	values[0x1]	128	1		T318	1		T319	7		T320	2
all_pins[0]	transitions[0x0=>0x1]	51	1		T320	2		T321	2		T322	2
all_pins[0]	transitions[0x1=>0x0]	83	1		T257	5		T318	3		T320	5
all_pins[1]	values[0x0]	438034	1		T1	1		T2	656		T3	1
all_pins[1]	values[0x1]	160	1		T257	5		T318	4		T319	7
all_pins[1]	transitions[0x0=>0x1]	140	1		T257	5		T318	4		T319	7
all_pins[1]	transitions[0x1=>0x0]	1217	1		T34	1188		T325	2		T257	1
all_pins[2]	values[0x0]	436957	1		T1	1		T2	656		T3	1
all_pins[2]	values[0x1]	1237	1		T34	1188		T325	2		T257	1
all_pins[2]	transitions[0x0=>0x1]	35	1		T258	1		T320	1		T321	1
all_pins[2]	transitions[0x1=>0x0]	286547	1		T2	582		T6	5459		T34	448
all_pins[3]	values[0x0]	150445	1		T1	1		T2	74		T3	1
all_pins[3]	values[0x1]	287749	1		T2	582		T6	5459		T34	1636
all_pins[3]	transitions[0x0=>0x1]	253193	1		T2	540		T6	4904		T34	448
all_pins[3]	transitions[0x1=>0x0]	78383	1		T2	36		T6	22		T34	1636
all_pins[4]	values[0x0]	325255	1		T1	1		T2	578		T3	1
all_pins[4]	values[0x1]	112939	1		T2	78		T6	577		T34	2824
all_pins[4]	transitions[0x0=>0x1]	112923	1		T2	78		T6	577		T34	2824
all_pins[4]	transitions[0x1=>0x0]	48	1		T257	3		T319	1		T320	3
all_pins[5]	values[0x0]	438130	1		T1	1		T2	656		T3	1
all_pins[5]	values[0x1]	64	1		T257	3		T319	1		T320	4
all_pins[5]	transitions[0x0=>0x1]	29	1		T257	3		T320	2		T322	1
all_pins[5]	transitions[0x1=>0x0]	83	1		T318	1		T319	5		T320	1