Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	369803	1		T1	2		T2	2		T3	2
all_values[1]	369803	1		T1	2		T2	2		T3	2
all_values[2]	369803	1		T1	2		T2	2		T3	2
all_values[3]	369803	1		T1	2		T2	2		T3	2
all_values[4]	369803	1		T1	2		T2	2		T3	2
all_values[5]	369803	1		T1	2		T2	2		T3	2

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	746061	1		T1	12		T2	12		T3	12
auto[1]	1472757	1		T22	5952		T29	13544		T28	5920

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1084240	1		T1	7		T2	7		T3	7
auto[1]	1134578	1		T1	5		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	369633	1		T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	170	1		T256	4		T257	2		T258	1
all_values[1]	auto[0]	auto[1]	369631	1		T1	2		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	172	1		T256	7		T257	5		T258	3
all_values[2]	auto[0]	auto[0]	1643	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	55	1		T256	1		T257	1		T258	2
all_values[2]	auto[1]	auto[0]	368053	1		T22	1488		T29	3386		T28	1480
all_values[2]	auto[1]	auto[1]	52	1		T257	1		T333	1		T331	2
all_values[3]	auto[0]	auto[0]	1648	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	68	1		T256	1		T258	2		T333	1
all_values[3]	auto[1]	auto[0]	74068	1		T22	1488		T28	1480		T34	1761
all_values[3]	auto[1]	auto[1]	294019	1		T29	3386		T41	6376		T42	5866
all_values[4]	auto[0]	auto[0]	1152	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	542	1		T1	1		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	268034	1		T22	1		T29	1693		T28	1
all_values[4]	auto[1]	auto[1]	100075	1		T22	1487		T29	1693		T28	1479
all_values[5]	auto[0]	auto[0]	1591	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	98	1		T17	1		T43	1		T71	1
all_values[5]	auto[1]	auto[0]	368051	1		T22	1488		T29	3386		T28	1480
all_values[5]	auto[1]	auto[1]	63	1		T257	3		T333	2		T331	5