Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	235985	1		T2	34		T7	4		T20	20
auto[FlashEraseBank]	263656	1		T1	13		T2	6		T3	20

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	247477	1		T2	40		T3	20		T7	2
auto[FlashOpProgram]	232162	1		T1	13		T7	1		T14	283
auto[FlashOpErase]	16002	1		T7	1		T15	100		T23	41
auto[FlashOpInvalid]	4000	1		T15	200		T125	200		T223	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	247477	1		T2	40		T3	20		T7	2
op[FlashOpProgram]	232162	1		T1	13		T7	1		T14	283
op[FlashOpErase]	16002	1		T7	1		T15	100		T23	41
read_erase_read	554	1		T64	2		T27	13		T35	2
read_prog_read	831	1		T14	3		T16	4		T17	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	354933	1		T1	13		T2	40		T3	20
auto[FlashPartInfo]	141030	1		T14	116		T22	259		T15	12
auto[FlashPartInfo1]	853	1		T14	1		T17	1		T43	3
auto[FlashPartInfo2]	2825	1		T22	2		T17	3		T43	2

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	174549	1		T2	40		T3	20		T7	2
auto[FlashPartData]	auto[FlashOpProgram]	172876	1		T1	13		T7	1		T14	251
auto[FlashPartData]	auto[FlashOpErase]	3588	1		T7	1		T15	98		T23	41
auto[FlashPartData]	auto[FlashOpInvalid]	3920	1		T15	196		T125	198		T223	200
auto[FlashPartInfo]	auto[FlashOpRead]	70456	1		T14	84		T15	4		T17	90
auto[FlashPartInfo]	auto[FlashOpProgram]	58126	1		T14	32		T22	259		T15	2
auto[FlashPartInfo]	auto[FlashOpErase]	12382	1		T15	2		T27	7		T57	219
auto[FlashPartInfo]	auto[FlashOpInvalid]	66	1		T15	4		T125	2		T155	6
auto[FlashPartInfo1]	auto[FlashOpRead]	676	1		T14	1		T17	1		T43	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T162	1		T133	32		T163	1
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T162	1		T163	1		T137	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T162	2		T163	2		T137	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1796	1		T17	2		T43	2		T65	7
auto[FlashPartInfo2]	auto[FlashOpProgram]	994	1		T22	2		T17	1		T9	1
auto[FlashPartInfo2]	auto[FlashOpErase]	27	1		T36	1		T50	2		T168	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T162	2		T163	4		T417	2