Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31830	1		T7	4		T15	400		T16	20
auto[1]	66	1		T27	22		T89	3		T418	3
auto[2]	67	1		T30	1		T153	4		T178	4
auto[3]	229	1		T27	8		T33	30		T214	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8061	1		T7	1		T15	100		T16	5
evic_idx[1]	8046	1		T7	1		T15	100		T16	5
evic_idx[2]	8046	1		T7	1		T15	100		T16	5
evic_idx[3]	8039	1		T7	1		T15	100		T16	5

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31300	1		T7	4		T15	400		T64	16
evic_op[2]	296	1		T16	20		T64	16		T84	12

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7747	1		T7	1		T15	100		T64	4
evic_idx[0]	evic_op[1]	auto[1]	15	1		T27	8		T220	3		T419	2
evic_idx[0]	evic_op[1]	auto[2]	16	1		T220	5		T323	5		T420	3
evic_idx[0]	evic_op[1]	auto[3]	62	1		T27	3		T33	8		T204	4
evic_idx[0]	evic_op[2]	auto[0]	60	1		T16	5		T64	4		T84	3
evic_idx[0]	evic_op[2]	auto[1]	1	1		T418	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	2	1		T46	1		T421	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	8	1		T31	1		T45	1		T422	1
evic_idx[1]	evic_op[1]	auto[0]	7748	1		T7	1		T15	100		T64	4
evic_idx[1]	evic_op[1]	auto[1]	12	1		T27	5		T220	3		T419	1
evic_idx[1]	evic_op[1]	auto[2]	11	1		T220	3		T323	3		T420	3
evic_idx[1]	evic_op[1]	auto[3]	47	1		T27	2		T33	6		T204	1
evic_idx[1]	evic_op[2]	auto[0]	67	1		T16	5		T64	4		T84	3
evic_idx[1]	evic_op[2]	auto[1]	4	1		T89	1		T418	1		T423	1
evic_idx[1]	evic_op[2]	auto[2]	4	1		T424	1		T46	1		T425	1
evic_idx[1]	evic_op[2]	auto[3]	4	1		T46	1		T426	1		T427	1
evic_idx[2]	evic_op[1]	auto[0]	7751	1		T7	1		T15	100		T64	4
evic_idx[2]	evic_op[1]	auto[1]	16	1		T27	4		T220	3		T419	3
evic_idx[2]	evic_op[1]	auto[2]	8	1		T220	2		T323	3		T420	2
evic_idx[2]	evic_op[1]	auto[3]	48	1		T27	2		T33	9		T204	2
evic_idx[2]	evic_op[2]	auto[0]	62	1		T16	5		T64	4		T84	3
evic_idx[2]	evic_op[2]	auto[1]	2	1		T89	1		T418	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	4	1		T30	1		T46	1		T421	1
evic_idx[2]	evic_op[2]	auto[3]	6	1		T214	1		T32	1		T428	1
evic_idx[3]	evic_op[1]	auto[0]	7751	1		T7	1		T15	100		T64	4
evic_idx[3]	evic_op[1]	auto[1]	13	1		T27	5		T220	3		T419	1
evic_idx[3]	evic_op[1]	auto[2]	9	1		T220	2		T323	4		T420	1
evic_idx[3]	evic_op[1]	auto[3]	46	1		T27	1		T33	7		T204	2
evic_idx[3]	evic_op[2]	auto[0]	60	1		T16	5		T64	4		T84	3
evic_idx[3]	evic_op[2]	auto[1]	3	1		T89	1		T429	1		T430	1
evic_idx[3]	evic_op[2]	auto[2]	1	1		T427	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	8	1		T431	1		T432	1		T433	1