Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg
Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
18 |
3 |
15 |
83.33 |
Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
prog_lvl_cp |
3 |
3 |
0 |
0.00 |
100 |
1 |
1 |
0 |
|
rd_lvl_cp |
15 |
0 |
15 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable prog_lvl_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
3 |
0 |
0.00 |
User Defined Bins for prog_lvl_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER |
prog_lvl[1] |
0 |
1 |
1 |
prog_lvl[2] |
0 |
1 |
1 |
prog_lvl[3] |
0 |
1 |
1 |
Summary for Variable rd_lvl_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
15 |
0 |
15 |
100.00 |
User Defined Bins for rd_lvl_cp
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
rd_lvl[1] |
53403 |
1 |
|
T42 |
2066 |
|
T337 |
1375 |
|
T338 |
942 |
rd_lvl[2] |
57124 |
1 |
|
T42 |
893 |
|
T232 |
1128 |
|
T339 |
2391 |
rd_lvl[3] |
9633 |
1 |
|
T42 |
336 |
|
T232 |
489 |
|
T339 |
1736 |
rd_lvl[4] |
34103 |
1 |
|
T41 |
5148 |
|
T42 |
415 |
|
T232 |
138 |
rd_lvl[5] |
15096 |
1 |
|
T41 |
1228 |
|
T42 |
173 |
|
T232 |
482 |
rd_lvl[6] |
11798 |
1 |
|
T42 |
16 |
|
T232 |
454 |
|
T340 |
332 |
rd_lvl[7] |
5576 |
1 |
|
T42 |
137 |
|
T232 |
70 |
|
T341 |
1964 |
rd_lvl[8] |
11519 |
1 |
|
T29 |
2909 |
|
T42 |
136 |
|
T232 |
71 |
rd_lvl[9] |
7272 |
1 |
|
T29 |
477 |
|
T42 |
214 |
|
T232 |
68 |
rd_lvl[10] |
10430 |
1 |
|
T42 |
56 |
|
T342 |
1263 |
|
T337 |
97 |
rd_lvl[11] |
6928 |
1 |
|
T42 |
184 |
|
T340 |
37 |
|
T342 |
288 |
rd_lvl[12] |
4212 |
1 |
|
T232 |
88 |
|
T343 |
9 |
|
T344 |
56 |
rd_lvl[13] |
2495 |
1 |
|
T232 |
86 |
|
T345 |
35 |
|
T343 |
9 |
rd_lvl[14] |
6764 |
1 |
|
T42 |
184 |
|
T298 |
1322 |
|
T346 |
1537 |
rd_lvl[15] |
3684 |
1 |
|
T298 |
266 |
|
T38 |
567 |
|
T39 |
68 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |