Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::std_fault_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::std_fault_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::std_fault_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::std_fault_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_arb_fsm_err	1	0	1	100.00	100	1	1	0
cp_ctrl_cnt_err	1	0	1	100.00	100	1	1	0
cp_fifo_err	1	0	1	100.00	100	1	1	0
cp_lcmgr_err	1	0	1	100.00	100	1	1	0
cp_lcmgr_intg_err	1	0	1	100.00	100	1	1	0
cp_phy_fsm_err	1	0	1	100.00	100	1	1	0
cp_prog_intg_err	1	0	1	100.00	100	1	1	0
cp_storage_err	1	1	0	0.00	100	1	1	0

Summary for Variable cp_arb_fsm_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_arb_fsm_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seen	50	1		T18	10		T19	10		T53	10

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Summary for Variable cp_ctrl_cnt_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_ctrl_cnt_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seen	100	1		T18	20		T19	20		T53	20

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Summary for Variable cp_fifo_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_fifo_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seen	500	1		T18	100		T19	100		T53	100

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Summary for Variable cp_lcmgr_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_lcmgr_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seen	353	1		T81	1		T83	1		T189	1

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Summary for Variable cp_lcmgr_intg_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_lcmgr_intg_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seen	20	1		T126	1		T185	1		T186	1

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Summary for Variable cp_phy_fsm_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_phy_fsm_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seen	200	1		T18	40		T19	40		T53	40

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Summary for Variable cp_prog_intg_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_prog_intg_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seen	15	1		T9	5		T11	5		T102	5

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Summary for Variable cp_storage_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for cp_storage_err

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
seen	0	1	1