Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	369803	1		T1	2		T2	2		T3	2
all_pins[1]	369803	1		T1	2		T2	2		T3	2
all_pins[2]	369803	1		T1	2		T2	2		T3	2
all_pins[3]	369803	1		T1	2		T2	2		T3	2
all_pins[4]	369803	1		T1	2		T2	2		T3	2
all_pins[5]	369803	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1856537	1		T1	12		T2	12		T3	12
values[0x1]	362281	1		T22	1487		T29	5079		T28	1479
transitions[0x0=>0x1]	320457	1		T22	1487		T29	3386		T28	1479
transitions[0x1=>0x0]	320442	1		T22	1487		T29	3386		T28	1479

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	369633	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	170	1		T256	4		T257	2		T258	1
all_pins[0]	transitions[0x0=>0x1]	74	1		T256	1		T258	1		T333	2
all_pins[0]	transitions[0x1=>0x0]	76	1		T256	4		T257	3		T258	3
all_pins[1]	values[0x0]	369631	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	172	1		T256	7		T257	5		T258	3
all_pins[1]	transitions[0x0=>0x1]	148	1		T256	7		T257	4		T258	3
all_pins[1]	transitions[0x1=>0x0]	5503	1		T38	1143		T39	23		T40	675
all_pins[2]	values[0x0]	364276	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	5527	1		T38	1143		T39	23		T40	675
all_pins[2]	transitions[0x0=>0x1]	40	1		T331	2		T349	1		T350	2
all_pins[2]	transitions[0x1=>0x0]	240427	1		T29	3386		T41	6376		T42	4810
all_pins[3]	values[0x0]	123889	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	245914	1		T29	3386		T41	6376		T42	4810
all_pins[3]	transitions[0x0=>0x1]	209750	1		T29	1693		T41	4782		T42	4269
all_pins[3]	transitions[0x1=>0x0]	74271	1		T22	1487		T28	1479		T34	1760
all_pins[4]	values[0x0]	259368	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	110435	1		T22	1487		T29	1693		T28	1479
all_pins[4]	transitions[0x0=>0x1]	110418	1		T22	1487		T29	1693		T28	1479
all_pins[4]	transitions[0x1=>0x0]	46	1		T257	3		T333	2		T331	3
all_pins[5]	values[0x0]	369740	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	63	1		T257	3		T333	2		T331	5
all_pins[5]	transitions[0x0=>0x1]	27	1		T257	1		T331	2		T332	1
all_pins[5]	transitions[0x1=>0x0]	119	1		T256	4		T257	1		T258	1