Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T256	7		T257	4		T258	7
all_values[1]	281	1		T256	7		T257	4		T258	7
all_values[2]	281	1		T256	7		T257	4		T258	7
all_values[3]	281	1		T256	7		T257	4		T258	7
all_values[4]	281	1		T256	7		T257	4		T258	7
all_values[5]	281	1		T256	7		T257	4		T258	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	936	1		T256	22		T257	10		T258	30
auto[1]	750	1		T256	20		T257	14		T258	12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	545	1		T256	17		T257	8		T258	13
auto[1]	1141	1		T256	25		T257	16		T258	29

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	995	1		T256	26		T257	13		T258	28
auto[1]	691	1		T256	16		T257	11		T258	14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	86	1		T256	1		T257	1		T258	4
all_values[0]	auto[0]	auto[1]	auto[1]	82	1		T256	3		T331	4		T332	1
all_values[0]	auto[1]	auto[0]	auto[1]	59	1		T256	2		T257	1		T258	2
all_values[0]	auto[1]	auto[1]	auto[1]	54	1		T256	1		T257	2		T258	1
all_values[1]	auto[0]	auto[0]	auto[1]	87	1		T256	1		T258	2		T331	4
all_values[1]	auto[0]	auto[1]	auto[1]	78	1		T256	1		T257	3		T258	4
all_values[1]	auto[1]	auto[0]	auto[1]	63	1		T256	1		T258	1		T333	2
all_values[1]	auto[1]	auto[1]	auto[1]	53	1		T256	4		T257	1		T331	1
all_values[2]	auto[0]	auto[0]	auto[0]	96	1		T256	5		T257	1		T258	4
all_values[2]	auto[0]	auto[1]	auto[0]	78	1		T256	1		T257	1		T258	1
all_values[2]	auto[1]	auto[0]	auto[1]	65	1		T256	1		T257	1		T258	1
all_values[2]	auto[1]	auto[1]	auto[1]	42	1		T257	1		T258	1		T331	2
all_values[3]	auto[0]	auto[0]	auto[0]	96	1		T256	1		T257	1		T258	4
all_values[3]	auto[0]	auto[1]	auto[0]	64	1		T256	3		T257	1		T333	1
all_values[3]	auto[1]	auto[0]	auto[1]	82	1		T256	1		T257	1		T258	3
all_values[3]	auto[1]	auto[1]	auto[1]	39	1		T256	2		T257	1		T333	1
all_values[4]	auto[0]	auto[0]	auto[0]	62	1		T256	3		T257	4		T258	1
all_values[4]	auto[0]	auto[0]	auto[1]	26	1		T258	3		T332	1		T334	1
all_values[4]	auto[0]	auto[1]	auto[0]	43	1		T256	1		T333	1		T331	1
all_values[4]	auto[0]	auto[1]	auto[1]	35	1		T256	2		T258	1		T333	1
all_values[4]	auto[1]	auto[0]	auto[1]	64	1		T258	1		T333	1		T331	1
all_values[4]	auto[1]	auto[1]	auto[1]	51	1		T256	1		T258	1		T333	1
all_values[5]	auto[0]	auto[0]	auto[0]	53	1		T256	3		T331	1		T332	1
all_values[5]	auto[0]	auto[0]	auto[1]	28	1		T256	1		T258	1		T333	1
all_values[5]	auto[0]	auto[1]	auto[0]	53	1		T258	3		T332	1		T335	2
all_values[5]	auto[0]	auto[1]	auto[1]	28	1		T257	1		T331	4		T336	2
all_values[5]	auto[1]	auto[0]	auto[1]	69	1		T256	2		T258	3		T333	2
all_values[5]	auto[1]	auto[1]	auto[1]	50	1		T256	1		T257	3		T333	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal