Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T269	7		T270	4		T277	4
all_values[1]	272	1		T269	7		T270	4		T277	4
all_values[2]	272	1		T269	7		T270	4		T277	4
all_values[3]	272	1		T269	7		T270	4		T277	4
all_values[4]	272	1		T269	7		T270	4		T277	4
all_values[5]	272	1		T269	7		T270	4		T277	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	867	1		T269	27		T270	12		T277	16
auto[1]	765	1		T269	15		T270	12		T277	8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	494	1		T269	9		T270	9		T277	7
auto[1]	1138	1		T269	33		T270	15		T277	17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	924	1		T269	22		T270	14		T277	13
auto[1]	708	1		T269	20		T270	10		T277	11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	76	1		T269	1		T270	1		T337	3
all_values[0]	auto[0]	auto[1]	auto[1]	80	1		T269	3		T270	1		T277	2
all_values[0]	auto[1]	auto[0]	auto[1]	62	1		T269	2		T277	2		T337	4
all_values[0]	auto[1]	auto[1]	auto[1]	54	1		T269	1		T270	2		T338	2
all_values[1]	auto[0]	auto[0]	auto[1]	87	1		T269	3		T270	2		T277	2
all_values[1]	auto[0]	auto[1]	auto[1]	73	1		T269	2		T270	1		T337	2
all_values[1]	auto[1]	auto[0]	auto[1]	54	1		T269	2		T270	1		T277	2
all_values[1]	auto[1]	auto[1]	auto[1]	58	1		T337	3		T338	2		T339	1
all_values[2]	auto[0]	auto[0]	auto[0]	82	1		T277	2		T337	1		T339	1
all_values[2]	auto[0]	auto[1]	auto[0]	70	1		T269	1		T270	1		T277	2
all_values[2]	auto[1]	auto[0]	auto[1]	68	1		T269	5		T270	2		T338	2
all_values[2]	auto[1]	auto[1]	auto[1]	52	1		T269	1		T270	1		T337	3
all_values[3]	auto[0]	auto[0]	auto[0]	78	1		T269	3		T270	1		T277	1
all_values[3]	auto[0]	auto[1]	auto[0]	79	1		T269	1		T270	2		T277	1
all_values[3]	auto[1]	auto[0]	auto[1]	62	1		T269	1		T277	1		T337	2
all_values[3]	auto[1]	auto[1]	auto[1]	53	1		T269	2		T270	1		T277	1
all_values[4]	auto[0]	auto[0]	auto[0]	54	1		T269	1		T270	2		T277	1
all_values[4]	auto[0]	auto[0]	auto[1]	24	1		T269	2		T339	1		T340	1
all_values[4]	auto[0]	auto[1]	auto[0]	51	1		T269	1		T270	1		T337	1
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T277	1		T337	1		T341	2
all_values[4]	auto[1]	auto[0]	auto[1]	62	1		T269	1		T277	1		T337	3
all_values[4]	auto[1]	auto[1]	auto[1]	51	1		T269	2		T270	1		T277	1
all_values[5]	auto[0]	auto[0]	auto[0]	47	1		T269	2		T270	1		T337	1
all_values[5]	auto[0]	auto[0]	auto[1]	33	1		T269	1		T277	1		T339	1
all_values[5]	auto[0]	auto[1]	auto[0]	33	1		T270	1		T337	1		T341	1
all_values[5]	auto[0]	auto[1]	auto[1]	27	1		T269	1		T337	1		T338	1
all_values[5]	auto[1]	auto[0]	auto[1]	78	1		T269	3		T270	2		T277	3
all_values[5]	auto[1]	auto[1]	auto[1]	54	1		T337	2		T338	1		T339	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal