Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	337565	1		T1	2		T2	1		T3	2
all_values[1]	337565	1		T1	2		T2	1		T3	2
all_values[2]	337565	1		T1	2		T2	1		T3	2
all_values[3]	337565	1		T1	2		T2	1		T3	2
all_values[4]	337565	1		T1	2		T2	1		T3	2
all_values[5]	337565	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	681485	1		T1	12		T2	6		T3	12
auto[1]	1343905	1		T32	5404		T44	46460		T37	6872

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	989274	1		T1	7		T2	4		T3	7
auto[1]	1036116	1		T1	5		T2	2		T3	5

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	337420	1		T1	2		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	145	1		T245	2		T246	2		T253	4
all_values[1]	auto[0]	auto[1]	337403	1		T1	2		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	162	1		T245	3		T246	2		T253	2
all_values[2]	auto[0]	auto[0]	1616	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	51	1		T245	1		T246	1		T253	1
all_values[2]	auto[1]	auto[0]	335844	1		T32	1351		T44	11615		T37	1718
all_values[2]	auto[1]	auto[1]	54	1		T245	1		T328	2		T329	3
all_values[3]	auto[0]	auto[0]	1609	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	52	1		T245	2		T246	2		T327	1
all_values[3]	auto[1]	auto[0]	88130	1		T32	1351		T44	24		T37	1718
all_values[3]	auto[1]	auto[1]	247774	1		T44	11591		T46	3010		T47	1762
all_values[4]	auto[0]	auto[0]	1148	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	522	1		T1	1		T3	1		T10	1
all_values[4]	auto[1]	auto[0]	223504	1		T32	1		T44	10522		T37	1
all_values[4]	auto[1]	auto[1]	112391	1		T32	1350		T44	1093		T37	1717
all_values[5]	auto[0]	auto[0]	1569	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	95	1		T48	1		T49	1		T50	1
all_values[5]	auto[1]	auto[0]	335854	1		T32	1351		T44	11615		T37	1718
all_values[5]	auto[1]	auto[1]	47	1		T245	2		T329	3		T332	4