Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	235723	1		T1	1		T3	4		T10	2
auto[FlashEraseBank]	263220	1		T1	1		T10	10		T12	6

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	259311	1		T3	2		T10	6		T11	253
auto[FlashOpProgram]	220675	1		T1	2		T3	1		T10	6
auto[FlashOpErase]	14957	1		T3	1		T11	128		T17	4
auto[FlashOpInvalid]	4000	1		T18	200		T90	200		T156	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	259311	1		T3	2		T10	6		T11	253
op[FlashOpProgram]	220675	1		T1	2		T3	1		T10	6
op[FlashOpErase]	14957	1		T3	1		T11	128		T17	4
read_erase_read	577	1		T17	2		T26	5		T28	1
read_prog_read	797	1		T10	5		T17	1		T26	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	355006	1		T1	2		T3	4		T10	12
auto[FlashPartInfo]	136555	1		T11	509		T18	102		T26	1142
auto[FlashPartInfo1]	2274	1		T18	76		T13	3		T48	2
auto[FlashPartInfo2]	5108	1		T18	120		T26	2		T13	7

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	187639	1		T3	2		T10	6		T12	42
auto[FlashPartData]	auto[FlashOpProgram]	162842	1		T1	2		T3	1		T10	6
auto[FlashPartData]	auto[FlashOpErase]	2605	1		T3	1		T17	4		T18	44
auto[FlashPartData]	auto[FlashOpInvalid]	1920	1		T18	88		T90	86		T156	106
auto[FlashPartInfo]	auto[FlashOpRead]	67965	1		T11	253		T18	34		T26	546
auto[FlashPartInfo]	auto[FlashOpProgram]	55906	1		T11	128		T18	17		T26	577
auto[FlashPartInfo]	auto[FlashOpErase]	11980	1		T11	128		T18	17		T26	19
auto[FlashPartInfo]	auto[FlashOpInvalid]	704	1		T18	34		T90	54		T156	40
auto[FlashPartInfo1]	auto[FlashOpRead]	1394	1		T18	38		T13	3		T48	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T410	1		T151	32		T160	1
auto[FlashPartInfo1]	auto[FlashOpErase]	1	1		T411	1		-	-		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	716	1		T18	38		T90	32		T156	36
auto[FlashPartInfo2]	auto[FlashOpRead]	2313	1		T18	40		T13	7		T48	9
auto[FlashPartInfo2]	auto[FlashOpProgram]	1764	1		T18	20		T26	1		T71	12
auto[FlashPartInfo2]	auto[FlashOpErase]	371	1		T18	20		T26	1		T87	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	660	1		T18	40		T90	28		T156	18