Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28501	1		T3	4		T10	24		T11	256
auto[1]	43	1		T36	1		T104	5		T263	2
auto[2]	61	1		T36	2		T157	4		T31	4
auto[3]	257	1		T36	6		T35	1		T51	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7209	1		T3	1		T10	6		T11	64
evic_idx[1]	7223	1		T3	1		T10	6		T11	64
evic_idx[2]	7223	1		T3	1		T10	6		T11	64
evic_idx[3]	7207	1		T3	1		T10	6		T11	64

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28018	1		T3	4		T11	256		T17	16
evic_op[2]	316	1		T10	24		T17	16		T104	5

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6936	1		T3	1		T11	64		T17	4
evic_idx[0]	evic_op[1]	auto[1]	4	1		T412	2		T413	1		T213	1
evic_idx[0]	evic_op[1]	auto[2]	4	1		T157	1		T412	1		T414	1
evic_idx[0]	evic_op[1]	auto[3]	58	1		T36	3		T386	5		T157	4
evic_idx[0]	evic_op[2]	auto[0]	62	1		T10	6		T17	4		T216	8
evic_idx[0]	evic_op[2]	auto[1]	5	1		T104	2		T263	1		T415	1
evic_idx[0]	evic_op[2]	auto[2]	3	1		T416	1		T417	1		T418	1
evic_idx[0]	evic_op[2]	auto[3]	5	1		T297	1		T419	1		T420	1
evic_idx[1]	evic_op[1]	auto[0]	6935	1		T3	1		T11	64		T17	4
evic_idx[1]	evic_op[1]	auto[1]	8	1		T36	1		T421	2		T412	2
evic_idx[1]	evic_op[1]	auto[2]	9	1		T36	1		T157	1		T412	2
evic_idx[1]	evic_op[1]	auto[3]	58	1		T386	4		T157	3		T421	1
evic_idx[1]	evic_op[2]	auto[0]	62	1		T10	6		T17	4		T216	8
evic_idx[1]	evic_op[2]	auto[1]	5	1		T104	1		T263	1		T415	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T422	1		T423	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	12	1		T424	1		T425	1		T426	1
evic_idx[2]	evic_op[1]	auto[0]	6934	1		T3	1		T11	64		T17	4
evic_idx[2]	evic_op[1]	auto[1]	8	1		T421	2		T412	2		T413	3
evic_idx[2]	evic_op[1]	auto[2]	12	1		T36	1		T157	1		T412	2
evic_idx[2]	evic_op[1]	auto[3]	51	1		T36	2		T386	3		T157	1
evic_idx[2]	evic_op[2]	auto[0]	63	1		T10	6		T17	4		T216	8
evic_idx[2]	evic_op[2]	auto[1]	4	1		T104	1		T427	1		T415	1
evic_idx[2]	evic_op[2]	auto[2]	7	1		T428	1		T429	1		T430	1
evic_idx[2]	evic_op[2]	auto[3]	12	1		T51	1		T431	1		T432	1
evic_idx[3]	evic_op[1]	auto[0]	6933	1		T3	1		T11	64		T17	4
evic_idx[3]	evic_op[1]	auto[1]	7	1		T421	3		T412	1		T413	2
evic_idx[3]	evic_op[1]	auto[2]	8	1		T157	1		T412	1		T414	2
evic_idx[3]	evic_op[1]	auto[3]	53	1		T36	1		T386	2		T157	4
evic_idx[3]	evic_op[2]	auto[0]	60	1		T10	6		T17	4		T216	8
evic_idx[3]	evic_op[2]	auto[1]	2	1		T104	1		T433	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	4	1		T428	2		T434	1		T435	1
evic_idx[3]	evic_op[2]	auto[3]	8	1		T35	1		T52	1		T436	1