Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	35159	1		T44	2388		T333	16191		T334	15792
rd_lvl[2]	26605	1		T44	1815		T333	11936		T334	11728
rd_lvl[3]	4582	1		T44	1091		T335	346		T336	1307
rd_lvl[4]	34787	1		T44	1005		T335	94		T337	5153
rd_lvl[5]	17981	1		T44	846		T338	2430		T337	1267
rd_lvl[6]	18499	1		T44	22		T46	2741		T313	571
rd_lvl[7]	11422	1		T44	806		T46	151		T313	228
rd_lvl[8]	19675	1		T44	809		T313	56		T339	1531
rd_lvl[9]	7716	1		T44	981		T313	75		T42	165
rd_lvl[10]	5605	1		T44	622		T313	78		T340	1047
rd_lvl[11]	1742	1		T44	23		T42	10		T43	324
rd_lvl[12]	6056	1		T47	1445		T341	1149		T342	54
rd_lvl[13]	4957	1		T47	317		T343	452		T341	464
rd_lvl[14]	11469	1		T44	7		T343	1012		T344	1308
rd_lvl[15]	3533	1		T344	347		T41	181		T345	340