Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	337565	1		T1	2		T2	1		T3	2
all_pins[1]	337565	1		T1	2		T2	1		T3	2
all_pins[2]	337565	1		T1	2		T2	1		T3	2
all_pins[3]	337565	1		T1	2		T2	1		T3	2
all_pins[4]	337565	1		T1	2		T2	1		T3	2
all_pins[5]	337565	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1686190	1		T1	12		T2	6		T3	12
values[0x1]	339200	1		T32	1350		T44	11553		T37	1717
transitions[0x0=>0x1]	302343	1		T32	1350		T44	10439		T37	1717
transitions[0x1=>0x0]	302324	1		T32	1350		T44	10439		T37	1717

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	337420	1		T1	2		T2	1		T3	2
all_pins[0]	values[0x1]	145	1		T245	2		T246	2		T253	4
all_pins[0]	transitions[0x0=>0x1]	70	1		T245	2		T246	2		T253	2
all_pins[0]	transitions[0x1=>0x0]	87	1		T245	3		T246	2		T329	3
all_pins[1]	values[0x0]	337403	1		T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	162	1		T245	3		T246	2		T253	2
all_pins[1]	transitions[0x0=>0x1]	130	1		T245	3		T246	2		T253	2
all_pins[1]	transitions[0x1=>0x0]	3967	1		T41	106		T347	337		T348	1250
all_pins[2]	values[0x0]	333566	1		T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	3999	1		T41	106		T347	337		T348	1250
all_pins[2]	transitions[0x0=>0x1]	44	1		T328	1		T329	3		T330	1
all_pins[2]	transitions[0x1=>0x0]	209998	1		T44	10415		T46	2892		T47	1762
all_pins[3]	values[0x0]	123612	1		T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	213953	1		T44	10415		T46	2892		T47	1762
all_pins[3]	transitions[0x0=>0x1]	181200	1		T44	9301		T46	2892		T47	1762
all_pins[3]	transitions[0x1=>0x0]	88141	1		T32	1350		T44	24		T37	1717
all_pins[4]	values[0x0]	216671	1		T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	120894	1		T32	1350		T44	1138		T37	1717
all_pins[4]	transitions[0x0=>0x1]	120876	1		T32	1350		T44	1138		T37	1717
all_pins[4]	transitions[0x1=>0x0]	29	1		T329	1		T332	3		T349	2
all_pins[5]	values[0x0]	337518	1		T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	47	1		T245	2		T329	3		T332	4
all_pins[5]	transitions[0x0=>0x1]	23	1		T245	1		T329	2		T332	3
all_pins[5]	transitions[0x1=>0x0]	102	1		T245	1		T246	2		T253	3