Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	231808	1		T2	4		T3	41		T15	1
auto[FlashEraseBank]	257645	1		T3	10		T9	14		T10	4

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	249177	1		T2	2		T3	51		T15	1
auto[FlashOpProgram]	220600	1		T2	1		T9	14		T10	10
auto[FlashOpErase]	15676	1		T2	1		T18	84		T20	4
auto[FlashOpInvalid]	4000	1		T18	200		T61	200		T91	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	249177	1		T2	2		T3	51		T15	1
op[FlashOpProgram]	220600	1		T2	1		T9	14		T10	10
op[FlashOpErase]	15676	1		T2	1		T18	84		T20	4
read_erase_read	530	1		T20	2		T37	5		T42	11
read_prog_read	853	1		T10	9		T20	1		T11	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	345119	1		T2	4		T3	51		T15	1
auto[FlashPartInfo]	136719	1		T18	60		T11	117		T37	1170
auto[FlashPartInfo1]	2156	1		T18	64		T55	1		T63	4
auto[FlashPartInfo2]	5459	1		T18	90		T11	5		T76	17

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	179281	1		T2	2		T3	51		T15	1
auto[FlashPartData]	auto[FlashOpProgram]	161177	1		T2	1		T9	14		T10	10
auto[FlashPartData]	auto[FlashOpErase]	2613	1		T2	1		T18	59		T20	4
auto[FlashPartData]	auto[FlashOpInvalid]	2048	1		T18	118		T61	106		T91	108
auto[FlashPartInfo]	auto[FlashOpRead]	65868	1		T18	20		T11	78		T37	674
auto[FlashPartInfo]	auto[FlashOpProgram]	57467	1		T18	10		T11	39		T37	482
auto[FlashPartInfo]	auto[FlashOpErase]	12718	1		T18	10		T37	14		T27	350
auto[FlashPartInfo]	auto[FlashOpInvalid]	666	1		T18	20		T61	26		T91	28
auto[FlashPartInfo1]	auto[FlashOpRead]	1322	1		T18	32		T55	1		T63	4
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T92	1		T294	1		T162	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T92	1		T434	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	668	1		T18	32		T61	36		T91	32
auto[FlashPartInfo2]	auto[FlashOpRead]	2706	1		T18	30		T11	5		T76	5
auto[FlashPartInfo2]	auto[FlashOpProgram]	1792	1		T18	15		T76	12		T88	12
auto[FlashPartInfo2]	auto[FlashOpErase]	343	1		T18	15		T42	8		T61	16
auto[FlashPartInfo2]	auto[FlashOpInvalid]	618	1		T18	30		T61	32		T91	32