Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30179	1		T2	4		T10	40		T18	336
auto[1]	56	1		T110	5		T169	2		T282	2
auto[2]	63	1		T34	4		T73	12		T258	4
auto[3]	308	1		T42	9		T123	1		T228	20

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7660	1		T2	1		T10	10		T18	84
evic_idx[1]	7656	1		T2	1		T10	10		T18	84
evic_idx[2]	7646	1		T2	1		T10	10		T18	84
evic_idx[3]	7644	1		T2	1		T10	10		T18	84

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Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29702	1		T2	4		T18	336		T20	8
evic_op[2]	350	1		T10	40		T20	16		T59	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[3]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7343	1		T2	1		T18	84		T20	2
evic_idx[0]	evic_op[1]	auto[1]	11	1		T354	1		T355	2		T356	1
evic_idx[0]	evic_op[1]	auto[2]	8	1		T357	4		T358	1		T359	1
evic_idx[0]	evic_op[1]	auto[3]	68	1		T42	1		T228	3		T170	4
evic_idx[0]	evic_op[2]	auto[0]	73	1		T10	10		T20	4		T59	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T169	1		T360	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	6	1		T361	1		T362	1		T363	1
evic_idx[0]	evic_op[2]	auto[3]	10	1		T310	1		T57	1		T220	1
evic_idx[1]	evic_op[1]	auto[0]	7345	1		T2	1		T18	84		T20	2
evic_idx[1]	evic_op[1]	auto[1]	10	1		T355	2		T356	1		T358	1
evic_idx[1]	evic_op[1]	auto[2]	6	1		T357	3		T358	1		T359	1
evic_idx[1]	evic_op[1]	auto[3]	74	1		T42	3		T228	4		T170	4
evic_idx[1]	evic_op[2]	auto[0]	66	1		T10	10		T20	4		T227	5
evic_idx[1]	evic_op[2]	auto[1]	4	1		T110	1		T169	1		T360	1
evic_idx[1]	evic_op[2]	auto[2]	4	1		T364	1		T365	1		T366	1
evic_idx[1]	evic_op[2]	auto[3]	8	1		T123	1		T367	1		T368	1
evic_idx[2]	evic_op[1]	auto[0]	7344	1		T2	1		T18	84		T20	2
evic_idx[2]	evic_op[1]	auto[1]	7	1		T355	2		T356	1		T358	1
evic_idx[2]	evic_op[1]	auto[2]	5	1		T357	2		T359	1		T321	2
evic_idx[2]	evic_op[1]	auto[3]	64	1		T42	3		T228	7		T170	3
evic_idx[2]	evic_op[2]	auto[0]	71	1		T10	10		T20	4		T227	5
evic_idx[2]	evic_op[2]	auto[1]	6	1		T110	2		T282	1		T360	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T362	1		T369	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	9	1		T210	1		T330	1		T370	1
evic_idx[3]	evic_op[1]	auto[0]	7342	1		T2	1		T18	84		T20	2
evic_idx[3]	evic_op[1]	auto[1]	9	1		T354	1		T355	2		T358	1
evic_idx[3]	evic_op[1]	auto[2]	4	1		T357	2		T359	1		T321	1
evic_idx[3]	evic_op[1]	auto[3]	62	1		T42	2		T228	6		T170	3
evic_idx[3]	evic_op[2]	auto[0]	69	1		T10	10		T20	4		T227	5
evic_idx[3]	evic_op[2]	auto[1]	7	1		T110	2		T282	1		T360	1
evic_idx[3]	evic_op[2]	auto[3]	13	1		T371	1		T372	1		T362	1