Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	37692	1		T54	15132		T339	15789		T340	1788
rd_lvl[2]	44936	1		T53	1351		T54	10756		T339	11587
rd_lvl[3]	11632	1		T53	561		T340	364		T341	293
rd_lvl[4]	21201	1		T53	103		T342	5896		T340	166
rd_lvl[5]	7917	1		T53	322		T342	652		T340	49
rd_lvl[6]	9917	1		T53	292		T343	464		T340	19
rd_lvl[7]	9413	1		T343	176		T340	3		T344	79
rd_lvl[8]	23875	1		T53	1		T343	4		T345	2602
rd_lvl[9]	10610	1		T346	405		T343	158		T345	322
rd_lvl[10]	7039	1		T346	1146		T343	158		T347	1079
rd_lvl[11]	2178	1		T340	27		T348	354		T349	358
rd_lvl[12]	7867	1		T52	1388		T53	109		T340	1
rd_lvl[13]	3323	1		T52	224		T53	109		T50	270
rd_lvl[14]	5959	1		T50	1395		T340	27		T350	1291
rd_lvl[15]	4201	1		T49	189		T350	323		T351	491