Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	321026	1		T1	1		T2	2		T3	2
all_pins[1]	321026	1		T1	1		T2	2		T3	2
all_pins[2]	321026	1		T1	1		T2	2		T3	2
all_pins[3]	321026	1		T1	1		T2	2		T3	2
all_pins[4]	321026	1		T1	1		T2	2		T3	2
all_pins[5]	321026	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1605821	1		T1	6		T2	12		T3	12
values[0x1]	320335	1		T44	1624		T52	3224		T45	1510
transitions[0x0=>0x1]	285672	1		T44	1624		T52	3224		T45	1510
transitions[0x1=>0x0]	285662	1		T44	1624		T52	3224		T45	1510

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	320870	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	156	1		T262	1		T269	1		T331	6
all_pins[0]	transitions[0x0=>0x1]	75	1		T269	1		T331	4		T333	1
all_pins[0]	transitions[0x1=>0x0]	87	1		T262	3		T269	1		T332	3
all_pins[1]	values[0x0]	320858	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	168	1		T262	4		T269	1		T331	2
all_pins[1]	transitions[0x0=>0x1]	132	1		T262	3		T269	1		T331	2
all_pins[1]	transitions[0x1=>0x0]	2985	1		T49	112		T351	1209		T373	1032
all_pins[2]	values[0x0]	318005	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	3021	1		T49	112		T351	1209		T373	1032
all_pins[2]	transitions[0x0=>0x1]	51	1		T269	1		T331	2		T332	1
all_pins[2]	transitions[0x1=>0x0]	207840	1		T52	1612		T53	2848		T54	25888
all_pins[3]	values[0x0]	110216	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	210810	1		T52	1612		T53	2848		T54	25888
all_pins[3]	transitions[0x0=>0x1]	179310	1		T52	1612		T53	2457		T54	23339
all_pins[3]	transitions[0x1=>0x0]	74582	1		T44	1624		T52	1612		T45	1510
all_pins[4]	values[0x0]	214944	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	106082	1		T44	1624		T52	1612		T45	1510
all_pins[4]	transitions[0x0=>0x1]	106060	1		T44	1624		T52	1612		T45	1510
all_pins[4]	transitions[0x1=>0x0]	76	1		T262	3		T269	3		T333	1
all_pins[5]	values[0x0]	320928	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	98	1		T262	3		T269	3		T331	2
all_pins[5]	transitions[0x0=>0x1]	44	1		T262	2		T269	2		T331	1
all_pins[5]	transitions[0x1=>0x0]	92	1		T331	4		T332	1		T333	1