Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	293	1		T262	4		T269	4		T331	7
all_values[1]	293	1		T262	4		T269	4		T331	7
all_values[2]	293	1		T262	4		T269	4		T331	7
all_values[3]	293	1		T262	4		T269	4		T331	7
all_values[4]	293	1		T262	4		T269	4		T331	7
all_values[5]	293	1		T262	4		T269	4		T331	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	950	1		T262	11		T269	18		T331	21
auto[1]	808	1		T262	13		T269	6		T331	21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	551	1		T262	2		T269	6		T331	15
auto[1]	1207	1		T262	22		T269	18		T331	27

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1020	1		T262	10		T269	15		T331	26
auto[1]	738	1		T262	14		T269	9		T331	16

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	92	1		T262	2		T269	3		T331	1
all_values[0]	auto[0]	auto[1]	auto[1]	77	1		T262	1		T331	3		T332	1
all_values[0]	auto[1]	auto[0]	auto[1]	72	1		T262	1		T269	1		T331	1
all_values[0]	auto[1]	auto[1]	auto[1]	52	1		T331	2		T333	1		T334	2
all_values[1]	auto[0]	auto[0]	auto[1]	94	1		T269	2		T331	4		T332	1
all_values[1]	auto[0]	auto[1]	auto[1]	80	1		T262	1		T269	2		T331	1
all_values[1]	auto[1]	auto[0]	auto[1]	64	1		T262	2		T331	1		T332	2
all_values[1]	auto[1]	auto[1]	auto[1]	55	1		T262	1		T331	1		T332	3
all_values[2]	auto[0]	auto[0]	auto[0]	89	1		T269	2		T331	2		T332	3
all_values[2]	auto[0]	auto[1]	auto[0]	84	1		T262	1		T332	2		T333	3
all_values[2]	auto[1]	auto[0]	auto[1]	65	1		T262	3		T269	2		T331	3
all_values[2]	auto[1]	auto[1]	auto[1]	55	1		T331	2		T332	2		T333	1
all_values[3]	auto[0]	auto[0]	auto[0]	106	1		T269	3		T331	3		T332	3
all_values[3]	auto[0]	auto[1]	auto[0]	75	1		T262	1		T331	4		T332	1
all_values[3]	auto[1]	auto[0]	auto[1]	59	1		T262	1		T269	1		T332	3
all_values[3]	auto[1]	auto[1]	auto[1]	53	1		T262	2		T333	2		T335	1
all_values[4]	auto[0]	auto[0]	auto[0]	52	1		T331	1		T332	2		T336	2
all_values[4]	auto[0]	auto[0]	auto[1]	34	1		T262	1		T269	1		T333	1
all_values[4]	auto[0]	auto[1]	auto[0]	48	1		T331	3		T332	4		T333	3
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T262	1		T331	1		T333	1
all_values[4]	auto[1]	auto[0]	auto[1]	81	1		T262	1		T269	1		T331	1
all_values[4]	auto[1]	auto[1]	auto[1]	48	1		T262	1		T269	2		T331	1
all_values[5]	auto[0]	auto[0]	auto[0]	52	1		T269	1		T331	1		T332	2
all_values[5]	auto[0]	auto[0]	auto[1]	23	1		T334	2		T337	1		T338	2
all_values[5]	auto[0]	auto[1]	auto[0]	45	1		T331	1		T332	3		T333	1
all_values[5]	auto[0]	auto[1]	auto[1]	39	1		T262	2		T269	1		T331	1
all_values[5]	auto[1]	auto[0]	auto[1]	67	1		T269	1		T331	3		T332	2
all_values[5]	auto[1]	auto[1]	auto[1]	67	1		T262	2		T269	1		T331	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal