FLASH_CTRL Lint Results

Tuesday June 27 2023 20:09:22 UTC

GitHub Revision: fd9a3c14c

Branch: os_regression

Tool: VERILATOR

Build Mode Flow Warnings Flow Errors Lint Warnings Lint Errors
default 0 2 19 0

Messages for Build Mode 'default'

Flow Errors

ERROR: %Warning-WIDTH: ../src/lowrisc_systems_flash_ctrl_pkg_0.1/rtl/autogen/flash_ctrl_pkg.sv:311:18: Operator PATMEMBER expects 10 bits on the Pattern value, but Pattern value's MUL generates 32 bits.

ERROR: Failed to build lowrisc:ip:flash_ctrl:0.1 : '['make', '-j', '120', 'Vflash_ctrl.mk']' exited with an error: 2

Lint Warnings

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv:65:55: Operator LT expects 32 bits on the LHS, but LHS's VARREF 'curr_incr_cnt' generates 2 bits.

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv:153:36: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'idx' generates 1 bits.

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv:213:26: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'idx' generates 1 bits.

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv:230:17: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'idx' generates 1 bits.

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:251:66: Operator LTE expects 32 bits on the LHS, but LHS's VARREF 'host_outstanding' generates 2 bits.

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:430:65: Operator EQ expects 2 bits on the RHS, but RHS's CONST '1'h1' generates 1 bits.

%Warning-WIDTH: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv:737:24: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS's VARREF 'MaxBeatCnt' generates 32 bits.

%Warning-WIDTH: ../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_region_cfg.sv:116:47: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's MUL generates 32 bits.

%Warning-UNOPTFLAT: ../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv:228:12: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_tl_gate.tl_d2h_error'

%Warning-UNOPTFLAT: ../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv:56:39: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.gen_normal_case.gnt_tree[0]'

%Warning-UNOPTFLAT: ../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl_core_reg_top.sv:66:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_reg_core.reg_we_err'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:406:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.flash_rd_req'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv:667:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_rd.intg_err_pre'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:54:38: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.ecc_single_err_o'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv:405:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_rd.data_err'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:120:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.prog_ack'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:123:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.erase_ack'

%Warning-UNOPTFLAT: ../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv:138:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.rd_stage_data_valid'

%Warning-UNOPTFLAT: ../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv:300:15: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.flash_phy_rsp'

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