FLASH_CTRL Lint Results
Saturday June 08 2024 00:41:57 UTC
Branch: os_regression
Tool: VERILATOR
| Build Mode |
Flow Infos |
Flow Warnings |
Flow Errors |
Lint Infos |
Lint Warnings |
Lint Errors |
| default |
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Messages for Build Mode 'default'
Flow Errors
ERROR: %Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_pkg_0.1/rtl/flash_ctrl_pkg.sv:296:18: Operator PATMEMBER expects 10 bits on the Pattern value, but Pattern value's MUL generates 32 bits.
ERROR: Failed to build lowrisc:opentitan:top_earlgrey_flash_ctrl:0.1 : '['make', 'Vflash_ctrl.mk']' exited with an error: 2
Lint Warnings
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv:65:55: Operator LT expects 32 bits on the LHS, but LHS's VARREF 'curr_incr_cnt' generates 2 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv:153:36: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'idx' generates 1 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv:213:26: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'idx' generates 1 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv:230:17: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'idx' generates 1 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv:754:56: Operator XOR expects 32 bits on the RHS, but RHS's VARREF 'addr_xor_muxed' generates 17 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:248:66: Operator LTE expects 32 bits on the LHS, but LHS's VARREF 'host_outstanding' generates 2 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:428:65: Operator EQ expects 2 bits on the RHS, but RHS's CONST '1'h1' generates 1 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_region_cfg.sv:110:47: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS's MUL generates 32 bits.
%Warning-WIDTH: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv:743:24: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS's VARREF 'MaxBeatCnt' generates 32 bits.
%Warning-WIDTH: ../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv:512:77: Operator XOR expects 32 bits on the RHS, but RHS's VARREF 'addr_xor' generates 12 bits.
%Warning-WIDTH: ../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv:512:77: Operator XOR expects 32 bits on the RHS, but RHS's VARREF 'addr_xor' generates 17 bits.
%Warning-UNUSED: ../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv:267:19: Signal is not used: 'sramreqaddrfifo_wdata'
%Warning-UNDRIVEN: ../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv:267:42: Signal is not driven: 'sramreqaddrfifo_rdata'
%Warning-UNUSED: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv:470:9: Signal is not used: 'fifo_addr_xor_valid'
%Warning-UNUSED: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv:571:9: Signal is not used: 'host_req'
%Warning-LATCH: ../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv:493:5: Latch inferred for signal 'flash_ctrl.u_tl_adapter_eflash.gen_no_rmask.gen_data_xor_addr.addr_xor' (not all control paths of combinational always assign a value)
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv:156:11: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_flash_hw_if.rma_ack_d'
%Warning-UNOPTFLAT: ../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv:56:39: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.gen_normal_case.gnt_tree[0]'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_reg_0.1/rtl/flash_ctrl_core_reg_top.sv:63:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_reg_core.reg_we_err'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:404:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.flash_rd_req'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv:768:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_rd.intg_err_pre'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv:418:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.u_rd.data_err'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:52:38: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.ecc_single_err_o'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:118:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.prog_ack'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:121:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.erase_ack'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv:136:9: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.u_eflash.gen_flash_cores[0].u_core.rd_stage_data_valid'
%Warning-UNOPTFLAT: ../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl.sv:290:15: Signal unoptimizable: Feedback to clock or circular logic: 'flash_ctrl.flash_phy_rsp'
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