Summary for Variable dai_access_cmd
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for dai_access_cmd
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| dai_digest |
2605 |
1 |
|
|
T2 |
3 |
|
T3 |
4 |
|
T6 |
2 |
| dai_wr |
5765 |
1 |
|
|
T1 |
6 |
|
T2 |
5 |
|
T3 |
10 |
| dai_rd |
10325 |
1 |
|
|
T1 |
6 |
|
T2 |
6 |
|
T3 |
32 |
Summary for Variable lc_creator_seed_sw_rw_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_creator_seed_sw_rw_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8532 |
1 |
|
|
T1 |
2 |
|
T2 |
10 |
|
T3 |
25 |
| auto[1] |
10163 |
1 |
|
|
T1 |
10 |
|
T2 |
4 |
|
T3 |
21 |
Summary for Cross dai_access_secret2
Samples crossed: lc_creator_seed_sw_rw_en dai_access_cmd
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins for dai_access_secret2
Bins
| lc_creator_seed_sw_rw_en | dai_access_cmd | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
dai_digest |
1477 |
1 |
|
|
T2 |
1 |
|
T3 |
3 |
|
T6 |
1 |
| auto[0] |
dai_wr |
2055 |
1 |
|
|
T1 |
1 |
|
T2 |
4 |
|
T3 |
4 |
| auto[0] |
dai_rd |
5000 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T3 |
18 |
| auto[1] |
dai_digest |
1128 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T6 |
1 |
| auto[1] |
dai_wr |
3710 |
1 |
|
|
T1 |
5 |
|
T2 |
1 |
|
T3 |
6 |
| auto[1] |
dai_rd |
5325 |
1 |
|
|
T1 |
5 |
|
T2 |
1 |
|
T3 |
14 |