Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	46765	1			T4	77		T9	63		T17	7
access_err	62607	1			T1	33		T2	18		T4	1
write_blank_err	400	1			T5	4		T6	7		T7	8
ecc_uncorr_err	58437	1			T5	827		T99	141		T6	317
ecc_corr_err	1202	1			T17	3		T40	19		T31	74
no_err	85205	1			T1	36		T2	15		T3	5

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	585	1			T5	9		T6	23		T7	4
secret2	27892	1			T1	13		T2	4		T3	1
secret1	26407	1			T1	6		T2	3		T4	1
secret0	31146	1			T1	10		T3	3		T4	82
hw_cfg1	30732	1			T2	2		T4	2		T8	5
hw_cfg0	29679	1			T1	6		T2	3		T4	4
rot_creator_auth_state	19120	1			T1	10		T2	2		T4	4
rot_creator_auth_codesign	21413	1			T1	9		T2	11		T4	3
owner_sw_cfg	19864	1			T1	10		T2	5		T8	2
creator_sw_cfg	19022	1			T1	4		T2	2		T3	1
vendor_test	28756	1			T1	1		T2	1		T4	1

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	5891	1			T132	152		T158	25		T342	267
fsm_err	secret1	4209	1			T164	48		T269	211		T343	148
fsm_err	secret0	2238	1			T4	77		T14	264		T344	268
fsm_err	hw_cfg1	3971	1			T110	121		T6	405		T204	164
fsm_err	hw_cfg0	6699	1			T9	63		T145	68		T153	51
fsm_err	rot_creator_auth_state	1946	1			T100	562		T220	5		T156	36
fsm_err	rot_creator_auth_codesign	4090	1			T252	432		T207	5		T220	2
fsm_err	owner_sw_cfg	3291	1			T157	17		T238	23		T345	108
fsm_err	creator_sw_cfg	2675	1			T164	54		T242	46		T200	54
fsm_err	vendor_test	11755	1			T17	7		T5	76		T99	35
access_err	life_cycle	585	1			T5	9		T6	23		T7	4
access_err	secret2	10693	1			T1	9		T2	1		T8	6
access_err	secret1	6587	1			T12	19		T40	4		T5	69
access_err	secret0	5208	1			T8	1		T12	6		T17	4
access_err	hw_cfg1	1296	1			T8	1		T12	5		T108	1
access_err	hw_cfg0	2326	1			T1	1		T2	3		T12	4
access_err	rot_creator_auth_state	5639	1			T1	5		T2	1		T12	4
access_err	rot_creator_auth_codesign	8140	1			T1	8		T2	8		T12	17
access_err	owner_sw_cfg	7153	1			T1	9		T2	4		T12	2
access_err	creator_sw_cfg	7696	1			T1	1		T2	1		T12	11
access_err	vendor_test	7284	1			T4	1		T109	3		T110	1
write_blank_err	secret2	12	1			T5	1		T211	1		T214	1
write_blank_err	secret1	25	1			T7	1		T162	1		T229	1
write_blank_err	secret0	44	1			T160	1		T14	1		T16	1
write_blank_err	hw_cfg1	51	1			T6	1		T161	1		T15	1
write_blank_err	hw_cfg0	21	1			T5	1		T115	1		T132	1
write_blank_err	rot_creator_auth_state	123	1			T5	2		T6	3		T162	7
write_blank_err	rot_creator_auth_codesign	62	1			T7	1		T15	4		T346	3
write_blank_err	owner_sw_cfg	20	1			T6	3		T7	3		T160	1
write_blank_err	creator_sw_cfg	18	1			T7	3		T211	1		T154	3
write_blank_err	vendor_test	24	1			T132	2		T233	2		T347	1
ecc_uncorr_err	secret2	6217	1			T5	318		T157	29		T220	27
ecc_uncorr_err	secret1	7682	1			T7	348		T162	106		T164	36
ecc_uncorr_err	secret0	16043	1			T99	41		T160	541		T157	25
ecc_uncorr_err	hw_cfg1	14957	1			T6	317		T157	33		T161	407
ecc_uncorr_err	hw_cfg0	8293	1			T5	509		T99	68		T115	544
ecc_uncorr_err	rot_creator_auth_state	3010	1			T157	24		T163	2		T164	93
ecc_uncorr_err	rot_creator_auth_codesign	730	1			T163	2		T164	41		T220	9
ecc_uncorr_err	owner_sw_cfg	731	1			T99	32		T163	5		T200	54
ecc_uncorr_err	creator_sw_cfg	774	1			T157	40		T282	15		T223	25
ecc_corr_err	secret2	51	1			T40	1		T104	1		T72	4
ecc_corr_err	secret1	110	1			T17	2		T104	2		T164	1
ecc_corr_err	secret0	138	1			T31	5		T99	1		T157	1
ecc_corr_err	hw_cfg1	252	1			T40	6		T31	22		T99	1
ecc_corr_err	hw_cfg0	204	1			T40	2		T31	20		T104	11
ecc_corr_err	rot_creator_auth_state	120	1			T40	2		T31	11		T99	2
ecc_corr_err	rot_creator_auth_codesign	117	1			T31	4		T98	1		T157	3
ecc_corr_err	owner_sw_cfg	122	1			T17	1		T40	2		T31	11
ecc_corr_err	creator_sw_cfg	88	1			T40	6		T31	1		T157	1
no_err	secret2	5028	1			T1	4		T2	3		T3	1
no_err	secret1	7794	1			T1	6		T2	3		T4	1
no_err	secret0	7475	1			T1	10		T3	3		T4	5
no_err	hw_cfg1	10205	1			T2	2		T4	2		T8	4
no_err	hw_cfg0	12136	1			T1	5		T4	4		T8	6
no_err	rot_creator_auth_state	8282	1			T1	5		T2	1		T4	4
no_err	rot_creator_auth_codesign	8274	1			T1	1		T2	3		T4	3
no_err	owner_sw_cfg	8547	1			T1	1		T2	1		T8	2
no_err	creator_sw_cfg	7771	1			T1	3		T2	1		T3	1
no_err	vendor_test	9693	1			T1	1		T2	1		T8	9

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded