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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.88 93.84 96.70 95.84 91.17 97.14 96.33 93.14


Total test records in report: 1324
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T1262 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.2453243095 Apr 28 03:37:51 PM PDT 24 Apr 28 03:37:53 PM PDT 24 38515756 ps
T1263 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.4025861070 Apr 28 03:37:51 PM PDT 24 Apr 28 03:37:54 PM PDT 24 552723273 ps
T1264 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.93900230 Apr 28 03:37:36 PM PDT 24 Apr 28 03:37:42 PM PDT 24 409763828 ps
T1265 /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2913220724 Apr 28 03:37:46 PM PDT 24 Apr 28 03:37:48 PM PDT 24 139210176 ps
T1266 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1540469481 Apr 28 03:37:36 PM PDT 24 Apr 28 03:37:42 PM PDT 24 321260523 ps
T361 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3063839563 Apr 28 03:37:40 PM PDT 24 Apr 28 03:38:02 PM PDT 24 2494815423 ps
T1267 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1179693748 Apr 28 03:37:40 PM PDT 24 Apr 28 03:37:45 PM PDT 24 62291582 ps
T312 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.796176878 Apr 28 03:37:48 PM PDT 24 Apr 28 03:37:50 PM PDT 24 160352295 ps
T1268 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2449239451 Apr 28 03:37:43 PM PDT 24 Apr 28 03:37:50 PM PDT 24 298589703 ps
T1269 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3609636054 Apr 28 03:37:33 PM PDT 24 Apr 28 03:37:36 PM PDT 24 87851888 ps
T1270 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.1825372196 Apr 28 03:37:51 PM PDT 24 Apr 28 03:37:53 PM PDT 24 40731310 ps
T362 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.700819454 Apr 28 03:37:32 PM PDT 24 Apr 28 03:37:55 PM PDT 24 4404854807 ps
T1271 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1676123950 Apr 28 03:37:47 PM PDT 24 Apr 28 03:37:49 PM PDT 24 584660893 ps
T1272 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.920828630 Apr 28 03:37:52 PM PDT 24 Apr 28 03:37:54 PM PDT 24 36049107 ps
T359 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1456913533 Apr 28 03:37:37 PM PDT 24 Apr 28 03:38:01 PM PDT 24 2469359336 ps
T1273 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.34587432 Apr 28 03:37:51 PM PDT 24 Apr 28 03:37:53 PM PDT 24 76948923 ps
T360 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2367152296 Apr 28 03:37:41 PM PDT 24 Apr 28 03:37:56 PM PDT 24 9752114647 ps
T1274 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1222495468 Apr 28 03:37:42 PM PDT 24 Apr 28 03:37:47 PM PDT 24 447270936 ps
T1275 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1822690627 Apr 28 03:37:27 PM PDT 24 Apr 28 03:37:29 PM PDT 24 647332771 ps
T1276 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.32597275 Apr 28 03:37:46 PM PDT 24 Apr 28 03:37:48 PM PDT 24 73170717 ps
T313 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3364911526 Apr 28 03:37:37 PM PDT 24 Apr 28 03:37:44 PM PDT 24 1400844175 ps
T354 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3288474781 Apr 28 03:37:38 PM PDT 24 Apr 28 03:38:05 PM PDT 24 4561352190 ps
T1277 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2810610704 Apr 28 03:37:50 PM PDT 24 Apr 28 03:37:52 PM PDT 24 52454839 ps
T1278 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2414915116 Apr 28 03:37:34 PM PDT 24 Apr 28 03:37:41 PM PDT 24 696322078 ps
T1279 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.104983581 Apr 28 03:37:33 PM PDT 24 Apr 28 03:37:44 PM PDT 24 710728065 ps
T1280 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2732703147 Apr 28 03:37:37 PM PDT 24 Apr 28 03:37:42 PM PDT 24 287062605 ps
T1281 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3910994531 Apr 28 03:37:47 PM PDT 24 Apr 28 03:37:49 PM PDT 24 101762363 ps
T1282 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3855522266 Apr 28 03:37:35 PM PDT 24 Apr 28 03:37:41 PM PDT 24 72665834 ps
T1283 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3434192310 Apr 28 03:37:42 PM PDT 24 Apr 28 03:37:44 PM PDT 24 97533455 ps
T1284 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3672712843 Apr 28 03:37:27 PM PDT 24 Apr 28 03:37:33 PM PDT 24 89938537 ps
T1285 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3348677630 Apr 28 03:37:31 PM PDT 24 Apr 28 03:37:34 PM PDT 24 78562010 ps
T1286 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3653583592 Apr 28 03:37:46 PM PDT 24 Apr 28 03:37:48 PM PDT 24 43071015 ps
T1287 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.4284265280 Apr 28 03:37:29 PM PDT 24 Apr 28 03:37:33 PM PDT 24 200332770 ps
T1288 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2579653434 Apr 28 03:37:46 PM PDT 24 Apr 28 03:37:48 PM PDT 24 61045418 ps
T1289 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3201305947 Apr 28 03:37:28 PM PDT 24 Apr 28 03:37:29 PM PDT 24 505588417 ps
T1290 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1031630844 Apr 28 03:37:42 PM PDT 24 Apr 28 03:37:46 PM PDT 24 413265232 ps
T316 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1346122931 Apr 28 03:37:45 PM PDT 24 Apr 28 03:37:47 PM PDT 24 575228422 ps
T1291 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.64717056 Apr 28 03:37:41 PM PDT 24 Apr 28 03:37:46 PM PDT 24 117883255 ps
T1292 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2015666144 Apr 28 03:37:36 PM PDT 24 Apr 28 03:37:43 PM PDT 24 86459159 ps
T1293 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2454419458 Apr 28 03:37:48 PM PDT 24 Apr 28 03:37:50 PM PDT 24 36632987 ps
T1294 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3556474655 Apr 28 03:37:41 PM PDT 24 Apr 28 03:37:44 PM PDT 24 63700230 ps
T1295 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3066247690 Apr 28 03:37:31 PM PDT 24 Apr 28 03:37:36 PM PDT 24 534540683 ps
T1296 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3885758601 Apr 28 03:37:31 PM PDT 24 Apr 28 03:37:35 PM PDT 24 56240349 ps
T1297 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2033388545 Apr 28 03:37:35 PM PDT 24 Apr 28 03:37:38 PM PDT 24 95280964 ps
T1298 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.539843581 Apr 28 03:37:49 PM PDT 24 Apr 28 03:37:51 PM PDT 24 41870444 ps
T1299 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.743905250 Apr 28 03:37:37 PM PDT 24 Apr 28 03:37:46 PM PDT 24 596059019 ps
T1300 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3849246184 Apr 28 03:37:30 PM PDT 24 Apr 28 03:37:32 PM PDT 24 135818004 ps
T1301 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2988689651 Apr 28 03:37:29 PM PDT 24 Apr 28 03:37:31 PM PDT 24 547950222 ps
T1302 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.642685616 Apr 28 03:37:35 PM PDT 24 Apr 28 03:37:48 PM PDT 24 1688998651 ps
T1303 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2979810166 Apr 28 03:37:51 PM PDT 24 Apr 28 03:37:53 PM PDT 24 579198258 ps
T1304 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1135104706 Apr 28 03:37:35 PM PDT 24 Apr 28 03:37:39 PM PDT 24 143016393 ps
T1305 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.909865783 Apr 28 03:37:35 PM PDT 24 Apr 28 03:37:40 PM PDT 24 103623667 ps
T1306 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.4012560847 Apr 28 03:37:28 PM PDT 24 Apr 28 03:37:30 PM PDT 24 122816447 ps
T1307 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.1799724472 Apr 28 03:37:49 PM PDT 24 Apr 28 03:37:51 PM PDT 24 72697237 ps
T1308 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.3115303108 Apr 28 03:37:49 PM PDT 24 Apr 28 03:37:51 PM PDT 24 71395088 ps
T1309 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1282069338 Apr 28 03:37:40 PM PDT 24 Apr 28 03:37:53 PM PDT 24 9698332499 ps
T1310 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2795459212 Apr 28 03:37:28 PM PDT 24 Apr 28 03:37:29 PM PDT 24 53794897 ps
T1311 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3395116472 Apr 28 03:37:41 PM PDT 24 Apr 28 03:37:44 PM PDT 24 79284389 ps
T1312 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1814218504 Apr 28 03:37:35 PM PDT 24 Apr 28 03:37:42 PM PDT 24 505560101 ps
T1313 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1280064196 Apr 28 03:37:33 PM PDT 24 Apr 28 03:37:36 PM PDT 24 155763630 ps
T1314 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.4044580414 Apr 28 03:37:41 PM PDT 24 Apr 28 03:37:43 PM PDT 24 97760179 ps
T1315 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3459561073 Apr 28 03:37:35 PM PDT 24 Apr 28 03:37:38 PM PDT 24 101297830 ps
T1316 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.559548736 Apr 28 03:37:33 PM PDT 24 Apr 28 03:37:36 PM PDT 24 81790504 ps
T314 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2964381772 Apr 28 03:37:28 PM PDT 24 Apr 28 03:37:32 PM PDT 24 59460176 ps
T1317 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1406098516 Apr 28 03:37:35 PM PDT 24 Apr 28 03:37:43 PM PDT 24 407752139 ps
T1318 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.2817708951 Apr 28 03:37:52 PM PDT 24 Apr 28 03:37:54 PM PDT 24 39399691 ps
T1319 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.69885951 Apr 28 03:37:47 PM PDT 24 Apr 28 03:37:49 PM PDT 24 150859007 ps
T355 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3613873471 Apr 28 03:37:47 PM PDT 24 Apr 28 03:38:10 PM PDT 24 2558067891 ps
T1320 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.4083934888 Apr 28 03:37:38 PM PDT 24 Apr 28 03:37:44 PM PDT 24 1582006937 ps
T315 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1160604205 Apr 28 03:37:41 PM PDT 24 Apr 28 03:37:44 PM PDT 24 90707008 ps
T1321 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.1251013326 Apr 28 03:37:48 PM PDT 24 Apr 28 03:37:50 PM PDT 24 52118817 ps
T1322 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3285169390 Apr 28 03:37:27 PM PDT 24 Apr 28 03:37:31 PM PDT 24 431383946 ps
T1323 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.267093063 Apr 28 03:37:35 PM PDT 24 Apr 28 03:37:46 PM PDT 24 1232496678 ps
T1324 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.599430283 Apr 28 03:37:41 PM PDT 24 Apr 28 03:37:45 PM PDT 24 244275062 ps

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.1132184073
Short name T6
Test name
Test status
Simulation time 3470701673 ps
CPU time 25.3 seconds
Started Apr 28 01:59:36 PM PDT 24
Finished Apr 28 02:00:02 PM PDT 24
Peak memory 241484 kb
Host smart-01086c83-1ba3-448e-931b-682674b41b16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132184073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.1132184073
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.219575577
Short name T16
Test name
Test status
Simulation time 48837307507 ps
CPU time 288.23 seconds
Started Apr 28 02:01:31 PM PDT 24
Finished Apr 28 02:06:20 PM PDT 24
Peak memory 289568 kb
Host smart-6fbb70d9-63c8-408b-80d2-bc77cb696c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219575577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.
219575577
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.1505637222
Short name T8
Test name
Test status
Simulation time 38129495335 ps
CPU time 1029.78 seconds
Started Apr 28 02:00:16 PM PDT 24
Finished Apr 28 02:17:26 PM PDT 24
Peak memory 439732 kb
Host smart-101b49fd-2b39-49dd-a837-3c58fb59de63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505637222 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.1505637222
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.676806703
Short name T141
Test name
Test status
Simulation time 30227043728 ps
CPU time 271.54 seconds
Started Apr 28 01:58:30 PM PDT 24
Finished Apr 28 02:03:02 PM PDT 24
Peak memory 270472 kb
Host smart-29ad9547-38d3-43b2-976b-fc56d6487c3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676806703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.
676806703
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.2378872099
Short name T25
Test name
Test status
Simulation time 182489218968 ps
CPU time 253.74 seconds
Started Apr 28 01:57:27 PM PDT 24
Finished Apr 28 02:01:41 PM PDT 24
Peak memory 277012 kb
Host smart-8c855ac5-13e3-4136-a8c5-ddf98f99f2e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378872099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.2378872099
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.2162387310
Short name T160
Test name
Test status
Simulation time 117110962 ps
CPU time 3.16 seconds
Started Apr 28 02:05:21 PM PDT 24
Finished Apr 28 02:05:24 PM PDT 24
Peak memory 241712 kb
Host smart-7cf59cc8-a484-4ae4-a210-4a4f1538ee64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162387310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.2162387310
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.3758571050
Short name T65
Test name
Test status
Simulation time 1070548844 ps
CPU time 23.94 seconds
Started Apr 28 01:59:45 PM PDT 24
Finished Apr 28 02:00:10 PM PDT 24
Peak memory 247996 kb
Host smart-478de01e-0e17-4e59-aadf-c3eac1747b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758571050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.3758571050
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.1950103971
Short name T11
Test name
Test status
Simulation time 458018344 ps
CPU time 3.95 seconds
Started Apr 28 02:06:42 PM PDT 24
Finished Apr 28 02:06:46 PM PDT 24
Peak memory 241484 kb
Host smart-afe6fc52-101c-4d6d-9f26-d7e1992bb871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950103971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.1950103971
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.3056575173
Short name T173
Test name
Test status
Simulation time 37517672830 ps
CPU time 164.79 seconds
Started Apr 28 02:03:08 PM PDT 24
Finished Apr 28 02:05:54 PM PDT 24
Peak memory 264340 kb
Host smart-40ee57e4-93f5-44d5-b379-ff3dc2c5901f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056575173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.3056575173
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.3438067664
Short name T53
Test name
Test status
Simulation time 329853598 ps
CPU time 4.23 seconds
Started Apr 28 02:04:25 PM PDT 24
Finished Apr 28 02:04:30 PM PDT 24
Peak memory 241440 kb
Host smart-734323b6-d678-4c40-be7c-7330d3a5a3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438067664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.3438067664
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.1558698125
Short name T135
Test name
Test status
Simulation time 109091390212 ps
CPU time 389.65 seconds
Started Apr 28 02:01:09 PM PDT 24
Finished Apr 28 02:07:40 PM PDT 24
Peak memory 273724 kb
Host smart-89628c3c-34f0-4bf7-9e83-586b77ac291f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558698125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.1558698125
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1411793133
Short name T268
Test name
Test status
Simulation time 4587289833 ps
CPU time 18.33 seconds
Started Apr 28 03:37:32 PM PDT 24
Finished Apr 28 03:37:51 PM PDT 24
Peak memory 244308 kb
Host smart-5e57583b-ccda-474f-88a1-4a0a113271e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411793133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.1411793133
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.1137845996
Short name T22
Test name
Test status
Simulation time 604129907900 ps
CPU time 1059.88 seconds
Started Apr 28 01:56:52 PM PDT 24
Finished Apr 28 02:14:33 PM PDT 24
Peak memory 272780 kb
Host smart-9fd83a75-150f-4c56-a126-a268393b5908
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137845996 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.1137845996
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.3073943604
Short name T38
Test name
Test status
Simulation time 219699553 ps
CPU time 4.14 seconds
Started Apr 28 02:06:22 PM PDT 24
Finished Apr 28 02:06:27 PM PDT 24
Peak memory 241556 kb
Host smart-1941d30e-405d-4d50-aafc-a413c5cbaa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073943604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.3073943604
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.1269277931
Short name T119
Test name
Test status
Simulation time 20577958082 ps
CPU time 146 seconds
Started Apr 28 01:58:44 PM PDT 24
Finished Apr 28 02:01:11 PM PDT 24
Peak memory 273788 kb
Host smart-7ef8ffb2-1706-4169-82e3-42a5d5866207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269277931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.1269277931
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.4292909546
Short name T122
Test name
Test status
Simulation time 6084526609 ps
CPU time 120.31 seconds
Started Apr 28 01:58:55 PM PDT 24
Finished Apr 28 02:00:55 PM PDT 24
Peak memory 244448 kb
Host smart-f37b724b-4274-40bd-9415-44d4706e6184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292909546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.4292909546
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.4096958056
Short name T44
Test name
Test status
Simulation time 487203122 ps
CPU time 3.45 seconds
Started Apr 28 01:57:27 PM PDT 24
Finished Apr 28 01:57:31 PM PDT 24
Peak memory 241400 kb
Host smart-8b802657-46a3-40ed-ac66-819569255e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096958056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.4096958056
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.725733930
Short name T243
Test name
Test status
Simulation time 59108115960 ps
CPU time 516.56 seconds
Started Apr 28 02:01:45 PM PDT 24
Finished Apr 28 02:10:22 PM PDT 24
Peak memory 264252 kb
Host smart-2264ba3d-7620-4ecb-a747-f860b1d58c48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725733930 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.725733930
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.4071799666
Short name T154
Test name
Test status
Simulation time 14743256188 ps
CPU time 31.5 seconds
Started Apr 28 02:01:56 PM PDT 24
Finished Apr 28 02:02:28 PM PDT 24
Peak memory 250652 kb
Host smart-4d3976ed-8e78-4703-b66a-e420ec7b75b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071799666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.4071799666
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.4086301867
Short name T4
Test name
Test status
Simulation time 1879666498004 ps
CPU time 3024.16 seconds
Started Apr 28 01:57:05 PM PDT 24
Finished Apr 28 02:47:30 PM PDT 24
Peak memory 299288 kb
Host smart-b6405597-c2c3-4226-bc20-abce60b86c07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086301867 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.4086301867
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.2576994434
Short name T56
Test name
Test status
Simulation time 465875022 ps
CPU time 5.54 seconds
Started Apr 28 02:06:09 PM PDT 24
Finished Apr 28 02:06:15 PM PDT 24
Peak memory 241400 kb
Host smart-7286acd3-0bf7-4c79-a975-9eca4fd60f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576994434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.2576994434
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.1692578478
Short name T87
Test name
Test status
Simulation time 432262831 ps
CPU time 3.94 seconds
Started Apr 28 02:03:14 PM PDT 24
Finished Apr 28 02:03:18 PM PDT 24
Peak memory 241324 kb
Host smart-93960703-dc21-4c50-92be-245c43928cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692578478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1692578478
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.3378655657
Short name T32
Test name
Test status
Simulation time 3685451993 ps
CPU time 23.4 seconds
Started Apr 28 01:58:33 PM PDT 24
Finished Apr 28 01:58:56 PM PDT 24
Peak memory 242092 kb
Host smart-41cced5e-0b98-4761-a749-8c005b82fd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378655657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.3378655657
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.2131985853
Short name T67
Test name
Test status
Simulation time 2389019389 ps
CPU time 5.3 seconds
Started Apr 28 02:04:48 PM PDT 24
Finished Apr 28 02:04:53 PM PDT 24
Peak memory 241416 kb
Host smart-f525c8c1-6947-440f-956b-d4ac6858c58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131985853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2131985853
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.1550359465
Short name T138
Test name
Test status
Simulation time 272749177591 ps
CPU time 1724.27 seconds
Started Apr 28 01:58:24 PM PDT 24
Finished Apr 28 02:27:09 PM PDT 24
Peak memory 371128 kb
Host smart-4bea48c8-fa5b-45c9-b85b-672fb50a0142
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550359465 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.1550359465
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.3293535498
Short name T170
Test name
Test status
Simulation time 90825405 ps
CPU time 3.56 seconds
Started Apr 28 02:06:26 PM PDT 24
Finished Apr 28 02:06:30 PM PDT 24
Peak memory 241320 kb
Host smart-18ea40d1-c521-44bc-b3b6-15938acc9837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293535498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.3293535498
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.3221446817
Short name T29
Test name
Test status
Simulation time 2482730656 ps
CPU time 6.19 seconds
Started Apr 28 02:00:13 PM PDT 24
Finished Apr 28 02:00:20 PM PDT 24
Peak memory 241880 kb
Host smart-4b5899d4-2916-4676-b042-30d06fc1cb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221446817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.3221446817
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.4242893722
Short name T35
Test name
Test status
Simulation time 205730869 ps
CPU time 4.75 seconds
Started Apr 28 02:06:17 PM PDT 24
Finished Apr 28 02:06:22 PM PDT 24
Peak memory 241248 kb
Host smart-d65a12ea-dedc-47b7-a895-c8e4e1a646c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242893722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.4242893722
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.4049256950
Short name T379
Test name
Test status
Simulation time 16851584468 ps
CPU time 113.2 seconds
Started Apr 28 02:03:09 PM PDT 24
Finished Apr 28 02:05:03 PM PDT 24
Peak memory 258632 kb
Host smart-b819027c-0b3e-4fa8-b740-8994990dda36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049256950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.4049256950
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.971977832
Short name T17
Test name
Test status
Simulation time 132114087 ps
CPU time 2.01 seconds
Started Apr 28 01:57:15 PM PDT 24
Finished Apr 28 01:57:17 PM PDT 24
Peak memory 240016 kb
Host smart-f8d2f591-5e61-489f-8089-1a4db205b0af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971977832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.971977832
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.1700324813
Short name T219
Test name
Test status
Simulation time 381997441 ps
CPU time 3.67 seconds
Started Apr 28 02:01:05 PM PDT 24
Finished Apr 28 02:01:09 PM PDT 24
Peak memory 241260 kb
Host smart-03b17ef9-0634-4f35-87d8-427ebcfa4d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700324813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.1700324813
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.3558156917
Short name T42
Test name
Test status
Simulation time 1050130454 ps
CPU time 25.7 seconds
Started Apr 28 02:01:09 PM PDT 24
Finished Apr 28 02:01:35 PM PDT 24
Peak memory 242012 kb
Host smart-57448d8e-8807-424a-9127-99dc02da8358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558156917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.3558156917
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.4264904256
Short name T256
Test name
Test status
Simulation time 30124208477 ps
CPU time 368.1 seconds
Started Apr 28 02:02:01 PM PDT 24
Finished Apr 28 02:08:10 PM PDT 24
Peak memory 296296 kb
Host smart-ae11cb34-9e53-41b3-ba93-6b762ef831a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264904256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.4264904256
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2920598586
Short name T310
Test name
Test status
Simulation time 382564508 ps
CPU time 7.04 seconds
Started Apr 28 03:37:33 PM PDT 24
Finished Apr 28 03:37:41 PM PDT 24
Peak memory 237684 kb
Host smart-379e1cd7-1484-4d76-bb56-7ea8b2f32156
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920598586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.2920598586
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.3146874092
Short name T50
Test name
Test status
Simulation time 111207049 ps
CPU time 4.56 seconds
Started Apr 28 02:05:20 PM PDT 24
Finished Apr 28 02:05:25 PM PDT 24
Peak memory 241412 kb
Host smart-72f4d4ea-2d32-42e1-aeff-2f6bf61474d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146874092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.3146874092
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.3556173082
Short name T169
Test name
Test status
Simulation time 926241159 ps
CPU time 17.06 seconds
Started Apr 28 02:01:20 PM PDT 24
Finished Apr 28 02:01:37 PM PDT 24
Peak memory 241752 kb
Host smart-d0203540-11b8-4964-8778-21b952ba913d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556173082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3556173082
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.1660134895
Short name T14
Test name
Test status
Simulation time 1290711166872 ps
CPU time 2309.42 seconds
Started Apr 28 01:57:50 PM PDT 24
Finished Apr 28 02:36:20 PM PDT 24
Peak memory 464704 kb
Host smart-a0154dee-32fe-428c-ba2c-dbe9e9b4703f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660134895 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.1660134895
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.2637039647
Short name T234
Test name
Test status
Simulation time 146695025 ps
CPU time 5.25 seconds
Started Apr 28 02:00:56 PM PDT 24
Finished Apr 28 02:01:02 PM PDT 24
Peak memory 247596 kb
Host smart-a3073c86-d6d0-4dce-b691-397ee3571987
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637039647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2637039647
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.640779696
Short name T75
Test name
Test status
Simulation time 705284750 ps
CPU time 19.62 seconds
Started Apr 28 01:58:07 PM PDT 24
Finished Apr 28 01:58:27 PM PDT 24
Peak memory 241392 kb
Host smart-50440eda-e1eb-49e8-8cf5-da5ef0703f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640779696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.640779696
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.1551463731
Short name T457
Test name
Test status
Simulation time 224803988 ps
CPU time 5.03 seconds
Started Apr 28 01:58:02 PM PDT 24
Finished Apr 28 01:58:07 PM PDT 24
Peak memory 241280 kb
Host smart-2864fff3-28af-43c5-ac28-a85ce8a393c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551463731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.1551463731
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.2767686322
Short name T247
Test name
Test status
Simulation time 164267336 ps
CPU time 4.67 seconds
Started Apr 28 02:03:59 PM PDT 24
Finished Apr 28 02:04:04 PM PDT 24
Peak memory 241676 kb
Host smart-5ec1bf9d-ceb4-4acb-996d-61acc9ac80c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767686322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.2767686322
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.1456913533
Short name T359
Test name
Test status
Simulation time 2469359336 ps
CPU time 21.5 seconds
Started Apr 28 03:37:37 PM PDT 24
Finished Apr 28 03:38:01 PM PDT 24
Peak memory 245680 kb
Host smart-663d0530-0e47-4aed-9487-f33662f5ae3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456913533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.1456913533
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.1487242062
Short name T363
Test name
Test status
Simulation time 645626454 ps
CPU time 9.06 seconds
Started Apr 28 01:58:12 PM PDT 24
Finished Apr 28 01:58:22 PM PDT 24
Peak memory 241264 kb
Host smart-b2ef1754-7a72-474d-95a9-b4a496300f28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1487242062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.1487242062
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.1637293745
Short name T62
Test name
Test status
Simulation time 7151203404 ps
CPU time 16.74 seconds
Started Apr 28 01:58:42 PM PDT 24
Finished Apr 28 01:58:59 PM PDT 24
Peak memory 242920 kb
Host smart-53843c76-a4c5-4888-a540-112752b168a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637293745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.1637293745
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.4128598088
Short name T45
Test name
Test status
Simulation time 196921732 ps
CPU time 4.79 seconds
Started Apr 28 02:00:51 PM PDT 24
Finished Apr 28 02:00:56 PM PDT 24
Peak memory 241424 kb
Host smart-09d8ff32-87c9-459a-ac08-cdccd79cd185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128598088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.4128598088
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.3014328506
Short name T948
Test name
Test status
Simulation time 485106322 ps
CPU time 11.54 seconds
Started Apr 28 02:04:39 PM PDT 24
Finished Apr 28 02:04:50 PM PDT 24
Peak memory 241332 kb
Host smart-dfb3d198-1611-4bc0-958c-3b5a1736dcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014328506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.3014328506
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.2699857647
Short name T148
Test name
Test status
Simulation time 149122694 ps
CPU time 5.63 seconds
Started Apr 28 02:04:49 PM PDT 24
Finished Apr 28 02:04:55 PM PDT 24
Peak memory 241208 kb
Host smart-30e5a7e2-1779-47a0-ba4e-fdd906d6e6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699857647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.2699857647
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.2993620124
Short name T1082
Test name
Test status
Simulation time 97460668 ps
CPU time 3.78 seconds
Started Apr 28 02:05:15 PM PDT 24
Finished Apr 28 02:05:19 PM PDT 24
Peak memory 241196 kb
Host smart-ca71ca9e-7f5f-44d8-ae7f-960a40e84c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993620124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.2993620124
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.3592470374
Short name T78
Test name
Test status
Simulation time 655191877 ps
CPU time 4.57 seconds
Started Apr 28 02:05:18 PM PDT 24
Finished Apr 28 02:05:23 PM PDT 24
Peak memory 241592 kb
Host smart-3a24d8ba-d9c4-4826-b608-89286281a456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592470374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.3592470374
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.935816594
Short name T208
Test name
Test status
Simulation time 1257126052 ps
CPU time 8.73 seconds
Started Apr 28 02:05:25 PM PDT 24
Finished Apr 28 02:05:34 PM PDT 24
Peak memory 241400 kb
Host smart-4cb379d4-2608-4bcf-9e0c-2ec96477267c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935816594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.935816594
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.2317435213
Short name T76
Test name
Test status
Simulation time 1077410923 ps
CPU time 17.03 seconds
Started Apr 28 02:05:31 PM PDT 24
Finished Apr 28 02:05:49 PM PDT 24
Peak memory 241076 kb
Host smart-e0a25d1e-ad04-4276-92fb-8b47eac3c97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317435213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.2317435213
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.499361735
Short name T121
Test name
Test status
Simulation time 314289241 ps
CPU time 7.88 seconds
Started Apr 28 02:05:31 PM PDT 24
Finished Apr 28 02:05:39 PM PDT 24
Peak memory 241592 kb
Host smart-855431e8-3cd0-4030-ae0a-ba207a31a427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499361735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.499361735
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.2993218165
Short name T151
Test name
Test status
Simulation time 513894903 ps
CPU time 15.93 seconds
Started Apr 28 01:57:11 PM PDT 24
Finished Apr 28 01:57:27 PM PDT 24
Peak memory 241424 kb
Host smart-6457dac3-e864-4485-a497-9f44b5c68dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993218165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2993218165
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.1229636274
Short name T139
Test name
Test status
Simulation time 5101886202 ps
CPU time 34.14 seconds
Started Apr 28 02:00:33 PM PDT 24
Finished Apr 28 02:01:08 PM PDT 24
Peak memory 242820 kb
Host smart-8f034dfa-84ea-450b-909c-d878ed51fae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229636274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.1229636274
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.225962742
Short name T129
Test name
Test status
Simulation time 396611565 ps
CPU time 9.9 seconds
Started Apr 28 02:01:44 PM PDT 24
Finished Apr 28 02:01:54 PM PDT 24
Peak memory 241504 kb
Host smart-addb1788-357a-4f4d-b8dd-9ad94942fd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225962742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.225962742
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.4215713339
Short name T128
Test name
Test status
Simulation time 461617615 ps
CPU time 6.01 seconds
Started Apr 28 02:04:02 PM PDT 24
Finished Apr 28 02:04:08 PM PDT 24
Peak memory 241192 kb
Host smart-92341ebd-d70c-425b-9285-7aa61f125c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215713339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.4215713339
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.3256256622
Short name T163
Test name
Test status
Simulation time 106373737 ps
CPU time 4.07 seconds
Started Apr 28 02:04:52 PM PDT 24
Finished Apr 28 02:04:57 PM PDT 24
Peak memory 241380 kb
Host smart-7e517e26-a4f7-423d-91a8-ecf3ec47b0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256256622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.3256256622
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.4179880977
Short name T592
Test name
Test status
Simulation time 66264523886 ps
CPU time 233.55 seconds
Started Apr 28 01:59:36 PM PDT 24
Finished Apr 28 02:03:31 PM PDT 24
Peak memory 256424 kb
Host smart-ea6e4704-7403-4424-9a23-5107a332e768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179880977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.4179880977
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.196829142
Short name T88
Test name
Test status
Simulation time 2081697942 ps
CPU time 42.59 seconds
Started Apr 28 02:00:29 PM PDT 24
Finished Apr 28 02:01:12 PM PDT 24
Peak memory 245344 kb
Host smart-2cedd985-a134-4655-865b-fda1a39f9b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196829142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.196829142
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.3562063804
Short name T261
Test name
Test status
Simulation time 455792463 ps
CPU time 3.71 seconds
Started Apr 28 02:04:58 PM PDT 24
Finished Apr 28 02:05:02 PM PDT 24
Peak memory 241388 kb
Host smart-d4980383-dc47-440f-9eb7-eb6c2e772148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562063804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.3562063804
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.1892412249
Short name T47
Test name
Test status
Simulation time 8036106356 ps
CPU time 28.35 seconds
Started Apr 28 01:59:38 PM PDT 24
Finished Apr 28 02:00:07 PM PDT 24
Peak memory 244532 kb
Host smart-ba92c56e-cf2a-4131-b737-5b98cd095e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892412249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.1892412249
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3063839563
Short name T361
Test name
Test status
Simulation time 2494815423 ps
CPU time 21.52 seconds
Started Apr 28 03:37:40 PM PDT 24
Finished Apr 28 03:38:02 PM PDT 24
Peak memory 239152 kb
Host smart-fd788f9e-69c6-4c5c-8b8e-2534c5edffb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063839563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.3063839563
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.1292538152
Short name T994
Test name
Test status
Simulation time 438005853 ps
CPU time 13.27 seconds
Started Apr 28 01:58:46 PM PDT 24
Finished Apr 28 01:58:59 PM PDT 24
Peak memory 241328 kb
Host smart-eed8b40a-40c2-4a2e-879d-c4c1b01946b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292538152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.1292538152
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.511962661
Short name T384
Test name
Test status
Simulation time 17908461773 ps
CPU time 100.45 seconds
Started Apr 28 01:59:44 PM PDT 24
Finished Apr 28 02:01:25 PM PDT 24
Peak memory 252564 kb
Host smart-a21596d1-57c8-47a8-ab2c-a95e02e3400a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511962661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.
511962661
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1099594897
Short name T327
Test name
Test status
Simulation time 243705751 ps
CPU time 3.87 seconds
Started Apr 28 03:37:30 PM PDT 24
Finished Apr 28 03:37:34 PM PDT 24
Peak memory 238860 kb
Host smart-3c82e931-7446-465e-9050-023b436f7ea7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099594897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.1099594897
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.438489464
Short name T206
Test name
Test status
Simulation time 8454986278 ps
CPU time 21.34 seconds
Started Apr 28 02:02:20 PM PDT 24
Finished Apr 28 02:02:42 PM PDT 24
Peak memory 241756 kb
Host smart-cbd5659e-8cc4-4b8e-9917-8268ab368698
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438489464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.438489464
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.1071142383
Short name T1067
Test name
Test status
Simulation time 1483193057 ps
CPU time 17.89 seconds
Started Apr 28 02:00:00 PM PDT 24
Finished Apr 28 02:00:19 PM PDT 24
Peak memory 247976 kb
Host smart-32b554a5-34a8-47dd-94aa-d984d43d3cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071142383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1071142383
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2033987844
Short name T271
Test name
Test status
Simulation time 1252229477 ps
CPU time 10.74 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:48 PM PDT 24
Peak memory 244064 kb
Host smart-d679a15c-984f-44c8-a6af-bb68b35f9a49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033987844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.2033987844
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.3555900939
Short name T284
Test name
Test status
Simulation time 2439776486560 ps
CPU time 3709.24 seconds
Started Apr 28 02:03:52 PM PDT 24
Finished Apr 28 03:05:42 PM PDT 24
Peak memory 575924 kb
Host smart-e0136183-9eda-4795-9c70-feddd2d8968f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555900939 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.3555900939
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.3409760150
Short name T567
Test name
Test status
Simulation time 202056863 ps
CPU time 4.39 seconds
Started Apr 28 01:56:56 PM PDT 24
Finished Apr 28 01:57:01 PM PDT 24
Peak memory 241284 kb
Host smart-289d187e-e77f-4f9d-9f11-7bb89bb16b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409760150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.3409760150
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.3843951557
Short name T765
Test name
Test status
Simulation time 1664120706 ps
CPU time 5.29 seconds
Started Apr 28 02:04:55 PM PDT 24
Finished Apr 28 02:05:01 PM PDT 24
Peak memory 241368 kb
Host smart-48d1701e-c0c8-4577-a073-3f857ae200a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843951557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.3843951557
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2465876173
Short name T353
Test name
Test status
Simulation time 2307593714 ps
CPU time 25.46 seconds
Started Apr 28 03:37:45 PM PDT 24
Finished Apr 28 03:38:11 PM PDT 24
Peak memory 239136 kb
Host smart-221a47c1-3ccd-4860-ada1-ad55f046cd06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465876173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.2465876173
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.737461774
Short name T356
Test name
Test status
Simulation time 1324802543 ps
CPU time 21.25 seconds
Started Apr 28 03:37:37 PM PDT 24
Finished Apr 28 03:38:00 PM PDT 24
Peak memory 239144 kb
Host smart-c9986d67-3e26-412a-b674-594a4c3fc081
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737461774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_int
g_err.737461774
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.749359381
Short name T366
Test name
Test status
Simulation time 269087179 ps
CPU time 10.2 seconds
Started Apr 28 01:56:54 PM PDT 24
Finished Apr 28 01:57:05 PM PDT 24
Peak memory 241232 kb
Host smart-b209e54d-4773-416a-a35d-ef552b8e559c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=749359381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.749359381
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.3007301603
Short name T258
Test name
Test status
Simulation time 3286310979 ps
CPU time 23.38 seconds
Started Apr 28 02:01:40 PM PDT 24
Finished Apr 28 02:02:04 PM PDT 24
Peak memory 241360 kb
Host smart-976ab43d-0903-45e0-81b4-3ec283edbdd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3007301603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.3007301603
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.2855843463
Short name T272
Test name
Test status
Simulation time 996851464 ps
CPU time 10.46 seconds
Started Apr 28 03:37:46 PM PDT 24
Finished Apr 28 03:37:57 PM PDT 24
Peak memory 243920 kb
Host smart-9c464d59-a7ef-412e-98fb-abb6037490b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855843463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.2855843463
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.39089365
Short name T267
Test name
Test status
Simulation time 2667607787 ps
CPU time 20.29 seconds
Started Apr 28 03:37:29 PM PDT 24
Finished Apr 28 03:37:50 PM PDT 24
Peak memory 239172 kb
Host smart-53dba0a0-2c7f-4e4e-802f-0ac34120c19e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39089365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg
_err.39089365
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.3541327508
Short name T132
Test name
Test status
Simulation time 95006718 ps
CPU time 3.41 seconds
Started Apr 28 02:06:41 PM PDT 24
Finished Apr 28 02:06:45 PM PDT 24
Peak memory 241328 kb
Host smart-c91ae4c3-6eac-4891-b199-b1ed2593f740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541327508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3541327508
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.3495718360
Short name T205
Test name
Test status
Simulation time 20391839370 ps
CPU time 109.6 seconds
Started Apr 28 01:56:52 PM PDT 24
Finished Apr 28 01:58:42 PM PDT 24
Peak memory 247344 kb
Host smart-14ffa354-1437-4e6f-81a9-e30eeeaccb79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495718360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
3495718360
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.1551629317
Short name T454
Test name
Test status
Simulation time 20198596001 ps
CPU time 42.97 seconds
Started Apr 28 01:58:38 PM PDT 24
Finished Apr 28 01:59:22 PM PDT 24
Peak memory 243100 kb
Host smart-b2b942b1-b75c-481d-addc-75155db2b85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551629317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1551629317
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.122282702
Short name T928
Test name
Test status
Simulation time 1194203772 ps
CPU time 22.84 seconds
Started Apr 28 02:00:25 PM PDT 24
Finished Apr 28 02:00:48 PM PDT 24
Peak memory 241632 kb
Host smart-ba348777-6d01-4af4-890b-aa90ea9435a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122282702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.122282702
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.2730817331
Short name T387
Test name
Test status
Simulation time 5750080008 ps
CPU time 33.83 seconds
Started Apr 28 02:00:38 PM PDT 24
Finished Apr 28 02:01:12 PM PDT 24
Peak memory 241472 kb
Host smart-31c96791-84cc-4a73-9e30-51945f8f4ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730817331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.2730817331
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.1044829303
Short name T664
Test name
Test status
Simulation time 10759122641 ps
CPU time 304.67 seconds
Started Apr 28 02:03:58 PM PDT 24
Finished Apr 28 02:09:03 PM PDT 24
Peak memory 272968 kb
Host smart-7e8d22ee-7379-49ad-a97c-807efbb95b0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044829303 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.1044829303
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.940709828
Short name T91
Test name
Test status
Simulation time 462806243 ps
CPU time 3.95 seconds
Started Apr 28 02:06:33 PM PDT 24
Finished Apr 28 02:06:38 PM PDT 24
Peak memory 241732 kb
Host smart-2fb0c652-98f6-4261-8ef7-e53c40c23a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940709828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.940709828
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.2928431795
Short name T368
Test name
Test status
Simulation time 219591443 ps
CPU time 7.76 seconds
Started Apr 28 01:57:01 PM PDT 24
Finished Apr 28 01:57:10 PM PDT 24
Peak memory 241628 kb
Host smart-d7a0cbdb-621d-48a7-900d-27abe17571ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928431795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.2928431795
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.4109240004
Short name T1215
Test name
Test status
Simulation time 771912162 ps
CPU time 9.65 seconds
Started Apr 28 03:37:30 PM PDT 24
Finished Apr 28 03:37:40 PM PDT 24
Peak memory 238024 kb
Host smart-6cd70f32-987c-4c5f-a1c2-27cccd2441d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109240004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.4109240004
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.643504213
Short name T308
Test name
Test status
Simulation time 245413271 ps
CPU time 1.78 seconds
Started Apr 28 03:37:27 PM PDT 24
Finished Apr 28 03:37:29 PM PDT 24
Peak memory 239112 kb
Host smart-e298c35b-cd75-4f86-911d-bca62315f569
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643504213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_re
set.643504213
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3285169390
Short name T1322
Test name
Test status
Simulation time 431383946 ps
CPU time 3.45 seconds
Started Apr 28 03:37:27 PM PDT 24
Finished Apr 28 03:37:31 PM PDT 24
Peak memory 247348 kb
Host smart-e056f9c8-fe12-47a5-a299-c461e2713d09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285169390 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.3285169390
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.4012560847
Short name T1306
Test name
Test status
Simulation time 122816447 ps
CPU time 1.56 seconds
Started Apr 28 03:37:28 PM PDT 24
Finished Apr 28 03:37:30 PM PDT 24
Peak memory 240052 kb
Host smart-1a1a2a40-2b8c-4f67-93a0-2518a98b9eca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012560847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.4012560847
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.526641271
Short name T1242
Test name
Test status
Simulation time 537179037 ps
CPU time 2.07 seconds
Started Apr 28 03:37:29 PM PDT 24
Finished Apr 28 03:37:32 PM PDT 24
Peak memory 229628 kb
Host smart-718999bb-06d2-4909-9d06-5b692cd7feb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526641271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.526641271
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2127939692
Short name T1259
Test name
Test status
Simulation time 502589385 ps
CPU time 1.63 seconds
Started Apr 28 03:37:30 PM PDT 24
Finished Apr 28 03:37:32 PM PDT 24
Peak memory 230560 kb
Host smart-15c05159-466c-4ad6-8ce7-3ae4a95fb609
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127939692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.2127939692
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1685325620
Short name T1197
Test name
Test status
Simulation time 517452767 ps
CPU time 1.4 seconds
Started Apr 28 03:37:30 PM PDT 24
Finished Apr 28 03:37:32 PM PDT 24
Peak memory 230824 kb
Host smart-f0e02f92-8919-4823-8ece-7c35252fda79
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685325620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.1685325620
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.404737216
Short name T1192
Test name
Test status
Simulation time 433167362 ps
CPU time 4.18 seconds
Started Apr 28 03:37:30 PM PDT 24
Finished Apr 28 03:37:35 PM PDT 24
Peak memory 246580 kb
Host smart-559635b3-8ab1-4009-a257-9058a6ce6307
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404737216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.404737216
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2146926717
Short name T358
Test name
Test status
Simulation time 732900143 ps
CPU time 10.5 seconds
Started Apr 28 03:37:27 PM PDT 24
Finished Apr 28 03:37:38 PM PDT 24
Peak memory 243984 kb
Host smart-7c1a9bac-753e-489f-a667-7a364ed9418c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146926717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.2146926717
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.785699057
Short name T307
Test name
Test status
Simulation time 1198884030 ps
CPU time 6.46 seconds
Started Apr 28 03:37:37 PM PDT 24
Finished Apr 28 03:37:45 PM PDT 24
Peak memory 237864 kb
Host smart-b676f1ec-c174-4e0c-b596-d5a4f6e2bad1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785699057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alias
ing.785699057
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.485665687
Short name T1222
Test name
Test status
Simulation time 385650214 ps
CPU time 5.17 seconds
Started Apr 28 03:37:29 PM PDT 24
Finished Apr 28 03:37:35 PM PDT 24
Peak memory 239044 kb
Host smart-ca9a4cfa-f752-471d-9856-c94427de5aec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485665687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_b
ash.485665687
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3459561073
Short name T1315
Test name
Test status
Simulation time 101297830 ps
CPU time 2.29 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:38 PM PDT 24
Peak memory 238952 kb
Host smart-9afb1860-366d-4f9c-b935-3dd1e364837f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459561073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.3459561073
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.160074966
Short name T1217
Test name
Test status
Simulation time 276603101 ps
CPU time 3.64 seconds
Started Apr 28 03:37:30 PM PDT 24
Finished Apr 28 03:37:35 PM PDT 24
Peak memory 247344 kb
Host smart-aa013a74-f91c-4982-b0bd-4782307d8b01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160074966 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.160074966
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1822690627
Short name T1275
Test name
Test status
Simulation time 647332771 ps
CPU time 2.08 seconds
Started Apr 28 03:37:27 PM PDT 24
Finished Apr 28 03:37:29 PM PDT 24
Peak memory 240024 kb
Host smart-c6229d22-fab8-4d82-868d-b268adb69be4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822690627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1822690627
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1291423632
Short name T1233
Test name
Test status
Simulation time 75160307 ps
CPU time 1.36 seconds
Started Apr 28 03:37:31 PM PDT 24
Finished Apr 28 03:37:33 PM PDT 24
Peak memory 229940 kb
Host smart-eb79585f-83cc-4a6c-9684-4dd1c4ea1edd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291423632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.1291423632
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3309621399
Short name T1245
Test name
Test status
Simulation time 69988580 ps
CPU time 1.36 seconds
Started Apr 28 03:37:31 PM PDT 24
Finished Apr 28 03:37:34 PM PDT 24
Peak memory 229324 kb
Host smart-e6e8c3f3-aaf2-4115-baf2-83bf2838184c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309621399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.3309621399
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.123071383
Short name T1249
Test name
Test status
Simulation time 48025977 ps
CPU time 1.35 seconds
Started Apr 28 03:37:28 PM PDT 24
Finished Apr 28 03:37:30 PM PDT 24
Peak memory 229564 kb
Host smart-561e4ea9-7e40-4fde-a949-af1471fc22a4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123071383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.
123071383
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.3521174938
Short name T1256
Test name
Test status
Simulation time 318630078 ps
CPU time 3.03 seconds
Started Apr 28 03:37:28 PM PDT 24
Finished Apr 28 03:37:32 PM PDT 24
Peak memory 239180 kb
Host smart-066f71c6-5925-4475-8b0e-dc653a0787c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521174938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.3521174938
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3672712843
Short name T1284
Test name
Test status
Simulation time 89938537 ps
CPU time 5.5 seconds
Started Apr 28 03:37:27 PM PDT 24
Finished Apr 28 03:37:33 PM PDT 24
Peak memory 239052 kb
Host smart-75dde98a-3830-411b-82e3-55be383890ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672712843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.3672712843
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.4220876532
Short name T1237
Test name
Test status
Simulation time 9763579130 ps
CPU time 14.12 seconds
Started Apr 28 03:37:33 PM PDT 24
Finished Apr 28 03:37:48 PM PDT 24
Peak memory 239188 kb
Host smart-6a54ae15-ce3a-4bb8-be08-0a7e30183f2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220876532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.4220876532
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.4083934888
Short name T1320
Test name
Test status
Simulation time 1582006937 ps
CPU time 3.7 seconds
Started Apr 28 03:37:38 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 247332 kb
Host smart-0aadf34c-03a2-4a85-ac6e-1d55e14b28ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083934888 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.4083934888
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.994707533
Short name T1228
Test name
Test status
Simulation time 41706272 ps
CPU time 1.54 seconds
Started Apr 28 03:37:42 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 239996 kb
Host smart-9e60de8a-ac96-4d12-beb0-d9f612f1bfd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994707533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.994707533
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3584273425
Short name T1241
Test name
Test status
Simulation time 140659320 ps
CPU time 1.66 seconds
Started Apr 28 03:37:39 PM PDT 24
Finished Apr 28 03:37:42 PM PDT 24
Peak memory 229604 kb
Host smart-ee22e27d-63db-4cd5-b1ea-27e40055c17a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584273425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.3584273425
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.909865783
Short name T1305
Test name
Test status
Simulation time 103623667 ps
CPU time 3.09 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:40 PM PDT 24
Peak memory 239008 kb
Host smart-edbe45f8-1d49-4522-ad06-b876ab1b3339
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909865783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_c
trl_same_csr_outstanding.909865783
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.2467508127
Short name T1201
Test name
Test status
Simulation time 86435833 ps
CPU time 3.44 seconds
Started Apr 28 03:37:37 PM PDT 24
Finished Apr 28 03:37:43 PM PDT 24
Peak memory 246476 kb
Host smart-b9e48534-fa26-4911-8710-2988458b9c96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467508127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.2467508127
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3621224276
Short name T266
Test name
Test status
Simulation time 669412115 ps
CPU time 10.46 seconds
Started Apr 28 03:37:41 PM PDT 24
Finished Apr 28 03:37:53 PM PDT 24
Peak memory 243348 kb
Host smart-cdd5121d-b027-4054-bd5d-c09b259c63a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621224276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.3621224276
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1556338361
Short name T273
Test name
Test status
Simulation time 132159202 ps
CPU time 2.59 seconds
Started Apr 28 03:37:39 PM PDT 24
Finished Apr 28 03:37:43 PM PDT 24
Peak memory 247216 kb
Host smart-09ea6790-7c69-42d9-ae14-7c053bd564eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556338361 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.1556338361
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3395116472
Short name T1311
Test name
Test status
Simulation time 79284389 ps
CPU time 1.63 seconds
Started Apr 28 03:37:41 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 239956 kb
Host smart-3ee8edfb-a470-4fbe-bd6d-4ef11c7da6c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395116472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.3395116472
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2033388545
Short name T1297
Test name
Test status
Simulation time 95280964 ps
CPU time 1.35 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:38 PM PDT 24
Peak memory 230872 kb
Host smart-11bd829d-f263-447c-8693-0c68246be2cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033388545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2033388545
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2732703147
Short name T1280
Test name
Test status
Simulation time 287062605 ps
CPU time 2.78 seconds
Started Apr 28 03:37:37 PM PDT 24
Finished Apr 28 03:37:42 PM PDT 24
Peak memory 238988 kb
Host smart-c5ec4428-a4dc-4bde-b369-4c0ad046f522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732703147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.2732703147
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2918402489
Short name T1206
Test name
Test status
Simulation time 487515996 ps
CPU time 4.72 seconds
Started Apr 28 03:37:38 PM PDT 24
Finished Apr 28 03:37:45 PM PDT 24
Peak memory 247228 kb
Host smart-fedd2ce3-599c-4ab0-b9c3-0bc3f228e545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918402489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.2918402489
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.941979227
Short name T1223
Test name
Test status
Simulation time 75605166 ps
CPU time 1.97 seconds
Started Apr 28 03:37:40 PM PDT 24
Finished Apr 28 03:37:43 PM PDT 24
Peak memory 239028 kb
Host smart-dc38d194-284d-4341-979a-1393ff9be8eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941979227 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.941979227
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.174214567
Short name T1232
Test name
Test status
Simulation time 44358719 ps
CPU time 2.04 seconds
Started Apr 28 03:37:38 PM PDT 24
Finished Apr 28 03:37:42 PM PDT 24
Peak memory 240496 kb
Host smart-4ae3d3ac-767a-4eab-ad06-ccf88d2b63f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174214567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.174214567
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.4197264417
Short name T1203
Test name
Test status
Simulation time 141666166 ps
CPU time 1.42 seconds
Started Apr 28 03:37:39 PM PDT 24
Finished Apr 28 03:37:42 PM PDT 24
Peak memory 229576 kb
Host smart-4d8bb7b8-6477-4976-a6e6-95c5f6e07c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197264417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.4197264417
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3580808628
Short name T325
Test name
Test status
Simulation time 192110455 ps
CPU time 3.19 seconds
Started Apr 28 03:37:36 PM PDT 24
Finished Apr 28 03:37:41 PM PDT 24
Peak memory 239120 kb
Host smart-6c8ca325-99f1-4869-84f5-fe513c6fcb63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580808628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.3580808628
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2122097642
Short name T1198
Test name
Test status
Simulation time 927862758 ps
CPU time 4.63 seconds
Started Apr 28 03:37:37 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 246936 kb
Host smart-82500b01-26f2-4668-b69c-90bd685df766
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122097642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2122097642
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.267093063
Short name T1323
Test name
Test status
Simulation time 1232496678 ps
CPU time 9.32 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:46 PM PDT 24
Peak memory 243168 kb
Host smart-4a5f91ca-bad9-4599-a821-c9e1be84f2bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267093063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_in
tg_err.267093063
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.512856507
Short name T1247
Test name
Test status
Simulation time 54954760 ps
CPU time 1.67 seconds
Started Apr 28 03:37:41 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 239080 kb
Host smart-f9647373-3d5f-4b4a-aca0-efd5e805c4e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512856507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.512856507
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1156938779
Short name T1260
Test name
Test status
Simulation time 42352513 ps
CPU time 1.44 seconds
Started Apr 28 03:37:42 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 229528 kb
Host smart-c3a6466d-b3e7-4a96-a7f4-f3bd920aed29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156938779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1156938779
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3606368629
Short name T1258
Test name
Test status
Simulation time 128453797 ps
CPU time 3.21 seconds
Started Apr 28 03:37:39 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 239044 kb
Host smart-894baa78-b171-4876-8261-f2b957466c75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606368629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.3606368629
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1814218504
Short name T1312
Test name
Test status
Simulation time 505560101 ps
CPU time 4.6 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:42 PM PDT 24
Peak memory 239016 kb
Host smart-40d7b460-6d16-4b80-a933-353422c3e75f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814218504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.1814218504
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1282069338
Short name T1309
Test name
Test status
Simulation time 9698332499 ps
CPU time 11.97 seconds
Started Apr 28 03:37:40 PM PDT 24
Finished Apr 28 03:37:53 PM PDT 24
Peak memory 243980 kb
Host smart-03de70ca-71f9-44e5-ad29-61ffbd349073
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282069338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.1282069338
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1725071525
Short name T1216
Test name
Test status
Simulation time 70311680 ps
CPU time 2.15 seconds
Started Apr 28 03:37:43 PM PDT 24
Finished Apr 28 03:37:46 PM PDT 24
Peak memory 243896 kb
Host smart-5ea27856-0c4e-4c3c-ba4d-ed1031b672f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725071525 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.1725071525
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1346122931
Short name T316
Test name
Test status
Simulation time 575228422 ps
CPU time 1.8 seconds
Started Apr 28 03:37:45 PM PDT 24
Finished Apr 28 03:37:47 PM PDT 24
Peak memory 240512 kb
Host smart-55562ce4-47be-4963-92b1-ae0fd5da00d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346122931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.1346122931
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.4044580414
Short name T1314
Test name
Test status
Simulation time 97760179 ps
CPU time 1.48 seconds
Started Apr 28 03:37:41 PM PDT 24
Finished Apr 28 03:37:43 PM PDT 24
Peak memory 229612 kb
Host smart-48b6ce33-9950-4001-9607-76a4e66cb686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044580414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.4044580414
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3556474655
Short name T1294
Test name
Test status
Simulation time 63700230 ps
CPU time 1.94 seconds
Started Apr 28 03:37:41 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 239096 kb
Host smart-a9ffd190-b40e-401e-a331-96ad3e802abd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556474655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.3556474655
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.57403052
Short name T1218
Test name
Test status
Simulation time 625822512 ps
CPU time 6.22 seconds
Started Apr 28 03:37:44 PM PDT 24
Finished Apr 28 03:37:50 PM PDT 24
Peak memory 239104 kb
Host smart-c61d9f7b-3143-41a4-82c2-4f6cbf0befef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57403052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.57403052
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2367152296
Short name T360
Test name
Test status
Simulation time 9752114647 ps
CPU time 14.34 seconds
Started Apr 28 03:37:41 PM PDT 24
Finished Apr 28 03:37:56 PM PDT 24
Peak memory 244680 kb
Host smart-0e1a3f4e-e61a-4630-a039-c4df8589004b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367152296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.2367152296
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1476932712
Short name T1205
Test name
Test status
Simulation time 136726409 ps
CPU time 2.86 seconds
Started Apr 28 03:37:39 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 247276 kb
Host smart-ea3511d1-22b4-4c6a-83c5-dc9dede838a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476932712 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.1476932712
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2883657360
Short name T1235
Test name
Test status
Simulation time 78396473 ps
CPU time 1.55 seconds
Started Apr 28 03:37:42 PM PDT 24
Finished Apr 28 03:37:45 PM PDT 24
Peak memory 239736 kb
Host smart-f8af58e0-173b-46e5-8b4d-a28c8fc45ed7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883657360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.2883657360
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1676123950
Short name T1271
Test name
Test status
Simulation time 584660893 ps
CPU time 1.66 seconds
Started Apr 28 03:37:47 PM PDT 24
Finished Apr 28 03:37:49 PM PDT 24
Peak memory 229592 kb
Host smart-c27bc808-2a7b-47a9-8207-949e91520402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676123950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.1676123950
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.599430283
Short name T1324
Test name
Test status
Simulation time 244275062 ps
CPU time 2.68 seconds
Started Apr 28 03:37:41 PM PDT 24
Finished Apr 28 03:37:45 PM PDT 24
Peak memory 237940 kb
Host smart-2601d121-b9d3-4120-92da-5acb03526f58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599430283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_c
trl_same_csr_outstanding.599430283
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1179693748
Short name T1267
Test name
Test status
Simulation time 62291582 ps
CPU time 3.28 seconds
Started Apr 28 03:37:40 PM PDT 24
Finished Apr 28 03:37:45 PM PDT 24
Peak memory 239112 kb
Host smart-31bbf834-719f-4bd8-bf27-8ec0c0377622
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179693748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1179693748
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1031630844
Short name T1290
Test name
Test status
Simulation time 413265232 ps
CPU time 3.29 seconds
Started Apr 28 03:37:42 PM PDT 24
Finished Apr 28 03:37:46 PM PDT 24
Peak memory 247252 kb
Host smart-d075e9ac-44bf-4d2e-aae8-0b2fd587b83f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031630844 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.1031630844
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1160604205
Short name T315
Test name
Test status
Simulation time 90707008 ps
CPU time 1.8 seconds
Started Apr 28 03:37:41 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 238940 kb
Host smart-fa284c84-d669-4a92-aac0-68047275eeac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160604205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.1160604205
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3434192310
Short name T1283
Test name
Test status
Simulation time 97533455 ps
CPU time 1.47 seconds
Started Apr 28 03:37:42 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 229812 kb
Host smart-f6537153-a635-4e59-9284-be5dfe68e164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434192310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3434192310
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.64717056
Short name T1291
Test name
Test status
Simulation time 117883255 ps
CPU time 3.3 seconds
Started Apr 28 03:37:41 PM PDT 24
Finished Apr 28 03:37:46 PM PDT 24
Peak memory 238120 kb
Host smart-2a24fbd7-591a-4def-9993-fc76ccede19a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64717056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ct
rl_same_csr_outstanding.64717056
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2449239451
Short name T1268
Test name
Test status
Simulation time 298589703 ps
CPU time 6.45 seconds
Started Apr 28 03:37:43 PM PDT 24
Finished Apr 28 03:37:50 PM PDT 24
Peak memory 246712 kb
Host smart-cae32933-1e7a-4b7f-a61f-ede82891b048
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449239451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.2449239451
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3910994531
Short name T1281
Test name
Test status
Simulation time 101762363 ps
CPU time 1.54 seconds
Started Apr 28 03:37:47 PM PDT 24
Finished Apr 28 03:37:49 PM PDT 24
Peak memory 240168 kb
Host smart-58bc5158-a9e0-4278-8605-681b78da6815
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910994531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3910994531
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2666850405
Short name T1236
Test name
Test status
Simulation time 138447497 ps
CPU time 1.48 seconds
Started Apr 28 03:37:45 PM PDT 24
Finished Apr 28 03:37:47 PM PDT 24
Peak memory 229840 kb
Host smart-7312854f-33cc-496b-8efc-524c4aa1a2ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666850405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.2666850405
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.911045425
Short name T324
Test name
Test status
Simulation time 138296717 ps
CPU time 3.41 seconds
Started Apr 28 03:37:46 PM PDT 24
Finished Apr 28 03:37:50 PM PDT 24
Peak memory 239004 kb
Host smart-9c9f8268-6482-4db7-bb04-86b6832053f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911045425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_c
trl_same_csr_outstanding.911045425
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1222495468
Short name T1274
Test name
Test status
Simulation time 447270936 ps
CPU time 4.22 seconds
Started Apr 28 03:37:42 PM PDT 24
Finished Apr 28 03:37:47 PM PDT 24
Peak memory 239040 kb
Host smart-96dd1e84-d777-4cea-bf18-e3c20c7a0bdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222495468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1222495468
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3230147914
Short name T1251
Test name
Test status
Simulation time 660738551 ps
CPU time 10.15 seconds
Started Apr 28 03:37:45 PM PDT 24
Finished Apr 28 03:37:56 PM PDT 24
Peak memory 239132 kb
Host smart-1c6146b8-eae1-4d4d-9924-ce74dd5eaa1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230147914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.3230147914
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2565834021
Short name T1234
Test name
Test status
Simulation time 1175250696 ps
CPU time 2.52 seconds
Started Apr 28 03:37:45 PM PDT 24
Finished Apr 28 03:37:48 PM PDT 24
Peak memory 245812 kb
Host smart-a64676e6-5e0e-4ee5-85a3-f87a224fa327
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565834021 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.2565834021
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1589274088
Short name T1221
Test name
Test status
Simulation time 663002601 ps
CPU time 2.3 seconds
Started Apr 28 03:37:47 PM PDT 24
Finished Apr 28 03:37:50 PM PDT 24
Peak memory 238948 kb
Host smart-a47ab0b3-d2a9-4ffa-bd4a-ee7a6a26207e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589274088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.1589274088
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.69885951
Short name T1319
Test name
Test status
Simulation time 150859007 ps
CPU time 1.38 seconds
Started Apr 28 03:37:47 PM PDT 24
Finished Apr 28 03:37:49 PM PDT 24
Peak memory 230864 kb
Host smart-a33f0346-3525-4c93-8c81-4a3777b3f2fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69885951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.69885951
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3383069800
Short name T1227
Test name
Test status
Simulation time 79588064 ps
CPU time 2.25 seconds
Started Apr 28 03:37:53 PM PDT 24
Finished Apr 28 03:37:56 PM PDT 24
Peak memory 238992 kb
Host smart-e79a3f87-ea4f-4ee4-b05b-8625086964d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383069800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.3383069800
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3578890189
Short name T1229
Test name
Test status
Simulation time 707854753 ps
CPU time 8.73 seconds
Started Apr 28 03:37:49 PM PDT 24
Finished Apr 28 03:37:58 PM PDT 24
Peak memory 246744 kb
Host smart-a005835f-c720-446f-9398-6d3b7a9b173d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578890189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.3578890189
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.4235108523
Short name T1257
Test name
Test status
Simulation time 1051239086 ps
CPU time 2.9 seconds
Started Apr 28 03:37:45 PM PDT 24
Finished Apr 28 03:37:48 PM PDT 24
Peak memory 245076 kb
Host smart-51b5c04e-f7f3-49c3-9692-8c121288f219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235108523 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.4235108523
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.796176878
Short name T312
Test name
Test status
Simulation time 160352295 ps
CPU time 1.67 seconds
Started Apr 28 03:37:48 PM PDT 24
Finished Apr 28 03:37:50 PM PDT 24
Peak memory 240040 kb
Host smart-59a06e8b-d9c6-4431-b759-b11f11a54420
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796176878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.796176878
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.2819477774
Short name T1226
Test name
Test status
Simulation time 148266890 ps
CPU time 1.43 seconds
Started Apr 28 03:37:48 PM PDT 24
Finished Apr 28 03:37:50 PM PDT 24
Peak memory 229464 kb
Host smart-41dc5663-1599-468a-8a37-1d3dc07e4113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819477774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.2819477774
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2599505357
Short name T329
Test name
Test status
Simulation time 156529657 ps
CPU time 2.9 seconds
Started Apr 28 03:37:52 PM PDT 24
Finished Apr 28 03:37:56 PM PDT 24
Peak memory 238104 kb
Host smart-f2f2a934-bbc5-4f41-88e0-5141e15e5dad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599505357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.2599505357
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2306665171
Short name T1204
Test name
Test status
Simulation time 122753880 ps
CPU time 4.69 seconds
Started Apr 28 03:37:52 PM PDT 24
Finished Apr 28 03:37:57 PM PDT 24
Peak memory 246348 kb
Host smart-464ec73b-daae-4142-b13e-2d398f0a04f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306665171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2306665171
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3613873471
Short name T355
Test name
Test status
Simulation time 2558067891 ps
CPU time 22.09 seconds
Started Apr 28 03:37:47 PM PDT 24
Finished Apr 28 03:38:10 PM PDT 24
Peak memory 243976 kb
Host smart-36f0b4e1-d2e2-496e-89e6-f08d60c1927a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613873471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.3613873471
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1889509182
Short name T309
Test name
Test status
Simulation time 224081996 ps
CPU time 3.13 seconds
Started Apr 28 03:37:32 PM PDT 24
Finished Apr 28 03:37:37 PM PDT 24
Peak memory 237684 kb
Host smart-9b850e78-ab62-4feb-bf33-6a670bc75357
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889509182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.1889509182
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3163617117
Short name T1219
Test name
Test status
Simulation time 970254474 ps
CPU time 12.33 seconds
Started Apr 28 03:37:32 PM PDT 24
Finished Apr 28 03:37:45 PM PDT 24
Peak memory 237732 kb
Host smart-b1ed5c88-bae1-41ed-9b6b-edbfec116d98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163617117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.3163617117
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1135104706
Short name T1304
Test name
Test status
Simulation time 143016393 ps
CPU time 2.36 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:39 PM PDT 24
Peak memory 238044 kb
Host smart-c2874684-9dc3-4831-9430-c75e5ac607f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135104706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.1135104706
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3047809855
Short name T1240
Test name
Test status
Simulation time 74864048 ps
CPU time 2.68 seconds
Started Apr 28 03:37:30 PM PDT 24
Finished Apr 28 03:37:34 PM PDT 24
Peak memory 247296 kb
Host smart-cfc443a8-388c-42bf-99ea-86a3e179999f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047809855 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.3047809855
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3053635580
Short name T317
Test name
Test status
Simulation time 41258901 ps
CPU time 1.49 seconds
Started Apr 28 03:37:28 PM PDT 24
Finished Apr 28 03:37:31 PM PDT 24
Peak memory 239564 kb
Host smart-14f0ce70-e026-45e4-8698-f7f628bc4ff4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053635580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.3053635580
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.559548736
Short name T1316
Test name
Test status
Simulation time 81790504 ps
CPU time 1.49 seconds
Started Apr 28 03:37:33 PM PDT 24
Finished Apr 28 03:37:36 PM PDT 24
Peak memory 229560 kb
Host smart-acbd6988-03f2-4026-89d8-575288df2970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559548736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.559548736
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2988689651
Short name T1301
Test name
Test status
Simulation time 547950222 ps
CPU time 1.63 seconds
Started Apr 28 03:37:29 PM PDT 24
Finished Apr 28 03:37:31 PM PDT 24
Peak memory 229552 kb
Host smart-979425af-787b-4a0a-9f71-7d8658d9485f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988689651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.2988689651
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3849246184
Short name T1300
Test name
Test status
Simulation time 135818004 ps
CPU time 1.37 seconds
Started Apr 28 03:37:30 PM PDT 24
Finished Apr 28 03:37:32 PM PDT 24
Peak memory 229940 kb
Host smart-991dcc03-03ef-4ca7-a9e3-98f64b9a6eb6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849246184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.3849246184
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3705333131
Short name T1239
Test name
Test status
Simulation time 104308914 ps
CPU time 1.94 seconds
Started Apr 28 03:37:29 PM PDT 24
Finished Apr 28 03:37:31 PM PDT 24
Peak memory 239008 kb
Host smart-bcc2daa4-275e-4591-b2ab-5e420ba90a0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705333131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.3705333131
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3885758601
Short name T1296
Test name
Test status
Simulation time 56240349 ps
CPU time 3.26 seconds
Started Apr 28 03:37:31 PM PDT 24
Finished Apr 28 03:37:35 PM PDT 24
Peak memory 246516 kb
Host smart-f8fdd69d-8ac8-40be-8e42-f1cb111318da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885758601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3885758601
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.2453243095
Short name T1262
Test name
Test status
Simulation time 38515756 ps
CPU time 1.43 seconds
Started Apr 28 03:37:51 PM PDT 24
Finished Apr 28 03:37:53 PM PDT 24
Peak memory 230836 kb
Host smart-887c9e9b-fd83-4b93-9039-dca662eb2cbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453243095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.2453243095
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.1251013326
Short name T1321
Test name
Test status
Simulation time 52118817 ps
CPU time 1.43 seconds
Started Apr 28 03:37:48 PM PDT 24
Finished Apr 28 03:37:50 PM PDT 24
Peak memory 229496 kb
Host smart-095892a9-2976-4e59-a4eb-db95892d91ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251013326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.1251013326
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2579653434
Short name T1288
Test name
Test status
Simulation time 61045418 ps
CPU time 1.39 seconds
Started Apr 28 03:37:46 PM PDT 24
Finished Apr 28 03:37:48 PM PDT 24
Peak memory 229984 kb
Host smart-27cc2970-f35b-4560-a301-a9baeaed6800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579653434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.2579653434
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2913220724
Short name T1265
Test name
Test status
Simulation time 139210176 ps
CPU time 1.48 seconds
Started Apr 28 03:37:46 PM PDT 24
Finished Apr 28 03:37:48 PM PDT 24
Peak memory 230840 kb
Host smart-289933a3-0fc4-400c-9adb-2bbb664b556f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913220724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.2913220724
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.1865504829
Short name T1225
Test name
Test status
Simulation time 551705586 ps
CPU time 1.9 seconds
Started Apr 28 03:37:49 PM PDT 24
Finished Apr 28 03:37:52 PM PDT 24
Peak memory 230796 kb
Host smart-a2fb12d0-b5e7-4188-bad8-e934327a408c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865504829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.1865504829
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.3115303108
Short name T1308
Test name
Test status
Simulation time 71395088 ps
CPU time 1.38 seconds
Started Apr 28 03:37:49 PM PDT 24
Finished Apr 28 03:37:51 PM PDT 24
Peak memory 230888 kb
Host smart-e99cb719-7866-4d91-baf9-55e28ba34c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115303108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.3115303108
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.4044853458
Short name T1207
Test name
Test status
Simulation time 37610564 ps
CPU time 1.45 seconds
Started Apr 28 03:37:48 PM PDT 24
Finished Apr 28 03:37:50 PM PDT 24
Peak memory 229684 kb
Host smart-224694a6-d500-424d-8be7-dd71051413d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044853458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.4044853458
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2790528139
Short name T1212
Test name
Test status
Simulation time 36511727 ps
CPU time 1.44 seconds
Started Apr 28 03:37:49 PM PDT 24
Finished Apr 28 03:37:51 PM PDT 24
Peak memory 229892 kb
Host smart-cf30abf4-ee24-459d-8480-7805f846d053
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790528139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.2790528139
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.920828630
Short name T1272
Test name
Test status
Simulation time 36049107 ps
CPU time 1.53 seconds
Started Apr 28 03:37:52 PM PDT 24
Finished Apr 28 03:37:54 PM PDT 24
Peak memory 229568 kb
Host smart-04d5b32c-34db-4146-954b-acf7aed250bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920828630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.920828630
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.32597275
Short name T1276
Test name
Test status
Simulation time 73170717 ps
CPU time 1.33 seconds
Started Apr 28 03:37:46 PM PDT 24
Finished Apr 28 03:37:48 PM PDT 24
Peak memory 229520 kb
Host smart-03e294c5-2ac2-4f11-8684-37e52a3110bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32597275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.32597275
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2964381772
Short name T314
Test name
Test status
Simulation time 59460176 ps
CPU time 3.16 seconds
Started Apr 28 03:37:28 PM PDT 24
Finished Apr 28 03:37:32 PM PDT 24
Peak memory 237752 kb
Host smart-1b349b1b-e1a8-4606-9d0a-6878650d0584
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964381772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.2964381772
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1406098516
Short name T1317
Test name
Test status
Simulation time 407752139 ps
CPU time 6.78 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:43 PM PDT 24
Peak memory 230792 kb
Host smart-3133ecfd-7de9-4360-b7a2-656c3fd6f51d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406098516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.1406098516
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3364911526
Short name T313
Test name
Test status
Simulation time 1400844175 ps
CPU time 4.24 seconds
Started Apr 28 03:37:37 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 238016 kb
Host smart-2b7d0612-46f1-4d0a-a858-f7d9a0da66fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364911526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.3364911526
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.4284265280
Short name T1287
Test name
Test status
Simulation time 200332770 ps
CPU time 3.41 seconds
Started Apr 28 03:37:29 PM PDT 24
Finished Apr 28 03:37:33 PM PDT 24
Peak memory 246352 kb
Host smart-d38431e7-a2bc-4116-acb7-9487281e9283
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284265280 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.4284265280
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.1654636471
Short name T318
Test name
Test status
Simulation time 107863423 ps
CPU time 1.63 seconds
Started Apr 28 03:37:31 PM PDT 24
Finished Apr 28 03:37:34 PM PDT 24
Peak memory 239028 kb
Host smart-f3e32cdd-ed21-4ff3-8243-83a0cbc4ba11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654636471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.1654636471
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.946056739
Short name T1214
Test name
Test status
Simulation time 154233552 ps
CPU time 1.4 seconds
Started Apr 28 03:37:31 PM PDT 24
Finished Apr 28 03:37:34 PM PDT 24
Peak memory 230836 kb
Host smart-5121f58e-9c18-4f38-a1cb-8013efa7c705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946056739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.946056739
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3348677630
Short name T1285
Test name
Test status
Simulation time 78562010 ps
CPU time 1.47 seconds
Started Apr 28 03:37:31 PM PDT 24
Finished Apr 28 03:37:34 PM PDT 24
Peak memory 229392 kb
Host smart-15337ff0-aab1-4d80-9152-24effded1be8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348677630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.3348677630
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.488573215
Short name T1248
Test name
Test status
Simulation time 128261749 ps
CPU time 1.3 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:39 PM PDT 24
Peak memory 230772 kb
Host smart-ae2b9d2c-d980-4854-8748-d967050fed7e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488573215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.
488573215
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3066247690
Short name T1295
Test name
Test status
Simulation time 534540683 ps
CPU time 3.66 seconds
Started Apr 28 03:37:31 PM PDT 24
Finished Apr 28 03:37:36 PM PDT 24
Peak memory 239064 kb
Host smart-bd2cb317-9486-43b5-bded-c265e67c1d41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066247690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.3066247690
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1131643479
Short name T1208
Test name
Test status
Simulation time 87988305 ps
CPU time 3.61 seconds
Started Apr 28 03:37:32 PM PDT 24
Finished Apr 28 03:37:36 PM PDT 24
Peak memory 246968 kb
Host smart-ce3ea262-6d79-411c-b3a1-f7e262525786
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131643479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1131643479
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.4235881466
Short name T357
Test name
Test status
Simulation time 1261225053 ps
CPU time 19.04 seconds
Started Apr 28 03:37:31 PM PDT 24
Finished Apr 28 03:37:52 PM PDT 24
Peak memory 244244 kb
Host smart-f2774bc3-c796-4816-8b32-c3f95718b380
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235881466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.4235881466
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1407012661
Short name T1209
Test name
Test status
Simulation time 79765883 ps
CPU time 1.39 seconds
Started Apr 28 03:37:51 PM PDT 24
Finished Apr 28 03:37:53 PM PDT 24
Peak memory 229888 kb
Host smart-16023adc-d02e-4e6e-8e26-c01de04b3f88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407012661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1407012661
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.1799724472
Short name T1307
Test name
Test status
Simulation time 72697237 ps
CPU time 1.52 seconds
Started Apr 28 03:37:49 PM PDT 24
Finished Apr 28 03:37:51 PM PDT 24
Peak memory 229548 kb
Host smart-c8e30b59-aae4-40da-9ed0-7f5068a32287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799724472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.1799724472
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.3293357304
Short name T1193
Test name
Test status
Simulation time 145166043 ps
CPU time 1.46 seconds
Started Apr 28 03:37:45 PM PDT 24
Finished Apr 28 03:37:47 PM PDT 24
Peak memory 229616 kb
Host smart-d0def7ee-c334-4cc5-9671-799630d41b88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293357304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.3293357304
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2454419458
Short name T1293
Test name
Test status
Simulation time 36632987 ps
CPU time 1.42 seconds
Started Apr 28 03:37:48 PM PDT 24
Finished Apr 28 03:37:50 PM PDT 24
Peak memory 230880 kb
Host smart-559ee05a-32bc-4a8f-83c1-4ac3e50f9f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454419458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.2454419458
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.539843581
Short name T1298
Test name
Test status
Simulation time 41870444 ps
CPU time 1.46 seconds
Started Apr 28 03:37:49 PM PDT 24
Finished Apr 28 03:37:51 PM PDT 24
Peak memory 230880 kb
Host smart-ab5603ce-9df6-45a4-845b-7503f3146acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539843581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.539843581
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3125250667
Short name T1200
Test name
Test status
Simulation time 41968410 ps
CPU time 1.5 seconds
Started Apr 28 03:37:52 PM PDT 24
Finished Apr 28 03:37:54 PM PDT 24
Peak memory 229528 kb
Host smart-ed8bf4d4-8303-4893-9b8c-ba8452d29fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125250667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3125250667
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.4115961709
Short name T1196
Test name
Test status
Simulation time 76399338 ps
CPU time 1.34 seconds
Started Apr 28 03:37:48 PM PDT 24
Finished Apr 28 03:37:50 PM PDT 24
Peak memory 230784 kb
Host smart-e392b9ea-b979-4c62-bf7a-37fea3ad2741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115961709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.4115961709
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3653583592
Short name T1286
Test name
Test status
Simulation time 43071015 ps
CPU time 1.46 seconds
Started Apr 28 03:37:46 PM PDT 24
Finished Apr 28 03:37:48 PM PDT 24
Peak memory 229664 kb
Host smart-344b8995-561c-411b-8ca7-de77945a478f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653583592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3653583592
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.3639609780
Short name T1246
Test name
Test status
Simulation time 139936133 ps
CPU time 1.48 seconds
Started Apr 28 03:37:53 PM PDT 24
Finished Apr 28 03:37:55 PM PDT 24
Peak memory 229800 kb
Host smart-2b489639-39f8-4dc3-9aef-0c3d343ed4be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639609780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.3639609780
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.384252372
Short name T1261
Test name
Test status
Simulation time 582832271 ps
CPU time 2.22 seconds
Started Apr 28 03:37:53 PM PDT 24
Finished Apr 28 03:37:55 PM PDT 24
Peak memory 229652 kb
Host smart-d674ae57-dd44-4323-99cc-8eb01ce6c3bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384252372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.384252372
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1480816866
Short name T337
Test name
Test status
Simulation time 375859722 ps
CPU time 3.89 seconds
Started Apr 28 03:37:33 PM PDT 24
Finished Apr 28 03:37:38 PM PDT 24
Peak memory 238056 kb
Host smart-a238b11c-4bc7-441a-b40f-7adac78ae477
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480816866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.1480816866
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.642685616
Short name T1302
Test name
Test status
Simulation time 1688998651 ps
CPU time 10.75 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:48 PM PDT 24
Peak memory 238972 kb
Host smart-91118e75-14cd-414d-9b70-98d96d832b69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642685616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_b
ash.642685616
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.293767815
Short name T1244
Test name
Test status
Simulation time 1072186489 ps
CPU time 3.15 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:41 PM PDT 24
Peak memory 239036 kb
Host smart-7c5fdf63-3785-4a43-9110-faac637e753a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293767815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_re
set.293767815
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.1485963788
Short name T1211
Test name
Test status
Simulation time 77594271 ps
CPU time 2.15 seconds
Started Apr 28 03:37:34 PM PDT 24
Finished Apr 28 03:37:38 PM PDT 24
Peak memory 245636 kb
Host smart-bd2c73a0-6d21-4c9a-ab04-9615502fe7e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485963788 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.1485963788
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3483802348
Short name T326
Test name
Test status
Simulation time 48677765 ps
CPU time 1.83 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:38 PM PDT 24
Peak memory 239116 kb
Host smart-7b1b868c-966f-4d6e-a7c7-ea95658849cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483802348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3483802348
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.2226298622
Short name T1255
Test name
Test status
Simulation time 72051601 ps
CPU time 1.43 seconds
Started Apr 28 03:37:28 PM PDT 24
Finished Apr 28 03:37:31 PM PDT 24
Peak memory 229540 kb
Host smart-7150fdf4-99d8-45ad-8e4c-057b2c2e4279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226298622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.2226298622
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3201305947
Short name T1289
Test name
Test status
Simulation time 505588417 ps
CPU time 1.32 seconds
Started Apr 28 03:37:28 PM PDT 24
Finished Apr 28 03:37:29 PM PDT 24
Peak memory 229248 kb
Host smart-2677d42d-fce0-415c-9d1a-8c3eaf1e1a8a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201305947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.3201305947
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2795459212
Short name T1310
Test name
Test status
Simulation time 53794897 ps
CPU time 1.36 seconds
Started Apr 28 03:37:28 PM PDT 24
Finished Apr 28 03:37:29 PM PDT 24
Peak memory 229324 kb
Host smart-12f5cacf-1452-4ac6-9353-85e94dc4f6c3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795459212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.2795459212
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3038044444
Short name T1254
Test name
Test status
Simulation time 1245465910 ps
CPU time 3.02 seconds
Started Apr 28 03:37:33 PM PDT 24
Finished Apr 28 03:37:37 PM PDT 24
Peak memory 237876 kb
Host smart-554eae10-5b9d-450f-81b5-b4c1012c125e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038044444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.3038044444
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2414915116
Short name T1278
Test name
Test status
Simulation time 696322078 ps
CPU time 5.85 seconds
Started Apr 28 03:37:34 PM PDT 24
Finished Apr 28 03:37:41 PM PDT 24
Peak memory 238964 kb
Host smart-ee4f6e9c-5a24-4785-9e5f-7dc26f7ee6a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414915116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.2414915116
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2979810166
Short name T1303
Test name
Test status
Simulation time 579198258 ps
CPU time 1.78 seconds
Started Apr 28 03:37:51 PM PDT 24
Finished Apr 28 03:37:53 PM PDT 24
Peak memory 229856 kb
Host smart-c522885e-385c-44c5-8206-46f346d88f7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979810166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2979810166
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.34587432
Short name T1273
Test name
Test status
Simulation time 76948923 ps
CPU time 1.46 seconds
Started Apr 28 03:37:51 PM PDT 24
Finished Apr 28 03:37:53 PM PDT 24
Peak memory 230828 kb
Host smart-0dd9e1a4-8018-46f1-b3ee-36503d515f09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34587432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.34587432
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2839626916
Short name T1194
Test name
Test status
Simulation time 39987436 ps
CPU time 1.49 seconds
Started Apr 28 03:37:58 PM PDT 24
Finished Apr 28 03:38:00 PM PDT 24
Peak memory 229808 kb
Host smart-8c9d5832-207a-4e26-a7e7-3112a8cbe30f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839626916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2839626916
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.4025861070
Short name T1263
Test name
Test status
Simulation time 552723273 ps
CPU time 2.14 seconds
Started Apr 28 03:37:51 PM PDT 24
Finished Apr 28 03:37:54 PM PDT 24
Peak memory 229620 kb
Host smart-09fbf131-4544-4b44-bd62-6d0acdac3e08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025861070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.4025861070
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2810610704
Short name T1277
Test name
Test status
Simulation time 52454839 ps
CPU time 1.52 seconds
Started Apr 28 03:37:50 PM PDT 24
Finished Apr 28 03:37:52 PM PDT 24
Peak memory 229900 kb
Host smart-d16ebc3b-b1a7-4b2f-aa7c-6c47c229ab67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810610704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2810610704
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.4215997941
Short name T1252
Test name
Test status
Simulation time 93345986 ps
CPU time 1.4 seconds
Started Apr 28 03:37:52 PM PDT 24
Finished Apr 28 03:37:54 PM PDT 24
Peak memory 229904 kb
Host smart-32a69b3c-f45f-4c34-ac1d-ea5ffef54d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215997941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.4215997941
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.79767837
Short name T1213
Test name
Test status
Simulation time 39165465 ps
CPU time 1.58 seconds
Started Apr 28 03:37:50 PM PDT 24
Finished Apr 28 03:37:52 PM PDT 24
Peak memory 229616 kb
Host smart-d72de216-7fa5-4a26-a683-a3143a424b40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79767837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.79767837
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.74346973
Short name T1231
Test name
Test status
Simulation time 38628419 ps
CPU time 1.45 seconds
Started Apr 28 03:37:52 PM PDT 24
Finished Apr 28 03:37:54 PM PDT 24
Peak memory 229636 kb
Host smart-f64ec184-a8c5-478f-8930-c38d19f3381b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74346973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.74346973
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.1825372196
Short name T1270
Test name
Test status
Simulation time 40731310 ps
CPU time 1.49 seconds
Started Apr 28 03:37:51 PM PDT 24
Finished Apr 28 03:37:53 PM PDT 24
Peak memory 230824 kb
Host smart-fcaeb19d-17d7-4b23-a3be-8033e1756bbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825372196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.1825372196
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.2817708951
Short name T1318
Test name
Test status
Simulation time 39399691 ps
CPU time 1.37 seconds
Started Apr 28 03:37:52 PM PDT 24
Finished Apr 28 03:37:54 PM PDT 24
Peak memory 230880 kb
Host smart-8be38bbb-7be3-4256-b765-fcf2da3e170a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817708951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.2817708951
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.93900230
Short name T1264
Test name
Test status
Simulation time 409763828 ps
CPU time 3.19 seconds
Started Apr 28 03:37:36 PM PDT 24
Finished Apr 28 03:37:42 PM PDT 24
Peak memory 247236 kb
Host smart-18383161-06d7-4ee9-bab7-508ce31ceb5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93900230 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.93900230
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.767627062
Short name T311
Test name
Test status
Simulation time 74674281 ps
CPU time 1.63 seconds
Started Apr 28 03:37:34 PM PDT 24
Finished Apr 28 03:37:37 PM PDT 24
Peak memory 239048 kb
Host smart-4814caff-76e2-4b96-840c-6b0707efe776
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767627062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.767627062
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.1742405527
Short name T1220
Test name
Test status
Simulation time 101184710 ps
CPU time 1.51 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:39 PM PDT 24
Peak memory 229644 kb
Host smart-8c18ca0f-7ff8-4423-9892-e5001acc0460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742405527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.1742405527
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1540469481
Short name T1266
Test name
Test status
Simulation time 321260523 ps
CPU time 3.13 seconds
Started Apr 28 03:37:36 PM PDT 24
Finished Apr 28 03:37:42 PM PDT 24
Peak memory 238988 kb
Host smart-91ee4959-e678-4619-a9fa-c627479122e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540469481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.1540469481
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.525344613
Short name T1202
Test name
Test status
Simulation time 2343126662 ps
CPU time 8.82 seconds
Started Apr 28 03:37:34 PM PDT 24
Finished Apr 28 03:37:43 PM PDT 24
Peak memory 239052 kb
Host smart-4aea1bf6-5c58-400b-a1b2-36408f022d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525344613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.525344613
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1083295312
Short name T1224
Test name
Test status
Simulation time 77193976 ps
CPU time 2.88 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:39 PM PDT 24
Peak memory 247260 kb
Host smart-77e5b815-1b77-4a8f-82a0-3426d159f065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083295312 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.1083295312
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2176355262
Short name T305
Test name
Test status
Simulation time 139896585 ps
CPU time 1.56 seconds
Started Apr 28 03:37:30 PM PDT 24
Finished Apr 28 03:37:33 PM PDT 24
Peak memory 240272 kb
Host smart-ce7273db-6b96-4328-9089-d8de1eac3850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176355262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2176355262
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1280064196
Short name T1313
Test name
Test status
Simulation time 155763630 ps
CPU time 1.52 seconds
Started Apr 28 03:37:33 PM PDT 24
Finished Apr 28 03:37:36 PM PDT 24
Peak memory 229640 kb
Host smart-530acada-f5dc-4786-91fe-1e14a6cd3575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280064196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1280064196
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1211826850
Short name T330
Test name
Test status
Simulation time 67733746 ps
CPU time 2.22 seconds
Started Apr 28 03:37:34 PM PDT 24
Finished Apr 28 03:37:37 PM PDT 24
Peak memory 238040 kb
Host smart-a126913b-2c02-4ba3-92d3-79cd82688a47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211826850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.1211826850
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3855522266
Short name T1282
Test name
Test status
Simulation time 72665834 ps
CPU time 4.72 seconds
Started Apr 28 03:37:35 PM PDT 24
Finished Apr 28 03:37:41 PM PDT 24
Peak memory 246720 kb
Host smart-dfb84d9d-ff76-40ec-9599-4afa37e683ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855522266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.3855522266
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.104983581
Short name T1279
Test name
Test status
Simulation time 710728065 ps
CPU time 10.28 seconds
Started Apr 28 03:37:33 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 239048 kb
Host smart-63fb104d-25b8-4e9d-92d2-cd359982ba7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104983581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_int
g_err.104983581
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.226118380
Short name T1250
Test name
Test status
Simulation time 212312532 ps
CPU time 2.18 seconds
Started Apr 28 03:37:34 PM PDT 24
Finished Apr 28 03:37:37 PM PDT 24
Peak memory 245424 kb
Host smart-e60ecb35-a615-4072-9f01-15638c62eb1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226118380 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.226118380
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.709522477
Short name T328
Test name
Test status
Simulation time 66627027 ps
CPU time 1.77 seconds
Started Apr 28 03:37:33 PM PDT 24
Finished Apr 28 03:37:36 PM PDT 24
Peak memory 238992 kb
Host smart-b4163fea-61db-450a-b93c-fa1e2698b97f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709522477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.709522477
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.87685064
Short name T1253
Test name
Test status
Simulation time 543354069 ps
CPU time 1.69 seconds
Started Apr 28 03:37:32 PM PDT 24
Finished Apr 28 03:37:35 PM PDT 24
Peak memory 229576 kb
Host smart-2e94f81b-d061-4c30-ade1-a502dd5e17af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87685064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.87685064
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1725841900
Short name T1238
Test name
Test status
Simulation time 1156217552 ps
CPU time 3.64 seconds
Started Apr 28 03:37:32 PM PDT 24
Finished Apr 28 03:37:37 PM PDT 24
Peak memory 239072 kb
Host smart-ddf97056-f630-446d-a4e5-8804ceddd251
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725841900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.1725841900
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1354459762
Short name T1195
Test name
Test status
Simulation time 69306597 ps
CPU time 5.02 seconds
Started Apr 28 03:37:36 PM PDT 24
Finished Apr 28 03:37:44 PM PDT 24
Peak memory 239108 kb
Host smart-4f48de83-0741-471f-a9a4-e3938259fe94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354459762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.1354459762
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.700819454
Short name T362
Test name
Test status
Simulation time 4404854807 ps
CPU time 21.9 seconds
Started Apr 28 03:37:32 PM PDT 24
Finished Apr 28 03:37:55 PM PDT 24
Peak memory 239104 kb
Host smart-79c62554-4d74-4373-9c9b-9bd014bf2f25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700819454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_int
g_err.700819454
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3466286457
Short name T269
Test name
Test status
Simulation time 109532765 ps
CPU time 2.88 seconds
Started Apr 28 03:37:36 PM PDT 24
Finished Apr 28 03:37:41 PM PDT 24
Peak memory 247220 kb
Host smart-54d1aaf7-5d7b-4181-a87b-2c177f65026c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466286457 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.3466286457
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3609636054
Short name T1269
Test name
Test status
Simulation time 87851888 ps
CPU time 1.93 seconds
Started Apr 28 03:37:33 PM PDT 24
Finished Apr 28 03:37:36 PM PDT 24
Peak memory 240628 kb
Host smart-efb10ecb-4a42-48b3-9bd8-192b39af375b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609636054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.3609636054
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.1515650547
Short name T1199
Test name
Test status
Simulation time 73599926 ps
CPU time 1.41 seconds
Started Apr 28 03:37:36 PM PDT 24
Finished Apr 28 03:37:40 PM PDT 24
Peak memory 229932 kb
Host smart-d87181ed-95d0-40c2-93f2-7ebe7e8e56a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515650547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.1515650547
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.1422977304
Short name T1230
Test name
Test status
Simulation time 164600175 ps
CPU time 3.03 seconds
Started Apr 28 03:37:37 PM PDT 24
Finished Apr 28 03:37:42 PM PDT 24
Peak memory 239124 kb
Host smart-b5df590c-49e9-4177-a419-63d79fa3b56a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422977304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.1422977304
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.743905250
Short name T1299
Test name
Test status
Simulation time 596059019 ps
CPU time 6.12 seconds
Started Apr 28 03:37:37 PM PDT 24
Finished Apr 28 03:37:46 PM PDT 24
Peak memory 246804 kb
Host smart-8a1ff1c5-2d3d-41fa-9045-1221a9486c50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743905250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.743905250
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2315302753
Short name T270
Test name
Test status
Simulation time 219834459 ps
CPU time 2.94 seconds
Started Apr 28 03:37:37 PM PDT 24
Finished Apr 28 03:37:42 PM PDT 24
Peak memory 247212 kb
Host smart-627bb397-e193-45f0-937e-37bcf41e528c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315302753 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.2315302753
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1282134706
Short name T306
Test name
Test status
Simulation time 43409437 ps
CPU time 1.68 seconds
Started Apr 28 03:37:39 PM PDT 24
Finished Apr 28 03:37:42 PM PDT 24
Peak memory 239104 kb
Host smart-5c62be86-e2ce-41a9-9653-0998a204ddc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282134706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1282134706
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1559715382
Short name T1210
Test name
Test status
Simulation time 43512797 ps
CPU time 1.41 seconds
Started Apr 28 03:37:38 PM PDT 24
Finished Apr 28 03:37:42 PM PDT 24
Peak memory 229580 kb
Host smart-2c0fbece-4d88-4e0a-a596-299362bef64a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559715382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1559715382
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3292291027
Short name T1243
Test name
Test status
Simulation time 142044474 ps
CPU time 2.13 seconds
Started Apr 28 03:37:42 PM PDT 24
Finished Apr 28 03:37:45 PM PDT 24
Peak memory 239080 kb
Host smart-917ddab1-2d27-4db6-953b-108340f3930d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292291027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.3292291027
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2015666144
Short name T1292
Test name
Test status
Simulation time 86459159 ps
CPU time 4.62 seconds
Started Apr 28 03:37:36 PM PDT 24
Finished Apr 28 03:37:43 PM PDT 24
Peak memory 246796 kb
Host smart-282b5cc5-9936-4c92-971a-57fbcd453e77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015666144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.2015666144
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3288474781
Short name T354
Test name
Test status
Simulation time 4561352190 ps
CPU time 25.24 seconds
Started Apr 28 03:37:38 PM PDT 24
Finished Apr 28 03:38:05 PM PDT 24
Peak memory 244256 kb
Host smart-244cc243-a4e0-47e0-80cb-bdf5f8072771
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288474781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.3288474781
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.1532285299
Short name T1002
Test name
Test status
Simulation time 55409933 ps
CPU time 1.92 seconds
Started Apr 28 01:56:58 PM PDT 24
Finished Apr 28 01:57:00 PM PDT 24
Peak memory 239764 kb
Host smart-20a188fb-1232-4231-af94-cc600d15151e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532285299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.1532285299
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.1962129789
Short name T300
Test name
Test status
Simulation time 1151614872 ps
CPU time 18.62 seconds
Started Apr 28 01:56:45 PM PDT 24
Finished Apr 28 01:57:04 PM PDT 24
Peak memory 241372 kb
Host smart-c82a5e0d-a2e1-44a1-bb64-bea78a271db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962129789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.1962129789
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.3111368834
Short name T835
Test name
Test status
Simulation time 2714068230 ps
CPU time 26.14 seconds
Started Apr 28 01:56:47 PM PDT 24
Finished Apr 28 01:57:13 PM PDT 24
Peak memory 248132 kb
Host smart-6059b2dc-9086-4600-a958-6d0273bd63cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111368834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.3111368834
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.2978334321
Short name T695
Test name
Test status
Simulation time 14913325238 ps
CPU time 32.74 seconds
Started Apr 28 01:56:46 PM PDT 24
Finished Apr 28 01:57:19 PM PDT 24
Peak memory 245312 kb
Host smart-af1d84d2-f7ee-4a27-bae2-4fc378490d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978334321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.2978334321
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.2966320063
Short name T970
Test name
Test status
Simulation time 2854294979 ps
CPU time 17.96 seconds
Started Apr 28 01:56:49 PM PDT 24
Finished Apr 28 01:57:07 PM PDT 24
Peak memory 248072 kb
Host smart-32c3502f-eda8-4a77-a133-9cac143ec337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966320063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.2966320063
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.1905023849
Short name T825
Test name
Test status
Simulation time 268373111 ps
CPU time 4.02 seconds
Started Apr 28 01:56:47 PM PDT 24
Finished Apr 28 01:56:51 PM PDT 24
Peak memory 241432 kb
Host smart-f1465d52-bc50-4d6e-b883-86957d50552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905023849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.1905023849
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.1316054900
Short name T885
Test name
Test status
Simulation time 5948296118 ps
CPU time 18.4 seconds
Started Apr 28 01:56:47 PM PDT 24
Finished Apr 28 01:57:06 PM PDT 24
Peak memory 240764 kb
Host smart-03cc8476-425d-414d-b2ba-6a4ed47f03cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316054900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.1316054900
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.718946300
Short name T215
Test name
Test status
Simulation time 11648420749 ps
CPU time 28.34 seconds
Started Apr 28 01:56:51 PM PDT 24
Finished Apr 28 01:57:19 PM PDT 24
Peak memory 244044 kb
Host smart-9ddf4349-b7a4-499c-a165-8d533eec8cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718946300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.718946300
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.673062099
Short name T1025
Test name
Test status
Simulation time 1495297996 ps
CPU time 13.65 seconds
Started Apr 28 01:56:52 PM PDT 24
Finished Apr 28 01:57:06 PM PDT 24
Peak memory 241328 kb
Host smart-8370c786-1c8b-4a76-8cf5-8fbcb76d8ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673062099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.673062099
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.2364458811
Short name T685
Test name
Test status
Simulation time 1127618700 ps
CPU time 15.47 seconds
Started Apr 28 01:56:49 PM PDT 24
Finished Apr 28 01:57:05 PM PDT 24
Peak memory 241464 kb
Host smart-2cfc8313-e2a9-475f-9736-deeb54cc24fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364458811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.2364458811
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.1610835050
Short name T426
Test name
Test status
Simulation time 6045835586 ps
CPU time 14.01 seconds
Started Apr 28 01:56:47 PM PDT 24
Finished Apr 28 01:57:02 PM PDT 24
Peak memory 241364 kb
Host smart-eb1709b7-cc21-4723-b3d6-f4fa5e91673d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610835050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.1610835050
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.214762229
Short name T176
Test name
Test status
Simulation time 5072870733 ps
CPU time 21.26 seconds
Started Apr 28 01:56:43 PM PDT 24
Finished Apr 28 01:57:04 PM PDT 24
Peak memory 241000 kb
Host smart-94008c71-1254-4728-9e7d-a75b98e3b07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214762229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.214762229
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.2854645592
Short name T239
Test name
Test status
Simulation time 9535419513 ps
CPU time 165.89 seconds
Started Apr 28 01:56:57 PM PDT 24
Finished Apr 28 01:59:43 PM PDT 24
Peak memory 262256 kb
Host smart-64a9bbde-9fa5-4b4a-b47e-81e7b537ee07
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854645592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.2854645592
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.3747248224
Short name T99
Test name
Test status
Simulation time 1518859466 ps
CPU time 11.16 seconds
Started Apr 28 01:56:43 PM PDT 24
Finished Apr 28 01:56:54 PM PDT 24
Peak memory 241200 kb
Host smart-6ce893b2-d7b8-4078-a334-55cd40a76a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747248224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.3747248224
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.3583894252
Short name T1123
Test name
Test status
Simulation time 978904499 ps
CPU time 18.79 seconds
Started Apr 28 01:56:52 PM PDT 24
Finished Apr 28 01:57:12 PM PDT 24
Peak memory 241420 kb
Host smart-cac65d5e-6895-40eb-ada9-ce974d064d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583894252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.3583894252
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.1597660632
Short name T630
Test name
Test status
Simulation time 111718321 ps
CPU time 1.82 seconds
Started Apr 28 01:56:43 PM PDT 24
Finished Apr 28 01:56:45 PM PDT 24
Peak memory 239832 kb
Host smart-b9069830-f15a-4fac-9e22-759bed7633dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1597660632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.1597660632
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.3386920092
Short name T1060
Test name
Test status
Simulation time 713467076 ps
CPU time 2.34 seconds
Started Apr 28 01:57:05 PM PDT 24
Finished Apr 28 01:57:08 PM PDT 24
Peak memory 240076 kb
Host smart-d7ac7c73-892e-4d8f-8a79-bc8c27a3f31b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386920092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.3386920092
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.3025924423
Short name T674
Test name
Test status
Simulation time 918069264 ps
CPU time 28.86 seconds
Started Apr 28 01:56:57 PM PDT 24
Finished Apr 28 01:57:26 PM PDT 24
Peak memory 248068 kb
Host smart-23815be3-51d7-4c03-b7b6-ee05bba2037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025924423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.3025924423
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.4103362199
Short name T41
Test name
Test status
Simulation time 212896097 ps
CPU time 8.05 seconds
Started Apr 28 01:57:02 PM PDT 24
Finished Apr 28 01:57:10 PM PDT 24
Peak memory 241632 kb
Host smart-63693411-f9ab-47dc-9ab9-3165db715b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103362199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.4103362199
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.1623970731
Short name T735
Test name
Test status
Simulation time 1506393100 ps
CPU time 11.3 seconds
Started Apr 28 01:56:59 PM PDT 24
Finished Apr 28 01:57:11 PM PDT 24
Peak memory 241328 kb
Host smart-df570980-999a-4b26-8068-0ae00067856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623970731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.1623970731
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.3813775497
Short name T486
Test name
Test status
Simulation time 14688738233 ps
CPU time 24.54 seconds
Started Apr 28 01:57:00 PM PDT 24
Finished Apr 28 01:57:25 PM PDT 24
Peak memory 241736 kb
Host smart-e7e27dfc-816c-449c-ab57-594e4eba339f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813775497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.3813775497
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.2620930035
Short name T155
Test name
Test status
Simulation time 4745272755 ps
CPU time 47.99 seconds
Started Apr 28 01:57:01 PM PDT 24
Finished Apr 28 01:57:49 PM PDT 24
Peak memory 246792 kb
Host smart-4c77e7ab-9b90-4e6a-a565-71421c25bad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620930035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.2620930035
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.3765992
Short name T464
Test name
Test status
Simulation time 775613289 ps
CPU time 15.78 seconds
Started Apr 28 01:57:01 PM PDT 24
Finished Apr 28 01:57:18 PM PDT 24
Peak memory 241408 kb
Host smart-e229e283-30b4-4c62-be18-dff19ccd88d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.3765992
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.2524895050
Short name T263
Test name
Test status
Simulation time 240742658 ps
CPU time 7.73 seconds
Started Apr 28 01:57:01 PM PDT 24
Finished Apr 28 01:57:10 PM PDT 24
Peak memory 241216 kb
Host smart-69b6bd40-09a2-4846-a7ac-201ea623921c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524895050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.2524895050
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.2023289591
Short name T391
Test name
Test status
Simulation time 12238049647 ps
CPU time 47.75 seconds
Started Apr 28 01:57:01 PM PDT 24
Finished Apr 28 01:57:50 PM PDT 24
Peak memory 241368 kb
Host smart-a7bd5cf9-bb01-432e-a6bd-e0b765915bdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023289591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.2023289591
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.3760782726
Short name T26
Test name
Test status
Simulation time 27678800056 ps
CPU time 200.67 seconds
Started Apr 28 01:57:05 PM PDT 24
Finished Apr 28 02:00:26 PM PDT 24
Peak memory 267824 kb
Host smart-90bac156-1268-4e74-baf9-d0f160699292
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760782726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3760782726
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.2313782434
Short name T828
Test name
Test status
Simulation time 640826564 ps
CPU time 12.05 seconds
Started Apr 28 01:57:05 PM PDT 24
Finished Apr 28 01:57:18 PM PDT 24
Peak memory 241632 kb
Host smart-96a54c27-e755-47ec-bdd4-81717579de52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313782434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.2313782434
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.206476575
Short name T342
Test name
Test status
Simulation time 66660807635 ps
CPU time 325.12 seconds
Started Apr 28 01:57:04 PM PDT 24
Finished Apr 28 02:02:30 PM PDT 24
Peak memory 273664 kb
Host smart-e5a56a2e-dbda-4224-8764-b15b1ac249e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206476575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.206476575
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.3366519377
Short name T687
Test name
Test status
Simulation time 338297571 ps
CPU time 10.98 seconds
Started Apr 28 01:57:00 PM PDT 24
Finished Apr 28 01:57:11 PM PDT 24
Peak memory 247876 kb
Host smart-b9d4037f-4dd7-4a08-9de3-7cda20a60968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366519377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.3366519377
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.2055361831
Short name T424
Test name
Test status
Simulation time 79985840 ps
CPU time 1.95 seconds
Started Apr 28 01:58:26 PM PDT 24
Finished Apr 28 01:58:29 PM PDT 24
Peak memory 239988 kb
Host smart-932b168c-c677-41ce-9844-a1cd4850cc76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055361831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.2055361831
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.126735056
Short name T562
Test name
Test status
Simulation time 25753286614 ps
CPU time 44.51 seconds
Started Apr 28 01:58:22 PM PDT 24
Finished Apr 28 01:59:07 PM PDT 24
Peak memory 242740 kb
Host smart-d71ffa8d-1007-47e6-9f4e-0dcec463315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126735056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.126735056
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.833382804
Short name T1185
Test name
Test status
Simulation time 1185849192 ps
CPU time 20.85 seconds
Started Apr 28 01:58:23 PM PDT 24
Finished Apr 28 01:58:44 PM PDT 24
Peak memory 241420 kb
Host smart-959dbbe9-6ef4-4be0-bf14-252fdfbbb6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833382804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.833382804
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.2225355958
Short name T693
Test name
Test status
Simulation time 4186221885 ps
CPU time 48.92 seconds
Started Apr 28 01:58:22 PM PDT 24
Finished Apr 28 01:59:11 PM PDT 24
Peak memory 241600 kb
Host smart-667bc3de-42b5-4ac8-b71d-8b588be1a59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225355958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2225355958
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.3238634029
Short name T228
Test name
Test status
Simulation time 197527266 ps
CPU time 4.17 seconds
Started Apr 28 01:58:28 PM PDT 24
Finished Apr 28 01:58:32 PM PDT 24
Peak memory 241328 kb
Host smart-69042c56-18e3-4f36-b37a-986e918fa0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238634029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3238634029
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.120063083
Short name T158
Test name
Test status
Simulation time 4625783247 ps
CPU time 28.19 seconds
Started Apr 28 01:58:22 PM PDT 24
Finished Apr 28 01:58:51 PM PDT 24
Peak memory 245932 kb
Host smart-5f8e7c30-5701-4a02-8fc1-5ab2506fe901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120063083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.120063083
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.4199266461
Short name T643
Test name
Test status
Simulation time 3120665490 ps
CPU time 26.04 seconds
Started Apr 28 01:58:22 PM PDT 24
Finished Apr 28 01:58:48 PM PDT 24
Peak memory 241768 kb
Host smart-1088e4fb-ebad-4b29-9bf0-7c6540c94b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199266461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.4199266461
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.3643188741
Short name T1033
Test name
Test status
Simulation time 629802071 ps
CPU time 14.25 seconds
Started Apr 28 01:58:22 PM PDT 24
Finished Apr 28 01:58:37 PM PDT 24
Peak memory 241364 kb
Host smart-01163581-a539-43ce-b995-e8cdc49da0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643188741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.3643188741
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.1927632927
Short name T820
Test name
Test status
Simulation time 2862576684 ps
CPU time 23.13 seconds
Started Apr 28 01:58:23 PM PDT 24
Finished Apr 28 01:58:47 PM PDT 24
Peak memory 248100 kb
Host smart-a5f23435-2dcf-4450-bc35-7b9916117d8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1927632927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.1927632927
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.276327385
Short name T960
Test name
Test status
Simulation time 3962045015 ps
CPU time 10.51 seconds
Started Apr 28 01:58:26 PM PDT 24
Finished Apr 28 01:58:37 PM PDT 24
Peak memory 248080 kb
Host smart-54172fca-8e22-4b06-a02b-13cf450120f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=276327385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.276327385
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.776113962
Short name T937
Test name
Test status
Simulation time 727677229 ps
CPU time 10.66 seconds
Started Apr 28 01:58:22 PM PDT 24
Finished Apr 28 01:58:33 PM PDT 24
Peak memory 241292 kb
Host smart-e6b86bf3-eb25-483e-94f6-bc1e1804a9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776113962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.776113962
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.2415886354
Short name T675
Test name
Test status
Simulation time 4962896231 ps
CPU time 73.63 seconds
Started Apr 28 01:58:25 PM PDT 24
Finished Apr 28 01:59:39 PM PDT 24
Peak memory 242436 kb
Host smart-6f58ce26-2c1d-4a6c-a617-5c067133fcc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415886354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.2415886354
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.3261064521
Short name T203
Test name
Test status
Simulation time 13265652840 ps
CPU time 26.81 seconds
Started Apr 28 01:58:24 PM PDT 24
Finished Apr 28 01:58:52 PM PDT 24
Peak memory 241548 kb
Host smart-b958da6d-1747-4f51-9a9d-b5991eb55adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261064521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.3261064521
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.1899367674
Short name T28
Test name
Test status
Simulation time 187256169 ps
CPU time 3.81 seconds
Started Apr 28 02:04:20 PM PDT 24
Finished Apr 28 02:04:24 PM PDT 24
Peak memory 241416 kb
Host smart-3c4caccc-21c6-4799-9d43-503a1c48e790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899367674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.1899367674
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.328131991
Short name T753
Test name
Test status
Simulation time 233159853 ps
CPU time 3.89 seconds
Started Apr 28 02:04:19 PM PDT 24
Finished Apr 28 02:04:24 PM PDT 24
Peak memory 241216 kb
Host smart-6a84f1b6-d8e5-42fa-8906-1163fadec1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328131991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.328131991
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.2059358298
Short name T932
Test name
Test status
Simulation time 85431288 ps
CPU time 2.85 seconds
Started Apr 28 02:04:20 PM PDT 24
Finished Apr 28 02:04:24 PM PDT 24
Peak memory 241736 kb
Host smart-501eb71f-f364-4c67-9ae6-27ca1ca98f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059358298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.2059358298
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.1170934213
Short name T395
Test name
Test status
Simulation time 791663251 ps
CPU time 7.02 seconds
Started Apr 28 02:04:19 PM PDT 24
Finished Apr 28 02:04:27 PM PDT 24
Peak memory 246792 kb
Host smart-ca8a8774-0db3-4bbd-b8f4-89ed36394bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170934213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.1170934213
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.2263071303
Short name T1052
Test name
Test status
Simulation time 149820811 ps
CPU time 4.72 seconds
Started Apr 28 02:04:27 PM PDT 24
Finished Apr 28 02:04:32 PM PDT 24
Peak memory 241492 kb
Host smart-47fd09ef-d476-4ac1-976b-ad8c2c640889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263071303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.2263071303
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.2830707012
Short name T791
Test name
Test status
Simulation time 366988100 ps
CPU time 6.17 seconds
Started Apr 28 02:04:25 PM PDT 24
Finished Apr 28 02:04:31 PM PDT 24
Peak memory 241424 kb
Host smart-81582ec5-ad8e-4514-8e1b-63cafc65e4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830707012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2830707012
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.4196210724
Short name T941
Test name
Test status
Simulation time 496601348 ps
CPU time 14.49 seconds
Started Apr 28 02:04:25 PM PDT 24
Finished Apr 28 02:04:40 PM PDT 24
Peak memory 241476 kb
Host smart-586335f2-e989-4e7f-8b41-10b4e416057f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196210724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.4196210724
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.3580168930
Short name T293
Test name
Test status
Simulation time 128416479 ps
CPU time 4.3 seconds
Started Apr 28 02:04:25 PM PDT 24
Finished Apr 28 02:04:30 PM PDT 24
Peak memory 241268 kb
Host smart-b231206f-2ac1-45a8-b309-6a47126b32f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580168930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.3580168930
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.1558140062
Short name T451
Test name
Test status
Simulation time 2805781426 ps
CPU time 6.29 seconds
Started Apr 28 02:04:26 PM PDT 24
Finished Apr 28 02:04:33 PM PDT 24
Peak memory 241520 kb
Host smart-ca5aed79-bcb4-4a55-9226-7aff66dee209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558140062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.1558140062
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.3553874815
Short name T1107
Test name
Test status
Simulation time 119202952 ps
CPU time 4.05 seconds
Started Apr 28 02:04:30 PM PDT 24
Finished Apr 28 02:04:35 PM PDT 24
Peak memory 241420 kb
Host smart-0fde67bd-7ca6-4474-bf9b-901b38e9c706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553874815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.3553874815
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.750997111
Short name T614
Test name
Test status
Simulation time 564617698 ps
CPU time 4.57 seconds
Started Apr 28 02:04:36 PM PDT 24
Finished Apr 28 02:04:41 PM PDT 24
Peak memory 241344 kb
Host smart-05f52db6-7179-4ad6-8d92-7aa8e5703864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750997111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.750997111
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.1592913731
Short name T466
Test name
Test status
Simulation time 328644368 ps
CPU time 4.72 seconds
Started Apr 28 02:04:34 PM PDT 24
Finished Apr 28 02:04:39 PM PDT 24
Peak memory 241300 kb
Host smart-95aab35f-5fc3-44fa-a016-446b97bccbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592913731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1592913731
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.2380954606
Short name T959
Test name
Test status
Simulation time 642901561 ps
CPU time 16.24 seconds
Started Apr 28 02:04:35 PM PDT 24
Finished Apr 28 02:04:52 PM PDT 24
Peak memory 241744 kb
Host smart-d74fa3bc-912f-43ee-b93f-90b22affc30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380954606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.2380954606
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.343235909
Short name T519
Test name
Test status
Simulation time 640269011 ps
CPU time 4.13 seconds
Started Apr 28 02:04:38 PM PDT 24
Finished Apr 28 02:04:42 PM PDT 24
Peak memory 241792 kb
Host smart-3a829f3e-7894-45f4-b189-882c432189ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343235909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.343235909
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.619105204
Short name T1038
Test name
Test status
Simulation time 616014664 ps
CPU time 17.49 seconds
Started Apr 28 02:04:30 PM PDT 24
Finished Apr 28 02:04:48 PM PDT 24
Peak memory 241240 kb
Host smart-635e5260-3bf7-4868-b43d-362db4925809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619105204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.619105204
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.2202215729
Short name T297
Test name
Test status
Simulation time 112384398 ps
CPU time 3.24 seconds
Started Apr 28 02:04:33 PM PDT 24
Finished Apr 28 02:04:37 PM PDT 24
Peak memory 241348 kb
Host smart-ddb0265a-112d-4eb8-b603-162f028d0ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202215729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.2202215729
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.3916797324
Short name T806
Test name
Test status
Simulation time 271888916 ps
CPU time 6.88 seconds
Started Apr 28 02:04:32 PM PDT 24
Finished Apr 28 02:04:39 PM PDT 24
Peak memory 246748 kb
Host smart-8b15a335-e9a9-4f53-af3a-f784abe25fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916797324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3916797324
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.557856882
Short name T90
Test name
Test status
Simulation time 160734906 ps
CPU time 3.98 seconds
Started Apr 28 02:04:32 PM PDT 24
Finished Apr 28 02:04:37 PM PDT 24
Peak memory 241640 kb
Host smart-ed6bfcfb-535c-4526-bf0c-a4c524321849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557856882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.557856882
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.2646056636
Short name T402
Test name
Test status
Simulation time 155925899 ps
CPU time 2.6 seconds
Started Apr 28 02:04:38 PM PDT 24
Finished Apr 28 02:04:41 PM PDT 24
Peak memory 241152 kb
Host smart-b613386b-8dbc-4f8b-977d-d97efdc90a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646056636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2646056636
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.3858945842
Short name T233
Test name
Test status
Simulation time 187907181 ps
CPU time 1.82 seconds
Started Apr 28 01:58:35 PM PDT 24
Finished Apr 28 01:58:38 PM PDT 24
Peak memory 239804 kb
Host smart-93d58514-6c67-42e2-9f77-face82629c0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858945842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.3858945842
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.3785052435
Short name T467
Test name
Test status
Simulation time 828656070 ps
CPU time 23.08 seconds
Started Apr 28 01:58:30 PM PDT 24
Finished Apr 28 01:58:53 PM PDT 24
Peak memory 241672 kb
Host smart-3152d573-8c3d-43f0-972b-601f0329d0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785052435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.3785052435
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.2395241528
Short name T408
Test name
Test status
Simulation time 6026847298 ps
CPU time 32.47 seconds
Started Apr 28 01:58:32 PM PDT 24
Finished Apr 28 01:59:05 PM PDT 24
Peak memory 241464 kb
Host smart-223b24e1-46ab-4514-b929-2a50778e5b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395241528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.2395241528
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.1337199429
Short name T942
Test name
Test status
Simulation time 152580855 ps
CPU time 4.16 seconds
Started Apr 28 01:58:28 PM PDT 24
Finished Apr 28 01:58:32 PM PDT 24
Peak memory 241384 kb
Host smart-f4e42763-6e98-4ce2-9b20-207e41bc68fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337199429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.1337199429
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.4199395583
Short name T217
Test name
Test status
Simulation time 827401021 ps
CPU time 20.62 seconds
Started Apr 28 01:58:29 PM PDT 24
Finished Apr 28 01:58:50 PM PDT 24
Peak memory 244996 kb
Host smart-0344b0fb-4d4c-4f75-8d22-e23b5199a0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199395583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.4199395583
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.811913678
Short name T421
Test name
Test status
Simulation time 833637373 ps
CPU time 20 seconds
Started Apr 28 01:58:34 PM PDT 24
Finished Apr 28 01:58:54 PM PDT 24
Peak memory 241352 kb
Host smart-ac5cd661-c855-49de-ae1b-4e35b75f22b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811913678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.811913678
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.1818604632
Short name T209
Test name
Test status
Simulation time 2632945441 ps
CPU time 10.96 seconds
Started Apr 28 01:58:35 PM PDT 24
Finished Apr 28 01:58:47 PM PDT 24
Peak memory 241452 kb
Host smart-80a6ee2b-f883-4ea5-9e80-9606952e8abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818604632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.1818604632
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.2663825992
Short name T1131
Test name
Test status
Simulation time 969450863 ps
CPU time 15.04 seconds
Started Apr 28 01:58:29 PM PDT 24
Finished Apr 28 01:58:44 PM PDT 24
Peak memory 241260 kb
Host smart-615a6917-b4d1-4806-a72c-fdb7ede6c545
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663825992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.2663825992
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.279455591
Short name T550
Test name
Test status
Simulation time 188996521 ps
CPU time 3.26 seconds
Started Apr 28 01:58:29 PM PDT 24
Finished Apr 28 01:58:32 PM PDT 24
Peak memory 241584 kb
Host smart-cea79d28-6d59-4b95-b85b-111e38cdc1d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279455591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.279455591
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.3278106252
Short name T401
Test name
Test status
Simulation time 596475035 ps
CPU time 11.23 seconds
Started Apr 28 01:58:25 PM PDT 24
Finished Apr 28 01:58:37 PM PDT 24
Peak memory 241212 kb
Host smart-8fb23678-2a53-4113-a02e-98ad4c2c19ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278106252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.3278106252
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.942139703
Short name T332
Test name
Test status
Simulation time 103183011620 ps
CPU time 1109.18 seconds
Started Apr 28 01:58:29 PM PDT 24
Finished Apr 28 02:16:59 PM PDT 24
Peak memory 334988 kb
Host smart-b87811fd-5e8c-46f2-84bf-17dc5966b543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942139703 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.942139703
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.1946729274
Short name T380
Test name
Test status
Simulation time 17891793773 ps
CPU time 36.79 seconds
Started Apr 28 01:58:30 PM PDT 24
Finished Apr 28 01:59:07 PM PDT 24
Peak memory 241608 kb
Host smart-603081ff-6765-4568-bfbe-7188082830f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946729274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.1946729274
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.1296059625
Short name T1029
Test name
Test status
Simulation time 533534765 ps
CPU time 4.5 seconds
Started Apr 28 02:04:36 PM PDT 24
Finished Apr 28 02:04:40 PM PDT 24
Peak memory 241712 kb
Host smart-bb8a8af7-eab5-46cc-b244-d05eea040839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296059625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.1296059625
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.2473787452
Short name T751
Test name
Test status
Simulation time 102268909 ps
CPU time 4.1 seconds
Started Apr 28 02:04:37 PM PDT 24
Finished Apr 28 02:04:41 PM PDT 24
Peak memory 241644 kb
Host smart-06f6828c-128c-411e-9137-dd11c3fbc86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473787452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.2473787452
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.3713429306
Short name T859
Test name
Test status
Simulation time 112273626 ps
CPU time 3.85 seconds
Started Apr 28 02:04:40 PM PDT 24
Finished Apr 28 02:04:44 PM PDT 24
Peak memory 241284 kb
Host smart-fb7f2618-bd86-4ef6-8370-65386547b25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713429306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3713429306
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.2200937437
Short name T881
Test name
Test status
Simulation time 4797797099 ps
CPU time 7.61 seconds
Started Apr 28 02:04:36 PM PDT 24
Finished Apr 28 02:04:44 PM PDT 24
Peak memory 241792 kb
Host smart-6512dd02-379c-44c3-89ef-94840863eca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200937437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.2200937437
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.4015330538
Short name T165
Test name
Test status
Simulation time 1420818733 ps
CPU time 4.34 seconds
Started Apr 28 02:04:38 PM PDT 24
Finished Apr 28 02:04:43 PM PDT 24
Peak memory 241680 kb
Host smart-7a621e59-8225-4fcc-b266-5421e5715c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015330538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.4015330538
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.3029790332
Short name T958
Test name
Test status
Simulation time 158405030 ps
CPU time 4.01 seconds
Started Apr 28 02:04:36 PM PDT 24
Finished Apr 28 02:04:41 PM PDT 24
Peak memory 246288 kb
Host smart-1b78c6d7-ef48-4bf5-b626-4ffc41dd8320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029790332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3029790332
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.3395058461
Short name T729
Test name
Test status
Simulation time 115454903 ps
CPU time 3.26 seconds
Started Apr 28 02:04:37 PM PDT 24
Finished Apr 28 02:04:41 PM PDT 24
Peak memory 241356 kb
Host smart-51811327-dad4-42ea-a735-d148e4d0da9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395058461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3395058461
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.38821266
Short name T242
Test name
Test status
Simulation time 433810494 ps
CPU time 5.63 seconds
Started Apr 28 02:04:37 PM PDT 24
Finished Apr 28 02:04:43 PM PDT 24
Peak memory 241428 kb
Host smart-0580ee63-5961-4e3b-8001-929393edf68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38821266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.38821266
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.2124030595
Short name T68
Test name
Test status
Simulation time 338066901 ps
CPU time 5.04 seconds
Started Apr 28 02:04:41 PM PDT 24
Finished Apr 28 02:04:46 PM PDT 24
Peak memory 241756 kb
Host smart-f1798de1-7b5b-4eb4-b790-bee29e6fa8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124030595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.2124030595
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.484583624
Short name T82
Test name
Test status
Simulation time 370499084 ps
CPU time 4.57 seconds
Started Apr 28 02:04:37 PM PDT 24
Finished Apr 28 02:04:42 PM PDT 24
Peak memory 241396 kb
Host smart-fcb31ddd-5e45-408c-953e-9707e7d5d985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484583624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.484583624
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.2452021117
Short name T518
Test name
Test status
Simulation time 1726626843 ps
CPU time 15.9 seconds
Started Apr 28 02:04:37 PM PDT 24
Finished Apr 28 02:04:53 PM PDT 24
Peak memory 241912 kb
Host smart-ea153b54-98a7-4670-9e92-a22c62bdaf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452021117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.2452021117
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.206981968
Short name T222
Test name
Test status
Simulation time 142745687 ps
CPU time 3.55 seconds
Started Apr 28 02:04:38 PM PDT 24
Finished Apr 28 02:04:42 PM PDT 24
Peak memory 241500 kb
Host smart-b261e09e-79a6-4b2a-beb9-32de72248c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206981968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.206981968
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.3584155002
Short name T632
Test name
Test status
Simulation time 773520951 ps
CPU time 11.95 seconds
Started Apr 28 02:04:36 PM PDT 24
Finished Apr 28 02:04:49 PM PDT 24
Peak memory 241908 kb
Host smart-dc25163c-26fc-45e4-a952-09bad1bcf3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584155002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.3584155002
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.4189593167
Short name T502
Test name
Test status
Simulation time 564370140 ps
CPU time 3.48 seconds
Started Apr 28 02:04:43 PM PDT 24
Finished Apr 28 02:04:47 PM PDT 24
Peak memory 241360 kb
Host smart-b6101a72-ef36-456c-9648-4d730d63fdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189593167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.4189593167
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.4170173754
Short name T248
Test name
Test status
Simulation time 1369995800 ps
CPU time 17.71 seconds
Started Apr 28 02:04:42 PM PDT 24
Finished Apr 28 02:05:01 PM PDT 24
Peak memory 241468 kb
Host smart-f831784d-3084-4410-8483-4f522702d1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170173754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.4170173754
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.3199479369
Short name T684
Test name
Test status
Simulation time 2228843288 ps
CPU time 5.39 seconds
Started Apr 28 02:04:42 PM PDT 24
Finished Apr 28 02:04:48 PM PDT 24
Peak memory 241912 kb
Host smart-cf298dd7-fa56-470a-8ab9-61872cbac4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199479369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.3199479369
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.1569175784
Short name T178
Test name
Test status
Simulation time 453211060 ps
CPU time 7.12 seconds
Started Apr 28 02:04:42 PM PDT 24
Finished Apr 28 02:04:49 PM PDT 24
Peak memory 241316 kb
Host smart-e40c7d9b-7cc7-4f1a-ba28-866dcfb3809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569175784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.1569175784
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.283317287
Short name T944
Test name
Test status
Simulation time 103853095 ps
CPU time 3.37 seconds
Started Apr 28 02:04:42 PM PDT 24
Finished Apr 28 02:04:46 PM PDT 24
Peak memory 241304 kb
Host smart-84a292cf-4cda-4052-b28d-869fc6633a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283317287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.283317287
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.3843929699
Short name T245
Test name
Test status
Simulation time 267992876 ps
CPU time 3.96 seconds
Started Apr 28 02:04:42 PM PDT 24
Finished Apr 28 02:04:46 PM PDT 24
Peak memory 241612 kb
Host smart-f5e9a833-5add-4ab8-a17d-83bc61c46428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843929699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.3843929699
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.1239904997
Short name T874
Test name
Test status
Simulation time 160297892 ps
CPU time 1.7 seconds
Started Apr 28 01:58:35 PM PDT 24
Finished Apr 28 01:58:37 PM PDT 24
Peak memory 239904 kb
Host smart-650035dd-ca6a-4317-8f88-798b0e738b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239904997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1239904997
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.366494890
Short name T1103
Test name
Test status
Simulation time 368005016 ps
CPU time 9.32 seconds
Started Apr 28 01:58:35 PM PDT 24
Finished Apr 28 01:58:45 PM PDT 24
Peak memory 241128 kb
Host smart-b82d4142-f99b-47be-a9a3-707014d2795d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366494890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.366494890
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.2991406109
Short name T513
Test name
Test status
Simulation time 1207435862 ps
CPU time 20.87 seconds
Started Apr 28 01:58:34 PM PDT 24
Finished Apr 28 01:58:55 PM PDT 24
Peak memory 241360 kb
Host smart-cfae1965-a0a1-4a85-ad56-996f4103cd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991406109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.2991406109
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.2682768138
Short name T479
Test name
Test status
Simulation time 8846233063 ps
CPU time 46.5 seconds
Started Apr 28 01:58:35 PM PDT 24
Finished Apr 28 01:59:21 PM PDT 24
Peak memory 241436 kb
Host smart-286289ec-ec42-4721-abe0-1b4261f9b7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682768138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.2682768138
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.1863519801
Short name T714
Test name
Test status
Simulation time 150746940 ps
CPU time 3.35 seconds
Started Apr 28 01:58:33 PM PDT 24
Finished Apr 28 01:58:37 PM PDT 24
Peak memory 241468 kb
Host smart-a6fb2e57-a5d8-4a32-9acf-9dde92445741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863519801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1863519801
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.1218177128
Short name T1041
Test name
Test status
Simulation time 2832238389 ps
CPU time 22.32 seconds
Started Apr 28 01:58:33 PM PDT 24
Finished Apr 28 01:58:56 PM PDT 24
Peak memory 241508 kb
Host smart-ce2db22e-bbef-4b1b-ba49-12bb9f78ca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218177128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.1218177128
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.245256299
Short name T230
Test name
Test status
Simulation time 378599965 ps
CPU time 8.51 seconds
Started Apr 28 01:58:34 PM PDT 24
Finished Apr 28 01:58:43 PM PDT 24
Peak memory 247908 kb
Host smart-b6134568-2af0-49ed-800b-36a0602d4f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245256299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.245256299
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.630754962
Short name T77
Test name
Test status
Simulation time 389617424 ps
CPU time 14.97 seconds
Started Apr 28 01:58:34 PM PDT 24
Finished Apr 28 01:58:50 PM PDT 24
Peak memory 241656 kb
Host smart-a3c8e1ad-85ea-45a5-a5b7-7aac7d16e1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630754962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.630754962
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.1189302796
Short name T938
Test name
Test status
Simulation time 513028872 ps
CPU time 4.42 seconds
Started Apr 28 01:58:36 PM PDT 24
Finished Apr 28 01:58:41 PM PDT 24
Peak memory 241484 kb
Host smart-27e001b1-18e8-4fcf-9bee-3d26fc3836e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1189302796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.1189302796
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.2290774759
Short name T501
Test name
Test status
Simulation time 2120023313 ps
CPU time 6.99 seconds
Started Apr 28 01:58:34 PM PDT 24
Finished Apr 28 01:58:42 PM PDT 24
Peak memory 247340 kb
Host smart-2823971f-f0d3-4537-bc26-3edcf2656ef9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2290774759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2290774759
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.3806281052
Short name T180
Test name
Test status
Simulation time 320331118 ps
CPU time 3.87 seconds
Started Apr 28 01:58:33 PM PDT 24
Finished Apr 28 01:58:38 PM PDT 24
Peak memory 241520 kb
Host smart-16c20f1f-9992-4d3a-abe7-2851a2621b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806281052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.3806281052
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.1872244488
Short name T1141
Test name
Test status
Simulation time 105761470074 ps
CPU time 541.68 seconds
Started Apr 28 01:58:35 PM PDT 24
Finished Apr 28 02:07:37 PM PDT 24
Peak memory 272724 kb
Host smart-96c69745-3416-4191-a092-dfed16f5e020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872244488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.1872244488
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.757351398
Short name T1006
Test name
Test status
Simulation time 1975917626 ps
CPU time 4.97 seconds
Started Apr 28 02:04:41 PM PDT 24
Finished Apr 28 02:04:46 PM PDT 24
Peak memory 241252 kb
Host smart-d20de972-3cf0-405f-8c7d-d5d3c4ef335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757351398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.757351398
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.3228135239
Short name T902
Test name
Test status
Simulation time 128078956 ps
CPU time 4.51 seconds
Started Apr 28 02:04:42 PM PDT 24
Finished Apr 28 02:04:47 PM PDT 24
Peak memory 241620 kb
Host smart-433d6198-65f2-4b1e-b628-cb6ca648f202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228135239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.3228135239
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.883843388
Short name T197
Test name
Test status
Simulation time 1613998910 ps
CPU time 6.03 seconds
Started Apr 28 02:04:42 PM PDT 24
Finished Apr 28 02:04:49 PM PDT 24
Peak memory 241792 kb
Host smart-458aa325-308d-4ff7-b40b-21acdbe8e46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883843388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.883843388
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.1512025809
Short name T1087
Test name
Test status
Simulation time 392519107 ps
CPU time 5.4 seconds
Started Apr 28 02:04:43 PM PDT 24
Finished Apr 28 02:04:49 PM PDT 24
Peak memory 241280 kb
Host smart-666fb6bb-667d-4b37-8864-c08f25771642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512025809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.1512025809
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.3230093996
Short name T1157
Test name
Test status
Simulation time 321905751 ps
CPU time 4.02 seconds
Started Apr 28 02:04:42 PM PDT 24
Finished Apr 28 02:04:47 PM PDT 24
Peak memory 241356 kb
Host smart-59b8a577-7018-406c-9a21-7225a3dd3ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230093996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.3230093996
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.536793815
Short name T981
Test name
Test status
Simulation time 1917580018 ps
CPU time 19.48 seconds
Started Apr 28 02:04:43 PM PDT 24
Finished Apr 28 02:05:03 PM PDT 24
Peak memory 241472 kb
Host smart-ef0a6945-2a41-4528-8c0f-e6726056a705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536793815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.536793815
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.2657236420
Short name T912
Test name
Test status
Simulation time 441326190 ps
CPU time 5.3 seconds
Started Apr 28 02:04:41 PM PDT 24
Finished Apr 28 02:04:47 PM PDT 24
Peak memory 241740 kb
Host smart-43c10599-efb6-4f25-8bc6-b6bfccd95f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657236420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.2657236420
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.510576520
Short name T434
Test name
Test status
Simulation time 1861723347 ps
CPU time 20.91 seconds
Started Apr 28 02:04:47 PM PDT 24
Finished Apr 28 02:05:09 PM PDT 24
Peak memory 241400 kb
Host smart-a2477d46-26ef-4dee-a62f-fe4a5d0e4294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510576520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.510576520
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.2663347871
Short name T984
Test name
Test status
Simulation time 429631882 ps
CPU time 3.23 seconds
Started Apr 28 02:04:47 PM PDT 24
Finished Apr 28 02:04:51 PM PDT 24
Peak memory 241736 kb
Host smart-d854b94d-7dd3-475a-b88e-a280f7eaceda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663347871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.2663347871
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.1146172941
Short name T837
Test name
Test status
Simulation time 191338331 ps
CPU time 5.11 seconds
Started Apr 28 02:04:46 PM PDT 24
Finished Apr 28 02:04:51 PM PDT 24
Peak memory 241400 kb
Host smart-9ef9e0d5-47d7-4c09-bc0e-9608f129c63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146172941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.1146172941
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.3010004090
Short name T854
Test name
Test status
Simulation time 207444829 ps
CPU time 4.49 seconds
Started Apr 28 02:04:49 PM PDT 24
Finished Apr 28 02:04:54 PM PDT 24
Peak memory 241192 kb
Host smart-7b8c0c30-4fa9-477d-911a-9092577c65e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010004090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.3010004090
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.3764533593
Short name T730
Test name
Test status
Simulation time 121670427 ps
CPU time 3.39 seconds
Started Apr 28 02:04:47 PM PDT 24
Finished Apr 28 02:04:51 PM PDT 24
Peak memory 241388 kb
Host smart-a3be3aed-201d-4667-8463-edf0716ee896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764533593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3764533593
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.2989718497
Short name T933
Test name
Test status
Simulation time 1269598761 ps
CPU time 17.89 seconds
Started Apr 28 02:04:50 PM PDT 24
Finished Apr 28 02:05:08 PM PDT 24
Peak memory 241712 kb
Host smart-6d15b566-f08a-429e-9a98-508c1466225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989718497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.2989718497
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.2157561038
Short name T534
Test name
Test status
Simulation time 2438279571 ps
CPU time 8.51 seconds
Started Apr 28 02:04:54 PM PDT 24
Finished Apr 28 02:05:03 PM PDT 24
Peak memory 241364 kb
Host smart-9c0ff1af-1513-49a1-bec1-d4a49f00af4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157561038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2157561038
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.979214397
Short name T708
Test name
Test status
Simulation time 1742779647 ps
CPU time 4.7 seconds
Started Apr 28 02:04:52 PM PDT 24
Finished Apr 28 02:04:58 PM PDT 24
Peak memory 241312 kb
Host smart-9b5de886-9b65-41e1-8396-bde6ef5782d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979214397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.979214397
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.3437532721
Short name T678
Test name
Test status
Simulation time 144001847 ps
CPU time 4.14 seconds
Started Apr 28 02:04:53 PM PDT 24
Finished Apr 28 02:04:57 PM PDT 24
Peak memory 241112 kb
Host smart-17d6f883-b43e-41cf-a57f-e6fb696d4fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437532721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.3437532721
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.1525439693
Short name T1094
Test name
Test status
Simulation time 4304974701 ps
CPU time 11.44 seconds
Started Apr 28 02:04:54 PM PDT 24
Finished Apr 28 02:05:06 PM PDT 24
Peak memory 241544 kb
Host smart-7055126e-b041-468b-b99c-1996ce655b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525439693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.1525439693
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.2928315724
Short name T857
Test name
Test status
Simulation time 191357366 ps
CPU time 2.16 seconds
Started Apr 28 01:58:44 PM PDT 24
Finished Apr 28 01:58:46 PM PDT 24
Peak memory 239752 kb
Host smart-ef5c21ba-5fd5-4a80-a60b-f1112262f6e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928315724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.2928315724
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.935283766
Short name T500
Test name
Test status
Simulation time 367610105 ps
CPU time 24.11 seconds
Started Apr 28 01:58:39 PM PDT 24
Finished Apr 28 01:59:03 PM PDT 24
Peak memory 241248 kb
Host smart-21384c9b-1a96-4d96-81f3-03f488b7b2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935283766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.935283766
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.2446883287
Short name T1092
Test name
Test status
Simulation time 2420663799 ps
CPU time 36.37 seconds
Started Apr 28 01:58:40 PM PDT 24
Finished Apr 28 01:59:17 PM PDT 24
Peak memory 241460 kb
Host smart-2a6af96a-f99c-4d85-960f-23f1f7d63323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446883287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.2446883287
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.2008179371
Short name T303
Test name
Test status
Simulation time 180070422 ps
CPU time 4.62 seconds
Started Apr 28 01:58:38 PM PDT 24
Finished Apr 28 01:58:44 PM PDT 24
Peak memory 241308 kb
Host smart-f630046a-078b-425d-b621-5ae54842dac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008179371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.2008179371
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.2079419096
Short name T299
Test name
Test status
Simulation time 1340336207 ps
CPU time 15.19 seconds
Started Apr 28 01:58:43 PM PDT 24
Finished Apr 28 01:58:58 PM PDT 24
Peak memory 241804 kb
Host smart-c3c6abe0-73c6-4c4c-966a-8eeb5635f901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079419096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.2079419096
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.1732100517
Short name T428
Test name
Test status
Simulation time 810196865 ps
CPU time 18.07 seconds
Started Apr 28 01:58:44 PM PDT 24
Finished Apr 28 01:59:03 PM PDT 24
Peak memory 241656 kb
Host smart-52c0888e-acfe-4fd1-a186-e99e851cda57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732100517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.1732100517
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.1121617018
Short name T319
Test name
Test status
Simulation time 835991783 ps
CPU time 12.07 seconds
Started Apr 28 01:58:40 PM PDT 24
Finished Apr 28 01:58:52 PM PDT 24
Peak memory 241364 kb
Host smart-9b699270-a616-4bf0-9bf4-77466aefbe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121617018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1121617018
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.929005023
Short name T400
Test name
Test status
Simulation time 2802095219 ps
CPU time 15.03 seconds
Started Apr 28 01:58:43 PM PDT 24
Finished Apr 28 01:58:59 PM PDT 24
Peak memory 241496 kb
Host smart-e77169f3-eaa8-4f4f-bc1e-bda02a7ab186
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929005023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.929005023
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.4063461355
Short name T1153
Test name
Test status
Simulation time 213253460 ps
CPU time 3.08 seconds
Started Apr 28 01:58:40 PM PDT 24
Finished Apr 28 01:58:43 PM PDT 24
Peak memory 247500 kb
Host smart-436059cb-5aed-4bda-94b5-7333f98d8ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063461355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.4063461355
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.1554054433
Short name T1187
Test name
Test status
Simulation time 57661764377 ps
CPU time 683.33 seconds
Started Apr 28 01:58:45 PM PDT 24
Finished Apr 28 02:10:08 PM PDT 24
Peak memory 297400 kb
Host smart-797ee522-dda0-4d13-9c43-f7fac22f421d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554054433 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.1554054433
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.2593943179
Short name T287
Test name
Test status
Simulation time 532392084 ps
CPU time 12.03 seconds
Started Apr 28 01:58:45 PM PDT 24
Finished Apr 28 01:58:57 PM PDT 24
Peak memory 241204 kb
Host smart-7023857a-c947-4868-9cde-365c19e5286a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593943179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.2593943179
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.4097619126
Short name T999
Test name
Test status
Simulation time 1681666868 ps
CPU time 10.6 seconds
Started Apr 28 02:05:01 PM PDT 24
Finished Apr 28 02:05:12 PM PDT 24
Peak memory 241524 kb
Host smart-9b9c4450-1d72-47a0-a2f3-09c722ba77b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097619126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.4097619126
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.2863319945
Short name T227
Test name
Test status
Simulation time 1626168381 ps
CPU time 5.11 seconds
Started Apr 28 02:05:01 PM PDT 24
Finished Apr 28 02:05:07 PM PDT 24
Peak memory 241628 kb
Host smart-1f99a916-54c6-4ec8-8c63-bb54053bd646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863319945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.2863319945
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.204902132
Short name T142
Test name
Test status
Simulation time 179158812 ps
CPU time 8.31 seconds
Started Apr 28 02:05:02 PM PDT 24
Finished Apr 28 02:05:11 PM PDT 24
Peak memory 241336 kb
Host smart-5ac39c95-fa0f-46f0-868e-be68fa29f421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204902132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.204902132
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.989920908
Short name T703
Test name
Test status
Simulation time 90243882 ps
CPU time 3.61 seconds
Started Apr 28 02:04:57 PM PDT 24
Finished Apr 28 02:05:01 PM PDT 24
Peak memory 241308 kb
Host smart-7a5b7c5d-b414-41ba-8c86-abf816815bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989920908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.989920908
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.513661173
Short name T798
Test name
Test status
Simulation time 485929582 ps
CPU time 5.01 seconds
Started Apr 28 02:04:59 PM PDT 24
Finished Apr 28 02:05:04 PM PDT 24
Peak memory 241556 kb
Host smart-fd663299-0273-4a91-a12d-4b9cf38e4987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513661173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.513661173
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.3330687894
Short name T161
Test name
Test status
Simulation time 220080147 ps
CPU time 3.41 seconds
Started Apr 28 02:05:00 PM PDT 24
Finished Apr 28 02:05:04 PM PDT 24
Peak memory 241284 kb
Host smart-6cf898ac-262c-4abd-87b9-a45b0cdcda85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330687894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.3330687894
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.3295981798
Short name T244
Test name
Test status
Simulation time 6445804646 ps
CPU time 20.84 seconds
Started Apr 28 02:04:58 PM PDT 24
Finished Apr 28 02:05:19 PM PDT 24
Peak memory 241312 kb
Host smart-06c7a03a-0470-4ab7-be31-8438a530e49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295981798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.3295981798
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.1745125700
Short name T249
Test name
Test status
Simulation time 865884318 ps
CPU time 13.24 seconds
Started Apr 28 02:05:01 PM PDT 24
Finished Apr 28 02:05:15 PM PDT 24
Peak memory 241336 kb
Host smart-60a9c204-6192-4f24-a855-a76090ec974f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745125700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.1745125700
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.239210216
Short name T489
Test name
Test status
Simulation time 516034044 ps
CPU time 3.6 seconds
Started Apr 28 02:04:58 PM PDT 24
Finished Apr 28 02:05:02 PM PDT 24
Peak memory 241692 kb
Host smart-04e6adea-cb14-4b95-83fb-317298bff22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239210216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.239210216
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.1713689908
Short name T323
Test name
Test status
Simulation time 134821392 ps
CPU time 6.64 seconds
Started Apr 28 02:04:58 PM PDT 24
Finished Apr 28 02:05:06 PM PDT 24
Peak memory 241060 kb
Host smart-3a43c3e2-9ef1-4092-a36a-10c8f9f5a2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713689908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.1713689908
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.3839412427
Short name T290
Test name
Test status
Simulation time 201744471 ps
CPU time 4.1 seconds
Started Apr 28 02:04:57 PM PDT 24
Finished Apr 28 02:05:02 PM PDT 24
Peak memory 241492 kb
Host smart-5c29e327-7cb1-4cf1-8ec4-bc5d3d49370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839412427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.3839412427
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.1538050448
Short name T602
Test name
Test status
Simulation time 2023603326 ps
CPU time 4.86 seconds
Started Apr 28 02:04:57 PM PDT 24
Finished Apr 28 02:05:03 PM PDT 24
Peak memory 241532 kb
Host smart-dff56a88-0509-4699-a7ff-4e680eb4c948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538050448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1538050448
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.40689784
Short name T838
Test name
Test status
Simulation time 559246831 ps
CPU time 4.38 seconds
Started Apr 28 02:05:04 PM PDT 24
Finished Apr 28 02:05:09 PM PDT 24
Peak memory 241396 kb
Host smart-2bc85586-db63-411b-a290-690837966e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40689784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.40689784
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.3151819919
Short name T1154
Test name
Test status
Simulation time 1217283802 ps
CPU time 9.74 seconds
Started Apr 28 02:05:03 PM PDT 24
Finished Apr 28 02:05:13 PM PDT 24
Peak memory 241804 kb
Host smart-ce793287-1eca-4645-b5e8-60db1f7c66ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151819919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.3151819919
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.1235392723
Short name T638
Test name
Test status
Simulation time 2429675470 ps
CPU time 5.71 seconds
Started Apr 28 02:05:03 PM PDT 24
Finished Apr 28 02:05:09 PM PDT 24
Peak memory 241720 kb
Host smart-db0573c8-fb78-4488-bfa5-fa662ddebc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235392723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.1235392723
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.1254109970
Short name T419
Test name
Test status
Simulation time 2109379269 ps
CPU time 14.39 seconds
Started Apr 28 02:05:05 PM PDT 24
Finished Apr 28 02:05:20 PM PDT 24
Peak memory 241396 kb
Host smart-02a7644e-7e1f-41dd-80b7-52cc25950ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254109970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.1254109970
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.4000965284
Short name T1044
Test name
Test status
Simulation time 477147604 ps
CPU time 4.12 seconds
Started Apr 28 02:05:04 PM PDT 24
Finished Apr 28 02:05:08 PM PDT 24
Peak memory 241460 kb
Host smart-f159ba57-dc12-4295-af65-735ee679917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000965284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.4000965284
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.3538578373
Short name T905
Test name
Test status
Simulation time 1275215294 ps
CPU time 3.7 seconds
Started Apr 28 02:05:03 PM PDT 24
Finished Apr 28 02:05:07 PM PDT 24
Peak memory 241240 kb
Host smart-4d6adce4-7c64-45df-8ee3-ff9bc44ac62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538578373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.3538578373
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.793152386
Short name T608
Test name
Test status
Simulation time 71973207 ps
CPU time 1.77 seconds
Started Apr 28 01:58:55 PM PDT 24
Finished Apr 28 01:58:57 PM PDT 24
Peak memory 239732 kb
Host smart-9b4e7b60-ecd7-4df7-a7cb-c8d33f85fabd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793152386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.793152386
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.876659386
Short name T848
Test name
Test status
Simulation time 1418584642 ps
CPU time 20.28 seconds
Started Apr 28 01:58:48 PM PDT 24
Finished Apr 28 01:59:09 PM PDT 24
Peak memory 241576 kb
Host smart-1a204e0a-f5bf-44e5-9970-2425f6ee90d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876659386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.876659386
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.3418242534
Short name T403
Test name
Test status
Simulation time 10218909954 ps
CPU time 33.59 seconds
Started Apr 28 01:58:48 PM PDT 24
Finished Apr 28 01:59:22 PM PDT 24
Peak memory 241888 kb
Host smart-2e9adeec-b13e-4e6f-b1f0-098279031e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418242534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.3418242534
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.2950301106
Short name T1042
Test name
Test status
Simulation time 1265081814 ps
CPU time 22.17 seconds
Started Apr 28 01:58:48 PM PDT 24
Finished Apr 28 01:59:11 PM PDT 24
Peak memory 241260 kb
Host smart-cae1482a-120b-4423-b687-de9b2b72e1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950301106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.2950301106
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.1579470401
Short name T116
Test name
Test status
Simulation time 367749592 ps
CPU time 4.45 seconds
Started Apr 28 01:58:43 PM PDT 24
Finished Apr 28 01:58:48 PM PDT 24
Peak memory 241440 kb
Host smart-2069d82a-889a-446c-9099-429da0fd319e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579470401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.1579470401
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.367530107
Short name T625
Test name
Test status
Simulation time 2542167652 ps
CPU time 16.32 seconds
Started Apr 28 01:58:49 PM PDT 24
Finished Apr 28 01:59:06 PM PDT 24
Peak memory 243076 kb
Host smart-ab02163d-a6fb-4120-945a-ca5b324137b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367530107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.367530107
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.967407789
Short name T515
Test name
Test status
Simulation time 973159380 ps
CPU time 11.71 seconds
Started Apr 28 01:58:48 PM PDT 24
Finished Apr 28 01:59:00 PM PDT 24
Peak memory 241624 kb
Host smart-aaff4a65-50a7-411d-9e75-89f02a430867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967407789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.967407789
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.3494105965
Short name T382
Test name
Test status
Simulation time 461066444 ps
CPU time 5.94 seconds
Started Apr 28 01:58:44 PM PDT 24
Finished Apr 28 01:58:50 PM PDT 24
Peak memory 241200 kb
Host smart-4b4ba53e-a27b-4536-9986-241416544ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494105965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.3494105965
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.753550000
Short name T442
Test name
Test status
Simulation time 620388306 ps
CPU time 20.06 seconds
Started Apr 28 01:58:43 PM PDT 24
Finished Apr 28 01:59:04 PM PDT 24
Peak memory 247876 kb
Host smart-e340e2a9-50ca-4db3-8f52-1aea6425cf2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753550000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.753550000
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.92374379
Short name T924
Test name
Test status
Simulation time 412426953 ps
CPU time 4.97 seconds
Started Apr 28 01:58:48 PM PDT 24
Finished Apr 28 01:58:54 PM PDT 24
Peak memory 241608 kb
Host smart-9be91551-f4bf-4791-a536-338393bd22e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92374379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.92374379
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.860077765
Short name T718
Test name
Test status
Simulation time 4526864636 ps
CPU time 16.98 seconds
Started Apr 28 01:58:47 PM PDT 24
Finished Apr 28 01:59:04 PM PDT 24
Peak memory 241416 kb
Host smart-77cad6ba-87e2-4c5c-b062-08eadd11c41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860077765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.860077765
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.1077718304
Short name T1007
Test name
Test status
Simulation time 101149075883 ps
CPU time 691.68 seconds
Started Apr 28 01:58:53 PM PDT 24
Finished Apr 28 02:10:25 PM PDT 24
Peak memory 313744 kb
Host smart-4ed1c168-8a7f-4274-8fa0-2096489b4c87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077718304 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.1077718304
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.1443821126
Short name T551
Test name
Test status
Simulation time 1839266664 ps
CPU time 12.83 seconds
Started Apr 28 01:58:47 PM PDT 24
Finished Apr 28 01:59:00 PM PDT 24
Peak memory 247952 kb
Host smart-1347c68d-e140-4237-a8cb-ccd784490679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443821126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.1443821126
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.2806031123
Short name T292
Test name
Test status
Simulation time 517052788 ps
CPU time 5.1 seconds
Started Apr 28 02:05:11 PM PDT 24
Finished Apr 28 02:05:16 PM PDT 24
Peak memory 241356 kb
Host smart-cbdc288b-2cb3-4abd-92b4-7b6e98db994e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806031123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2806031123
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.4247849320
Short name T894
Test name
Test status
Simulation time 2786607570 ps
CPU time 5.4 seconds
Started Apr 28 02:05:11 PM PDT 24
Finished Apr 28 02:05:16 PM PDT 24
Peak memory 241324 kb
Host smart-8ab7f371-2dc7-439f-8bd7-4b10a1d95d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247849320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.4247849320
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.1231304280
Short name T919
Test name
Test status
Simulation time 1732580358 ps
CPU time 5.95 seconds
Started Apr 28 02:05:08 PM PDT 24
Finished Apr 28 02:05:14 PM PDT 24
Peak memory 241716 kb
Host smart-03f0584a-0f4d-480a-a3de-1f9c05239d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231304280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.1231304280
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.3054436870
Short name T683
Test name
Test status
Simulation time 419917279 ps
CPU time 10.44 seconds
Started Apr 28 02:05:09 PM PDT 24
Finished Apr 28 02:05:19 PM PDT 24
Peak memory 241336 kb
Host smart-41dee991-b3c8-4c6c-8862-2b6ad9b6ecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054436870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.3054436870
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.4109146091
Short name T586
Test name
Test status
Simulation time 170031628 ps
CPU time 4.14 seconds
Started Apr 28 02:05:10 PM PDT 24
Finished Apr 28 02:05:14 PM PDT 24
Peak memory 241720 kb
Host smart-d112218a-0b43-482f-a72c-29dfd71c0c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109146091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.4109146091
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.1250657889
Short name T846
Test name
Test status
Simulation time 3568584581 ps
CPU time 6.94 seconds
Started Apr 28 02:05:11 PM PDT 24
Finished Apr 28 02:05:18 PM PDT 24
Peak memory 241848 kb
Host smart-5a5cf7f8-f591-45fc-8223-22e12c21dbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250657889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.1250657889
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.3953986816
Short name T1188
Test name
Test status
Simulation time 272843469 ps
CPU time 4.31 seconds
Started Apr 28 02:05:10 PM PDT 24
Finished Apr 28 02:05:15 PM PDT 24
Peak memory 241300 kb
Host smart-aae97d24-6946-4dba-9c79-b7349361d4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953986816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3953986816
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.4276823580
Short name T635
Test name
Test status
Simulation time 407757292 ps
CPU time 16.68 seconds
Started Apr 28 02:05:09 PM PDT 24
Finished Apr 28 02:05:26 PM PDT 24
Peak memory 241408 kb
Host smart-9a56be47-cf32-4130-bea4-5bf0d4bcf06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276823580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.4276823580
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.90056219
Short name T225
Test name
Test status
Simulation time 199204445 ps
CPU time 4.14 seconds
Started Apr 28 02:05:19 PM PDT 24
Finished Apr 28 02:05:24 PM PDT 24
Peak memory 241388 kb
Host smart-083b4b48-3dd6-4282-83d4-4892267fedfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90056219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.90056219
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.2643477773
Short name T63
Test name
Test status
Simulation time 497280965 ps
CPU time 4.09 seconds
Started Apr 28 02:05:13 PM PDT 24
Finished Apr 28 02:05:17 PM PDT 24
Peak memory 241492 kb
Host smart-0352b1b7-788c-453d-9875-212adec5d2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643477773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.2643477773
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.3376713089
Short name T788
Test name
Test status
Simulation time 325088899 ps
CPU time 18.37 seconds
Started Apr 28 02:05:14 PM PDT 24
Finished Apr 28 02:05:33 PM PDT 24
Peak memory 241176 kb
Host smart-c5500081-afbb-4d53-9bb6-1c2aeee905cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376713089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.3376713089
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.369694420
Short name T431
Test name
Test status
Simulation time 164124082 ps
CPU time 4.05 seconds
Started Apr 28 02:05:13 PM PDT 24
Finished Apr 28 02:05:17 PM PDT 24
Peak memory 241248 kb
Host smart-e80bdbe9-7440-49a2-8e84-949a4e4e5fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369694420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.369694420
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.3911984955
Short name T30
Test name
Test status
Simulation time 119297815 ps
CPU time 3.88 seconds
Started Apr 28 02:05:15 PM PDT 24
Finished Apr 28 02:05:19 PM PDT 24
Peak memory 241500 kb
Host smart-9b754c0e-aa5a-4f69-9ab8-4de1c288e2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911984955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.3911984955
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.2448965763
Short name T1136
Test name
Test status
Simulation time 1040850176 ps
CPU time 7.29 seconds
Started Apr 28 02:05:13 PM PDT 24
Finished Apr 28 02:05:20 PM PDT 24
Peak memory 241268 kb
Host smart-c4af996b-b018-493a-b5dd-196022ad1b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448965763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.2448965763
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.607784828
Short name T561
Test name
Test status
Simulation time 223660486 ps
CPU time 2.91 seconds
Started Apr 28 02:05:14 PM PDT 24
Finished Apr 28 02:05:18 PM PDT 24
Peak memory 241792 kb
Host smart-be404271-4bb8-457b-8eac-dda3730487aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607784828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.607784828
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.2005393637
Short name T623
Test name
Test status
Simulation time 168473622 ps
CPU time 7.05 seconds
Started Apr 28 02:05:16 PM PDT 24
Finished Apr 28 02:05:23 PM PDT 24
Peak memory 241300 kb
Host smart-7f9717e7-3e85-42d7-a066-14773d886f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005393637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.2005393637
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.1764653348
Short name T758
Test name
Test status
Simulation time 122077299 ps
CPU time 4.43 seconds
Started Apr 28 02:05:17 PM PDT 24
Finished Apr 28 02:05:22 PM PDT 24
Peak memory 241236 kb
Host smart-42162b36-d5f4-4f0c-9608-95efa4e55738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764653348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.1764653348
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.1414172537
Short name T537
Test name
Test status
Simulation time 1374023483 ps
CPU time 31.06 seconds
Started Apr 28 02:05:15 PM PDT 24
Finished Apr 28 02:05:46 PM PDT 24
Peak memory 241320 kb
Host smart-a7842adc-eb33-45f2-a14d-db8729ee6c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414172537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1414172537
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.418892708
Short name T580
Test name
Test status
Simulation time 923953046 ps
CPU time 2.23 seconds
Started Apr 28 01:59:03 PM PDT 24
Finished Apr 28 01:59:05 PM PDT 24
Peak memory 239828 kb
Host smart-851f0fa2-1dae-4a35-98fc-69da12f26dc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418892708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.418892708
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.2499122442
Short name T97
Test name
Test status
Simulation time 666493234 ps
CPU time 19.54 seconds
Started Apr 28 01:58:57 PM PDT 24
Finished Apr 28 01:59:17 PM PDT 24
Peak memory 241808 kb
Host smart-8825705f-f2d5-4079-bd02-31a73acad7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499122442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.2499122442
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.298282544
Short name T1169
Test name
Test status
Simulation time 456352790 ps
CPU time 12.83 seconds
Started Apr 28 01:58:58 PM PDT 24
Finished Apr 28 01:59:11 PM PDT 24
Peak memory 241348 kb
Host smart-a7bdd78b-f9a7-455a-b3c9-7c3db7edcd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298282544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.298282544
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.3644141096
Short name T733
Test name
Test status
Simulation time 701485705 ps
CPU time 28.4 seconds
Started Apr 28 01:58:58 PM PDT 24
Finished Apr 28 01:59:26 PM PDT 24
Peak memory 241796 kb
Host smart-44e7711c-c848-46b2-ac03-bb7b5759fb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644141096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.3644141096
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.455411644
Short name T73
Test name
Test status
Simulation time 2446792174 ps
CPU time 7.08 seconds
Started Apr 28 01:58:54 PM PDT 24
Finished Apr 28 01:59:01 PM PDT 24
Peak memory 241600 kb
Host smart-65f3a48e-3451-43ae-bbf2-ba400723a859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455411644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.455411644
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.553796473
Short name T1023
Test name
Test status
Simulation time 1030441954 ps
CPU time 24.77 seconds
Started Apr 28 01:58:57 PM PDT 24
Finished Apr 28 01:59:23 PM PDT 24
Peak memory 247988 kb
Host smart-cb3045d9-57e1-4c3d-babe-0f09d8e4801d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553796473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.553796473
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.609863305
Short name T1135
Test name
Test status
Simulation time 3128160303 ps
CPU time 17.57 seconds
Started Apr 28 01:58:58 PM PDT 24
Finished Apr 28 01:59:16 PM PDT 24
Peak memory 247972 kb
Host smart-879197eb-e0bf-4e24-a833-ca27d9980960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609863305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.609863305
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.196278078
Short name T417
Test name
Test status
Simulation time 445341840 ps
CPU time 6.22 seconds
Started Apr 28 01:58:57 PM PDT 24
Finished Apr 28 01:59:04 PM PDT 24
Peak memory 241864 kb
Host smart-756ccd6f-02e3-40ef-a6f4-3fc8a91e71ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196278078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.196278078
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.570963348
Short name T174
Test name
Test status
Simulation time 891753162 ps
CPU time 18.17 seconds
Started Apr 28 01:58:55 PM PDT 24
Finished Apr 28 01:59:13 PM PDT 24
Peak memory 241316 kb
Host smart-7e303f10-9a33-4cdc-ba09-f3e16863e874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570963348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.570963348
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.2844859759
Short name T367
Test name
Test status
Simulation time 2045668874 ps
CPU time 6.52 seconds
Started Apr 28 01:58:58 PM PDT 24
Finished Apr 28 01:59:04 PM PDT 24
Peak memory 241336 kb
Host smart-91dc5288-0d05-4e79-a544-d26e17124ff5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2844859759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.2844859759
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.2901343942
Short name T237
Test name
Test status
Simulation time 528398182 ps
CPU time 9.58 seconds
Started Apr 28 01:58:53 PM PDT 24
Finished Apr 28 01:59:03 PM PDT 24
Peak memory 241592 kb
Host smart-d9b98140-5529-4dc3-a0f3-909aaa8e7171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901343942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2901343942
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.671414605
Short name T1051
Test name
Test status
Simulation time 4829765125 ps
CPU time 92.38 seconds
Started Apr 28 01:59:02 PM PDT 24
Finished Apr 28 02:00:35 PM PDT 24
Peak memory 248124 kb
Host smart-2ca5fc89-5b0f-47d1-bbdc-08c8d940a0ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671414605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.
671414605
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.2491981565
Short name T280
Test name
Test status
Simulation time 208037062585 ps
CPU time 1236.78 seconds
Started Apr 28 01:59:03 PM PDT 24
Finished Apr 28 02:19:41 PM PDT 24
Peak memory 319784 kb
Host smart-1a38be85-5158-4122-a82e-a319cd577686
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491981565 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.2491981565
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.1923125825
Short name T405
Test name
Test status
Simulation time 10173881512 ps
CPU time 22.33 seconds
Started Apr 28 01:59:02 PM PDT 24
Finished Apr 28 01:59:25 PM PDT 24
Peak memory 242028 kb
Host smart-5aadc6cc-4aff-4b0f-9b3b-a9739ece921e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923125825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.1923125825
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.804138589
Short name T871
Test name
Test status
Simulation time 475289090 ps
CPU time 4.04 seconds
Started Apr 28 02:05:15 PM PDT 24
Finished Apr 28 02:05:19 PM PDT 24
Peak memory 241764 kb
Host smart-12b76958-1c23-4cc3-bf3b-63b2816874bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804138589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.804138589
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.2431847739
Short name T1100
Test name
Test status
Simulation time 1270752432 ps
CPU time 27.06 seconds
Started Apr 28 02:05:14 PM PDT 24
Finished Apr 28 02:05:41 PM PDT 24
Peak memory 247416 kb
Host smart-8a66f7f1-72ec-4a59-8814-39a06de9fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431847739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.2431847739
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.353982754
Short name T1026
Test name
Test status
Simulation time 127413067 ps
CPU time 3.4 seconds
Started Apr 28 02:05:21 PM PDT 24
Finished Apr 28 02:05:25 PM PDT 24
Peak memory 241776 kb
Host smart-1a7de949-9a5e-41b3-9ec7-2323f311ef85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353982754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.353982754
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.2244140111
Short name T1158
Test name
Test status
Simulation time 3416703969 ps
CPU time 7.82 seconds
Started Apr 28 02:05:24 PM PDT 24
Finished Apr 28 02:05:32 PM PDT 24
Peak memory 241324 kb
Host smart-338b150e-1514-4893-995a-407ff30f8f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244140111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.2244140111
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.3454314455
Short name T125
Test name
Test status
Simulation time 228745038 ps
CPU time 4.03 seconds
Started Apr 28 02:05:23 PM PDT 24
Finished Apr 28 02:05:27 PM PDT 24
Peak memory 241636 kb
Host smart-0522594f-a649-4cc8-9c5e-5760d2a9bea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454314455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.3454314455
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.2103412584
Short name T967
Test name
Test status
Simulation time 2061601634 ps
CPU time 17.02 seconds
Started Apr 28 02:05:19 PM PDT 24
Finished Apr 28 02:05:37 PM PDT 24
Peak memory 241512 kb
Host smart-1550ddf1-b39a-46d3-96bf-f33282f0f1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103412584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.2103412584
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.577774511
Short name T1155
Test name
Test status
Simulation time 495526295 ps
CPU time 11.11 seconds
Started Apr 28 02:05:20 PM PDT 24
Finished Apr 28 02:05:31 PM PDT 24
Peak memory 241268 kb
Host smart-5a6e63e4-4015-443c-8956-cc60bdb6feb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577774511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.577774511
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.2539850808
Short name T1114
Test name
Test status
Simulation time 419409301 ps
CPU time 3.97 seconds
Started Apr 28 02:05:23 PM PDT 24
Finished Apr 28 02:05:27 PM PDT 24
Peak memory 241660 kb
Host smart-aa4f190f-dbd5-4f90-8142-e55f8301bb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539850808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.2539850808
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.2203983778
Short name T590
Test name
Test status
Simulation time 522512003 ps
CPU time 4.64 seconds
Started Apr 28 02:05:19 PM PDT 24
Finished Apr 28 02:05:25 PM PDT 24
Peak memory 241324 kb
Host smart-32103201-e3f9-4e75-9b81-1aa6e0496cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203983778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2203983778
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.3332296362
Short name T677
Test name
Test status
Simulation time 277971291 ps
CPU time 4.61 seconds
Started Apr 28 02:05:20 PM PDT 24
Finished Apr 28 02:05:26 PM PDT 24
Peak memory 241272 kb
Host smart-6c80df66-10ef-4dc6-974f-1541a8715131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332296362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.3332296362
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.3018117750
Short name T441
Test name
Test status
Simulation time 303474719 ps
CPU time 3.94 seconds
Started Apr 28 02:05:24 PM PDT 24
Finished Apr 28 02:05:28 PM PDT 24
Peak memory 241160 kb
Host smart-6b708110-42be-4929-8339-ef296768d87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018117750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3018117750
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.280628710
Short name T484
Test name
Test status
Simulation time 560533506 ps
CPU time 4.76 seconds
Started Apr 28 02:05:24 PM PDT 24
Finished Apr 28 02:05:29 PM PDT 24
Peak memory 241728 kb
Host smart-76261ca6-0fdf-4702-870a-98381a34e84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280628710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.280628710
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.193385396
Short name T444
Test name
Test status
Simulation time 590570206 ps
CPU time 14.25 seconds
Started Apr 28 02:05:22 PM PDT 24
Finished Apr 28 02:05:36 PM PDT 24
Peak memory 241264 kb
Host smart-6c1c9df8-1a24-43dd-bc46-ef753cad9f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193385396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.193385396
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.1851887849
Short name T1050
Test name
Test status
Simulation time 1924625838 ps
CPU time 6.11 seconds
Started Apr 28 02:05:21 PM PDT 24
Finished Apr 28 02:05:28 PM PDT 24
Peak memory 241620 kb
Host smart-d6cb2f1d-a592-4e8c-8681-fce91c20534a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851887849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.1851887849
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.3029865785
Short name T1001
Test name
Test status
Simulation time 3912953081 ps
CPU time 11.3 seconds
Started Apr 28 02:05:20 PM PDT 24
Finished Apr 28 02:05:32 PM PDT 24
Peak memory 241848 kb
Host smart-4308a864-aad9-46c1-9ddb-52105e5c2dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029865785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.3029865785
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.1969475504
Short name T1150
Test name
Test status
Simulation time 323619795 ps
CPU time 4.09 seconds
Started Apr 28 02:05:27 PM PDT 24
Finished Apr 28 02:05:32 PM PDT 24
Peak memory 241368 kb
Host smart-6d39c66e-0b8b-49df-9ef4-aeb92fff6058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969475504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1969475504
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.2149927436
Short name T706
Test name
Test status
Simulation time 685849065 ps
CPU time 8.98 seconds
Started Apr 28 02:05:24 PM PDT 24
Finished Apr 28 02:05:34 PM PDT 24
Peak memory 241316 kb
Host smart-1ec142d9-31be-468e-87f0-f29d094c5b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149927436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.2149927436
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.3903152046
Short name T490
Test name
Test status
Simulation time 112630161 ps
CPU time 1.83 seconds
Started Apr 28 01:59:12 PM PDT 24
Finished Apr 28 01:59:14 PM PDT 24
Peak memory 239704 kb
Host smart-2b29d486-f71c-43c3-8618-21f7b8a3dfe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903152046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.3903152046
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.2159776620
Short name T991
Test name
Test status
Simulation time 1008263133 ps
CPU time 7.33 seconds
Started Apr 28 01:59:08 PM PDT 24
Finished Apr 28 01:59:16 PM PDT 24
Peak memory 241624 kb
Host smart-22a2eb72-47a9-4578-8a07-dc841b61d48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159776620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.2159776620
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.4088109006
Short name T660
Test name
Test status
Simulation time 1612547936 ps
CPU time 21.64 seconds
Started Apr 28 01:59:08 PM PDT 24
Finished Apr 28 01:59:31 PM PDT 24
Peak memory 241280 kb
Host smart-ef6717bc-c086-4fad-86ad-5bc9fd1650b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088109006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.4088109006
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.3848084272
Short name T749
Test name
Test status
Simulation time 389107124 ps
CPU time 5.91 seconds
Started Apr 28 01:59:09 PM PDT 24
Finished Apr 28 01:59:15 PM PDT 24
Peak memory 241268 kb
Host smart-f0da86a4-0d5d-423a-88cd-570e37cc0b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848084272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.3848084272
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.1201810248
Short name T1022
Test name
Test status
Simulation time 2320566731 ps
CPU time 4.16 seconds
Started Apr 28 01:59:08 PM PDT 24
Finished Apr 28 01:59:13 PM PDT 24
Peak memory 241396 kb
Host smart-123b1d8b-867e-46ec-84a3-76abf2c225f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201810248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.1201810248
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.2173967104
Short name T153
Test name
Test status
Simulation time 7348273464 ps
CPU time 47.61 seconds
Started Apr 28 01:59:08 PM PDT 24
Finished Apr 28 01:59:56 PM PDT 24
Peak memory 248164 kb
Host smart-d2c2bf9b-19cc-48bc-846c-f03734dececd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173967104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.2173967104
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.2722614721
Short name T1181
Test name
Test status
Simulation time 1240782981 ps
CPU time 15.67 seconds
Started Apr 28 01:59:08 PM PDT 24
Finished Apr 28 01:59:24 PM PDT 24
Peak memory 241404 kb
Host smart-917f0a22-fcd1-4d39-b5e4-6518b14e3fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722614721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2722614721
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.3237769265
Short name T873
Test name
Test status
Simulation time 641859931 ps
CPU time 16.92 seconds
Started Apr 28 01:59:08 PM PDT 24
Finished Apr 28 01:59:26 PM PDT 24
Peak memory 241396 kb
Host smart-ff9998c6-d510-4f59-9eb9-b5133947612e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237769265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.3237769265
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.4294689243
Short name T725
Test name
Test status
Simulation time 713274017 ps
CPU time 10.7 seconds
Started Apr 28 01:59:07 PM PDT 24
Finished Apr 28 01:59:19 PM PDT 24
Peak memory 241316 kb
Host smart-ba75f667-bd56-44ca-ace6-6886c4d7d007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294689243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.4294689243
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.1618258437
Short name T723
Test name
Test status
Simulation time 338541704 ps
CPU time 6.47 seconds
Started Apr 28 01:59:07 PM PDT 24
Finished Apr 28 01:59:14 PM PDT 24
Peak memory 241680 kb
Host smart-d32fb8ff-b6d3-4e48-9649-700e003d24ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1618258437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.1618258437
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.176182904
Short name T763
Test name
Test status
Simulation time 393501245 ps
CPU time 9.23 seconds
Started Apr 28 01:59:03 PM PDT 24
Finished Apr 28 01:59:13 PM PDT 24
Peak memory 241096 kb
Host smart-6dc7e279-be4e-4a79-af47-c3fd01a178a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176182904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.176182904
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.3480591384
Short name T884
Test name
Test status
Simulation time 9298313081 ps
CPU time 125.32 seconds
Started Apr 28 01:59:13 PM PDT 24
Finished Apr 28 02:01:18 PM PDT 24
Peak memory 256300 kb
Host smart-bec98530-4bc4-44be-a06f-646ec043d03c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480591384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.3480591384
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.3880031985
Short name T40
Test name
Test status
Simulation time 141956576792 ps
CPU time 878.95 seconds
Started Apr 28 01:59:16 PM PDT 24
Finished Apr 28 02:13:55 PM PDT 24
Peak memory 280940 kb
Host smart-5c4d0a94-f92c-4157-a777-786edae2f18e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880031985 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.3880031985
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.3413463794
Short name T583
Test name
Test status
Simulation time 6481694931 ps
CPU time 57.94 seconds
Started Apr 28 01:59:07 PM PDT 24
Finished Apr 28 02:00:06 PM PDT 24
Peak memory 242492 kb
Host smart-ef49efc2-d4a6-43f2-98d4-767392d73c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413463794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.3413463794
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.3013509262
Short name T768
Test name
Test status
Simulation time 245810623 ps
CPU time 3.84 seconds
Started Apr 28 02:05:25 PM PDT 24
Finished Apr 28 02:05:30 PM PDT 24
Peak memory 241288 kb
Host smart-1e2a6ef2-a24b-4ce3-ae7a-80e4e6769278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013509262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.3013509262
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.1234515506
Short name T1012
Test name
Test status
Simulation time 3056967972 ps
CPU time 22.76 seconds
Started Apr 28 02:05:27 PM PDT 24
Finished Apr 28 02:05:50 PM PDT 24
Peak memory 241848 kb
Host smart-08f554ba-4440-4b0e-8006-115c9f3c5ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234515506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.1234515506
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.1839556574
Short name T1140
Test name
Test status
Simulation time 121904725 ps
CPU time 4.05 seconds
Started Apr 28 02:05:28 PM PDT 24
Finished Apr 28 02:05:32 PM PDT 24
Peak memory 241844 kb
Host smart-dbf05ab6-ba96-447c-919d-a19666498a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839556574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.1839556574
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.92776349
Short name T655
Test name
Test status
Simulation time 657396761 ps
CPU time 5.65 seconds
Started Apr 28 02:05:27 PM PDT 24
Finished Apr 28 02:05:33 PM PDT 24
Peak memory 241296 kb
Host smart-d4c1f0f9-6b2f-452b-9e5f-02c1294668ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92776349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.92776349
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.3724263441
Short name T36
Test name
Test status
Simulation time 185484054 ps
CPU time 4.38 seconds
Started Apr 28 02:05:25 PM PDT 24
Finished Apr 28 02:05:29 PM PDT 24
Peak memory 241380 kb
Host smart-5135995b-d3de-453b-a156-382fdabe95b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724263441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.3724263441
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.3210443197
Short name T51
Test name
Test status
Simulation time 1841433537 ps
CPU time 5.04 seconds
Started Apr 28 02:05:25 PM PDT 24
Finished Apr 28 02:05:31 PM PDT 24
Peak memory 241648 kb
Host smart-94762fe0-4919-49b1-8da6-93562f72eef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210443197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.3210443197
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.647731479
Short name T976
Test name
Test status
Simulation time 310306687 ps
CPU time 6.84 seconds
Started Apr 28 02:05:25 PM PDT 24
Finished Apr 28 02:05:32 PM PDT 24
Peak memory 241484 kb
Host smart-daf28b93-f55b-44ca-9d86-7ae8a9b5b7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647731479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.647731479
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.674714635
Short name T637
Test name
Test status
Simulation time 144934797 ps
CPU time 4.68 seconds
Started Apr 28 02:05:27 PM PDT 24
Finished Apr 28 02:05:33 PM PDT 24
Peak memory 241776 kb
Host smart-f1f96674-2d39-4f2f-a428-34917254b005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674714635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.674714635
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.164783772
Short name T673
Test name
Test status
Simulation time 886094255 ps
CPU time 16.95 seconds
Started Apr 28 02:05:25 PM PDT 24
Finished Apr 28 02:05:43 PM PDT 24
Peak memory 241556 kb
Host smart-df0aa05f-c97f-45c6-bda4-80011c27fad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164783772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.164783772
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.3062144490
Short name T782
Test name
Test status
Simulation time 223131708 ps
CPU time 3.66 seconds
Started Apr 28 02:05:31 PM PDT 24
Finished Apr 28 02:05:35 PM PDT 24
Peak memory 241636 kb
Host smart-a5d75aa0-d111-4268-9f70-016c9383d8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062144490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.3062144490
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.3604121012
Short name T508
Test name
Test status
Simulation time 171664872 ps
CPU time 4.79 seconds
Started Apr 28 02:05:31 PM PDT 24
Finished Apr 28 02:05:36 PM PDT 24
Peak memory 241244 kb
Host smart-893500ce-7293-41f5-917d-3181dc693503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604121012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3604121012
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.2987910633
Short name T296
Test name
Test status
Simulation time 457227147 ps
CPU time 4.87 seconds
Started Apr 28 02:05:31 PM PDT 24
Finished Apr 28 02:05:36 PM PDT 24
Peak memory 241784 kb
Host smart-922666fa-a164-4a4e-b596-c17e52143e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987910633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.2987910633
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.602099755
Short name T166
Test name
Test status
Simulation time 228456208 ps
CPU time 3.65 seconds
Started Apr 28 02:05:32 PM PDT 24
Finished Apr 28 02:05:36 PM PDT 24
Peak memory 241532 kb
Host smart-e9babd09-fa9f-4fd4-beb2-bce8db63f642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602099755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.602099755
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.1401002910
Short name T410
Test name
Test status
Simulation time 467830253 ps
CPU time 12.25 seconds
Started Apr 28 02:05:31 PM PDT 24
Finished Apr 28 02:05:43 PM PDT 24
Peak memory 241692 kb
Host smart-c337a64b-314d-496a-9551-29fa92822991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401002910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.1401002910
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.3991700415
Short name T1176
Test name
Test status
Simulation time 173700979 ps
CPU time 3.89 seconds
Started Apr 28 02:05:31 PM PDT 24
Finished Apr 28 02:05:35 PM PDT 24
Peak memory 241668 kb
Host smart-8c59046b-b6ad-4d7f-a9df-ab2bcf44901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991700415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.3991700415
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.2936915448
Short name T628
Test name
Test status
Simulation time 1287792056 ps
CPU time 3.94 seconds
Started Apr 28 02:05:31 PM PDT 24
Finished Apr 28 02:05:36 PM PDT 24
Peak memory 241596 kb
Host smart-6732daeb-5eb0-4d2a-a27d-7d14a630db1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936915448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.2936915448
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.2215460461
Short name T546
Test name
Test status
Simulation time 272823695 ps
CPU time 4.17 seconds
Started Apr 28 02:05:37 PM PDT 24
Finished Apr 28 02:05:42 PM PDT 24
Peak memory 241308 kb
Host smart-059c93b2-b5b2-4783-9358-cf1dd758e080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215460461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.2215460461
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.3455125487
Short name T472
Test name
Test status
Simulation time 989257620 ps
CPU time 13.46 seconds
Started Apr 28 02:05:38 PM PDT 24
Finished Apr 28 02:05:52 PM PDT 24
Peak memory 241676 kb
Host smart-396b7c3e-78c2-490f-be4e-8dc25d831104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455125487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.3455125487
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.2007836776
Short name T416
Test name
Test status
Simulation time 66160670 ps
CPU time 2.11 seconds
Started Apr 28 01:59:18 PM PDT 24
Finished Apr 28 01:59:20 PM PDT 24
Peak memory 239944 kb
Host smart-1308e516-9caa-4fe1-935f-c96002e2ec1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007836776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.2007836776
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.540685010
Short name T84
Test name
Test status
Simulation time 4690779830 ps
CPU time 10.69 seconds
Started Apr 28 01:59:11 PM PDT 24
Finished Apr 28 01:59:22 PM PDT 24
Peak memory 248076 kb
Host smart-928d7f66-622b-45a5-86e1-c38d100ee09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540685010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.540685010
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.3714546124
Short name T1143
Test name
Test status
Simulation time 17513635208 ps
CPU time 54.24 seconds
Started Apr 28 01:59:13 PM PDT 24
Finished Apr 28 02:00:08 PM PDT 24
Peak memory 248824 kb
Host smart-a54d8183-2891-4f3c-b286-56b1d5f98f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714546124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.3714546124
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.370261198
Short name T1040
Test name
Test status
Simulation time 1671617041 ps
CPU time 14.99 seconds
Started Apr 28 01:59:12 PM PDT 24
Finished Apr 28 01:59:28 PM PDT 24
Peak memory 247964 kb
Host smart-a79d3122-e5ca-47b5-96c1-a7879b65d453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370261198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.370261198
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.3103328153
Short name T460
Test name
Test status
Simulation time 299165426 ps
CPU time 4.97 seconds
Started Apr 28 01:59:13 PM PDT 24
Finished Apr 28 01:59:18 PM PDT 24
Peak memory 241608 kb
Host smart-a38f7abe-a44c-4aa9-8a0c-3c86baccc031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103328153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.3103328153
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.772890765
Short name T659
Test name
Test status
Simulation time 8058500530 ps
CPU time 28.32 seconds
Started Apr 28 01:59:23 PM PDT 24
Finished Apr 28 01:59:52 PM PDT 24
Peak memory 241620 kb
Host smart-8c5dccbc-023b-4f35-b5fe-4d3fd40a6a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772890765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.772890765
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.1868546161
Short name T187
Test name
Test status
Simulation time 11470138593 ps
CPU time 33.95 seconds
Started Apr 28 01:59:23 PM PDT 24
Finished Apr 28 01:59:58 PM PDT 24
Peak memory 242516 kb
Host smart-31a7fa2c-8398-41c6-9816-525f456a3943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868546161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.1868546161
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.834843998
Short name T611
Test name
Test status
Simulation time 497251888 ps
CPU time 6.64 seconds
Started Apr 28 01:59:13 PM PDT 24
Finished Apr 28 01:59:20 PM PDT 24
Peak memory 241356 kb
Host smart-ffc2db8f-ab86-4e59-924c-071d2159ea02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834843998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.834843998
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.485775133
Short name T787
Test name
Test status
Simulation time 247865459 ps
CPU time 7.35 seconds
Started Apr 28 01:59:11 PM PDT 24
Finished Apr 28 01:59:19 PM PDT 24
Peak memory 241332 kb
Host smart-2475b82c-5f9e-4199-bf91-1c7990b11c14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485775133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.485775133
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.641135065
Short name T870
Test name
Test status
Simulation time 596082186 ps
CPU time 11.9 seconds
Started Apr 28 01:59:17 PM PDT 24
Finished Apr 28 01:59:29 PM PDT 24
Peak memory 241528 kb
Host smart-aa58fc56-3e82-4f5b-bc24-89e2631c1980
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641135065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.641135065
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.1747364452
Short name T1011
Test name
Test status
Simulation time 216264190 ps
CPU time 4.12 seconds
Started Apr 28 01:59:15 PM PDT 24
Finished Apr 28 01:59:19 PM PDT 24
Peak memory 241264 kb
Host smart-fc552bad-e7d4-4e15-a072-ee9a296d81a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747364452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.1747364452
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.3247667403
Short name T818
Test name
Test status
Simulation time 3312932398 ps
CPU time 17.92 seconds
Started Apr 28 01:59:23 PM PDT 24
Finished Apr 28 01:59:41 PM PDT 24
Peak memory 243780 kb
Host smart-f15ef69d-c9d7-4fac-8e63-047d8c11c874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247667403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.3247667403
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.2848896147
Short name T137
Test name
Test status
Simulation time 383306728254 ps
CPU time 2549.1 seconds
Started Apr 28 01:59:24 PM PDT 24
Finished Apr 28 02:41:54 PM PDT 24
Peak memory 301440 kb
Host smart-fe5a00f8-15f9-4ad0-854a-b804168c5b07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848896147 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.2848896147
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.2782144199
Short name T1070
Test name
Test status
Simulation time 365548509 ps
CPU time 11.76 seconds
Started Apr 28 01:59:22 PM PDT 24
Finished Apr 28 01:59:35 PM PDT 24
Peak memory 247900 kb
Host smart-6a835df2-9274-4f1e-be73-229f5f71d368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782144199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.2782144199
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.1992643056
Short name T1162
Test name
Test status
Simulation time 396803631 ps
CPU time 3.15 seconds
Started Apr 28 02:05:37 PM PDT 24
Finished Apr 28 02:05:41 PM PDT 24
Peak memory 241680 kb
Host smart-b908e3ad-fb63-4d82-a8b9-02eec1e31c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992643056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.1992643056
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.763662705
Short name T346
Test name
Test status
Simulation time 337730386 ps
CPU time 10.23 seconds
Started Apr 28 02:05:41 PM PDT 24
Finished Apr 28 02:05:52 PM PDT 24
Peak memory 241272 kb
Host smart-30dd367e-a145-48c9-90ec-321b60c0af26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763662705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.763662705
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.3698014441
Short name T909
Test name
Test status
Simulation time 2278784606 ps
CPU time 7.31 seconds
Started Apr 28 02:05:36 PM PDT 24
Finished Apr 28 02:05:44 PM PDT 24
Peak memory 241876 kb
Host smart-88b6a31a-2f3f-4d12-9423-720805ed83db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698014441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.3698014441
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.680165386
Short name T411
Test name
Test status
Simulation time 226478572 ps
CPU time 4.58 seconds
Started Apr 28 02:05:39 PM PDT 24
Finished Apr 28 02:05:44 PM PDT 24
Peak memory 241212 kb
Host smart-11c5b5e2-6fd9-496e-ba98-51130239bd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680165386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.680165386
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.1894244048
Short name T13
Test name
Test status
Simulation time 178807003 ps
CPU time 3.8 seconds
Started Apr 28 02:05:39 PM PDT 24
Finished Apr 28 02:05:43 PM PDT 24
Peak memory 241360 kb
Host smart-5bdea797-622c-4e29-a4ef-b159ba69a3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894244048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1894244048
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.1877645734
Short name T1106
Test name
Test status
Simulation time 988845946 ps
CPU time 8.04 seconds
Started Apr 28 02:05:37 PM PDT 24
Finished Apr 28 02:05:46 PM PDT 24
Peak memory 241308 kb
Host smart-767f4cf2-6e20-4d91-a72d-a512a22b05ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877645734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1877645734
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.1215849379
Short name T74
Test name
Test status
Simulation time 108742550 ps
CPU time 3.28 seconds
Started Apr 28 02:05:37 PM PDT 24
Finished Apr 28 02:05:41 PM PDT 24
Peak memory 241732 kb
Host smart-3712389a-a4bd-45e7-bf4e-5cbe399799e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215849379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.1215849379
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.2110007991
Short name T246
Test name
Test status
Simulation time 1707172628 ps
CPU time 6.49 seconds
Started Apr 28 02:05:41 PM PDT 24
Finished Apr 28 02:05:48 PM PDT 24
Peak memory 241256 kb
Host smart-6a9c5541-2af7-4d3c-8476-5170c4ba86b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110007991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.2110007991
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.3841855690
Short name T690
Test name
Test status
Simulation time 1770649251 ps
CPU time 5.74 seconds
Started Apr 28 02:05:37 PM PDT 24
Finished Apr 28 02:05:43 PM PDT 24
Peak memory 241824 kb
Host smart-9ebeef83-0905-4907-b35b-5fd709a3d417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841855690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.3841855690
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.4128008524
Short name T150
Test name
Test status
Simulation time 423831644 ps
CPU time 13.9 seconds
Started Apr 28 02:05:40 PM PDT 24
Finished Apr 28 02:05:54 PM PDT 24
Peak memory 241388 kb
Host smart-703d4eaa-2c4a-4c11-9457-9bdef41ee92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128008524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.4128008524
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.2309839974
Short name T633
Test name
Test status
Simulation time 132332035 ps
CPU time 3.34 seconds
Started Apr 28 02:05:41 PM PDT 24
Finished Apr 28 02:05:45 PM PDT 24
Peak memory 241728 kb
Host smart-5c4d0f26-afe5-4663-b48b-9b5ed1bb3d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309839974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.2309839974
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.3596208619
Short name T743
Test name
Test status
Simulation time 515237947 ps
CPU time 6.41 seconds
Started Apr 28 02:05:44 PM PDT 24
Finished Apr 28 02:05:51 PM PDT 24
Peak memory 241452 kb
Host smart-d828ba29-9021-4a67-b2df-a48261bb3130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596208619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.3596208619
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.2485855436
Short name T189
Test name
Test status
Simulation time 191692090 ps
CPU time 3.11 seconds
Started Apr 28 02:05:44 PM PDT 24
Finished Apr 28 02:05:47 PM PDT 24
Peak memory 241452 kb
Host smart-f5314096-fa0f-4d75-8fde-2cc3dabb8c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485855436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.2485855436
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.1520774568
Short name T504
Test name
Test status
Simulation time 509802711 ps
CPU time 6.44 seconds
Started Apr 28 02:05:46 PM PDT 24
Finished Apr 28 02:05:53 PM PDT 24
Peak memory 241444 kb
Host smart-07a17ef7-9b77-49c9-9f35-a951ba8b0d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520774568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.1520774568
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.3000885369
Short name T94
Test name
Test status
Simulation time 1823635653 ps
CPU time 5.41 seconds
Started Apr 28 02:05:44 PM PDT 24
Finished Apr 28 02:05:50 PM PDT 24
Peak memory 241348 kb
Host smart-e49a2e4f-4c1d-4745-8de9-4372f92e4f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000885369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.3000885369
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.1040306189
Short name T1059
Test name
Test status
Simulation time 699380346 ps
CPU time 9.29 seconds
Started Apr 28 02:05:43 PM PDT 24
Finished Apr 28 02:05:53 PM PDT 24
Peak memory 241520 kb
Host smart-c5f350d6-a71d-4d19-8b6d-71f36c75ca72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040306189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.1040306189
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.1034570609
Short name T164
Test name
Test status
Simulation time 107334641 ps
CPU time 3.83 seconds
Started Apr 28 02:05:43 PM PDT 24
Finished Apr 28 02:05:47 PM PDT 24
Peak memory 241376 kb
Host smart-09e3eedf-d008-4c45-b3e5-9e71996c474a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034570609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.1034570609
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.4177543473
Short name T979
Test name
Test status
Simulation time 240487711 ps
CPU time 12.67 seconds
Started Apr 28 02:05:46 PM PDT 24
Finished Apr 28 02:05:59 PM PDT 24
Peak memory 241120 kb
Host smart-9bb4a9c9-9c17-442e-a872-ab82bd7b9383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177543473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.4177543473
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.1204984201
Short name T1032
Test name
Test status
Simulation time 299637404 ps
CPU time 3.38 seconds
Started Apr 28 02:05:43 PM PDT 24
Finished Apr 28 02:05:47 PM PDT 24
Peak memory 241432 kb
Host smart-d8bd372d-6077-4254-9682-aa1ad61ecd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204984201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.1204984201
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.4018888922
Short name T988
Test name
Test status
Simulation time 170685733 ps
CPU time 2.58 seconds
Started Apr 28 02:05:42 PM PDT 24
Finished Apr 28 02:05:45 PM PDT 24
Peak memory 241348 kb
Host smart-85e3562e-052d-49af-9baa-d7fea8c61054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018888922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.4018888922
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.3200153159
Short name T830
Test name
Test status
Simulation time 168705703 ps
CPU time 1.51 seconds
Started Apr 28 01:59:30 PM PDT 24
Finished Apr 28 01:59:32 PM PDT 24
Peak memory 240032 kb
Host smart-3801fef4-7c44-4965-a611-88d883964776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200153159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.3200153159
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.1490073045
Short name T33
Test name
Test status
Simulation time 9686321006 ps
CPU time 16.71 seconds
Started Apr 28 01:59:31 PM PDT 24
Finished Apr 28 01:59:48 PM PDT 24
Peak memory 242020 kb
Host smart-ef2bceac-fa3a-42de-b6d5-8fd42c7e030c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490073045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1490073045
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.411374964
Short name T593
Test name
Test status
Simulation time 279041926 ps
CPU time 14.8 seconds
Started Apr 28 01:59:21 PM PDT 24
Finished Apr 28 01:59:36 PM PDT 24
Peak memory 241384 kb
Host smart-5ba3e2b4-3574-42e7-97ff-e3b2979fb4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411374964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.411374964
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.1885987194
Short name T378
Test name
Test status
Simulation time 8812222329 ps
CPU time 46.54 seconds
Started Apr 28 01:59:30 PM PDT 24
Finished Apr 28 02:00:18 PM PDT 24
Peak memory 247972 kb
Host smart-30e6ce5c-3501-4b4c-bba3-17518effe74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885987194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.1885987194
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.1450915792
Short name T1063
Test name
Test status
Simulation time 168038442 ps
CPU time 3.88 seconds
Started Apr 28 01:59:30 PM PDT 24
Finished Apr 28 01:59:35 PM PDT 24
Peak memory 241312 kb
Host smart-cea9ae87-75fc-4cc4-973e-7b7390159420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450915792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.1450915792
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.1003911669
Short name T963
Test name
Test status
Simulation time 903326157 ps
CPU time 14.44 seconds
Started Apr 28 01:59:27 PM PDT 24
Finished Apr 28 01:59:41 PM PDT 24
Peak memory 241460 kb
Host smart-74ff45ec-d674-4da1-96e5-4b6eff2cfccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003911669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1003911669
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.4294117288
Short name T1035
Test name
Test status
Simulation time 13801454612 ps
CPU time 28.94 seconds
Started Apr 28 01:59:30 PM PDT 24
Finished Apr 28 02:00:00 PM PDT 24
Peak memory 242516 kb
Host smart-82686ef5-ee07-4223-94f2-c0f7fe3f07f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294117288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.4294117288
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.1865434098
Short name T793
Test name
Test status
Simulation time 183663246 ps
CPU time 3.95 seconds
Started Apr 28 01:59:18 PM PDT 24
Finished Apr 28 01:59:22 PM PDT 24
Peak memory 241576 kb
Host smart-41e03c10-a7e5-4e14-b38d-3c57e392834c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865434098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.1865434098
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.3021165118
Short name T1076
Test name
Test status
Simulation time 1381207432 ps
CPU time 18.34 seconds
Started Apr 28 01:59:22 PM PDT 24
Finished Apr 28 01:59:40 PM PDT 24
Peak memory 247892 kb
Host smart-6d3be687-a08d-430f-a963-957a1af0113b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3021165118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.3021165118
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.1146003048
Short name T262
Test name
Test status
Simulation time 345535139 ps
CPU time 6.3 seconds
Started Apr 28 01:59:22 PM PDT 24
Finished Apr 28 01:59:29 PM PDT 24
Peak memory 241248 kb
Host smart-aa9099ac-cb09-4bf8-8947-ca807a3d13d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1146003048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1146003048
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.927246240
Short name T707
Test name
Test status
Simulation time 305736723 ps
CPU time 6.83 seconds
Started Apr 28 01:59:25 PM PDT 24
Finished Apr 28 01:59:33 PM PDT 24
Peak memory 241144 kb
Host smart-cc9ee446-dfa3-40d0-9c02-71409fcd4476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927246240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.927246240
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.3175670298
Short name T978
Test name
Test status
Simulation time 30234390623 ps
CPU time 150.09 seconds
Started Apr 28 01:59:31 PM PDT 24
Finished Apr 28 02:02:02 PM PDT 24
Peak memory 254700 kb
Host smart-66355daf-b0da-46b4-b103-b4984b21a984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175670298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.3175670298
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.1552236430
Short name T21
Test name
Test status
Simulation time 91412163415 ps
CPU time 1030.96 seconds
Started Apr 28 01:59:23 PM PDT 24
Finished Apr 28 02:16:35 PM PDT 24
Peak memory 280756 kb
Host smart-43bec6d8-df89-4c2e-bf4b-03342497f92d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552236430 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.1552236430
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.2788053614
Short name T298
Test name
Test status
Simulation time 543595784 ps
CPU time 10.06 seconds
Started Apr 28 01:59:30 PM PDT 24
Finished Apr 28 01:59:41 PM PDT 24
Peak memory 241208 kb
Host smart-7cd2a314-3cad-4620-98aa-0e9ab4dc26d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788053614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.2788053614
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.17550742
Short name T705
Test name
Test status
Simulation time 2146407348 ps
CPU time 5.58 seconds
Started Apr 28 02:05:54 PM PDT 24
Finished Apr 28 02:06:00 PM PDT 24
Peak memory 241448 kb
Host smart-6ac86f17-2284-44ab-99c3-d5588b68f2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17550742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.17550742
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.1952983009
Short name T627
Test name
Test status
Simulation time 131346657 ps
CPU time 5.72 seconds
Started Apr 28 02:05:48 PM PDT 24
Finished Apr 28 02:05:54 PM PDT 24
Peak memory 241652 kb
Host smart-8e1939b8-4f27-4a86-984b-5961a6a000b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952983009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.1952983009
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.1546033655
Short name T699
Test name
Test status
Simulation time 255119338 ps
CPU time 3.88 seconds
Started Apr 28 02:05:49 PM PDT 24
Finished Apr 28 02:05:53 PM PDT 24
Peak memory 241428 kb
Host smart-2c2c9464-a453-4945-be7e-764ceb6518d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546033655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.1546033655
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.3515111095
Short name T1084
Test name
Test status
Simulation time 911826835 ps
CPU time 5.95 seconds
Started Apr 28 02:05:49 PM PDT 24
Finished Apr 28 02:05:55 PM PDT 24
Peak memory 241744 kb
Host smart-cd96f85d-692e-49a7-be3a-0cc3d184b590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515111095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.3515111095
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.38920859
Short name T826
Test name
Test status
Simulation time 105437928 ps
CPU time 3.1 seconds
Started Apr 28 02:05:48 PM PDT 24
Finished Apr 28 02:05:51 PM PDT 24
Peak memory 241760 kb
Host smart-8724c32f-3659-4c63-bb9c-8babed6c304d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38920859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.38920859
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.4001113259
Short name T977
Test name
Test status
Simulation time 445484687 ps
CPU time 4.62 seconds
Started Apr 28 02:05:54 PM PDT 24
Finished Apr 28 02:06:00 PM PDT 24
Peak memory 241604 kb
Host smart-325476bd-c092-4208-a188-4d372b4ce7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001113259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.4001113259
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.1407608878
Short name T528
Test name
Test status
Simulation time 366483281 ps
CPU time 3.42 seconds
Started Apr 28 02:05:50 PM PDT 24
Finished Apr 28 02:05:53 PM PDT 24
Peak memory 241528 kb
Host smart-025cbe84-7ab7-4012-adbd-2b0c536633cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407608878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.1407608878
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.1376562082
Short name T853
Test name
Test status
Simulation time 1116616697 ps
CPU time 28.35 seconds
Started Apr 28 02:05:49 PM PDT 24
Finished Apr 28 02:06:18 PM PDT 24
Peak memory 241728 kb
Host smart-fb1a8bf5-6e33-4803-9269-6308016f078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376562082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1376562082
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.2388206485
Short name T657
Test name
Test status
Simulation time 113347286 ps
CPU time 4.14 seconds
Started Apr 28 02:05:48 PM PDT 24
Finished Apr 28 02:05:52 PM PDT 24
Peak memory 241664 kb
Host smart-ab068fb4-7993-44a2-ad86-e2192ab36888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388206485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.2388206485
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.1324326203
Short name T819
Test name
Test status
Simulation time 567857036 ps
CPU time 13.06 seconds
Started Apr 28 02:05:48 PM PDT 24
Finished Apr 28 02:06:01 PM PDT 24
Peak memory 241200 kb
Host smart-0972a92e-0275-44b8-bb8c-29a1046bd771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324326203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.1324326203
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.214736021
Short name T1015
Test name
Test status
Simulation time 158394082 ps
CPU time 4.45 seconds
Started Apr 28 02:05:54 PM PDT 24
Finished Apr 28 02:05:58 PM PDT 24
Peak memory 241260 kb
Host smart-7405588b-9bdd-4232-814e-b22e3c59726f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214736021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.214736021
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.1296624711
Short name T764
Test name
Test status
Simulation time 358584659 ps
CPU time 10.7 seconds
Started Apr 28 02:05:53 PM PDT 24
Finished Apr 28 02:06:05 PM PDT 24
Peak memory 241384 kb
Host smart-758ed7b7-e5e3-4a6a-b5c7-42066fb93114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296624711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.1296624711
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.3228074275
Short name T530
Test name
Test status
Simulation time 110817447 ps
CPU time 3.29 seconds
Started Apr 28 02:05:55 PM PDT 24
Finished Apr 28 02:05:59 PM PDT 24
Peak memory 241688 kb
Host smart-d8967c47-c90b-4446-a547-da3026c4255b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228074275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.3228074275
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.4163058464
Short name T147
Test name
Test status
Simulation time 1026025904 ps
CPU time 8.82 seconds
Started Apr 28 02:05:56 PM PDT 24
Finished Apr 28 02:06:05 PM PDT 24
Peak memory 241308 kb
Host smart-140f711b-41d2-486b-9e0a-9092ddac5df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163058464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.4163058464
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.2994244300
Short name T670
Test name
Test status
Simulation time 1578974332 ps
CPU time 3.48 seconds
Started Apr 28 02:05:52 PM PDT 24
Finished Apr 28 02:05:56 PM PDT 24
Peak memory 241716 kb
Host smart-94ba88ff-2c4a-4eba-8c10-b695d2ac4d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994244300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.2994244300
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.933876922
Short name T480
Test name
Test status
Simulation time 144694218 ps
CPU time 4.14 seconds
Started Apr 28 02:05:54 PM PDT 24
Finished Apr 28 02:05:59 PM PDT 24
Peak memory 241276 kb
Host smart-454d8150-0ff0-4d03-8d05-6d8d755d7876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933876922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.933876922
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.3326212878
Short name T527
Test name
Test status
Simulation time 423764675 ps
CPU time 4.64 seconds
Started Apr 28 02:05:55 PM PDT 24
Finished Apr 28 02:06:00 PM PDT 24
Peak memory 241280 kb
Host smart-996c3b92-a40b-4ef1-b3e0-e024b8746a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326212878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.3326212878
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.135866142
Short name T347
Test name
Test status
Simulation time 434297400 ps
CPU time 3.13 seconds
Started Apr 28 02:05:54 PM PDT 24
Finished Apr 28 02:05:58 PM PDT 24
Peak memory 241800 kb
Host smart-3eb91f31-b944-4612-a62c-10d3f95cedaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135866142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.135866142
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.2186986336
Short name T503
Test name
Test status
Simulation time 2260298981 ps
CPU time 5.68 seconds
Started Apr 28 02:05:54 PM PDT 24
Finished Apr 28 02:06:00 PM PDT 24
Peak memory 241852 kb
Host smart-7f0d51a3-f86e-4408-aa6a-aa03d82e8c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186986336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2186986336
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.1384685699
Short name T494
Test name
Test status
Simulation time 1085954191 ps
CPU time 2.69 seconds
Started Apr 28 02:05:55 PM PDT 24
Finished Apr 28 02:05:58 PM PDT 24
Peak memory 241656 kb
Host smart-542c712a-e49e-42cd-9e8b-fe7dca6f91f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384685699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.1384685699
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.2134501815
Short name T888
Test name
Test status
Simulation time 74247096 ps
CPU time 1.97 seconds
Started Apr 28 01:59:35 PM PDT 24
Finished Apr 28 01:59:38 PM PDT 24
Peak memory 240296 kb
Host smart-059e469b-b576-47ef-918d-e4d7e27bc79a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134501815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.2134501815
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.3902872134
Short name T557
Test name
Test status
Simulation time 699893101 ps
CPU time 22.07 seconds
Started Apr 28 01:59:25 PM PDT 24
Finished Apr 28 01:59:47 PM PDT 24
Peak memory 241496 kb
Host smart-f298714f-fa7e-4a3a-8d04-1ffc63ccc1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902872134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.3902872134
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.2656761383
Short name T381
Test name
Test status
Simulation time 990891535 ps
CPU time 15.88 seconds
Started Apr 28 01:59:26 PM PDT 24
Finished Apr 28 01:59:42 PM PDT 24
Peak memory 241420 kb
Host smart-f0d3b130-35f2-4e5b-a92b-fedd0a54a316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656761383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.2656761383
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.1849142129
Short name T1000
Test name
Test status
Simulation time 1928929435 ps
CPU time 5.54 seconds
Started Apr 28 01:59:29 PM PDT 24
Finished Apr 28 01:59:35 PM PDT 24
Peak memory 241368 kb
Host smart-7e0464c4-d5e5-47ee-acb7-53b4157f4059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849142129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.1849142129
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.4200445951
Short name T745
Test name
Test status
Simulation time 28453522586 ps
CPU time 60.24 seconds
Started Apr 28 01:59:26 PM PDT 24
Finished Apr 28 02:00:26 PM PDT 24
Peak memory 259152 kb
Host smart-028d2deb-99b0-44d0-88dd-2caa9f8e1233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200445951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.4200445951
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.2908119474
Short name T260
Test name
Test status
Simulation time 5913044722 ps
CPU time 44.08 seconds
Started Apr 28 01:59:27 PM PDT 24
Finished Apr 28 02:00:11 PM PDT 24
Peak memory 242780 kb
Host smart-b1280b8c-327b-4549-bc06-43dfd076574d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908119474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.2908119474
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.1975322344
Short name T1164
Test name
Test status
Simulation time 88754203 ps
CPU time 2.64 seconds
Started Apr 28 01:59:27 PM PDT 24
Finished Apr 28 01:59:30 PM PDT 24
Peak memory 241732 kb
Host smart-c2216c47-4a54-4ef5-bb59-7bc81062208c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975322344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.1975322344
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.980193788
Short name T563
Test name
Test status
Simulation time 3042986913 ps
CPU time 8.08 seconds
Started Apr 28 01:59:26 PM PDT 24
Finished Apr 28 01:59:34 PM PDT 24
Peak memory 247720 kb
Host smart-68b374ff-706c-4b96-957d-3edf6fe29b45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=980193788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.980193788
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.3430996052
Short name T373
Test name
Test status
Simulation time 969354182 ps
CPU time 9.28 seconds
Started Apr 28 01:59:24 PM PDT 24
Finished Apr 28 01:59:34 PM PDT 24
Peak memory 241372 kb
Host smart-407c8ec9-c12a-4ce3-83a6-bf1af556dfc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3430996052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.3430996052
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.2640519655
Short name T966
Test name
Test status
Simulation time 323760800 ps
CPU time 6.46 seconds
Started Apr 28 01:59:23 PM PDT 24
Finished Apr 28 01:59:30 PM PDT 24
Peak memory 247952 kb
Host smart-fdf9d5a2-4268-4944-b7b8-e8ca345f043c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640519655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.2640519655
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.3540084691
Short name T816
Test name
Test status
Simulation time 28168395035 ps
CPU time 157.48 seconds
Started Apr 28 01:59:30 PM PDT 24
Finished Apr 28 02:02:08 PM PDT 24
Peak memory 246908 kb
Host smart-cd045249-3190-4a23-a31f-2443d4cc2831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540084691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.3540084691
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.1371853153
Short name T1043
Test name
Test status
Simulation time 37136505914 ps
CPU time 389.12 seconds
Started Apr 28 01:59:29 PM PDT 24
Finished Apr 28 02:05:59 PM PDT 24
Peak memory 276948 kb
Host smart-1b02df34-c1c0-4837-994a-1bff0c391174
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371853153 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.1371853153
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.2430500630
Short name T294
Test name
Test status
Simulation time 4430065758 ps
CPU time 12.57 seconds
Started Apr 28 01:59:36 PM PDT 24
Finished Apr 28 01:59:49 PM PDT 24
Peak memory 242312 kb
Host smart-2a9c5d85-6dfc-4936-b322-0c8188dcd2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430500630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.2430500630
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.3634268627
Short name T220
Test name
Test status
Simulation time 2101749817 ps
CPU time 6.27 seconds
Started Apr 28 02:05:55 PM PDT 24
Finished Apr 28 02:06:02 PM PDT 24
Peak memory 241372 kb
Host smart-e08e31e1-b840-4265-bafc-ee3889e96772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634268627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.3634268627
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.754479637
Short name T934
Test name
Test status
Simulation time 204386707 ps
CPU time 7.32 seconds
Started Apr 28 02:05:53 PM PDT 24
Finished Apr 28 02:06:01 PM PDT 24
Peak memory 241584 kb
Host smart-dfa0d9db-efd4-4611-b6f9-cf38ff3a2c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754479637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.754479637
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.3611657728
Short name T114
Test name
Test status
Simulation time 135022175 ps
CPU time 3.64 seconds
Started Apr 28 02:06:00 PM PDT 24
Finished Apr 28 02:06:04 PM PDT 24
Peak memory 241424 kb
Host smart-41debdda-09b6-4112-9b3d-1b177d3fccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611657728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.3611657728
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.389534997
Short name T390
Test name
Test status
Simulation time 9114051705 ps
CPU time 23.01 seconds
Started Apr 28 02:06:00 PM PDT 24
Finished Apr 28 02:06:24 PM PDT 24
Peak memory 241376 kb
Host smart-39e37c02-c8d5-4573-a351-48b28f382e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389534997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.389534997
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.2165406743
Short name T900
Test name
Test status
Simulation time 1590642643 ps
CPU time 5.69 seconds
Started Apr 28 02:05:59 PM PDT 24
Finished Apr 28 02:06:05 PM PDT 24
Peak memory 241388 kb
Host smart-673a7b4d-c90e-4400-ac93-d10f26af112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165406743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2165406743
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.3663573341
Short name T291
Test name
Test status
Simulation time 1947447209 ps
CPU time 13.63 seconds
Started Apr 28 02:06:00 PM PDT 24
Finished Apr 28 02:06:14 PM PDT 24
Peak memory 241760 kb
Host smart-d0e4051b-955a-46c0-be56-dd0cd752b090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663573341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.3663573341
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.767738369
Short name T58
Test name
Test status
Simulation time 178780390 ps
CPU time 4.53 seconds
Started Apr 28 02:05:58 PM PDT 24
Finished Apr 28 02:06:03 PM PDT 24
Peak memory 241268 kb
Host smart-4695f040-7bea-4c8b-a0c7-806e3d1eb988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767738369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.767738369
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.1392313079
Short name T808
Test name
Test status
Simulation time 115078178 ps
CPU time 3.89 seconds
Started Apr 28 02:06:01 PM PDT 24
Finished Apr 28 02:06:05 PM PDT 24
Peak memory 241264 kb
Host smart-8ee46406-9f11-44ed-bfc7-93bd1179c047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392313079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.1392313079
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.1797337002
Short name T679
Test name
Test status
Simulation time 197672113 ps
CPU time 3.7 seconds
Started Apr 28 02:05:58 PM PDT 24
Finished Apr 28 02:06:02 PM PDT 24
Peak memory 241668 kb
Host smart-cb4cdbe7-d8b6-45d9-9921-715ea54b03b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797337002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.1797337002
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.2948940613
Short name T610
Test name
Test status
Simulation time 171730281 ps
CPU time 4.73 seconds
Started Apr 28 02:06:03 PM PDT 24
Finished Apr 28 02:06:07 PM PDT 24
Peak memory 241156 kb
Host smart-7cfa4038-8cb8-4883-b4e8-9de4ff283654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948940613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.2948940613
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.1210117917
Short name T780
Test name
Test status
Simulation time 164939000 ps
CPU time 4.46 seconds
Started Apr 28 02:05:59 PM PDT 24
Finished Apr 28 02:06:04 PM PDT 24
Peak memory 241264 kb
Host smart-890cefc0-671d-4219-860b-81120e78c0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210117917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.1210117917
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.3490399086
Short name T514
Test name
Test status
Simulation time 393213846 ps
CPU time 9.24 seconds
Started Apr 28 02:05:59 PM PDT 24
Finished Apr 28 02:06:08 PM PDT 24
Peak memory 241332 kb
Host smart-ed58c9fb-a969-46b0-992c-bd7d806e3db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490399086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.3490399086
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.837473601
Short name T37
Test name
Test status
Simulation time 568951422 ps
CPU time 4.72 seconds
Started Apr 28 02:06:01 PM PDT 24
Finished Apr 28 02:06:06 PM PDT 24
Peak memory 241424 kb
Host smart-935bfa8e-ea3f-4bd9-9187-e1fe1a14034e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837473601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.837473601
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.2254562918
Short name T669
Test name
Test status
Simulation time 803424589 ps
CPU time 10.03 seconds
Started Apr 28 02:06:09 PM PDT 24
Finished Apr 28 02:06:19 PM PDT 24
Peak memory 241168 kb
Host smart-b39c368b-fdb7-46df-b732-56dfa648bca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254562918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.2254562918
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.698383779
Short name T182
Test name
Test status
Simulation time 1823938232 ps
CPU time 5.15 seconds
Started Apr 28 02:06:05 PM PDT 24
Finished Apr 28 02:06:10 PM PDT 24
Peak memory 241660 kb
Host smart-7defef58-fe21-45eb-81a4-959b7a33c063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698383779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.698383779
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.450568945
Short name T975
Test name
Test status
Simulation time 139763830 ps
CPU time 5.91 seconds
Started Apr 28 02:06:04 PM PDT 24
Finished Apr 28 02:06:11 PM PDT 24
Peak memory 241408 kb
Host smart-ef300504-ad36-4c37-b94b-d40c502a5fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450568945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.450568945
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.621619019
Short name T59
Test name
Test status
Simulation time 157437564 ps
CPU time 3.62 seconds
Started Apr 28 02:06:12 PM PDT 24
Finished Apr 28 02:06:16 PM PDT 24
Peak memory 241768 kb
Host smart-3e23c75b-a10e-46f6-9634-99ef313e119b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621619019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.621619019
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.2664280772
Short name T1034
Test name
Test status
Simulation time 255712561 ps
CPU time 6.5 seconds
Started Apr 28 02:06:12 PM PDT 24
Finished Apr 28 02:06:19 PM PDT 24
Peak memory 241328 kb
Host smart-a1a21eec-5fe7-4127-a0a7-f206e6126ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664280772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2664280772
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.1326349358
Short name T198
Test name
Test status
Simulation time 115096110 ps
CPU time 3.55 seconds
Started Apr 28 02:06:05 PM PDT 24
Finished Apr 28 02:06:09 PM PDT 24
Peak memory 241604 kb
Host smart-f6a91c28-594b-4a6e-897b-a05eb39b490e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326349358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.1326349358
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.2000129015
Short name T1
Test name
Test status
Simulation time 187447997 ps
CPU time 8.99 seconds
Started Apr 28 02:06:12 PM PDT 24
Finished Apr 28 02:06:22 PM PDT 24
Peak memory 241788 kb
Host smart-806ac7ba-c6d6-49b2-ab23-a8ae70f73cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000129015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.2000129015
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.3294323574
Short name T72
Test name
Test status
Simulation time 5255042679 ps
CPU time 15.6 seconds
Started Apr 28 01:57:04 PM PDT 24
Finished Apr 28 01:57:20 PM PDT 24
Peak memory 241468 kb
Host smart-24753453-f107-4ce0-893c-c81c13a43eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294323574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.3294323574
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.830000130
Short name T66
Test name
Test status
Simulation time 3899402218 ps
CPU time 35.67 seconds
Started Apr 28 01:57:09 PM PDT 24
Finished Apr 28 01:57:45 PM PDT 24
Peak memory 244168 kb
Host smart-0e08a405-6299-4f3e-9ff8-dc243cec53bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830000130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.830000130
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.1674348785
Short name T485
Test name
Test status
Simulation time 399412787 ps
CPU time 24.74 seconds
Started Apr 28 01:57:13 PM PDT 24
Finished Apr 28 01:57:38 PM PDT 24
Peak memory 241428 kb
Host smart-e00d25d9-bbcc-483f-b08e-e3bcc1f85483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674348785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1674348785
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.3945853016
Short name T832
Test name
Test status
Simulation time 14936394050 ps
CPU time 38.22 seconds
Started Apr 28 01:57:13 PM PDT 24
Finished Apr 28 01:57:51 PM PDT 24
Peak memory 241860 kb
Host smart-b7e48981-1efc-4e1d-9838-d34d5818f0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945853016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.3945853016
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.2893759909
Short name T229
Test name
Test status
Simulation time 117755198 ps
CPU time 3.05 seconds
Started Apr 28 01:57:06 PM PDT 24
Finished Apr 28 01:57:09 PM PDT 24
Peak memory 241640 kb
Host smart-0dfe5214-5f91-4fac-86d5-4d1dc2d21c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893759909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.2893759909
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.4188792745
Short name T1191
Test name
Test status
Simulation time 4906553720 ps
CPU time 38.21 seconds
Started Apr 28 01:57:11 PM PDT 24
Finished Apr 28 01:57:50 PM PDT 24
Peak memory 256596 kb
Host smart-4678566c-23b7-4b95-98bd-7f581c0e2652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188792745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.4188792745
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.3298961376
Short name T1148
Test name
Test status
Simulation time 2352391999 ps
CPU time 24.04 seconds
Started Apr 28 01:57:11 PM PDT 24
Finished Apr 28 01:57:35 PM PDT 24
Peak memory 242128 kb
Host smart-24e4cc35-cb35-404c-8cd9-72da87352e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298961376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.3298961376
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.2271857598
Short name T253
Test name
Test status
Simulation time 525993936 ps
CPU time 10.93 seconds
Started Apr 28 01:57:10 PM PDT 24
Finished Apr 28 01:57:21 PM PDT 24
Peak memory 241332 kb
Host smart-4b5d9cb0-bd00-4ef4-b65e-ba90c2114457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2271857598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.2271857598
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.4037350594
Short name T374
Test name
Test status
Simulation time 137636214 ps
CPU time 4.64 seconds
Started Apr 28 01:57:10 PM PDT 24
Finished Apr 28 01:57:15 PM PDT 24
Peak memory 241608 kb
Host smart-f2dd0112-efdc-48eb-886b-14ef3df9e3fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037350594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.4037350594
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.869995109
Short name T238
Test name
Test status
Simulation time 17343292929 ps
CPU time 224.54 seconds
Started Apr 28 01:57:13 PM PDT 24
Finished Apr 28 02:00:58 PM PDT 24
Peak memory 271008 kb
Host smart-9c681841-1597-4cbd-aed9-27e44167a26d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869995109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.869995109
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.2925878158
Short name T598
Test name
Test status
Simulation time 523356128 ps
CPU time 6.07 seconds
Started Apr 28 01:57:05 PM PDT 24
Finished Apr 28 01:57:11 PM PDT 24
Peak memory 241564 kb
Host smart-4e4cb8a1-4036-4163-ace9-20b08d64823d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925878158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.2925878158
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.951689668
Short name T901
Test name
Test status
Simulation time 5883150508 ps
CPU time 49.8 seconds
Started Apr 28 01:57:14 PM PDT 24
Finished Apr 28 01:58:04 PM PDT 24
Peak memory 244016 kb
Host smart-f96c192b-b376-4ea7-afcb-78a1033e03ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951689668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.951689668
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.2051539404
Short name T800
Test name
Test status
Simulation time 2208424027820 ps
CPU time 5985.71 seconds
Started Apr 28 01:57:15 PM PDT 24
Finished Apr 28 03:37:02 PM PDT 24
Peak memory 387824 kb
Host smart-7b8f8831-8d75-48b1-971d-b0c7c4746afc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051539404 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.2051539404
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.2140688915
Short name T650
Test name
Test status
Simulation time 234885616 ps
CPU time 5.7 seconds
Started Apr 28 01:57:12 PM PDT 24
Finished Apr 28 01:57:19 PM PDT 24
Peak memory 241352 kb
Host smart-4fa733b9-f9dd-4eb2-996e-0a8d3077f9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140688915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.2140688915
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.1956424181
Short name T955
Test name
Test status
Simulation time 200091258 ps
CPU time 1.62 seconds
Started Apr 28 01:59:36 PM PDT 24
Finished Apr 28 01:59:38 PM PDT 24
Peak memory 240000 kb
Host smart-8cb3b369-1d7a-4fe1-b990-b546df6fc81b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956424181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.1956424181
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.455210599
Short name T54
Test name
Test status
Simulation time 863570977 ps
CPU time 17.26 seconds
Started Apr 28 01:59:36 PM PDT 24
Finished Apr 28 01:59:54 PM PDT 24
Peak memory 241880 kb
Host smart-d07cd772-b755-481d-928e-8952c07057bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455210599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.455210599
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.286175307
Short name T556
Test name
Test status
Simulation time 555754671 ps
CPU time 13.21 seconds
Started Apr 28 01:59:30 PM PDT 24
Finished Apr 28 01:59:44 PM PDT 24
Peak memory 241204 kb
Host smart-b6074f93-0039-4150-849e-9253106cf656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286175307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.286175307
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.2353855309
Short name T668
Test name
Test status
Simulation time 14281025176 ps
CPU time 45.81 seconds
Started Apr 28 01:59:31 PM PDT 24
Finished Apr 28 02:00:17 PM PDT 24
Peak memory 248052 kb
Host smart-9dabaff2-cf26-4e0f-8193-554630661c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353855309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.2353855309
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.4021325479
Short name T639
Test name
Test status
Simulation time 223400242 ps
CPU time 3.58 seconds
Started Apr 28 01:59:38 PM PDT 24
Finished Apr 28 01:59:43 PM PDT 24
Peak memory 241768 kb
Host smart-f02b6dc7-35f2-4b2c-b5e5-cb1cbc9008dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021325479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.4021325479
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.3502541661
Short name T212
Test name
Test status
Simulation time 12382094056 ps
CPU time 43.09 seconds
Started Apr 28 01:59:34 PM PDT 24
Finished Apr 28 02:00:18 PM PDT 24
Peak memory 248204 kb
Host smart-01d29516-2aaa-47fb-b913-d1cc973d9348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502541661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.3502541661
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.2735977852
Short name T1099
Test name
Test status
Simulation time 1140611138 ps
CPU time 28.03 seconds
Started Apr 28 01:59:37 PM PDT 24
Finished Apr 28 02:00:05 PM PDT 24
Peak memory 247916 kb
Host smart-bca08797-a1aa-4431-a446-15cd495b1c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735977852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.2735977852
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.1296167715
Short name T1097
Test name
Test status
Simulation time 927595685 ps
CPU time 12.89 seconds
Started Apr 28 01:59:30 PM PDT 24
Finished Apr 28 01:59:44 PM PDT 24
Peak memory 241720 kb
Host smart-a069c726-80a5-4ef3-84ee-8d57637ef3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296167715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.1296167715
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.3813029382
Short name T375
Test name
Test status
Simulation time 168262287 ps
CPU time 5.47 seconds
Started Apr 28 01:59:35 PM PDT 24
Finished Apr 28 01:59:41 PM PDT 24
Peak memory 241388 kb
Host smart-cbbed5e7-54f8-46af-b5e6-9605800d7188
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3813029382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.3813029382
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.2880948419
Short name T1093
Test name
Test status
Simulation time 945010391 ps
CPU time 7.22 seconds
Started Apr 28 01:59:30 PM PDT 24
Finished Apr 28 01:59:38 PM PDT 24
Peak memory 247764 kb
Host smart-b231a13a-93e2-4141-81fa-7c8680730845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880948419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.2880948419
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.1696216671
Short name T24
Test name
Test status
Simulation time 385627512441 ps
CPU time 3008.06 seconds
Started Apr 28 01:59:35 PM PDT 24
Finished Apr 28 02:49:44 PM PDT 24
Peak memory 297048 kb
Host smart-aa8a2b3a-22ef-4680-9cd4-c280cdb69c28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696216671 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.1696216671
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.2187569760
Short name T175
Test name
Test status
Simulation time 8723093283 ps
CPU time 15.62 seconds
Started Apr 28 01:59:34 PM PDT 24
Finished Apr 28 01:59:50 PM PDT 24
Peak memory 242236 kb
Host smart-bff10ae9-4dee-44e1-a9a5-c46674b6c2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187569760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.2187569760
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.3331102743
Short name T712
Test name
Test status
Simulation time 122655807 ps
CPU time 3.23 seconds
Started Apr 28 02:06:11 PM PDT 24
Finished Apr 28 02:06:15 PM PDT 24
Peak memory 241724 kb
Host smart-b6df286a-3ead-4cbc-92aa-aa345b6af3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331102743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3331102743
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.775088437
Short name T221
Test name
Test status
Simulation time 111250858 ps
CPU time 4.16 seconds
Started Apr 28 02:06:03 PM PDT 24
Finished Apr 28 02:06:07 PM PDT 24
Peak memory 241316 kb
Host smart-da69a51b-d531-4859-bed3-96fee2fe5e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775088437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.775088437
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.920656896
Short name T1113
Test name
Test status
Simulation time 140021359 ps
CPU time 3.69 seconds
Started Apr 28 02:06:24 PM PDT 24
Finished Apr 28 02:06:28 PM PDT 24
Peak memory 241768 kb
Host smart-a353dc9e-8b0d-4e4a-986e-709314e298a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920656896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.920656896
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.1478153417
Short name T696
Test name
Test status
Simulation time 552137376 ps
CPU time 3.93 seconds
Started Apr 28 02:06:05 PM PDT 24
Finished Apr 28 02:06:09 PM PDT 24
Peak memory 241384 kb
Host smart-c8491348-6bdd-4a1c-bf4b-68c9557d29ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478153417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1478153417
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.2880003522
Short name T681
Test name
Test status
Simulation time 341881904 ps
CPU time 4.97 seconds
Started Apr 28 02:06:12 PM PDT 24
Finished Apr 28 02:06:18 PM PDT 24
Peak memory 241396 kb
Host smart-d40a23bc-83d9-4d77-9e6a-4138564c20b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880003522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.2880003522
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.3360908732
Short name T488
Test name
Test status
Simulation time 83152972 ps
CPU time 3.04 seconds
Started Apr 28 02:06:04 PM PDT 24
Finished Apr 28 02:06:07 PM PDT 24
Peak memory 241720 kb
Host smart-8b3b2f3b-0a1e-4bae-878f-eba2383dc730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360908732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.3360908732
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.4152048785
Short name T533
Test name
Test status
Simulation time 471332015 ps
CPU time 4.16 seconds
Started Apr 28 02:06:04 PM PDT 24
Finished Apr 28 02:06:08 PM PDT 24
Peak memory 241716 kb
Host smart-195cd2b9-eb33-46dd-b2fc-0164319a8c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152048785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.4152048785
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.1983163265
Short name T956
Test name
Test status
Simulation time 233163529 ps
CPU time 3.6 seconds
Started Apr 28 02:06:08 PM PDT 24
Finished Apr 28 02:06:12 PM PDT 24
Peak memory 241452 kb
Host smart-bda01f63-281c-41c2-afb7-55d74a3dc434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983163265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.1983163265
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.377412785
Short name T829
Test name
Test status
Simulation time 1870142704 ps
CPU time 4.95 seconds
Started Apr 28 02:06:12 PM PDT 24
Finished Apr 28 02:06:17 PM PDT 24
Peak memory 241436 kb
Host smart-d9e6beb2-8244-4f46-bdd6-c39e7e099896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377412785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.377412785
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.3874455989
Short name T931
Test name
Test status
Simulation time 262060975 ps
CPU time 4.17 seconds
Started Apr 28 02:06:11 PM PDT 24
Finished Apr 28 02:06:16 PM PDT 24
Peak memory 241772 kb
Host smart-985462ba-0ecb-4752-b4b0-a89d1e5e85b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874455989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3874455989
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.368403158
Short name T647
Test name
Test status
Simulation time 147076911 ps
CPU time 1.94 seconds
Started Apr 28 01:59:42 PM PDT 24
Finished Apr 28 01:59:44 PM PDT 24
Peak memory 239732 kb
Host smart-c3ce56fc-a084-4a10-86e6-3e4505572059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368403158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.368403158
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.2122799107
Short name T1049
Test name
Test status
Simulation time 9017826586 ps
CPU time 25.19 seconds
Started Apr 28 01:59:42 PM PDT 24
Finished Apr 28 02:00:08 PM PDT 24
Peak memory 248092 kb
Host smart-36036a57-c665-486f-972d-714bc1432fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122799107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.2122799107
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.3709282113
Short name T1118
Test name
Test status
Simulation time 19717116509 ps
CPU time 53.17 seconds
Started Apr 28 01:59:40 PM PDT 24
Finished Apr 28 02:00:33 PM PDT 24
Peak memory 250676 kb
Host smart-7b54c755-5d51-4636-8f9d-2a3f1bc53b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709282113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3709282113
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.3291728119
Short name T536
Test name
Test status
Simulation time 1773728741 ps
CPU time 16.03 seconds
Started Apr 28 01:59:41 PM PDT 24
Finished Apr 28 01:59:57 PM PDT 24
Peak memory 247924 kb
Host smart-dcc80f75-3769-4e55-9d33-fa7254d83e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291728119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.3291728119
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.1526140560
Short name T987
Test name
Test status
Simulation time 135864237 ps
CPU time 5.02 seconds
Started Apr 28 01:59:35 PM PDT 24
Finished Apr 28 01:59:41 PM PDT 24
Peak memory 241472 kb
Host smart-b0360fc6-56d8-42e0-9022-cb955a4c79c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526140560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.1526140560
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.3113675964
Short name T710
Test name
Test status
Simulation time 490797399 ps
CPU time 16.54 seconds
Started Apr 28 01:59:39 PM PDT 24
Finished Apr 28 01:59:56 PM PDT 24
Peak memory 242084 kb
Host smart-3779aab7-e285-43fc-b4a9-b83c72eb0ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113675964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.3113675964
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.1328530616
Short name T105
Test name
Test status
Simulation time 6038687709 ps
CPU time 44.93 seconds
Started Apr 28 01:59:41 PM PDT 24
Finished Apr 28 02:00:26 PM PDT 24
Peak memory 241424 kb
Host smart-749d98cb-ff7b-46f8-a191-a4f73f5427d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328530616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.1328530616
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.3733088028
Short name T904
Test name
Test status
Simulation time 1167182461 ps
CPU time 7.46 seconds
Started Apr 28 01:59:34 PM PDT 24
Finished Apr 28 01:59:41 PM PDT 24
Peak memory 241388 kb
Host smart-2f4603f5-1dbc-40c9-b50b-f30b39921480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733088028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.3733088028
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.3486044891
Short name T1184
Test name
Test status
Simulation time 654568698 ps
CPU time 12.35 seconds
Started Apr 28 01:59:39 PM PDT 24
Finished Apr 28 01:59:52 PM PDT 24
Peak memory 241272 kb
Host smart-f2047dc9-41a9-4d4f-9de1-029075a59f19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3486044891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.3486044891
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.1730650510
Short name T525
Test name
Test status
Simulation time 467543426 ps
CPU time 5.27 seconds
Started Apr 28 01:59:38 PM PDT 24
Finished Apr 28 01:59:44 PM PDT 24
Peak memory 241640 kb
Host smart-a120640f-c0fa-4e74-8e8c-81faa79cd403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730650510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.1730650510
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.4251299170
Short name T499
Test name
Test status
Simulation time 6033266718 ps
CPU time 9.4 seconds
Started Apr 28 01:59:34 PM PDT 24
Finished Apr 28 01:59:45 PM PDT 24
Peak memory 248040 kb
Host smart-c08a645c-87cd-49fd-b00d-8a0a7e1d24b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251299170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.4251299170
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.2091909228
Short name T288
Test name
Test status
Simulation time 158855712164 ps
CPU time 1252.33 seconds
Started Apr 28 01:59:39 PM PDT 24
Finished Apr 28 02:20:32 PM PDT 24
Peak memory 295012 kb
Host smart-4fec184f-487e-4ddf-a8fd-f25b6ca30827
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091909228 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.2091909228
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.1805169581
Short name T104
Test name
Test status
Simulation time 942725462 ps
CPU time 26.72 seconds
Started Apr 28 01:59:41 PM PDT 24
Finished Apr 28 02:00:08 PM PDT 24
Peak memory 241228 kb
Host smart-f05e2a0c-996a-41bd-b151-3b3d42efc580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805169581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.1805169581
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.1921294921
Short name T917
Test name
Test status
Simulation time 626582448 ps
CPU time 4.47 seconds
Started Apr 28 02:06:09 PM PDT 24
Finished Apr 28 02:06:14 PM PDT 24
Peak memory 241372 kb
Host smart-00688ee5-5022-460b-9995-6bd033f2288c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921294921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1921294921
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.3131726977
Short name T520
Test name
Test status
Simulation time 152422505 ps
CPU time 3.7 seconds
Started Apr 28 02:06:13 PM PDT 24
Finished Apr 28 02:06:17 PM PDT 24
Peak memory 241276 kb
Host smart-094a2b84-dd9c-4ce2-a637-6080caee945d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131726977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.3131726977
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.3171068722
Short name T805
Test name
Test status
Simulation time 1672604876 ps
CPU time 6.32 seconds
Started Apr 28 02:06:11 PM PDT 24
Finished Apr 28 02:06:17 PM PDT 24
Peak memory 241440 kb
Host smart-757ec006-999c-4472-a84b-a759fdc8eda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171068722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.3171068722
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.2069390577
Short name T946
Test name
Test status
Simulation time 159528528 ps
CPU time 4.14 seconds
Started Apr 28 02:06:11 PM PDT 24
Finished Apr 28 02:06:15 PM PDT 24
Peak memory 241348 kb
Host smart-7197213d-8d1e-49e4-9d9f-48b0f0d0dcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069390577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.2069390577
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.3522792241
Short name T969
Test name
Test status
Simulation time 404416760 ps
CPU time 4.39 seconds
Started Apr 28 02:06:13 PM PDT 24
Finished Apr 28 02:06:18 PM PDT 24
Peak memory 241376 kb
Host smart-970816c7-f712-4ca0-97eb-72609dde5405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522792241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.3522792241
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.2567820383
Short name T423
Test name
Test status
Simulation time 597135146 ps
CPU time 4.58 seconds
Started Apr 28 02:06:09 PM PDT 24
Finished Apr 28 02:06:14 PM PDT 24
Peak memory 241412 kb
Host smart-7a9f8b1b-aa5f-4306-a04d-9b6ff193e3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567820383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.2567820383
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.447658032
Short name T1085
Test name
Test status
Simulation time 258190326 ps
CPU time 4 seconds
Started Apr 28 02:06:09 PM PDT 24
Finished Apr 28 02:06:14 PM PDT 24
Peak memory 241648 kb
Host smart-fec6383c-918c-46cd-acf0-892ab638e92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447658032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.447658032
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.3030267722
Short name T1065
Test name
Test status
Simulation time 283310455 ps
CPU time 3.9 seconds
Started Apr 28 02:06:10 PM PDT 24
Finished Apr 28 02:06:15 PM PDT 24
Peak memory 241308 kb
Host smart-e0d18660-957a-419d-af94-09ee7d3aaa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030267722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3030267722
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.2688097813
Short name T1132
Test name
Test status
Simulation time 2653627159 ps
CPU time 6.11 seconds
Started Apr 28 02:06:11 PM PDT 24
Finished Apr 28 02:06:17 PM PDT 24
Peak memory 241508 kb
Host smart-5f33e335-556e-485b-a450-f60aa26f67d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688097813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2688097813
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.1413723030
Short name T996
Test name
Test status
Simulation time 116434530 ps
CPU time 1.84 seconds
Started Apr 28 01:59:48 PM PDT 24
Finished Apr 28 01:59:50 PM PDT 24
Peak memory 239704 kb
Host smart-7e24ded3-ad0f-45cd-9277-2990af15eea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413723030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.1413723030
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.1893362804
Short name T1062
Test name
Test status
Simulation time 6062857148 ps
CPU time 31.89 seconds
Started Apr 28 01:59:47 PM PDT 24
Finished Apr 28 02:00:19 PM PDT 24
Peak memory 241428 kb
Host smart-a9f71632-3b67-4f28-acf3-09e8a09cca0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893362804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.1893362804
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.997120606
Short name T626
Test name
Test status
Simulation time 927262804 ps
CPU time 20.4 seconds
Started Apr 28 01:59:49 PM PDT 24
Finished Apr 28 02:00:10 PM PDT 24
Peak memory 241524 kb
Host smart-dfc9a51b-5248-497d-8981-2c5c15d4ef03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997120606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.997120606
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.1008479100
Short name T1111
Test name
Test status
Simulation time 356894267 ps
CPU time 4.02 seconds
Started Apr 28 01:59:48 PM PDT 24
Finished Apr 28 01:59:53 PM PDT 24
Peak memory 241612 kb
Host smart-e02b9c03-542b-4003-a76b-3a91b9df9d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008479100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1008479100
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.2765828367
Short name T568
Test name
Test status
Simulation time 1935936581 ps
CPU time 16.15 seconds
Started Apr 28 01:59:50 PM PDT 24
Finished Apr 28 02:00:06 PM PDT 24
Peak memory 241396 kb
Host smart-ebb88bf1-c55f-4e5b-858c-143630078cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765828367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2765828367
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.1905032232
Short name T601
Test name
Test status
Simulation time 3280951729 ps
CPU time 34.81 seconds
Started Apr 28 01:59:46 PM PDT 24
Finished Apr 28 02:00:21 PM PDT 24
Peak memory 241424 kb
Host smart-48356149-88b6-430e-b069-352fb9979a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905032232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.1905032232
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.4015034858
Short name T596
Test name
Test status
Simulation time 1271742256 ps
CPU time 17.98 seconds
Started Apr 28 01:59:44 PM PDT 24
Finished Apr 28 02:00:02 PM PDT 24
Peak memory 241272 kb
Host smart-7516cfb7-14b6-45ae-950d-db5a2ee384c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015034858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.4015034858
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.2685827558
Short name T727
Test name
Test status
Simulation time 356351364 ps
CPU time 9.86 seconds
Started Apr 28 01:59:44 PM PDT 24
Finished Apr 28 01:59:54 PM PDT 24
Peak memory 247884 kb
Host smart-a201d6a4-3aa0-4bc6-82e2-335303eeae88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685827558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.2685827558
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.3272597152
Short name T371
Test name
Test status
Simulation time 343442429 ps
CPU time 6.56 seconds
Started Apr 28 01:59:47 PM PDT 24
Finished Apr 28 01:59:54 PM PDT 24
Peak memory 241256 kb
Host smart-2a42accc-9c74-41d6-8803-aa51bf8d0c79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272597152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.3272597152
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.713205937
Short name T949
Test name
Test status
Simulation time 205289675 ps
CPU time 5.07 seconds
Started Apr 28 01:59:48 PM PDT 24
Finished Apr 28 01:59:54 PM PDT 24
Peak memory 241152 kb
Host smart-d5a73b00-3714-43ab-96d6-49eedf9a5b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713205937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.713205937
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.3138423752
Short name T631
Test name
Test status
Simulation time 8343003990 ps
CPU time 25.67 seconds
Started Apr 28 01:59:49 PM PDT 24
Finished Apr 28 02:00:15 PM PDT 24
Peak memory 241440 kb
Host smart-5d2d0173-4355-4993-bbe0-5f2f13966577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138423752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.3138423752
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.2507403271
Short name T386
Test name
Test status
Simulation time 147096060996 ps
CPU time 586.25 seconds
Started Apr 28 01:59:47 PM PDT 24
Finished Apr 28 02:09:34 PM PDT 24
Peak memory 277020 kb
Host smart-5c6259d4-1078-4477-9e85-00c4565de8f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507403271 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.2507403271
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.1314632918
Short name T1075
Test name
Test status
Simulation time 1097828870 ps
CPU time 11.97 seconds
Started Apr 28 01:59:47 PM PDT 24
Finished Apr 28 01:59:59 PM PDT 24
Peak memory 241212 kb
Host smart-267be99f-9f7d-409c-bce4-88161be7c978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314632918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.1314632918
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.1967270172
Short name T543
Test name
Test status
Simulation time 290075630 ps
CPU time 4.48 seconds
Started Apr 28 02:06:09 PM PDT 24
Finished Apr 28 02:06:14 PM PDT 24
Peak memory 241356 kb
Host smart-2453d1ba-eb3e-4f67-84f6-f6480b516db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967270172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.1967270172
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.3489161672
Short name T629
Test name
Test status
Simulation time 2421952024 ps
CPU time 5.18 seconds
Started Apr 28 02:06:11 PM PDT 24
Finished Apr 28 02:06:16 PM PDT 24
Peak memory 241468 kb
Host smart-97fcc4f8-8856-43df-bc45-43f5f248847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489161672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3489161672
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.2609803406
Short name T96
Test name
Test status
Simulation time 303286523 ps
CPU time 4.16 seconds
Started Apr 28 02:06:16 PM PDT 24
Finished Apr 28 02:06:21 PM PDT 24
Peak memory 241496 kb
Host smart-8b86591b-e2bc-4572-954d-4c8681a8eac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609803406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.2609803406
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.714600365
Short name T1010
Test name
Test status
Simulation time 492209817 ps
CPU time 3.4 seconds
Started Apr 28 02:06:18 PM PDT 24
Finished Apr 28 02:06:21 PM PDT 24
Peak memory 241696 kb
Host smart-474ef50e-1378-482b-a23c-549806ed1f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714600365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.714600365
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.4128262546
Short name T621
Test name
Test status
Simulation time 117061557 ps
CPU time 4.29 seconds
Started Apr 28 02:06:15 PM PDT 24
Finished Apr 28 02:06:20 PM PDT 24
Peak memory 241820 kb
Host smart-5246ae4b-48fb-477c-8810-a5998c23dde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128262546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.4128262546
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.3861986357
Short name T177
Test name
Test status
Simulation time 2029245031 ps
CPU time 4.46 seconds
Started Apr 28 02:06:15 PM PDT 24
Finished Apr 28 02:06:20 PM PDT 24
Peak memory 241452 kb
Host smart-8ec6fabf-d0b8-4d03-ae3a-b2a2928a7667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861986357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.3861986357
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.3305142228
Short name T1124
Test name
Test status
Simulation time 161499946 ps
CPU time 4.05 seconds
Started Apr 28 02:06:16 PM PDT 24
Finished Apr 28 02:06:20 PM PDT 24
Peak memory 241328 kb
Host smart-12774f4a-220d-46b5-9e9a-eac69e6b056e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305142228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.3305142228
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.331286327
Short name T320
Test name
Test status
Simulation time 231658918 ps
CPU time 3.62 seconds
Started Apr 28 02:06:15 PM PDT 24
Finished Apr 28 02:06:19 PM PDT 24
Peak memory 241420 kb
Host smart-1edb24d1-8c2f-436c-a543-637998c55193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331286327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.331286327
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.1870858342
Short name T585
Test name
Test status
Simulation time 387350318 ps
CPU time 4.64 seconds
Started Apr 28 02:06:17 PM PDT 24
Finished Apr 28 02:06:22 PM PDT 24
Peak memory 241336 kb
Host smart-fcb4e0e0-6803-47a2-85c6-24b4e6686912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870858342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.1870858342
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.688986875
Short name T201
Test name
Test status
Simulation time 57172238 ps
CPU time 1.81 seconds
Started Apr 28 01:59:57 PM PDT 24
Finished Apr 28 01:59:59 PM PDT 24
Peak memory 239820 kb
Host smart-20275a2f-7a43-47da-b069-93ddf67850dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688986875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.688986875
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.30205492
Short name T70
Test name
Test status
Simulation time 1001837385 ps
CPU time 13.6 seconds
Started Apr 28 01:59:53 PM PDT 24
Finished Apr 28 02:00:06 PM PDT 24
Peak memory 241432 kb
Host smart-9f0ea837-f0eb-495f-a1b1-dcb8a31bda40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30205492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.30205492
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.1842002137
Short name T487
Test name
Test status
Simulation time 361563070 ps
CPU time 19.98 seconds
Started Apr 28 01:59:55 PM PDT 24
Finished Apr 28 02:00:16 PM PDT 24
Peak memory 240660 kb
Host smart-02ba1955-0398-473c-84d8-e71632c155d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842002137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1842002137
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.2473300090
Short name T952
Test name
Test status
Simulation time 496518837 ps
CPU time 13.36 seconds
Started Apr 28 01:59:54 PM PDT 24
Finished Apr 28 02:00:08 PM PDT 24
Peak memory 241236 kb
Host smart-224f7e16-2ad2-46ea-a893-026baf3c8062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473300090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.2473300090
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.458793025
Short name T882
Test name
Test status
Simulation time 319609183 ps
CPU time 3.85 seconds
Started Apr 28 01:59:47 PM PDT 24
Finished Apr 28 01:59:51 PM PDT 24
Peak memory 241436 kb
Host smart-c509d082-5acd-43aa-9f29-1ae84e9d8712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458793025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.458793025
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.3300102933
Short name T216
Test name
Test status
Simulation time 3627306846 ps
CPU time 45.32 seconds
Started Apr 28 01:59:52 PM PDT 24
Finished Apr 28 02:00:38 PM PDT 24
Peak memory 248096 kb
Host smart-ca3ea8e2-e242-4979-b506-ae907af18ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300102933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3300102933
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.356614285
Short name T492
Test name
Test status
Simulation time 491817521 ps
CPU time 12.99 seconds
Started Apr 28 01:59:52 PM PDT 24
Finished Apr 28 02:00:06 PM PDT 24
Peak memory 241708 kb
Host smart-c8204b73-2dc9-4a0f-8ff4-3956b3c93dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356614285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.356614285
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.2546404175
Short name T778
Test name
Test status
Simulation time 224033336 ps
CPU time 11.17 seconds
Started Apr 28 01:59:54 PM PDT 24
Finished Apr 28 02:00:05 PM PDT 24
Peak memory 241348 kb
Host smart-c0d364ad-5f36-4487-a6c5-06bea2ee95be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546404175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.2546404175
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.1329678619
Short name T1120
Test name
Test status
Simulation time 1493345661 ps
CPU time 23.36 seconds
Started Apr 28 01:59:50 PM PDT 24
Finished Apr 28 02:00:14 PM PDT 24
Peak memory 241120 kb
Host smart-6999cfc2-3b57-4f66-a10d-e46122d4818a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1329678619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.1329678619
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.2633400683
Short name T12
Test name
Test status
Simulation time 364276059 ps
CPU time 10.25 seconds
Started Apr 28 01:59:55 PM PDT 24
Finished Apr 28 02:00:06 PM PDT 24
Peak memory 240532 kb
Host smart-788ab1c5-45b7-4ca9-a5ba-e00e6bc24e85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633400683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.2633400683
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.559723911
Short name T617
Test name
Test status
Simulation time 607681674 ps
CPU time 9.63 seconds
Started Apr 28 01:59:47 PM PDT 24
Finished Apr 28 01:59:57 PM PDT 24
Peak memory 241636 kb
Host smart-523ff182-08f3-493d-b1f9-2dcf118607c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559723911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.559723911
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.2136245975
Short name T995
Test name
Test status
Simulation time 134239435000 ps
CPU time 337.21 seconds
Started Apr 28 01:59:54 PM PDT 24
Finished Apr 28 02:05:32 PM PDT 24
Peak memory 282436 kb
Host smart-22778fe3-ec39-4eb9-9d3a-a4423f5fbd96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136245975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.2136245975
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.1170623840
Short name T911
Test name
Test status
Simulation time 28053130186 ps
CPU time 433.78 seconds
Started Apr 28 01:59:56 PM PDT 24
Finished Apr 28 02:07:11 PM PDT 24
Peak memory 256288 kb
Host smart-3e89122f-3734-4440-987e-c943aa90ce79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170623840 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.1170623840
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.75271294
Short name T109
Test name
Test status
Simulation time 4107368354 ps
CPU time 23.51 seconds
Started Apr 28 01:59:54 PM PDT 24
Finished Apr 28 02:00:18 PM PDT 24
Peak memory 241488 kb
Host smart-fc41f7ef-ccbb-4966-94a6-55dedbad1b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75271294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.75271294
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.3886625037
Short name T771
Test name
Test status
Simulation time 160890076 ps
CPU time 4.25 seconds
Started Apr 28 02:06:15 PM PDT 24
Finished Apr 28 02:06:20 PM PDT 24
Peak memory 241344 kb
Host smart-ce24701f-12d6-4fe0-a4e2-06295659e090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886625037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.3886625037
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.1767545349
Short name T1145
Test name
Test status
Simulation time 446585804 ps
CPU time 4.31 seconds
Started Apr 28 02:06:16 PM PDT 24
Finished Apr 28 02:06:21 PM PDT 24
Peak memory 241428 kb
Host smart-8f8273d0-8297-46a4-921d-ed75e4bf91f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767545349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.1767545349
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.620009410
Short name T665
Test name
Test status
Simulation time 1577415662 ps
CPU time 4.52 seconds
Started Apr 28 02:06:16 PM PDT 24
Finished Apr 28 02:06:21 PM PDT 24
Peak memory 241412 kb
Host smart-a41f4149-7a3e-47cf-ae5f-b0281d497c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620009410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.620009410
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.3297394197
Short name T779
Test name
Test status
Simulation time 373809936 ps
CPU time 4.51 seconds
Started Apr 28 02:06:21 PM PDT 24
Finished Apr 28 02:06:27 PM PDT 24
Peak memory 241744 kb
Host smart-062a4856-dd95-4d23-bc72-5bc274151b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297394197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.3297394197
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.3558013500
Short name T876
Test name
Test status
Simulation time 614982688 ps
CPU time 4.94 seconds
Started Apr 28 02:06:22 PM PDT 24
Finished Apr 28 02:06:27 PM PDT 24
Peak memory 241460 kb
Host smart-80273c91-f7c1-4622-87a6-7c3a0cb6d6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558013500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3558013500
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.307049884
Short name T731
Test name
Test status
Simulation time 191567127 ps
CPU time 3.96 seconds
Started Apr 28 02:06:23 PM PDT 24
Finished Apr 28 02:06:27 PM PDT 24
Peak memory 241404 kb
Host smart-a23a0a8d-fc48-4463-aab4-5354015eb5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307049884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.307049884
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.1081224104
Short name T867
Test name
Test status
Simulation time 254062166 ps
CPU time 3.33 seconds
Started Apr 28 02:06:21 PM PDT 24
Finished Apr 28 02:06:25 PM PDT 24
Peak memory 241428 kb
Host smart-a51a9e2d-fb8c-456a-9fe4-e53c75d07d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081224104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.1081224104
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.3267853782
Short name T619
Test name
Test status
Simulation time 138901009 ps
CPU time 5.43 seconds
Started Apr 28 02:06:22 PM PDT 24
Finished Apr 28 02:06:28 PM PDT 24
Peak memory 241236 kb
Host smart-4057acae-1bbe-4c16-9e8a-1d1e7fa0c93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267853782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.3267853782
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.2454698182
Short name T667
Test name
Test status
Simulation time 223353664 ps
CPU time 4.3 seconds
Started Apr 28 02:06:22 PM PDT 24
Finished Apr 28 02:06:27 PM PDT 24
Peak memory 241392 kb
Host smart-1b758661-462d-4071-8073-ae70597183e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454698182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.2454698182
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.2912648752
Short name T1047
Test name
Test status
Simulation time 116421119 ps
CPU time 3.89 seconds
Started Apr 28 02:06:26 PM PDT 24
Finished Apr 28 02:06:31 PM PDT 24
Peak memory 241256 kb
Host smart-610d2a57-5e30-4bd5-93c0-a4adff6cf0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912648752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.2912648752
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.1798486197
Short name T436
Test name
Test status
Simulation time 43952903 ps
CPU time 1.7 seconds
Started Apr 28 02:00:01 PM PDT 24
Finished Apr 28 02:00:03 PM PDT 24
Peak memory 239744 kb
Host smart-ea9bb601-b8b2-49f6-861f-5dc931f5fa55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798486197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.1798486197
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.4121943126
Short name T595
Test name
Test status
Simulation time 428722675 ps
CPU time 14.62 seconds
Started Apr 28 01:59:57 PM PDT 24
Finished Apr 28 02:00:12 PM PDT 24
Peak memory 241348 kb
Host smart-ea04b19e-5510-44fa-a387-500b80ada25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121943126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.4121943126
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.2147805876
Short name T1147
Test name
Test status
Simulation time 6915641713 ps
CPU time 45.14 seconds
Started Apr 28 01:59:57 PM PDT 24
Finished Apr 28 02:00:43 PM PDT 24
Peak memory 248092 kb
Host smart-fe41da57-c7d0-4168-939f-63659d67f200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147805876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.2147805876
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.1203428717
Short name T120
Test name
Test status
Simulation time 2594058161 ps
CPU time 5.33 seconds
Started Apr 28 01:59:57 PM PDT 24
Finished Apr 28 02:00:03 PM PDT 24
Peak memory 241780 kb
Host smart-546ef036-598e-4ce2-bd71-2b258edc16a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203428717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.1203428717
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.1458343204
Short name T769
Test name
Test status
Simulation time 2695875251 ps
CPU time 33.45 seconds
Started Apr 28 02:00:00 PM PDT 24
Finished Apr 28 02:00:34 PM PDT 24
Peak memory 248104 kb
Host smart-4e7f9ba6-b7b3-418c-8f52-56b277c116fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458343204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.1458343204
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.1457424504
Short name T797
Test name
Test status
Simulation time 3227718328 ps
CPU time 32.68 seconds
Started Apr 28 01:59:57 PM PDT 24
Finished Apr 28 02:00:30 PM PDT 24
Peak memory 241916 kb
Host smart-c9928a5b-4f8e-4991-84c2-95a0a02d7083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457424504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.1457424504
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.1950004712
Short name T1018
Test name
Test status
Simulation time 691398430 ps
CPU time 9.9 seconds
Started Apr 28 01:59:58 PM PDT 24
Finished Apr 28 02:00:08 PM PDT 24
Peak memory 241276 kb
Host smart-83589701-a3cc-43e3-ad0b-790d3f040a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950004712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1950004712
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.2606208883
Short name T473
Test name
Test status
Simulation time 570844295 ps
CPU time 14.06 seconds
Started Apr 28 01:59:56 PM PDT 24
Finished Apr 28 02:00:11 PM PDT 24
Peak memory 241416 kb
Host smart-fb8db77c-a9ea-47ea-bb12-9a33afe90346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606208883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.2606208883
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.1910859739
Short name T364
Test name
Test status
Simulation time 2323808864 ps
CPU time 5.6 seconds
Started Apr 28 02:00:00 PM PDT 24
Finished Apr 28 02:00:05 PM PDT 24
Peak memory 241460 kb
Host smart-7a63775d-2227-4d55-bd82-5c7040c8caab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1910859739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.1910859739
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.1752615656
Short name T833
Test name
Test status
Simulation time 786807785 ps
CPU time 13.97 seconds
Started Apr 28 02:00:01 PM PDT 24
Finished Apr 28 02:00:15 PM PDT 24
Peak memory 247904 kb
Host smart-26134d0c-c42d-4117-96ef-bcd0e0674bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752615656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.1752615656
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.1853386159
Short name T350
Test name
Test status
Simulation time 6765602293 ps
CPU time 169.17 seconds
Started Apr 28 02:00:03 PM PDT 24
Finished Apr 28 02:02:52 PM PDT 24
Peak memory 264456 kb
Host smart-f1d84725-acc2-49fb-9b7a-dd32277b658f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853386159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.1853386159
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.3181757872
Short name T1137
Test name
Test status
Simulation time 25016461229 ps
CPU time 360.69 seconds
Started Apr 28 02:00:02 PM PDT 24
Finished Apr 28 02:06:03 PM PDT 24
Peak memory 265832 kb
Host smart-abe0fb32-d09a-4503-9ee4-a89e5dc258b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181757872 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.3181757872
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.4199065450
Short name T997
Test name
Test status
Simulation time 13331834727 ps
CPU time 27.31 seconds
Started Apr 28 01:59:58 PM PDT 24
Finished Apr 28 02:00:26 PM PDT 24
Peak memory 242272 kb
Host smart-338d8e2c-2ba5-40b0-848b-739522779287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199065450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.4199065450
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.193778193
Short name T922
Test name
Test status
Simulation time 484611220 ps
CPU time 3.47 seconds
Started Apr 28 02:06:22 PM PDT 24
Finished Apr 28 02:06:26 PM PDT 24
Peak memory 241356 kb
Host smart-ea506834-6522-49db-a0f5-e49559d4826e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193778193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.193778193
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.18452971
Short name T52
Test name
Test status
Simulation time 526080864 ps
CPU time 4.51 seconds
Started Apr 28 02:06:22 PM PDT 24
Finished Apr 28 02:06:27 PM PDT 24
Peak memory 241416 kb
Host smart-9721b5df-9b39-4553-a61f-e953d19b2a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18452971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.18452971
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.158220277
Short name T491
Test name
Test status
Simulation time 293701755 ps
CPU time 3.35 seconds
Started Apr 28 02:06:21 PM PDT 24
Finished Apr 28 02:06:26 PM PDT 24
Peak memory 241320 kb
Host smart-87cd9216-c09a-4fda-8cbf-788b2aa467a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158220277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.158220277
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.2790755565
Short name T1110
Test name
Test status
Simulation time 205153274 ps
CPU time 3.75 seconds
Started Apr 28 02:06:25 PM PDT 24
Finished Apr 28 02:06:29 PM PDT 24
Peak memory 241324 kb
Host smart-5827af1a-7d2d-4416-9161-8aa7fe4992a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790755565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.2790755565
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.3400853001
Short name T413
Test name
Test status
Simulation time 140621138 ps
CPU time 4.06 seconds
Started Apr 28 02:06:22 PM PDT 24
Finished Apr 28 02:06:27 PM PDT 24
Peak memory 241360 kb
Host smart-1b4162f4-7af0-4791-8763-12e71e79ea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400853001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.3400853001
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.3063148524
Short name T815
Test name
Test status
Simulation time 463755333 ps
CPU time 4.14 seconds
Started Apr 28 02:06:21 PM PDT 24
Finished Apr 28 02:06:25 PM PDT 24
Peak memory 241332 kb
Host smart-abafb3b0-d091-4ca9-b80e-d8441e2782bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063148524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.3063148524
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.307245406
Short name T651
Test name
Test status
Simulation time 165172483 ps
CPU time 4.23 seconds
Started Apr 28 02:06:28 PM PDT 24
Finished Apr 28 02:06:32 PM PDT 24
Peak memory 241788 kb
Host smart-aa5e1975-6e05-4aa6-a1f5-59b9c5f9b307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307245406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.307245406
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.2099411576
Short name T1086
Test name
Test status
Simulation time 148180083 ps
CPU time 4.17 seconds
Started Apr 28 02:06:29 PM PDT 24
Finished Apr 28 02:06:33 PM PDT 24
Peak memory 241736 kb
Host smart-868eb1ee-16d0-4307-a873-71079f6cfab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099411576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.2099411576
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.3039595443
Short name T786
Test name
Test status
Simulation time 58692567 ps
CPU time 1.81 seconds
Started Apr 28 02:00:10 PM PDT 24
Finished Apr 28 02:00:12 PM PDT 24
Peak memory 239804 kb
Host smart-2d2cc7ec-b0d6-464d-95f3-0b0a03007d3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039595443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.3039595443
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.3268341631
Short name T85
Test name
Test status
Simulation time 12946545821 ps
CPU time 35.31 seconds
Started Apr 28 02:00:07 PM PDT 24
Finished Apr 28 02:00:42 PM PDT 24
Peak memory 242332 kb
Host smart-79aae336-afdd-490e-b81a-c0e0dda7c708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268341631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.3268341631
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.627279738
Short name T831
Test name
Test status
Simulation time 2359646017 ps
CPU time 14.14 seconds
Started Apr 28 02:00:06 PM PDT 24
Finished Apr 28 02:00:20 PM PDT 24
Peak memory 241400 kb
Host smart-f3bac5e6-3434-4f73-b199-b627b2b8ef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627279738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.627279738
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.3790041145
Short name T529
Test name
Test status
Simulation time 2144242148 ps
CPU time 23.87 seconds
Started Apr 28 02:00:08 PM PDT 24
Finished Apr 28 02:00:32 PM PDT 24
Peak memory 242300 kb
Host smart-a039c8a5-ee90-4055-9310-23d19b9491c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790041145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.3790041145
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.536359774
Short name T921
Test name
Test status
Simulation time 311471066 ps
CPU time 4.27 seconds
Started Apr 28 02:00:01 PM PDT 24
Finished Apr 28 02:00:05 PM PDT 24
Peak memory 241360 kb
Host smart-13a34d05-5a2d-4a73-b242-18115133f034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536359774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.536359774
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.2669249376
Short name T897
Test name
Test status
Simulation time 2436569110 ps
CPU time 38.74 seconds
Started Apr 28 02:00:07 PM PDT 24
Finished Apr 28 02:00:46 PM PDT 24
Peak memory 246564 kb
Host smart-4225e7c8-589f-42ee-9010-c678be6e565d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669249376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.2669249376
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.1822299848
Short name T495
Test name
Test status
Simulation time 1758995130 ps
CPU time 24.37 seconds
Started Apr 28 02:00:11 PM PDT 24
Finished Apr 28 02:00:36 PM PDT 24
Peak memory 247964 kb
Host smart-4f2980c1-0420-433a-9c45-6d97628da3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822299848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.1822299848
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.2835751968
Short name T957
Test name
Test status
Simulation time 284725343 ps
CPU time 7.05 seconds
Started Apr 28 02:00:09 PM PDT 24
Finished Apr 28 02:00:16 PM PDT 24
Peak memory 241392 kb
Host smart-b4080982-ad64-40e8-890b-c400393d0368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835751968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2835751968
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.415418456
Short name T1172
Test name
Test status
Simulation time 820244736 ps
CPU time 6.57 seconds
Started Apr 28 02:00:02 PM PDT 24
Finished Apr 28 02:00:09 PM PDT 24
Peak memory 241220 kb
Host smart-d62a826e-ca03-438d-99c9-4443862ba43f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415418456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.415418456
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.1261664731
Short name T940
Test name
Test status
Simulation time 5139069810 ps
CPU time 13.23 seconds
Started Apr 28 02:00:08 PM PDT 24
Finished Apr 28 02:00:21 PM PDT 24
Peak memory 248052 kb
Host smart-fe510260-5ae0-4b2b-b402-09f78a6ceaaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1261664731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.1261664731
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.4220808175
Short name T571
Test name
Test status
Simulation time 948490560 ps
CPU time 11.91 seconds
Started Apr 28 02:00:02 PM PDT 24
Finished Apr 28 02:00:15 PM PDT 24
Peak memory 241600 kb
Host smart-01ca460f-e3fe-42e8-b1a4-53c4a1daf488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220808175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.4220808175
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.2859638017
Short name T1019
Test name
Test status
Simulation time 25193755833 ps
CPU time 231.29 seconds
Started Apr 28 02:00:12 PM PDT 24
Finished Apr 28 02:04:04 PM PDT 24
Peak memory 247144 kb
Host smart-fd00ba35-ee01-4a20-8c2f-cab99e06a315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859638017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.2859638017
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.3318998922
Short name T335
Test name
Test status
Simulation time 147418433309 ps
CPU time 1555.34 seconds
Started Apr 28 02:00:10 PM PDT 24
Finished Apr 28 02:26:06 PM PDT 24
Peak memory 294440 kb
Host smart-19de557c-92f2-4853-b2df-98bddde05823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318998922 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.3318998922
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.1724527047
Short name T578
Test name
Test status
Simulation time 1695500746 ps
CPU time 18.38 seconds
Started Apr 28 02:00:11 PM PDT 24
Finished Apr 28 02:00:30 PM PDT 24
Peak memory 241388 kb
Host smart-ce3d317a-fdd3-45af-83af-ca1cb8483774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724527047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.1724527047
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.648854290
Short name T962
Test name
Test status
Simulation time 135662137 ps
CPU time 3.82 seconds
Started Apr 28 02:06:28 PM PDT 24
Finished Apr 28 02:06:32 PM PDT 24
Peak memory 241732 kb
Host smart-2ae2a8ae-ea85-4f05-8585-894c39f5fc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648854290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.648854290
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.2386098352
Short name T898
Test name
Test status
Simulation time 464533910 ps
CPU time 4.59 seconds
Started Apr 28 02:06:28 PM PDT 24
Finished Apr 28 02:06:33 PM PDT 24
Peak memory 241716 kb
Host smart-8f39648f-96a0-40b3-97b4-279ad0d5fb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386098352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.2386098352
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.3404042964
Short name T918
Test name
Test status
Simulation time 3117270202 ps
CPU time 7.42 seconds
Started Apr 28 02:06:30 PM PDT 24
Finished Apr 28 02:06:38 PM PDT 24
Peak memory 241800 kb
Host smart-49a256f5-9cc3-428b-8de7-783171e75926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404042964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.3404042964
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.1254534631
Short name T538
Test name
Test status
Simulation time 186614490 ps
CPU time 4.81 seconds
Started Apr 28 02:06:28 PM PDT 24
Finished Apr 28 02:06:33 PM PDT 24
Peak memory 241272 kb
Host smart-1d4f2de8-c7dd-42dd-8db7-1915b53af97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254534631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.1254534631
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.980156040
Short name T1142
Test name
Test status
Simulation time 296039371 ps
CPU time 3.79 seconds
Started Apr 28 02:06:28 PM PDT 24
Finished Apr 28 02:06:32 PM PDT 24
Peak memory 241372 kb
Host smart-c8329cbc-27a8-4c0b-ad00-375dfa5995c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980156040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.980156040
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.1643345728
Short name T789
Test name
Test status
Simulation time 144354630 ps
CPU time 4.99 seconds
Started Apr 28 02:06:28 PM PDT 24
Finished Apr 28 02:06:34 PM PDT 24
Peak memory 241344 kb
Host smart-05af2c9c-c392-48bd-9374-4273e7d26d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643345728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.1643345728
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.266872211
Short name T195
Test name
Test status
Simulation time 211642348 ps
CPU time 4.16 seconds
Started Apr 28 02:06:28 PM PDT 24
Finished Apr 28 02:06:33 PM PDT 24
Peak memory 241404 kb
Host smart-f558204f-a6a0-40a4-94f7-2911ea328efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266872211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.266872211
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.1828907882
Short name T1134
Test name
Test status
Simulation time 2783805853 ps
CPU time 5.61 seconds
Started Apr 28 02:06:29 PM PDT 24
Finished Apr 28 02:06:35 PM PDT 24
Peak memory 241552 kb
Host smart-cd98f13f-b5d0-4485-a235-39c5337c1bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828907882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.1828907882
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.3093579637
Short name T438
Test name
Test status
Simulation time 180466103 ps
CPU time 3.28 seconds
Started Apr 28 02:06:33 PM PDT 24
Finished Apr 28 02:06:36 PM PDT 24
Peak memory 241652 kb
Host smart-00362f9a-4dda-40aa-b3aa-cbcfdb847b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093579637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.3093579637
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.651546213
Short name T1139
Test name
Test status
Simulation time 353485721 ps
CPU time 5.03 seconds
Started Apr 28 02:06:29 PM PDT 24
Finished Apr 28 02:06:34 PM PDT 24
Peak memory 241752 kb
Host smart-eb623d74-38f3-4764-b4a2-1a650e143949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651546213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.651546213
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.1168336391
Short name T202
Test name
Test status
Simulation time 117171379 ps
CPU time 1.95 seconds
Started Apr 28 02:00:18 PM PDT 24
Finished Apr 28 02:00:20 PM PDT 24
Peak memory 239852 kb
Host smart-52b7543b-0d46-4122-9054-81523986c743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168336391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.1168336391
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.1386595472
Short name T767
Test name
Test status
Simulation time 370204108 ps
CPU time 2.91 seconds
Started Apr 28 02:00:22 PM PDT 24
Finished Apr 28 02:00:26 PM PDT 24
Peak memory 246036 kb
Host smart-7578c2b1-090b-4528-a0c0-5f062ee0b94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386595472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.1386595472
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.89698359
Short name T1072
Test name
Test status
Simulation time 1323083611 ps
CPU time 23.8 seconds
Started Apr 28 02:00:16 PM PDT 24
Finished Apr 28 02:00:40 PM PDT 24
Peak memory 241448 kb
Host smart-223d95c2-207b-4159-ad35-9a4db1119711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89698359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.89698359
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.878049089
Short name T1055
Test name
Test status
Simulation time 642173728 ps
CPU time 20.08 seconds
Started Apr 28 02:00:22 PM PDT 24
Finished Apr 28 02:00:42 PM PDT 24
Peak memory 241544 kb
Host smart-dc4993b3-e6e3-46e0-a1ab-fd9298facb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878049089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.878049089
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.1156326676
Short name T545
Test name
Test status
Simulation time 12158682561 ps
CPU time 38.23 seconds
Started Apr 28 02:00:22 PM PDT 24
Finished Apr 28 02:01:00 PM PDT 24
Peak memory 247364 kb
Host smart-4d3ec52c-4d06-4dd5-9eee-929e11677243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156326676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.1156326676
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.1108142007
Short name T926
Test name
Test status
Simulation time 1153711404 ps
CPU time 12.54 seconds
Started Apr 28 02:00:15 PM PDT 24
Finished Apr 28 02:00:28 PM PDT 24
Peak memory 241816 kb
Host smart-29f0826e-04c4-4a56-9a3f-20aa62947cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108142007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.1108142007
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.1352576714
Short name T1177
Test name
Test status
Simulation time 141211374 ps
CPU time 3.85 seconds
Started Apr 28 02:00:22 PM PDT 24
Finished Apr 28 02:00:27 PM PDT 24
Peak memory 241308 kb
Host smart-559a90ba-f56c-4392-9233-80654feece50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352576714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.1352576714
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.2105715883
Short name T813
Test name
Test status
Simulation time 7613839545 ps
CPU time 27.71 seconds
Started Apr 28 02:00:11 PM PDT 24
Finished Apr 28 02:00:39 PM PDT 24
Peak memory 241364 kb
Host smart-e8f15400-c2f2-4625-928f-520663c43b63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2105715883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.2105715883
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.1089837421
Short name T302
Test name
Test status
Simulation time 103702586 ps
CPU time 3.36 seconds
Started Apr 28 02:00:15 PM PDT 24
Finished Apr 28 02:00:18 PM PDT 24
Peak memory 247844 kb
Host smart-824bfcc4-6cf5-4397-86c4-09ba942f9642
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1089837421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.1089837421
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.3615392304
Short name T432
Test name
Test status
Simulation time 844502669 ps
CPU time 9.11 seconds
Started Apr 28 02:00:11 PM PDT 24
Finished Apr 28 02:00:21 PM PDT 24
Peak memory 241532 kb
Host smart-a610d0a5-3801-41a9-b983-7e9e8dbbcee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615392304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.3615392304
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.1574347159
Short name T412
Test name
Test status
Simulation time 75987500551 ps
CPU time 198.74 seconds
Started Apr 28 02:00:15 PM PDT 24
Finished Apr 28 02:03:34 PM PDT 24
Peak memory 249808 kb
Host smart-7d785003-96ff-408a-b484-744332e5aacb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574347159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.1574347159
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.971077740
Short name T526
Test name
Test status
Simulation time 1714281147 ps
CPU time 25.47 seconds
Started Apr 28 02:00:16 PM PDT 24
Finished Apr 28 02:00:42 PM PDT 24
Peak memory 241928 kb
Host smart-001c86c9-3100-425b-95f7-81538501e095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971077740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.971077740
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.3463046111
Short name T79
Test name
Test status
Simulation time 112748413 ps
CPU time 3.03 seconds
Started Apr 28 02:06:33 PM PDT 24
Finished Apr 28 02:06:36 PM PDT 24
Peak memory 241368 kb
Host smart-406d8d57-6bda-4b24-92d6-1b63d7d169b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463046111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.3463046111
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.2773800526
Short name T827
Test name
Test status
Simulation time 289196946 ps
CPU time 4.09 seconds
Started Apr 28 02:06:34 PM PDT 24
Finished Apr 28 02:06:38 PM PDT 24
Peak memory 241376 kb
Host smart-0912a07b-ac1d-410e-b14b-057bffa12df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773800526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.2773800526
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.1920676829
Short name T478
Test name
Test status
Simulation time 116065415 ps
CPU time 4.05 seconds
Started Apr 28 02:06:36 PM PDT 24
Finished Apr 28 02:06:40 PM PDT 24
Peak memory 241644 kb
Host smart-18501be5-028f-428d-974c-4f99087e2632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920676829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.1920676829
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.3612235754
Short name T134
Test name
Test status
Simulation time 416771090 ps
CPU time 2.99 seconds
Started Apr 28 02:06:33 PM PDT 24
Finished Apr 28 02:06:37 PM PDT 24
Peak memory 241708 kb
Host smart-0a930c6c-47f9-4dfc-a072-7d69a3d29e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612235754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3612235754
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.2168784716
Short name T858
Test name
Test status
Simulation time 221620742 ps
CPU time 4.74 seconds
Started Apr 28 02:06:35 PM PDT 24
Finished Apr 28 02:06:40 PM PDT 24
Peak memory 241344 kb
Host smart-78d82d7d-71d3-4514-8f84-83e58974b24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168784716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2168784716
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.539620109
Short name T218
Test name
Test status
Simulation time 287234797 ps
CPU time 3.99 seconds
Started Apr 28 02:06:35 PM PDT 24
Finished Apr 28 02:06:39 PM PDT 24
Peak memory 241592 kb
Host smart-e3c91652-67d0-4faa-bbaf-1a6845dd1773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539620109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.539620109
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.1299433077
Short name T741
Test name
Test status
Simulation time 2797448856 ps
CPU time 5.57 seconds
Started Apr 28 02:06:37 PM PDT 24
Finished Apr 28 02:06:43 PM PDT 24
Peak memory 241800 kb
Host smart-e5d81e39-00af-419d-bfa1-214e116f0848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299433077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.1299433077
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.3299518444
Short name T914
Test name
Test status
Simulation time 82480971 ps
CPU time 2.82 seconds
Started Apr 28 02:06:36 PM PDT 24
Finished Apr 28 02:06:39 PM PDT 24
Peak memory 241504 kb
Host smart-31f3c1c4-3a83-4885-bb51-8451249250b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299518444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.3299518444
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.4070937947
Short name T1115
Test name
Test status
Simulation time 285562464 ps
CPU time 4.61 seconds
Started Apr 28 02:06:37 PM PDT 24
Finished Apr 28 02:06:41 PM PDT 24
Peak memory 241676 kb
Host smart-281f7650-500a-435e-85b0-e7441963672e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070937947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.4070937947
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.366677863
Short name T618
Test name
Test status
Simulation time 407052490 ps
CPU time 4.44 seconds
Started Apr 28 02:06:33 PM PDT 24
Finished Apr 28 02:06:38 PM PDT 24
Peak memory 241480 kb
Host smart-da08ff69-e514-429a-bac9-20972ecb5487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366677863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.366677863
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.1386227000
Short name T493
Test name
Test status
Simulation time 65284124 ps
CPU time 1.83 seconds
Started Apr 28 02:00:25 PM PDT 24
Finished Apr 28 02:00:27 PM PDT 24
Peak memory 240032 kb
Host smart-8454424e-c789-4bf3-8559-40640198a858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386227000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1386227000
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.3063544527
Short name T64
Test name
Test status
Simulation time 776546499 ps
CPU time 5.86 seconds
Started Apr 28 02:00:25 PM PDT 24
Finished Apr 28 02:00:32 PM PDT 24
Peak memory 247640 kb
Host smart-ce1610e3-ff4a-4230-b651-c4f9e64ab00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063544527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.3063544527
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.1160055366
Short name T157
Test name
Test status
Simulation time 749399109 ps
CPU time 19.2 seconds
Started Apr 28 02:00:20 PM PDT 24
Finished Apr 28 02:00:40 PM PDT 24
Peak memory 241336 kb
Host smart-bcbf18c0-0bb4-440d-9a23-532aa7bb09af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160055366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1160055366
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.4283081987
Short name T654
Test name
Test status
Simulation time 2346120595 ps
CPU time 5.3 seconds
Started Apr 28 02:00:19 PM PDT 24
Finished Apr 28 02:00:25 PM PDT 24
Peak memory 241352 kb
Host smart-06112787-215c-4246-8c3c-931a25b3ac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283081987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.4283081987
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.1800894465
Short name T973
Test name
Test status
Simulation time 2557075969 ps
CPU time 6.1 seconds
Started Apr 28 02:00:17 PM PDT 24
Finished Apr 28 02:00:24 PM PDT 24
Peak memory 241764 kb
Host smart-077e5a58-57e8-4044-9595-92447c508334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800894465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.1800894465
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.3450912419
Short name T168
Test name
Test status
Simulation time 610533524 ps
CPU time 5.6 seconds
Started Apr 28 02:00:25 PM PDT 24
Finished Apr 28 02:00:31 PM PDT 24
Peak memory 241796 kb
Host smart-9ddfd1f6-5b28-465b-b00c-9d0dbe823c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450912419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.3450912419
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.3570742373
Short name T839
Test name
Test status
Simulation time 536381059 ps
CPU time 8.2 seconds
Started Apr 28 02:00:24 PM PDT 24
Finished Apr 28 02:00:33 PM PDT 24
Peak memory 241448 kb
Host smart-550a9787-a284-4670-ad36-c1b7aa3b35cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570742373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.3570742373
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.2769785865
Short name T671
Test name
Test status
Simulation time 1922690726 ps
CPU time 11.53 seconds
Started Apr 28 02:00:21 PM PDT 24
Finished Apr 28 02:00:33 PM PDT 24
Peak memory 242048 kb
Host smart-98d0f101-300d-4b83-a490-9b31dc6e0f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769785865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.2769785865
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.2652071912
Short name T240
Test name
Test status
Simulation time 725508247 ps
CPU time 12.21 seconds
Started Apr 28 02:00:21 PM PDT 24
Finished Apr 28 02:00:34 PM PDT 24
Peak memory 241316 kb
Host smart-9be3387f-bd56-4278-be52-03322a1981d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652071912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2652071912
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.328155215
Short name T470
Test name
Test status
Simulation time 1599129841 ps
CPU time 12 seconds
Started Apr 28 02:00:26 PM PDT 24
Finished Apr 28 02:00:38 PM PDT 24
Peak memory 241296 kb
Host smart-173f03ce-aec0-4b06-93c2-f8abc32108a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328155215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.328155215
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.2149713261
Short name T653
Test name
Test status
Simulation time 381261293 ps
CPU time 5.48 seconds
Started Apr 28 02:00:17 PM PDT 24
Finished Apr 28 02:00:22 PM PDT 24
Peak memory 241308 kb
Host smart-2772a57a-ec32-4f3c-8d3e-514f43f2f9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149713261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2149713261
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.1403235851
Short name T389
Test name
Test status
Simulation time 12284257139 ps
CPU time 141.43 seconds
Started Apr 28 02:00:24 PM PDT 24
Finished Apr 28 02:02:46 PM PDT 24
Peak memory 248144 kb
Host smart-e2588907-1834-4028-94e8-0ff2b69a7b88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403235851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.1403235851
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.2185917316
Short name T1182
Test name
Test status
Simulation time 1399096592341 ps
CPU time 2710.79 seconds
Started Apr 28 02:00:24 PM PDT 24
Finished Apr 28 02:45:35 PM PDT 24
Peak memory 690540 kb
Host smart-dfa29318-fc89-4437-af04-5a40c1baa336
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185917316 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.2185917316
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.2244897869
Short name T774
Test name
Test status
Simulation time 141269268 ps
CPU time 4.08 seconds
Started Apr 28 02:06:34 PM PDT 24
Finished Apr 28 02:06:39 PM PDT 24
Peak memory 241388 kb
Host smart-a4c621c2-abe8-475d-a6ca-9d9ef2bd2a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244897869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2244897869
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.2037199047
Short name T86
Test name
Test status
Simulation time 329816115 ps
CPU time 4.68 seconds
Started Apr 28 02:06:36 PM PDT 24
Finished Apr 28 02:06:41 PM PDT 24
Peak memory 241716 kb
Host smart-f45eefbb-63b4-48e2-b4ec-bd8638bdf480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037199047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.2037199047
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.1735584676
Short name T181
Test name
Test status
Simulation time 479038201 ps
CPU time 4.49 seconds
Started Apr 28 02:06:36 PM PDT 24
Finished Apr 28 02:06:41 PM PDT 24
Peak memory 241712 kb
Host smart-10f73f7a-207c-4f6b-9da8-fc8d5b062b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735584676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.1735584676
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.4041219799
Short name T824
Test name
Test status
Simulation time 101549657 ps
CPU time 3.38 seconds
Started Apr 28 02:06:40 PM PDT 24
Finished Apr 28 02:06:44 PM PDT 24
Peak memory 241312 kb
Host smart-2e946e7e-3912-4c39-b51a-ae76b96b5509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041219799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.4041219799
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.3781173262
Short name T200
Test name
Test status
Simulation time 268894645 ps
CPU time 4.28 seconds
Started Apr 28 02:06:41 PM PDT 24
Finished Apr 28 02:06:46 PM PDT 24
Peak memory 241396 kb
Host smart-93fbee1a-4c45-4cdf-8124-73d6fe5f6e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781173262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.3781173262
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.2977056956
Short name T965
Test name
Test status
Simulation time 350313325 ps
CPU time 4.78 seconds
Started Apr 28 02:06:39 PM PDT 24
Finished Apr 28 02:06:44 PM PDT 24
Peak memory 241440 kb
Host smart-8fcc9c33-02a6-4586-8d6f-5eb54f91199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977056956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.2977056956
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.1375778341
Short name T564
Test name
Test status
Simulation time 166209789 ps
CPU time 3.66 seconds
Started Apr 28 02:06:42 PM PDT 24
Finished Apr 28 02:06:46 PM PDT 24
Peak memory 241716 kb
Host smart-98b82876-2067-4f5e-8d27-a96ad0568b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375778341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.1375778341
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.3702791133
Short name T680
Test name
Test status
Simulation time 224685852 ps
CPU time 3.55 seconds
Started Apr 28 02:06:40 PM PDT 24
Finished Apr 28 02:06:44 PM PDT 24
Peak memory 241432 kb
Host smart-167c4286-e31c-484e-b5ce-1a200122b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702791133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3702791133
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.3633257625
Short name T742
Test name
Test status
Simulation time 215238204 ps
CPU time 3.69 seconds
Started Apr 28 02:06:44 PM PDT 24
Finished Apr 28 02:06:48 PM PDT 24
Peak memory 241356 kb
Host smart-2c2d63de-2cac-4056-b28d-12204b607650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633257625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.3633257625
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.2360941686
Short name T821
Test name
Test status
Simulation time 52658392 ps
CPU time 1.65 seconds
Started Apr 28 02:00:34 PM PDT 24
Finished Apr 28 02:00:36 PM PDT 24
Peak memory 239736 kb
Host smart-efe2cf4f-fbff-4980-9ce9-eb132fbfdf75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360941686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.2360941686
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.2756322985
Short name T950
Test name
Test status
Simulation time 1516097829 ps
CPU time 15.46 seconds
Started Apr 28 02:00:29 PM PDT 24
Finished Apr 28 02:00:45 PM PDT 24
Peak memory 241416 kb
Host smart-f54f385c-cac7-4c8e-bae9-339c77ab9099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756322985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.2756322985
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.2656499158
Short name T509
Test name
Test status
Simulation time 2814724269 ps
CPU time 16.55 seconds
Started Apr 28 02:00:29 PM PDT 24
Finished Apr 28 02:00:46 PM PDT 24
Peak memory 241440 kb
Host smart-932eb103-9002-4a30-ad4b-362e5448a095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656499158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.2656499158
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.2772099436
Short name T1037
Test name
Test status
Simulation time 1803680810 ps
CPU time 4.09 seconds
Started Apr 28 02:00:26 PM PDT 24
Finished Apr 28 02:00:31 PM PDT 24
Peak memory 241388 kb
Host smart-c9e1e70a-709e-485a-946c-b372daee1871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772099436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.2772099436
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.1903911201
Short name T223
Test name
Test status
Simulation time 1603469456 ps
CPU time 14.57 seconds
Started Apr 28 02:00:30 PM PDT 24
Finished Apr 28 02:00:45 PM PDT 24
Peak memory 241768 kb
Host smart-8fdf7af2-0b27-44ba-b5b3-230d9343c04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903911201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.1903911201
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.3938827615
Short name T106
Test name
Test status
Simulation time 2877206735 ps
CPU time 32.65 seconds
Started Apr 28 02:00:33 PM PDT 24
Finished Apr 28 02:01:06 PM PDT 24
Peak memory 241468 kb
Host smart-b648940e-f186-42b0-bcf4-affd9c73340e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938827615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.3938827615
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.144797995
Short name T694
Test name
Test status
Simulation time 1029978693 ps
CPU time 13.48 seconds
Started Apr 28 02:00:31 PM PDT 24
Finished Apr 28 02:00:45 PM PDT 24
Peak memory 241320 kb
Host smart-8a8e130e-b72b-450f-b9fb-a52fe5064352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144797995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.144797995
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.452679176
Short name T1104
Test name
Test status
Simulation time 2076502475 ps
CPU time 4.99 seconds
Started Apr 28 02:00:30 PM PDT 24
Finished Apr 28 02:00:35 PM PDT 24
Peak memory 241344 kb
Host smart-a4459612-e3d4-476b-b946-3aafbc7fa5c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=452679176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.452679176
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.929321064
Short name T1009
Test name
Test status
Simulation time 305024153 ps
CPU time 7.02 seconds
Started Apr 28 02:00:34 PM PDT 24
Finished Apr 28 02:00:42 PM PDT 24
Peak memory 241292 kb
Host smart-7e764347-3798-4514-9efb-9c5132feeaf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929321064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.929321064
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.148741622
Short name T399
Test name
Test status
Simulation time 854272772 ps
CPU time 10.44 seconds
Started Apr 28 02:00:26 PM PDT 24
Finished Apr 28 02:00:37 PM PDT 24
Peak memory 241540 kb
Host smart-8ad12541-d9e1-4554-b8b6-7cdcb2bb134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148741622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.148741622
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.1929324340
Short name T697
Test name
Test status
Simulation time 11649493516 ps
CPU time 27.87 seconds
Started Apr 28 02:00:32 PM PDT 24
Finished Apr 28 02:01:00 PM PDT 24
Peak memory 242120 kb
Host smart-080f29a5-addd-420a-86df-5acfd203628b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929324340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.1929324340
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.188035953
Short name T1130
Test name
Test status
Simulation time 207227444 ps
CPU time 4.43 seconds
Started Apr 28 02:06:44 PM PDT 24
Finished Apr 28 02:06:48 PM PDT 24
Peak memory 241404 kb
Host smart-1980190a-777c-4b72-890d-6fbfc493e276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188035953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.188035953
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.3179042268
Short name T124
Test name
Test status
Simulation time 1975102112 ps
CPU time 5.31 seconds
Started Apr 28 02:06:44 PM PDT 24
Finished Apr 28 02:06:49 PM PDT 24
Peak memory 241768 kb
Host smart-2336ee08-2b80-4350-9db5-ea7d8e8a475b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179042268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.3179042268
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.1161927206
Short name T599
Test name
Test status
Simulation time 156162909 ps
CPU time 4.36 seconds
Started Apr 28 02:06:42 PM PDT 24
Finished Apr 28 02:06:46 PM PDT 24
Peak memory 241324 kb
Host smart-6a288d46-9ca2-4c5a-bf42-febc481bd788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161927206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1161927206
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.3409836853
Short name T968
Test name
Test status
Simulation time 149919532 ps
CPU time 3.63 seconds
Started Apr 28 02:06:41 PM PDT 24
Finished Apr 28 02:06:45 PM PDT 24
Peak memory 241676 kb
Host smart-874fd54f-8cc3-431e-99e4-0b1e3f0725a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409836853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3409836853
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.2953925252
Short name T193
Test name
Test status
Simulation time 382240413 ps
CPU time 3.85 seconds
Started Apr 28 02:06:43 PM PDT 24
Finished Apr 28 02:06:48 PM PDT 24
Peak memory 241436 kb
Host smart-534eeb48-1436-487e-82d2-da44ee667878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953925252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.2953925252
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.2232379692
Short name T612
Test name
Test status
Simulation time 2642296337 ps
CPU time 5.77 seconds
Started Apr 28 02:06:57 PM PDT 24
Finished Apr 28 02:07:03 PM PDT 24
Peak memory 241792 kb
Host smart-8a6c0580-0122-4e3b-8adc-96ac1643dfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232379692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.2232379692
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.423375993
Short name T167
Test name
Test status
Simulation time 1319219520 ps
CPU time 4.07 seconds
Started Apr 28 02:06:45 PM PDT 24
Finished Apr 28 02:06:49 PM PDT 24
Peak memory 241468 kb
Host smart-5f9aeaae-2745-4eab-b682-f611dca96720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423375993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.423375993
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.2909109032
Short name T809
Test name
Test status
Simulation time 1732382760 ps
CPU time 5.01 seconds
Started Apr 28 02:06:42 PM PDT 24
Finished Apr 28 02:06:47 PM PDT 24
Peak memory 241332 kb
Host smart-197145ab-ace9-477e-9895-39ca43107c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909109032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.2909109032
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.4152110148
Short name T406
Test name
Test status
Simulation time 167965016 ps
CPU time 2.11 seconds
Started Apr 28 02:00:41 PM PDT 24
Finished Apr 28 02:00:43 PM PDT 24
Peak memory 239944 kb
Host smart-b4b495e2-0204-4c40-8d23-e22dfae8c8de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152110148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.4152110148
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.228940441
Short name T766
Test name
Test status
Simulation time 257397664 ps
CPU time 4.83 seconds
Started Apr 28 02:00:39 PM PDT 24
Finished Apr 28 02:00:45 PM PDT 24
Peak memory 241396 kb
Host smart-6c0fc22b-cc4e-45ae-9a54-b04597971361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228940441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.228940441
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.3632788058
Short name T861
Test name
Test status
Simulation time 3391440961 ps
CPU time 30.63 seconds
Started Apr 28 02:00:43 PM PDT 24
Finished Apr 28 02:01:14 PM PDT 24
Peak memory 244276 kb
Host smart-9ae5845a-b49a-48c1-82a5-c65fc8c916ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632788058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3632788058
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.3693847037
Short name T1098
Test name
Test status
Simulation time 3134525152 ps
CPU time 28.4 seconds
Started Apr 28 02:00:40 PM PDT 24
Finished Apr 28 02:01:09 PM PDT 24
Peak memory 241404 kb
Host smart-e11e5c03-8925-45e7-a084-b775f1b35c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693847037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3693847037
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.3285827391
Short name T196
Test name
Test status
Simulation time 1561063310 ps
CPU time 4.14 seconds
Started Apr 28 02:00:42 PM PDT 24
Finished Apr 28 02:00:47 PM PDT 24
Peak memory 241700 kb
Host smart-8879b278-edea-43d4-8406-8dc546e29747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285827391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3285827391
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.2276177504
Short name T822
Test name
Test status
Simulation time 354992406 ps
CPU time 8.1 seconds
Started Apr 28 02:00:40 PM PDT 24
Finished Apr 28 02:00:49 PM PDT 24
Peak memory 241684 kb
Host smart-d7090c67-9da2-4108-bf22-99f4725eec0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276177504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.2276177504
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.3854627765
Short name T676
Test name
Test status
Simulation time 10686086879 ps
CPU time 28.9 seconds
Started Apr 28 02:00:41 PM PDT 24
Finished Apr 28 02:01:10 PM PDT 24
Peak memory 242184 kb
Host smart-8a154cc5-5e3a-4f35-99c2-0f737f78ba13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854627765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.3854627765
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.43983264
Short name T414
Test name
Test status
Simulation time 378504638 ps
CPU time 4.15 seconds
Started Apr 28 02:00:39 PM PDT 24
Finished Apr 28 02:00:43 PM PDT 24
Peak memory 241204 kb
Host smart-e504c59b-a0b2-4d30-8a27-3f34f50d608d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43983264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.43983264
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.1926090212
Short name T1045
Test name
Test status
Simulation time 8260816582 ps
CPU time 20.17 seconds
Started Apr 28 02:00:40 PM PDT 24
Finished Apr 28 02:01:01 PM PDT 24
Peak memory 248028 kb
Host smart-64c2be85-e6bb-4eac-a488-573495c5d828
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1926090212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1926090212
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.990002646
Short name T620
Test name
Test status
Simulation time 2625492100 ps
CPU time 6.89 seconds
Started Apr 28 02:00:40 PM PDT 24
Finished Apr 28 02:00:47 PM PDT 24
Peak memory 241272 kb
Host smart-d1557e3c-cb01-49e8-9603-cf92e61c7505
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=990002646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.990002646
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.2490439675
Short name T1054
Test name
Test status
Simulation time 96839427 ps
CPU time 3.1 seconds
Started Apr 28 02:00:34 PM PDT 24
Finished Apr 28 02:00:37 PM PDT 24
Peak memory 241356 kb
Host smart-4a9c7843-4186-446e-9476-e1fc7184f9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490439675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.2490439675
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.2067489205
Short name T1057
Test name
Test status
Simulation time 7696742989 ps
CPU time 86.1 seconds
Started Apr 28 02:00:38 PM PDT 24
Finished Apr 28 02:02:05 PM PDT 24
Peak memory 244876 kb
Host smart-88107f90-0812-4057-bc82-4d5d57a31ca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067489205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.2067489205
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.2469131809
Short name T46
Test name
Test status
Simulation time 187132191 ps
CPU time 4.31 seconds
Started Apr 28 02:06:47 PM PDT 24
Finished Apr 28 02:06:52 PM PDT 24
Peak memory 241392 kb
Host smart-3651633f-985c-474a-9be5-c7a59cf1e018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469131809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.2469131809
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.3723446589
Short name T532
Test name
Test status
Simulation time 475022925 ps
CPU time 4.79 seconds
Started Apr 28 02:06:45 PM PDT 24
Finished Apr 28 02:06:50 PM PDT 24
Peak memory 241776 kb
Host smart-ba582ee5-1fa6-45f0-8347-a1cd4ee852cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723446589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3723446589
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.602770202
Short name T224
Test name
Test status
Simulation time 150996758 ps
CPU time 3.06 seconds
Started Apr 28 02:06:48 PM PDT 24
Finished Apr 28 02:06:51 PM PDT 24
Peak memory 241324 kb
Host smart-1d3ef888-d1c0-4126-a157-7a8423439409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602770202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.602770202
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.3498435441
Short name T570
Test name
Test status
Simulation time 1721505510 ps
CPU time 4.53 seconds
Started Apr 28 02:06:50 PM PDT 24
Finished Apr 28 02:06:55 PM PDT 24
Peak memory 241680 kb
Host smart-7230337c-6714-4ce7-bd3a-74ced5291ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498435441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.3498435441
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.3332895274
Short name T194
Test name
Test status
Simulation time 190173675 ps
CPU time 3.97 seconds
Started Apr 28 02:06:49 PM PDT 24
Finished Apr 28 02:06:54 PM PDT 24
Peak memory 241680 kb
Host smart-655b242e-65c1-480c-88a4-5aa6741c1a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332895274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.3332895274
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.1900266265
Short name T744
Test name
Test status
Simulation time 244808046 ps
CPU time 4.22 seconds
Started Apr 28 02:06:49 PM PDT 24
Finished Apr 28 02:06:54 PM PDT 24
Peak memory 241292 kb
Host smart-4df859e9-8fb5-4692-941a-589ef77eed8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900266265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.1900266265
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.3267107546
Short name T1017
Test name
Test status
Simulation time 332957471 ps
CPU time 4.13 seconds
Started Apr 28 02:06:46 PM PDT 24
Finished Apr 28 02:06:50 PM PDT 24
Peak memory 241468 kb
Host smart-f20741ea-7ed7-41c2-9f00-3a9b6d54bed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267107546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.3267107546
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.561211129
Short name T1078
Test name
Test status
Simulation time 103084685 ps
CPU time 3.55 seconds
Started Apr 28 02:06:47 PM PDT 24
Finished Apr 28 02:06:52 PM PDT 24
Peak memory 241296 kb
Host smart-407f9ea0-45d4-49a3-95e1-2589c32feb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561211129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.561211129
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.2316572152
Short name T915
Test name
Test status
Simulation time 405333046 ps
CPU time 3.33 seconds
Started Apr 28 02:06:47 PM PDT 24
Finished Apr 28 02:06:51 PM PDT 24
Peak memory 241524 kb
Host smart-5122efc4-7b85-4dee-b86c-cc05cd55a1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316572152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.2316572152
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.2628562527
Short name T974
Test name
Test status
Simulation time 287427197 ps
CPU time 4.07 seconds
Started Apr 28 02:06:47 PM PDT 24
Finished Apr 28 02:06:51 PM PDT 24
Peak memory 241428 kb
Host smart-f51d3eb0-69d0-4035-bd10-51abc1294e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628562527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.2628562527
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.178058122
Short name T1068
Test name
Test status
Simulation time 177657483 ps
CPU time 1.62 seconds
Started Apr 28 01:57:26 PM PDT 24
Finished Apr 28 01:57:28 PM PDT 24
Peak memory 240056 kb
Host smart-6e0e9d4c-885c-4c48-9072-04cf3b8b43c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178058122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.178058122
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.3198828398
Short name T123
Test name
Test status
Simulation time 2983788309 ps
CPU time 17.59 seconds
Started Apr 28 01:57:19 PM PDT 24
Finished Apr 28 01:57:38 PM PDT 24
Peak memory 241544 kb
Host smart-b9437ab4-502a-4d77-bf6b-7286aae0421d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198828398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.3198828398
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1399021418
Short name T49
Test name
Test status
Simulation time 1267403855 ps
CPU time 21.91 seconds
Started Apr 28 01:57:18 PM PDT 24
Finished Apr 28 01:57:40 PM PDT 24
Peak memory 248004 kb
Host smart-f06e3637-5f47-4685-b8a4-284180f9ce5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399021418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1399021418
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.10397209
Short name T584
Test name
Test status
Simulation time 1382508467 ps
CPU time 38.61 seconds
Started Apr 28 01:57:23 PM PDT 24
Finished Apr 28 01:58:02 PM PDT 24
Peak memory 241860 kb
Host smart-5db91003-3698-49d1-8b2f-75ccb6670c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10397209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.10397209
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.2938683662
Short name T746
Test name
Test status
Simulation time 991615660 ps
CPU time 24.06 seconds
Started Apr 28 01:57:19 PM PDT 24
Finished Apr 28 01:57:43 PM PDT 24
Peak memory 241212 kb
Host smart-bdbc0340-9528-4f38-91f1-48948e4af926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938683662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.2938683662
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.2216065160
Short name T581
Test name
Test status
Simulation time 135627425 ps
CPU time 3.72 seconds
Started Apr 28 01:57:13 PM PDT 24
Finished Apr 28 01:57:18 PM PDT 24
Peak memory 241440 kb
Host smart-9d0b99b7-f8b1-482f-8ac0-8c5cf59b9d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216065160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.2216065160
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.3973625879
Short name T159
Test name
Test status
Simulation time 2612041903 ps
CPU time 18.81 seconds
Started Apr 28 01:57:24 PM PDT 24
Finished Apr 28 01:57:43 PM PDT 24
Peak memory 242276 kb
Host smart-cd1cae8b-03a7-470e-9ff5-d2a390e82e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973625879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.3973625879
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.1133649068
Short name T875
Test name
Test status
Simulation time 1760805926 ps
CPU time 20.2 seconds
Started Apr 28 01:57:24 PM PDT 24
Finished Apr 28 01:57:44 PM PDT 24
Peak memory 241820 kb
Host smart-b0078718-b5d5-42c2-8d94-3e1cbff409e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133649068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1133649068
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.1689160219
Short name T265
Test name
Test status
Simulation time 241286674 ps
CPU time 2.96 seconds
Started Apr 28 01:57:22 PM PDT 24
Finished Apr 28 01:57:25 PM PDT 24
Peak memory 241348 kb
Host smart-7751ca6d-0896-4f44-a907-cc5890611ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689160219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.1689160219
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.618241236
Short name T1119
Test name
Test status
Simulation time 631222023 ps
CPU time 21.35 seconds
Started Apr 28 01:57:18 PM PDT 24
Finished Apr 28 01:57:40 PM PDT 24
Peak memory 241272 kb
Host smart-800da8b0-5f26-4eac-8782-daae878b173d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618241236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.618241236
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.3859296973
Short name T636
Test name
Test status
Simulation time 551323148 ps
CPU time 6.03 seconds
Started Apr 28 01:57:23 PM PDT 24
Finished Apr 28 01:57:30 PM PDT 24
Peak memory 241620 kb
Host smart-93cffd26-801a-4073-a6db-3fbf04475e70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3859296973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3859296973
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.1400709534
Short name T471
Test name
Test status
Simulation time 259705212 ps
CPU time 5.67 seconds
Started Apr 28 01:57:13 PM PDT 24
Finished Apr 28 01:57:20 PM PDT 24
Peak memory 241616 kb
Host smart-4d7502d6-3b70-4b40-b59b-da0059d5d1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400709534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.1400709534
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.3348435429
Short name T108
Test name
Test status
Simulation time 159935995578 ps
CPU time 496.8 seconds
Started Apr 28 01:57:27 PM PDT 24
Finished Apr 28 02:05:45 PM PDT 24
Peak memory 325424 kb
Host smart-f5a91c1e-1eb9-4e63-bf1d-d105e098c5ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348435429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
3348435429
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.3141492028
Short name T146
Test name
Test status
Simulation time 420171665992 ps
CPU time 3260.92 seconds
Started Apr 28 01:57:23 PM PDT 24
Finished Apr 28 02:51:45 PM PDT 24
Peak memory 593316 kb
Host smart-683da289-f365-4678-a993-602c4aca538e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141492028 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.3141492028
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.3573899489
Short name T535
Test name
Test status
Simulation time 857036769 ps
CPU time 30.3 seconds
Started Apr 28 01:57:25 PM PDT 24
Finished Apr 28 01:57:56 PM PDT 24
Peak memory 247864 kb
Host smart-72f29fef-5e13-4b9c-9079-fa7e6cb6cb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573899489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.3573899489
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.810806092
Short name T497
Test name
Test status
Simulation time 1070852352 ps
CPU time 2.57 seconds
Started Apr 28 02:00:54 PM PDT 24
Finished Apr 28 02:00:57 PM PDT 24
Peak memory 240104 kb
Host smart-b7e48c41-64cb-4628-aac6-f0e71734d16e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810806092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.810806092
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.1766475686
Short name T1081
Test name
Test status
Simulation time 809768939 ps
CPU time 16.66 seconds
Started Apr 28 02:00:43 PM PDT 24
Finished Apr 28 02:01:00 PM PDT 24
Peak memory 242588 kb
Host smart-ac443ace-06ff-4552-b0b9-0cac38fb2ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766475686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1766475686
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.2202409480
Short name T641
Test name
Test status
Simulation time 1087508325 ps
CPU time 33.54 seconds
Started Apr 28 02:00:45 PM PDT 24
Finished Apr 28 02:01:19 PM PDT 24
Peak memory 241708 kb
Host smart-c3bc66fa-1acb-4b18-8148-37b15aa75e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202409480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.2202409480
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.2629321736
Short name T392
Test name
Test status
Simulation time 444035777 ps
CPU time 13.9 seconds
Started Apr 28 02:00:47 PM PDT 24
Finished Apr 28 02:01:02 PM PDT 24
Peak memory 241368 kb
Host smart-55f14891-3339-4011-92a3-cd2f90d9bfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629321736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2629321736
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.1831915835
Short name T783
Test name
Test status
Simulation time 159232912 ps
CPU time 3.07 seconds
Started Apr 28 02:00:40 PM PDT 24
Finished Apr 28 02:00:44 PM PDT 24
Peak memory 241260 kb
Host smart-e6a00d4a-4507-4830-b449-2ea964398910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831915835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1831915835
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.2409349563
Short name T352
Test name
Test status
Simulation time 1290856807 ps
CPU time 27.19 seconds
Started Apr 28 02:00:44 PM PDT 24
Finished Apr 28 02:01:11 PM PDT 24
Peak memory 248668 kb
Host smart-4361c32a-94c9-4ec8-a559-f20c67193071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409349563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.2409349563
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.604863517
Short name T980
Test name
Test status
Simulation time 2320137519 ps
CPU time 25.04 seconds
Started Apr 28 02:00:44 PM PDT 24
Finished Apr 28 02:01:10 PM PDT 24
Peak memory 241564 kb
Host smart-a5771c62-27cd-4135-8fc4-268baccc8fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604863517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.604863517
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.2422762321
Short name T759
Test name
Test status
Simulation time 147479741 ps
CPU time 6.97 seconds
Started Apr 28 02:00:44 PM PDT 24
Finished Apr 28 02:00:52 PM PDT 24
Peak memory 241580 kb
Host smart-cde9f605-6818-4519-855d-c98bf12e796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422762321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.2422762321
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.4238283514
Short name T107
Test name
Test status
Simulation time 5410583303 ps
CPU time 14.05 seconds
Started Apr 28 02:00:43 PM PDT 24
Finished Apr 28 02:00:58 PM PDT 24
Peak memory 241412 kb
Host smart-ece97d0a-9471-47f8-811d-2bccd6e806d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238283514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.4238283514
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.1010797843
Short name T1096
Test name
Test status
Simulation time 4024066478 ps
CPU time 12.15 seconds
Started Apr 28 02:00:44 PM PDT 24
Finished Apr 28 02:00:56 PM PDT 24
Peak memory 241444 kb
Host smart-b02228f2-2202-409b-bc1a-fa9e21ccc63d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010797843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.1010797843
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.3890620978
Short name T188
Test name
Test status
Simulation time 418928868 ps
CPU time 9.62 seconds
Started Apr 28 02:00:39 PM PDT 24
Finished Apr 28 02:00:49 PM PDT 24
Peak memory 241220 kb
Host smart-0679db8d-79b6-419c-bdd1-f4e3d4d1c39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890620978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.3890620978
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.1406540206
Short name T1161
Test name
Test status
Simulation time 9842516240 ps
CPU time 82.89 seconds
Started Apr 28 02:00:52 PM PDT 24
Finished Apr 28 02:02:15 PM PDT 24
Peak memory 250072 kb
Host smart-63731f7c-ae74-426f-aa3a-6e45b431135b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406540206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.1406540206
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.3697125810
Short name T333
Test name
Test status
Simulation time 974291934423 ps
CPU time 1469.32 seconds
Started Apr 28 02:00:52 PM PDT 24
Finished Apr 28 02:25:22 PM PDT 24
Peak memory 321448 kb
Host smart-631363b1-cbb3-4608-8dff-e2b86c9bb612
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697125810 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.3697125810
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.1178754564
Short name T856
Test name
Test status
Simulation time 1919470448 ps
CPU time 40.73 seconds
Started Apr 28 02:00:56 PM PDT 24
Finished Apr 28 02:01:37 PM PDT 24
Peak memory 241880 kb
Host smart-6d540891-908a-4789-9509-aca1abadc636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178754564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.1178754564
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.1130796293
Short name T448
Test name
Test status
Simulation time 145093072 ps
CPU time 1.85 seconds
Started Apr 28 02:00:55 PM PDT 24
Finished Apr 28 02:00:57 PM PDT 24
Peak memory 239724 kb
Host smart-e6f32f18-831d-459b-8575-56a678a8eb83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130796293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.1130796293
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.168453921
Short name T343
Test name
Test status
Simulation time 7290686121 ps
CPU time 17.99 seconds
Started Apr 28 02:00:54 PM PDT 24
Finished Apr 28 02:01:13 PM PDT 24
Peak memory 243216 kb
Host smart-50b564ab-e805-4a86-b8a3-b24e747d1b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168453921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.168453921
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.1338402383
Short name T1180
Test name
Test status
Simulation time 742323982 ps
CPU time 21.35 seconds
Started Apr 28 02:00:54 PM PDT 24
Finished Apr 28 02:01:16 PM PDT 24
Peak memory 241420 kb
Host smart-afdbd0fd-09d3-449d-8b8c-d7b98eeffe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338402383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.1338402383
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.2397140894
Short name T377
Test name
Test status
Simulation time 1736690199 ps
CPU time 19.29 seconds
Started Apr 28 02:00:51 PM PDT 24
Finished Apr 28 02:01:10 PM PDT 24
Peak memory 241388 kb
Host smart-db4cecfb-d26b-4bf5-9608-fdc436474c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397140894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.2397140894
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.2724302796
Short name T722
Test name
Test status
Simulation time 3574137726 ps
CPU time 14.74 seconds
Started Apr 28 02:00:55 PM PDT 24
Finished Apr 28 02:01:10 PM PDT 24
Peak memory 248024 kb
Host smart-68d788fb-9531-42da-ba21-1c9075ee17e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724302796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2724302796
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.365936494
Short name T1189
Test name
Test status
Simulation time 2677881855 ps
CPU time 29.46 seconds
Started Apr 28 02:00:55 PM PDT 24
Finished Apr 28 02:01:25 PM PDT 24
Peak memory 241668 kb
Host smart-bec55d21-3a40-4369-bcfc-648996d88e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365936494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.365936494
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.476635124
Short name T658
Test name
Test status
Simulation time 405202837 ps
CPU time 3.8 seconds
Started Apr 28 02:00:51 PM PDT 24
Finished Apr 28 02:00:55 PM PDT 24
Peak memory 241784 kb
Host smart-95719896-e5e7-4938-9ada-0fea26b68234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476635124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.476635124
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.4294465365
Short name T701
Test name
Test status
Simulation time 2619584295 ps
CPU time 20.41 seconds
Started Apr 28 02:00:51 PM PDT 24
Finished Apr 28 02:01:12 PM PDT 24
Peak memory 241404 kb
Host smart-18499ecb-6b94-4b82-80b2-fa62488380fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294465365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.4294465365
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.2441618228
Short name T552
Test name
Test status
Simulation time 458618035 ps
CPU time 4.16 seconds
Started Apr 28 02:00:52 PM PDT 24
Finished Apr 28 02:00:57 PM PDT 24
Peak memory 241272 kb
Host smart-3aee065a-98f0-4ccc-94fe-13817cec49e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441618228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.2441618228
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.3633123786
Short name T761
Test name
Test status
Simulation time 5953955396 ps
CPU time 181.33 seconds
Started Apr 28 02:00:55 PM PDT 24
Finished Apr 28 02:03:57 PM PDT 24
Peak memory 260064 kb
Host smart-9698c7e0-44fc-4ece-9e56-6b938eb7ffa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633123786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.3633123786
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.4368984
Short name T721
Test name
Test status
Simulation time 1147773225570 ps
CPU time 4111.54 seconds
Started Apr 28 02:00:55 PM PDT 24
Finished Apr 28 03:09:28 PM PDT 24
Peak memory 589184 kb
Host smart-6d2cb544-6086-4eb3-97af-04311b6a9bd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4368984 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.4368984
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.4028810245
Short name T844
Test name
Test status
Simulation time 1994419681 ps
CPU time 6.74 seconds
Started Apr 28 02:00:58 PM PDT 24
Finished Apr 28 02:01:05 PM PDT 24
Peak memory 241220 kb
Host smart-d7623156-fe35-4ab1-a098-ec042cb52447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028810245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.4028810245
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.4175656188
Short name T760
Test name
Test status
Simulation time 128935588 ps
CPU time 1.97 seconds
Started Apr 28 02:00:59 PM PDT 24
Finished Apr 28 02:01:02 PM PDT 24
Peak memory 240092 kb
Host smart-3c604943-9bfb-4c19-a2c6-e8282944d08f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175656188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.4175656188
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.3054868317
Short name T92
Test name
Test status
Simulation time 2246986646 ps
CPU time 18.95 seconds
Started Apr 28 02:01:01 PM PDT 24
Finished Apr 28 02:01:20 PM PDT 24
Peak memory 248132 kb
Host smart-6505d920-8f2d-49dc-adb2-cbfd88e686cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054868317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.3054868317
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.185717596
Short name T558
Test name
Test status
Simulation time 722566870 ps
CPU time 11.94 seconds
Started Apr 28 02:01:00 PM PDT 24
Finished Apr 28 02:01:12 PM PDT 24
Peak memory 241308 kb
Host smart-2ae65433-b82c-4519-a9cc-1dba4b2dbf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185717596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.185717596
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.3817073986
Short name T1108
Test name
Test status
Simulation time 20992381561 ps
CPU time 47.88 seconds
Started Apr 28 02:01:06 PM PDT 24
Finished Apr 28 02:01:54 PM PDT 24
Peak memory 248000 kb
Host smart-da013998-170e-4e78-bda6-080742a6fe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817073986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.3817073986
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.2609777065
Short name T1186
Test name
Test status
Simulation time 1194169237 ps
CPU time 3.43 seconds
Started Apr 28 02:00:59 PM PDT 24
Finished Apr 28 02:01:02 PM PDT 24
Peak memory 241316 kb
Host smart-f8e72a32-66f8-4c4a-9cb9-dd9198568775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609777065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.2609777065
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.2642816903
Short name T1030
Test name
Test status
Simulation time 17077991164 ps
CPU time 148.28 seconds
Started Apr 28 02:01:09 PM PDT 24
Finished Apr 28 02:03:38 PM PDT 24
Peak memory 243920 kb
Host smart-de0d5966-e38f-4096-8641-a2690d6bef7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642816903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.2642816903
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.764337669
Short name T869
Test name
Test status
Simulation time 2069656047 ps
CPU time 23.47 seconds
Started Apr 28 02:00:59 PM PDT 24
Finished Apr 28 02:01:23 PM PDT 24
Peak memory 241716 kb
Host smart-2f72c638-9cb6-4045-93eb-bf5e4691346e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764337669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.764337669
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.3043435505
Short name T577
Test name
Test status
Simulation time 142261755 ps
CPU time 6.35 seconds
Started Apr 28 02:00:57 PM PDT 24
Finished Apr 28 02:01:03 PM PDT 24
Peak memory 241176 kb
Host smart-b78408f0-a205-4f60-ac8e-0c33015adab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043435505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.3043435505
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.2855963155
Short name T1089
Test name
Test status
Simulation time 11493895555 ps
CPU time 18.76 seconds
Started Apr 28 02:00:54 PM PDT 24
Finished Apr 28 02:01:14 PM PDT 24
Peak memory 248088 kb
Host smart-c0f49b2f-4e7e-4d09-9920-9b1f745d68ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2855963155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.2855963155
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.127581810
Short name T369
Test name
Test status
Simulation time 308266372 ps
CPU time 5.47 seconds
Started Apr 28 02:01:05 PM PDT 24
Finished Apr 28 02:01:11 PM PDT 24
Peak memory 241352 kb
Host smart-399d2cb5-14a9-4aa5-adac-c14b210c4be8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=127581810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.127581810
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.1955616408
Short name T776
Test name
Test status
Simulation time 184498869 ps
CPU time 6.26 seconds
Started Apr 28 02:00:57 PM PDT 24
Finished Apr 28 02:01:04 PM PDT 24
Peak memory 241604 kb
Host smart-55553449-ad76-4337-980f-adc159b2b606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955616408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.1955616408
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.757391537
Short name T232
Test name
Test status
Simulation time 6512945010 ps
CPU time 26.97 seconds
Started Apr 28 02:01:06 PM PDT 24
Finished Apr 28 02:01:34 PM PDT 24
Peak memory 243804 kb
Host smart-5cf573c5-a69e-4511-9200-70bd3f696fb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757391537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.
757391537
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.7480213
Short name T304
Test name
Test status
Simulation time 226221767650 ps
CPU time 1377.82 seconds
Started Apr 28 02:01:00 PM PDT 24
Finished Apr 28 02:23:58 PM PDT 24
Peak memory 263496 kb
Host smart-8d11ab09-ec63-4ee1-aeb6-b0f4ad570273
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7480213 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.7480213
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.2405811542
Short name T1144
Test name
Test status
Simulation time 1467448703 ps
CPU time 20.36 seconds
Started Apr 28 02:01:01 PM PDT 24
Finished Apr 28 02:01:22 PM PDT 24
Peak memory 241264 kb
Host smart-ca7f582c-4edc-4f79-a81e-513ea4dc2888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405811542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.2405811542
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.3585501276
Short name T1101
Test name
Test status
Simulation time 167614568 ps
CPU time 1.74 seconds
Started Apr 28 02:01:10 PM PDT 24
Finished Apr 28 02:01:12 PM PDT 24
Peak memory 240076 kb
Host smart-820bc721-8f52-4438-a0f1-249e22ebd54d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585501276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3585501276
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.2616117739
Short name T55
Test name
Test status
Simulation time 1084908795 ps
CPU time 13.39 seconds
Started Apr 28 02:01:07 PM PDT 24
Finished Apr 28 02:01:21 PM PDT 24
Peak memory 248004 kb
Host smart-4ab4bdf9-8205-4df1-a394-0fbced14bcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616117739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2616117739
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.1724900023
Short name T823
Test name
Test status
Simulation time 1124977910 ps
CPU time 10.49 seconds
Started Apr 28 02:01:09 PM PDT 24
Finished Apr 28 02:01:20 PM PDT 24
Peak memory 241748 kb
Host smart-dc03b654-3563-4790-88bd-bbcc24e0681c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724900023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.1724900023
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.2971143018
Short name T415
Test name
Test status
Simulation time 6431544081 ps
CPU time 68.52 seconds
Started Apr 28 02:01:06 PM PDT 24
Finished Apr 28 02:02:15 PM PDT 24
Peak memory 243140 kb
Host smart-37a50e69-171a-496d-95d2-4b0c0f47e6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971143018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.2971143018
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.1673625030
Short name T990
Test name
Test status
Simulation time 3227993347 ps
CPU time 17.44 seconds
Started Apr 28 02:01:07 PM PDT 24
Finished Apr 28 02:01:25 PM PDT 24
Peak memory 243160 kb
Host smart-9cc60a8a-0baf-4201-b588-6ae43d2c718b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673625030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.1673625030
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.3664967141
Short name T235
Test name
Test status
Simulation time 19556381887 ps
CPU time 34.15 seconds
Started Apr 28 02:01:04 PM PDT 24
Finished Apr 28 02:01:38 PM PDT 24
Peak memory 248108 kb
Host smart-38a9ca41-c42e-4429-aebc-63f35a474b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664967141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.3664967141
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.3096184383
Short name T81
Test name
Test status
Simulation time 549342895 ps
CPU time 15.84 seconds
Started Apr 28 02:01:06 PM PDT 24
Finished Apr 28 02:01:22 PM PDT 24
Peak memory 241752 kb
Host smart-c51c8186-9cbb-45e5-9a80-ea2e9867f600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096184383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3096184383
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.312273359
Short name T226
Test name
Test status
Simulation time 2169439752 ps
CPU time 20.25 seconds
Started Apr 28 02:01:06 PM PDT 24
Finished Apr 28 02:01:27 PM PDT 24
Peak memory 247996 kb
Host smart-0275a64f-c457-4ff0-af5c-2e5afd72e88d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312273359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.312273359
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.80248471
Short name T887
Test name
Test status
Simulation time 2958489283 ps
CPU time 6.92 seconds
Started Apr 28 02:01:05 PM PDT 24
Finished Apr 28 02:01:13 PM PDT 24
Peak memory 241712 kb
Host smart-90094b06-084d-4bcf-8415-cca7706898f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80248471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.80248471
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.1494673848
Short name T575
Test name
Test status
Simulation time 3288356026 ps
CPU time 25.77 seconds
Started Apr 28 02:01:05 PM PDT 24
Finished Apr 28 02:01:31 PM PDT 24
Peak memory 241320 kb
Host smart-e9a362b2-a4b6-4f22-8975-4b9382f1dcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494673848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.1494673848
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.2402838299
Short name T713
Test name
Test status
Simulation time 39065673157 ps
CPU time 455.14 seconds
Started Apr 28 02:01:14 PM PDT 24
Finished Apr 28 02:08:49 PM PDT 24
Peak memory 262540 kb
Host smart-cff8ffae-2542-4a1d-abb8-da990ad735e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402838299 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.2402838299
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.72418818
Short name T877
Test name
Test status
Simulation time 10120329909 ps
CPU time 28.22 seconds
Started Apr 28 02:01:04 PM PDT 24
Finished Apr 28 02:01:32 PM PDT 24
Peak memory 242332 kb
Host smart-5708ddde-16a7-4fb9-9b4a-f18d288cee1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72418818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.72418818
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.1152397675
Short name T1031
Test name
Test status
Simulation time 65388600 ps
CPU time 1.88 seconds
Started Apr 28 02:01:16 PM PDT 24
Finished Apr 28 02:01:19 PM PDT 24
Peak memory 239780 kb
Host smart-9964906d-604d-4896-a615-94d44a683678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152397675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.1152397675
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.2551572280
Short name T1083
Test name
Test status
Simulation time 2463782932 ps
CPU time 21.48 seconds
Started Apr 28 02:01:10 PM PDT 24
Finished Apr 28 02:01:32 PM PDT 24
Peak memory 241868 kb
Host smart-0b68c69b-f232-48b3-a3e8-beca64da41a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551572280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2551572280
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.3556980520
Short name T452
Test name
Test status
Simulation time 141001814 ps
CPU time 3.45 seconds
Started Apr 28 02:01:09 PM PDT 24
Finished Apr 28 02:01:13 PM PDT 24
Peak memory 241692 kb
Host smart-ed36ce8f-d9c7-488d-948b-f68534a50111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556980520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3556980520
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.1648363964
Short name T459
Test name
Test status
Simulation time 2586000402 ps
CPU time 5.12 seconds
Started Apr 28 02:01:20 PM PDT 24
Finished Apr 28 02:01:25 PM PDT 24
Peak memory 241344 kb
Host smart-c28efe65-beb8-41b4-add4-bb0ffb3d30f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648363964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.1648363964
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.3679525897
Short name T716
Test name
Test status
Simulation time 2319603614 ps
CPU time 32.95 seconds
Started Apr 28 02:01:10 PM PDT 24
Finished Apr 28 02:01:44 PM PDT 24
Peak memory 248104 kb
Host smart-54c06da9-5d66-4090-a738-3d86271149ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679525897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.3679525897
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.2526857581
Short name T376
Test name
Test status
Simulation time 4614725991 ps
CPU time 36.71 seconds
Started Apr 28 02:01:23 PM PDT 24
Finished Apr 28 02:02:00 PM PDT 24
Peak memory 241636 kb
Host smart-42fd4fe4-7717-4d40-bf5e-edca256a79fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526857581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.2526857581
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.3061104163
Short name T903
Test name
Test status
Simulation time 178813952 ps
CPU time 9.45 seconds
Started Apr 28 02:01:10 PM PDT 24
Finished Apr 28 02:01:20 PM PDT 24
Peak memory 241228 kb
Host smart-0bcdee6d-362b-4ba6-ac27-99bea55ad46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061104163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.3061104163
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.3196130079
Short name T455
Test name
Test status
Simulation time 527217762 ps
CPU time 7.78 seconds
Started Apr 28 02:01:08 PM PDT 24
Finished Apr 28 02:01:16 PM PDT 24
Peak memory 247916 kb
Host smart-4921c37d-aa34-41f2-b21f-d162d631a754
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3196130079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.3196130079
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.307675248
Short name T866
Test name
Test status
Simulation time 135296700 ps
CPU time 3.29 seconds
Started Apr 28 02:01:22 PM PDT 24
Finished Apr 28 02:01:26 PM PDT 24
Peak memory 241228 kb
Host smart-01bba2cb-16b0-4991-9f42-8fd179b30c0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=307675248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.307675248
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.4064012046
Short name T481
Test name
Test status
Simulation time 865364826 ps
CPU time 6.07 seconds
Started Apr 28 02:01:10 PM PDT 24
Finished Apr 28 02:01:16 PM PDT 24
Peak memory 241556 kb
Host smart-3323e2a2-e129-4cb3-8bb8-0cae443c55e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064012046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.4064012046
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.3184155299
Short name T579
Test name
Test status
Simulation time 26070963586 ps
CPU time 160.48 seconds
Started Apr 28 02:01:14 PM PDT 24
Finished Apr 28 02:03:55 PM PDT 24
Peak memory 253756 kb
Host smart-2914c219-e8dc-4aff-bef3-80eb9f6e192f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184155299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.3184155299
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.54820519
Short name T15
Test name
Test status
Simulation time 211084596252 ps
CPU time 933.64 seconds
Started Apr 28 02:01:14 PM PDT 24
Finished Apr 28 02:16:48 PM PDT 24
Peak memory 278048 kb
Host smart-39ba2f58-1367-4202-8f62-8134d166ea53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54820519 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.54820519
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.189555224
Short name T606
Test name
Test status
Simulation time 3599181188 ps
CPU time 21.53 seconds
Started Apr 28 02:01:16 PM PDT 24
Finished Apr 28 02:01:38 PM PDT 24
Peak memory 241492 kb
Host smart-8f1f4b8f-eff6-4fc0-b416-dec4ff7645d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189555224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.189555224
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.248360906
Short name T600
Test name
Test status
Simulation time 102238338 ps
CPU time 2.11 seconds
Started Apr 28 02:01:18 PM PDT 24
Finished Apr 28 02:01:21 PM PDT 24
Peak memory 240116 kb
Host smart-823417aa-7ba7-4de6-9e6f-36117381c68c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248360906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.248360906
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.2129408115
Short name T71
Test name
Test status
Simulation time 733444954 ps
CPU time 12.89 seconds
Started Apr 28 02:01:25 PM PDT 24
Finished Apr 28 02:01:39 PM PDT 24
Peak memory 241476 kb
Host smart-8427c912-8dce-4ad9-b8ea-29236734e96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129408115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.2129408115
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.2389825323
Short name T947
Test name
Test status
Simulation time 1487099856 ps
CPU time 24.01 seconds
Started Apr 28 02:01:16 PM PDT 24
Finished Apr 28 02:01:41 PM PDT 24
Peak memory 241716 kb
Host smart-4a2bbc28-7461-428b-8d1d-8a235a2a997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389825323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.2389825323
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.1973750997
Short name T31
Test name
Test status
Simulation time 810373289 ps
CPU time 25.5 seconds
Started Apr 28 02:01:15 PM PDT 24
Finished Apr 28 02:01:41 PM PDT 24
Peak memory 241664 kb
Host smart-2cec3856-bd80-4f49-a2b7-64ae1a835bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973750997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.1973750997
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.1118669804
Short name T115
Test name
Test status
Simulation time 275902336 ps
CPU time 4.56 seconds
Started Apr 28 02:01:23 PM PDT 24
Finished Apr 28 02:01:28 PM PDT 24
Peak memory 241676 kb
Host smart-52109d49-ecc4-47bb-89b0-60057dee5d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118669804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.1118669804
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.1302546963
Short name T510
Test name
Test status
Simulation time 3449596151 ps
CPU time 27.49 seconds
Started Apr 28 02:01:22 PM PDT 24
Finished Apr 28 02:01:50 PM PDT 24
Peak memory 241592 kb
Host smart-ef9fe601-2244-4389-8226-f868a8b0092f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302546963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1302546963
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.3345334612
Short name T998
Test name
Test status
Simulation time 984489445 ps
CPU time 8.02 seconds
Started Apr 28 02:01:15 PM PDT 24
Finished Apr 28 02:01:23 PM PDT 24
Peak memory 241336 kb
Host smart-a8bfb2ad-6bdf-4cb3-b15b-092f35dbb164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345334612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.3345334612
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.3343839891
Short name T1105
Test name
Test status
Simulation time 491592906 ps
CPU time 11.32 seconds
Started Apr 28 02:01:23 PM PDT 24
Finished Apr 28 02:01:35 PM PDT 24
Peak memory 241284 kb
Host smart-51b7e608-2de3-41aa-9c6f-9143f83cc11a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3343839891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.3343839891
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.174134843
Short name T555
Test name
Test status
Simulation time 279704652 ps
CPU time 10.18 seconds
Started Apr 28 02:01:21 PM PDT 24
Finished Apr 28 02:01:32 PM PDT 24
Peak memory 241364 kb
Host smart-7a0b1752-8724-43fa-a98e-8045e9548c5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=174134843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.174134843
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.1992606573
Short name T560
Test name
Test status
Simulation time 1151815410 ps
CPU time 7.41 seconds
Started Apr 28 02:01:13 PM PDT 24
Finished Apr 28 02:01:21 PM PDT 24
Peak memory 241124 kb
Host smart-0d4aabf4-ebac-4d93-a5fe-df427c8c5f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992606573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1992606573
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.1094690219
Short name T1121
Test name
Test status
Simulation time 5990484335 ps
CPU time 73.02 seconds
Started Apr 28 02:01:21 PM PDT 24
Finished Apr 28 02:02:34 PM PDT 24
Peak memory 242784 kb
Host smart-4b8f6183-ab19-4b68-be46-85461565ee35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094690219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.1094690219
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.3985544234
Short name T943
Test name
Test status
Simulation time 2647768786 ps
CPU time 28.43 seconds
Started Apr 28 02:01:19 PM PDT 24
Finished Apr 28 02:01:48 PM PDT 24
Peak memory 242872 kb
Host smart-1daa2d89-f001-402b-a25b-1d41ef6f7772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985544234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.3985544234
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.1415025269
Short name T985
Test name
Test status
Simulation time 148103154 ps
CPU time 2.24 seconds
Started Apr 28 02:01:29 PM PDT 24
Finished Apr 28 02:01:31 PM PDT 24
Peak memory 239892 kb
Host smart-909ed58d-19c2-4ce3-bfd6-0bbab785d2dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415025269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.1415025269
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.982776292
Short name T1117
Test name
Test status
Simulation time 948426738 ps
CPU time 14.6 seconds
Started Apr 28 02:01:27 PM PDT 24
Finished Apr 28 02:01:42 PM PDT 24
Peak memory 247944 kb
Host smart-ee2ed67b-aa81-4788-9dab-5c21406f0781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982776292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.982776292
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.1104476955
Short name T1183
Test name
Test status
Simulation time 265404621 ps
CPU time 11.7 seconds
Started Apr 28 02:01:34 PM PDT 24
Finished Apr 28 02:01:46 PM PDT 24
Peak memory 241392 kb
Host smart-5b0869ce-4e3e-46bd-963f-e5052cf2c32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104476955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.1104476955
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.3590409436
Short name T1004
Test name
Test status
Simulation time 6081640774 ps
CPU time 10.52 seconds
Started Apr 28 02:01:24 PM PDT 24
Finished Apr 28 02:01:35 PM PDT 24
Peak memory 241780 kb
Host smart-1bf49f66-ef6d-47cd-95e2-a6cf41ae250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590409436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.3590409436
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.2182813942
Short name T704
Test name
Test status
Simulation time 1728250929 ps
CPU time 5.35 seconds
Started Apr 28 02:01:21 PM PDT 24
Finished Apr 28 02:01:27 PM PDT 24
Peak memory 241480 kb
Host smart-753d360c-5fa6-456c-a193-3f75b7c5d676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182813942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.2182813942
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.2934953221
Short name T752
Test name
Test status
Simulation time 449993635 ps
CPU time 10.8 seconds
Started Apr 28 02:01:39 PM PDT 24
Finished Apr 28 02:01:50 PM PDT 24
Peak memory 241452 kb
Host smart-40bef003-5864-45de-861f-b8e58da45281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934953221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.2934953221
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.1082779640
Short name T393
Test name
Test status
Simulation time 1289779870 ps
CPU time 24.55 seconds
Started Apr 28 02:01:30 PM PDT 24
Finished Apr 28 02:01:55 PM PDT 24
Peak memory 247840 kb
Host smart-b86482c1-abda-4b51-803b-4e2851f04d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082779640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1082779640
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.3227304291
Short name T589
Test name
Test status
Simulation time 108204180 ps
CPU time 4.38 seconds
Started Apr 28 02:01:25 PM PDT 24
Finished Apr 28 02:01:30 PM PDT 24
Peak memory 241696 kb
Host smart-3dbd7b27-8d50-4cb6-9ba6-c04caa83b58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227304291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3227304291
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.3727369587
Short name T734
Test name
Test status
Simulation time 761638306 ps
CPU time 10.36 seconds
Started Apr 28 02:01:19 PM PDT 24
Finished Apr 28 02:01:30 PM PDT 24
Peak memory 241284 kb
Host smart-0d39f5ee-78d9-43a9-a08f-da3e8507a012
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3727369587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.3727369587
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.3170133494
Short name T748
Test name
Test status
Simulation time 432546364 ps
CPU time 5.68 seconds
Started Apr 28 02:01:39 PM PDT 24
Finished Apr 28 02:01:45 PM PDT 24
Peak memory 241388 kb
Host smart-c8f77fa2-7597-4777-a162-d905b316fa0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170133494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.3170133494
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.1367849738
Short name T700
Test name
Test status
Simulation time 1435403870 ps
CPU time 8.61 seconds
Started Apr 28 02:01:21 PM PDT 24
Finished Apr 28 02:01:30 PM PDT 24
Peak memory 241184 kb
Host smart-d2ebd9dd-fd25-4555-bdb6-0305af41f28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367849738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.1367849738
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.1289298292
Short name T953
Test name
Test status
Simulation time 2557732295 ps
CPU time 27.07 seconds
Started Apr 28 02:01:39 PM PDT 24
Finished Apr 28 02:02:06 PM PDT 24
Peak memory 242096 kb
Host smart-23443098-4db8-4b72-a25c-42b8eda3d24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289298292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.1289298292
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.3475876219
Short name T843
Test name
Test status
Simulation time 160141990 ps
CPU time 2.38 seconds
Started Apr 28 02:01:39 PM PDT 24
Finished Apr 28 02:01:42 PM PDT 24
Peak memory 240188 kb
Host smart-e7392bee-a063-4560-90c6-a3ad4fcf5c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475876219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.3475876219
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.54502384
Short name T60
Test name
Test status
Simulation time 141208870 ps
CPU time 6.17 seconds
Started Apr 28 02:01:39 PM PDT 24
Finished Apr 28 02:01:46 PM PDT 24
Peak memory 241356 kb
Host smart-2c737023-140b-462e-8d37-f32270501003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54502384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.54502384
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.2709471823
Short name T802
Test name
Test status
Simulation time 270693586 ps
CPU time 13.86 seconds
Started Apr 28 02:01:34 PM PDT 24
Finished Apr 28 02:01:48 PM PDT 24
Peak memory 241348 kb
Host smart-a390c4a1-1ce1-4117-9dd0-976c59562d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709471823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.2709471823
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.2241639135
Short name T640
Test name
Test status
Simulation time 849598676 ps
CPU time 9.6 seconds
Started Apr 28 02:01:34 PM PDT 24
Finished Apr 28 02:01:44 PM PDT 24
Peak memory 241420 kb
Host smart-513149c2-fcf6-409c-b26f-04d1cb536fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241639135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.2241639135
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.1797265329
Short name T604
Test name
Test status
Simulation time 140387192 ps
CPU time 4.79 seconds
Started Apr 28 02:01:39 PM PDT 24
Finished Apr 28 02:01:44 PM PDT 24
Peak memory 241324 kb
Host smart-1b61cd5e-b32a-46e6-8257-1c8ecf0333aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797265329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.1797265329
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.2338099342
Short name T891
Test name
Test status
Simulation time 1038460908 ps
CPU time 28.97 seconds
Started Apr 28 02:01:37 PM PDT 24
Finished Apr 28 02:02:06 PM PDT 24
Peak memory 243224 kb
Host smart-0a82b801-c72a-42e1-ac5b-2a52c45319b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338099342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.2338099342
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.1259888480
Short name T7
Test name
Test status
Simulation time 1663195575 ps
CPU time 35.07 seconds
Started Apr 28 02:01:37 PM PDT 24
Finished Apr 28 02:02:12 PM PDT 24
Peak memory 241224 kb
Host smart-aa20f3f6-8906-4e2a-b680-2333939316ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259888480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.1259888480
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.2464815931
Short name T517
Test name
Test status
Simulation time 165841314 ps
CPU time 8.05 seconds
Started Apr 28 02:01:32 PM PDT 24
Finished Apr 28 02:01:40 PM PDT 24
Peak memory 241440 kb
Host smart-8a74ec5c-abbc-4d37-8f1a-983e7cac947d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464815931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.2464815931
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.2501086150
Short name T1088
Test name
Test status
Simulation time 655623030 ps
CPU time 20.04 seconds
Started Apr 28 02:01:31 PM PDT 24
Finished Apr 28 02:01:51 PM PDT 24
Peak memory 241636 kb
Host smart-a7cc75e0-da49-4439-bfb0-657dd61c2078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2501086150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.2501086150
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.1299685253
Short name T422
Test name
Test status
Simulation time 419352495 ps
CPU time 5.31 seconds
Started Apr 28 02:01:35 PM PDT 24
Finished Apr 28 02:01:41 PM PDT 24
Peak memory 241320 kb
Host smart-c0764668-be58-4e1f-91e9-1161b7c7e727
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299685253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.1299685253
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.375234063
Short name T463
Test name
Test status
Simulation time 537803014 ps
CPU time 4.95 seconds
Started Apr 28 02:01:30 PM PDT 24
Finished Apr 28 02:01:35 PM PDT 24
Peak memory 241564 kb
Host smart-b0966f7b-96de-44ec-8773-f10f591efa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375234063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.375234063
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.1200478380
Short name T398
Test name
Test status
Simulation time 3249251103 ps
CPU time 11.02 seconds
Started Apr 28 02:01:39 PM PDT 24
Finished Apr 28 02:01:51 PM PDT 24
Peak memory 241004 kb
Host smart-70302bfd-cafd-4524-8c79-e6e61f21aca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200478380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.1200478380
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.2242019303
Short name T732
Test name
Test status
Simulation time 72111634451 ps
CPU time 585.15 seconds
Started Apr 28 02:01:34 PM PDT 24
Finished Apr 28 02:11:20 PM PDT 24
Peak memory 360884 kb
Host smart-f4bbc148-d372-4b78-b775-ba97e26d7cf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242019303 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.2242019303
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.2014729850
Short name T549
Test name
Test status
Simulation time 360626387 ps
CPU time 8.21 seconds
Started Apr 28 02:01:33 PM PDT 24
Finished Apr 28 02:01:42 PM PDT 24
Peak memory 241344 kb
Host smart-f48ed590-693c-4498-aaaa-b2b29ea7e15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014729850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.2014729850
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.551961212
Short name T1165
Test name
Test status
Simulation time 187844526 ps
CPU time 1.84 seconds
Started Apr 28 02:01:44 PM PDT 24
Finished Apr 28 02:01:46 PM PDT 24
Peak memory 239652 kb
Host smart-4a07737e-209a-4f28-a68e-c221fcc5c1af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551961212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.551961212
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3814570635
Short name T43
Test name
Test status
Simulation time 3455790466 ps
CPU time 32.3 seconds
Started Apr 28 02:01:50 PM PDT 24
Finished Apr 28 02:02:23 PM PDT 24
Peak memory 242840 kb
Host smart-138cc19b-0e10-4582-ab62-7e5c45f09518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814570635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3814570635
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.3265237072
Short name T603
Test name
Test status
Simulation time 8378881152 ps
CPU time 24.07 seconds
Started Apr 28 02:01:49 PM PDT 24
Finished Apr 28 02:02:13 PM PDT 24
Peak memory 241336 kb
Host smart-8388b3b6-39f9-49a0-9379-495cfffe86bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265237072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.3265237072
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.2340171856
Short name T1077
Test name
Test status
Simulation time 4479682254 ps
CPU time 39.78 seconds
Started Apr 28 02:01:50 PM PDT 24
Finished Apr 28 02:02:30 PM PDT 24
Peak memory 241396 kb
Host smart-5e7bc7ea-8947-4b6c-a35e-361d08e07cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340171856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.2340171856
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.767460820
Short name T792
Test name
Test status
Simulation time 273451096 ps
CPU time 3.45 seconds
Started Apr 28 02:01:39 PM PDT 24
Finished Apr 28 02:01:43 PM PDT 24
Peak memory 241344 kb
Host smart-55dc0613-eaae-4d23-a993-56f37c583f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767460820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.767460820
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.3646118783
Short name T1166
Test name
Test status
Simulation time 632957861 ps
CPU time 8.98 seconds
Started Apr 28 02:01:46 PM PDT 24
Finished Apr 28 02:01:55 PM PDT 24
Peak memory 241764 kb
Host smart-34a138e1-bcb1-4ac7-9ba9-ce90bb9c079d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646118783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3646118783
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.3033963778
Short name T906
Test name
Test status
Simulation time 469723114 ps
CPU time 14.47 seconds
Started Apr 28 02:01:46 PM PDT 24
Finished Apr 28 02:02:01 PM PDT 24
Peak memory 241296 kb
Host smart-38695b31-e715-450f-87c5-f82979f9815a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033963778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.3033963778
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.3640646229
Short name T709
Test name
Test status
Simulation time 941854575 ps
CPU time 15.56 seconds
Started Apr 28 02:01:39 PM PDT 24
Finished Apr 28 02:01:55 PM PDT 24
Peak memory 241472 kb
Host smart-6a1eead5-fa3b-4643-babc-d689c1cc733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640646229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.3640646229
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.941957304
Short name T754
Test name
Test status
Simulation time 296829089 ps
CPU time 7.6 seconds
Started Apr 28 02:01:45 PM PDT 24
Finished Apr 28 02:01:53 PM PDT 24
Peak memory 241340 kb
Host smart-7efb0994-caaf-420e-9499-b859225b7663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=941957304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.941957304
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.1701336346
Short name T860
Test name
Test status
Simulation time 6411650243 ps
CPU time 9.74 seconds
Started Apr 28 02:01:42 PM PDT 24
Finished Apr 28 02:01:52 PM PDT 24
Peak memory 241336 kb
Host smart-f43928df-c738-427a-94e9-f31f7a5edb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701336346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1701336346
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.2242812566
Short name T301
Test name
Test status
Simulation time 5226081796 ps
CPU time 56.93 seconds
Started Apr 28 02:01:49 PM PDT 24
Finished Apr 28 02:02:46 PM PDT 24
Peak memory 241392 kb
Host smart-21878f4f-d8e9-4fdd-a96b-01e830872f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242812566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.2242812566
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.3203739700
Short name T185
Test name
Test status
Simulation time 3056953812 ps
CPU time 25.17 seconds
Started Apr 28 02:01:46 PM PDT 24
Finished Apr 28 02:02:11 PM PDT 24
Peak memory 247968 kb
Host smart-271b6a3c-eac9-41e3-a608-be34cb2fd7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203739700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3203739700
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.1827645227
Short name T547
Test name
Test status
Simulation time 824480110 ps
CPU time 2.08 seconds
Started Apr 28 02:01:49 PM PDT 24
Finished Apr 28 02:01:52 PM PDT 24
Peak memory 240004 kb
Host smart-5d21a7c2-5ae3-4fda-ba77-e79caa1f9f0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827645227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.1827645227
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.1135695041
Short name T277
Test name
Test status
Simulation time 1540247964 ps
CPU time 30.59 seconds
Started Apr 28 02:01:47 PM PDT 24
Finished Apr 28 02:02:18 PM PDT 24
Peak memory 241604 kb
Host smart-73fbe861-be58-426e-ab24-6b3695800c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135695041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1135695041
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.2169573413
Short name T790
Test name
Test status
Simulation time 328684647 ps
CPU time 6.13 seconds
Started Apr 28 02:01:49 PM PDT 24
Finished Apr 28 02:01:55 PM PDT 24
Peak memory 241204 kb
Host smart-d72841bb-ea71-47f8-afc6-1e98cb73ac6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169573413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.2169573413
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.1031643921
Short name T199
Test name
Test status
Simulation time 2121009305 ps
CPU time 4.95 seconds
Started Apr 28 02:01:46 PM PDT 24
Finished Apr 28 02:01:52 PM PDT 24
Peak memory 241332 kb
Host smart-3e713e24-f97f-481b-a9bd-59fb406e13a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031643921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.1031643921
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.2472520420
Short name T755
Test name
Test status
Simulation time 3738702330 ps
CPU time 24.48 seconds
Started Apr 28 02:01:44 PM PDT 24
Finished Apr 28 02:02:09 PM PDT 24
Peak memory 248132 kb
Host smart-5c610b83-48c6-4f9d-9553-fff13c0462e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472520420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.2472520420
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.1190593253
Short name T773
Test name
Test status
Simulation time 1146383768 ps
CPU time 14.78 seconds
Started Apr 28 02:01:52 PM PDT 24
Finished Apr 28 02:02:07 PM PDT 24
Peak memory 247948 kb
Host smart-20bfc3b4-79ee-4ec7-b019-572a875bfc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190593253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.1190593253
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.2692870319
Short name T566
Test name
Test status
Simulation time 4212433831 ps
CPU time 34.33 seconds
Started Apr 28 02:01:44 PM PDT 24
Finished Apr 28 02:02:19 PM PDT 24
Peak memory 242668 kb
Host smart-66f4def0-5567-42b7-bb2a-e797c0ec1e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692870319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.2692870319
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.1881394384
Short name T496
Test name
Test status
Simulation time 566374888 ps
CPU time 15.22 seconds
Started Apr 28 02:01:45 PM PDT 24
Finished Apr 28 02:02:01 PM PDT 24
Peak memory 247896 kb
Host smart-52309eb7-13a5-413a-809e-bbd1d338c483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881394384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1881394384
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.1187925974
Short name T645
Test name
Test status
Simulation time 1262647969 ps
CPU time 9.31 seconds
Started Apr 28 02:01:54 PM PDT 24
Finished Apr 28 02:02:03 PM PDT 24
Peak memory 241316 kb
Host smart-d70b29c0-0bd4-4610-a321-f6378057ae72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1187925974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.1187925974
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.4218345009
Short name T983
Test name
Test status
Simulation time 2078892567 ps
CPU time 5.03 seconds
Started Apr 28 02:01:44 PM PDT 24
Finished Apr 28 02:01:50 PM PDT 24
Peak memory 241324 kb
Host smart-52c50f84-47d3-44ae-b1d5-ce9368957ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218345009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.4218345009
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.4150670969
Short name T594
Test name
Test status
Simulation time 7585096997 ps
CPU time 75.82 seconds
Started Apr 28 02:01:50 PM PDT 24
Finished Apr 28 02:03:06 PM PDT 24
Peak memory 244904 kb
Host smart-a03e4409-2eb1-4b70-8e87-509fd04352c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150670969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.4150670969
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.2086658787
Short name T274
Test name
Test status
Simulation time 110517913439 ps
CPU time 1142.72 seconds
Started Apr 28 02:01:49 PM PDT 24
Finished Apr 28 02:20:53 PM PDT 24
Peak memory 304396 kb
Host smart-8492bd06-e97c-4334-9088-475d7fe26ac3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086658787 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.2086658787
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.405993297
Short name T524
Test name
Test status
Simulation time 13907966751 ps
CPU time 32.1 seconds
Started Apr 28 02:01:49 PM PDT 24
Finished Apr 28 02:02:22 PM PDT 24
Peak memory 241644 kb
Host smart-d5bbe9b3-b281-49db-9be7-e2ce459af975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405993297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.405993297
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.3661537478
Short name T770
Test name
Test status
Simulation time 104414073 ps
CPU time 1.88 seconds
Started Apr 28 01:57:35 PM PDT 24
Finished Apr 28 01:57:38 PM PDT 24
Peak memory 239832 kb
Host smart-92a5bfda-fc32-4faf-9af9-5d92212cc97d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661537478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.3661537478
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.3332816941
Short name T505
Test name
Test status
Simulation time 622371079 ps
CPU time 8.64 seconds
Started Apr 28 01:57:27 PM PDT 24
Finished Apr 28 01:57:36 PM PDT 24
Peak memory 241332 kb
Host smart-39768d38-7a4e-406c-ba08-7428f0506f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332816941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.3332816941
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.419874471
Short name T425
Test name
Test status
Simulation time 325144173 ps
CPU time 6.98 seconds
Started Apr 28 01:57:34 PM PDT 24
Finished Apr 28 01:57:42 PM PDT 24
Peak memory 241368 kb
Host smart-1dd50ffe-b3e6-4198-a9df-03dc060560fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419874471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.419874471
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.3696920503
Short name T9
Test name
Test status
Simulation time 2078556448 ps
CPU time 29.14 seconds
Started Apr 28 01:57:31 PM PDT 24
Finished Apr 28 01:58:01 PM PDT 24
Peak memory 241700 kb
Host smart-ae7aa78d-34b5-4dda-a284-43c68f0bf720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696920503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.3696920503
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.165782641
Short name T750
Test name
Test status
Simulation time 857782392 ps
CPU time 26.21 seconds
Started Apr 28 01:57:33 PM PDT 24
Finished Apr 28 01:57:59 PM PDT 24
Peak memory 241388 kb
Host smart-d65e943d-28cf-4944-a457-42220a330357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165782641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.165782641
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.3335836175
Short name T886
Test name
Test status
Simulation time 1068959551 ps
CPU time 21.6 seconds
Started Apr 28 01:57:31 PM PDT 24
Finished Apr 28 01:57:53 PM PDT 24
Peak memory 244136 kb
Host smart-eca97948-7877-403c-9b0f-cac907250da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335836175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.3335836175
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.2546545293
Short name T511
Test name
Test status
Simulation time 8257350732 ps
CPU time 16.14 seconds
Started Apr 28 01:57:32 PM PDT 24
Finished Apr 28 01:57:48 PM PDT 24
Peak memory 248080 kb
Host smart-9440814e-33e4-4c30-b5cc-b323eaa904e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546545293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.2546545293
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.4270123734
Short name T747
Test name
Test status
Simulation time 412087145 ps
CPU time 4.58 seconds
Started Apr 28 01:57:33 PM PDT 24
Finished Apr 28 01:57:38 PM PDT 24
Peak memory 241524 kb
Host smart-218ae1dd-4142-4a27-9caf-16e74838e418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270123734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.4270123734
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.1713541308
Short name T927
Test name
Test status
Simulation time 10370287588 ps
CPU time 27.89 seconds
Started Apr 28 01:57:30 PM PDT 24
Finished Apr 28 01:57:58 PM PDT 24
Peak memory 241508 kb
Host smart-d1ad0a71-5778-4c16-8ee2-a748833d2397
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713541308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.1713541308
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.2369334354
Short name T572
Test name
Test status
Simulation time 201980866 ps
CPU time 3.69 seconds
Started Apr 28 01:57:39 PM PDT 24
Finished Apr 28 01:57:43 PM PDT 24
Peak memory 247664 kb
Host smart-f3c0e211-95d8-431c-b3ce-0b981ccb6e86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369334354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.2369334354
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.1038362943
Short name T27
Test name
Test status
Simulation time 9973355084 ps
CPU time 168.83 seconds
Started Apr 28 01:57:35 PM PDT 24
Finished Apr 28 02:00:24 PM PDT 24
Peak memory 267748 kb
Host smart-c98dc68a-0391-487a-bd44-ae667bdf024d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038362943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1038362943
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.3250575018
Short name T409
Test name
Test status
Simulation time 347735687 ps
CPU time 4.21 seconds
Started Apr 28 01:57:28 PM PDT 24
Finished Apr 28 01:57:32 PM PDT 24
Peak memory 241196 kb
Host smart-f49e2a57-cc16-4608-821c-27aead1f3be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250575018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.3250575018
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.210479951
Short name T348
Test name
Test status
Simulation time 2006957537 ps
CPU time 82.4 seconds
Started Apr 28 01:57:40 PM PDT 24
Finished Apr 28 01:59:03 PM PDT 24
Peak memory 256252 kb
Host smart-13c91328-f8bb-4829-ab11-bfcb8f3779f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210479951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.210479951
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.1684668880
Short name T283
Test name
Test status
Simulation time 103853666346 ps
CPU time 2380.64 seconds
Started Apr 28 01:57:41 PM PDT 24
Finished Apr 28 02:37:23 PM PDT 24
Peak memory 280088 kb
Host smart-365c9675-292e-49c2-b4db-85000ae37014
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684668880 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.1684668880
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.949969574
Short name T19
Test name
Test status
Simulation time 1115143593 ps
CPU time 23.15 seconds
Started Apr 28 01:57:39 PM PDT 24
Finished Apr 28 01:58:03 PM PDT 24
Peak memory 241300 kb
Host smart-01cd8b39-5cdf-437b-9993-b258378fa1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949969574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.949969574
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.1228648803
Short name T1179
Test name
Test status
Simulation time 78835214 ps
CPU time 1.59 seconds
Started Apr 28 02:02:00 PM PDT 24
Finished Apr 28 02:02:02 PM PDT 24
Peak memory 239888 kb
Host smart-c38eb5d1-adce-4685-8cd0-da98b7b14199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228648803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.1228648803
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.3284250559
Short name T781
Test name
Test status
Simulation time 5020532080 ps
CPU time 16.83 seconds
Started Apr 28 02:01:56 PM PDT 24
Finished Apr 28 02:02:13 PM PDT 24
Peak memory 241444 kb
Host smart-53ac4ddc-19ef-4182-958d-182490795d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284250559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.3284250559
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.2974973696
Short name T156
Test name
Test status
Simulation time 1394497735 ps
CPU time 32.85 seconds
Started Apr 28 02:02:01 PM PDT 24
Finished Apr 28 02:02:34 PM PDT 24
Peak memory 241268 kb
Host smart-ff13f740-8c60-4232-bda3-bdd6bc1f3513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974973696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.2974973696
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.2337985905
Short name T569
Test name
Test status
Simulation time 2352969827 ps
CPU time 24.55 seconds
Started Apr 28 02:01:59 PM PDT 24
Finished Apr 28 02:02:24 PM PDT 24
Peak memory 241404 kb
Host smart-666dc7ab-0e8c-4efb-ad54-ec6e30098d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337985905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.2337985905
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.1275677692
Short name T95
Test name
Test status
Simulation time 150891679 ps
CPU time 4.32 seconds
Started Apr 28 02:01:50 PM PDT 24
Finished Apr 28 02:01:55 PM PDT 24
Peak memory 241676 kb
Host smart-bfad0777-fa2a-456d-abb9-a8232709cffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275677692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1275677692
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.1473595037
Short name T622
Test name
Test status
Simulation time 558994300 ps
CPU time 6.75 seconds
Started Apr 28 02:02:00 PM PDT 24
Finished Apr 28 02:02:08 PM PDT 24
Peak memory 247976 kb
Host smart-8160050c-6dec-43dd-a742-2898d51d0f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473595037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.1473595037
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.2477924341
Short name T1174
Test name
Test status
Simulation time 814922884 ps
CPU time 11.05 seconds
Started Apr 28 02:02:00 PM PDT 24
Finished Apr 28 02:02:12 PM PDT 24
Peak memory 241764 kb
Host smart-3c6a01f6-6a08-41db-8507-cb28ec1e15e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477924341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.2477924341
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.3873872275
Short name T321
Test name
Test status
Simulation time 1388115074 ps
CPU time 14.19 seconds
Started Apr 28 02:01:49 PM PDT 24
Finished Apr 28 02:02:04 PM PDT 24
Peak memory 241300 kb
Host smart-4d1b8d25-12b5-4438-9c7c-691b64db0fc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3873872275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.3873872275
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.4284746124
Short name T370
Test name
Test status
Simulation time 358529351 ps
CPU time 3.79 seconds
Started Apr 28 02:01:56 PM PDT 24
Finished Apr 28 02:02:00 PM PDT 24
Peak memory 241504 kb
Host smart-0e685fef-e638-4c80-a0c4-f560a4a83d02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4284746124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.4284746124
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.3860095162
Short name T662
Test name
Test status
Simulation time 182698034 ps
CPU time 2.87 seconds
Started Apr 28 02:01:51 PM PDT 24
Finished Apr 28 02:01:54 PM PDT 24
Peak memory 241120 kb
Host smart-664319d7-c587-401d-beff-12fa0a2a881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860095162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3860095162
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.1801690367
Short name T285
Test name
Test status
Simulation time 66788721530 ps
CPU time 1595.16 seconds
Started Apr 28 02:01:59 PM PDT 24
Finished Apr 28 02:28:35 PM PDT 24
Peak memory 279924 kb
Host smart-a3d2610d-8cbe-4613-ad9a-d16a0ce940a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801690367 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.1801690367
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.983652095
Short name T184
Test name
Test status
Simulation time 4399595073 ps
CPU time 49.45 seconds
Started Apr 28 02:02:01 PM PDT 24
Finished Apr 28 02:02:51 PM PDT 24
Peak memory 248028 kb
Host smart-011b2146-7758-4218-a119-4df7b74a12dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983652095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.983652095
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.1014442151
Short name T18
Test name
Test status
Simulation time 50303421 ps
CPU time 1.69 seconds
Started Apr 28 02:02:08 PM PDT 24
Finished Apr 28 02:02:11 PM PDT 24
Peak memory 239996 kb
Host smart-b14c8470-9ffd-4afb-b140-8742d5072639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014442151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1014442151
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.4156658997
Short name T34
Test name
Test status
Simulation time 2332474463 ps
CPU time 23.86 seconds
Started Apr 28 02:02:00 PM PDT 24
Finished Apr 28 02:02:25 PM PDT 24
Peak memory 241696 kb
Host smart-ab056422-6bc4-4a1c-86b0-57fdde439399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156658997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.4156658997
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.1615829239
Short name T795
Test name
Test status
Simulation time 3712857990 ps
CPU time 15.28 seconds
Started Apr 28 02:02:00 PM PDT 24
Finished Apr 28 02:02:16 PM PDT 24
Peak memory 241980 kb
Host smart-fc0d2274-34fa-43a3-935c-877bf6d63282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615829239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.1615829239
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.490600645
Short name T756
Test name
Test status
Simulation time 4063527960 ps
CPU time 8.23 seconds
Started Apr 28 02:02:00 PM PDT 24
Finished Apr 28 02:02:09 PM PDT 24
Peak memory 241704 kb
Host smart-54749a8d-362f-46b1-aa59-f80f11af1f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490600645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.490600645
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.1716574133
Short name T1125
Test name
Test status
Simulation time 404661129 ps
CPU time 4.19 seconds
Started Apr 28 02:02:11 PM PDT 24
Finished Apr 28 02:02:15 PM PDT 24
Peak memory 241580 kb
Host smart-475acb89-ac71-4abf-9610-f5da53ba401f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716574133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.1716574133
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.4267241037
Short name T862
Test name
Test status
Simulation time 2116983555 ps
CPU time 18.65 seconds
Started Apr 28 02:02:00 PM PDT 24
Finished Apr 28 02:02:19 PM PDT 24
Peak memory 245124 kb
Host smart-919e7ee1-b8da-4bb6-a715-77a13b4aa71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267241037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.4267241037
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.2107297106
Short name T1167
Test name
Test status
Simulation time 13353986960 ps
CPU time 27.33 seconds
Started Apr 28 02:02:00 PM PDT 24
Finished Apr 28 02:02:28 PM PDT 24
Peak memory 242536 kb
Host smart-a7e6090f-2bbb-42f3-beea-074c05a22de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107297106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.2107297106
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.236315684
Short name T10
Test name
Test status
Simulation time 222260734 ps
CPU time 5.82 seconds
Started Apr 28 02:02:00 PM PDT 24
Finished Apr 28 02:02:06 PM PDT 24
Peak memory 241784 kb
Host smart-a07d2bb9-2382-4984-abf8-bd167d4eff7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236315684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.236315684
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.1969586725
Short name T383
Test name
Test status
Simulation time 2311834547 ps
CPU time 19.43 seconds
Started Apr 28 02:02:02 PM PDT 24
Finished Apr 28 02:02:22 PM PDT 24
Peak memory 241324 kb
Host smart-87d0a7ff-c071-4179-a2a3-2ca1b8ae5ffe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1969586725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.1969586725
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.3579180232
Short name T588
Test name
Test status
Simulation time 304679759 ps
CPU time 7.65 seconds
Started Apr 28 02:02:06 PM PDT 24
Finished Apr 28 02:02:14 PM PDT 24
Peak memory 241384 kb
Host smart-0b82db6e-b267-44e3-9483-8b2bbd8a4f8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3579180232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.3579180232
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.67720119
Short name T565
Test name
Test status
Simulation time 5872515648 ps
CPU time 14.39 seconds
Started Apr 28 02:02:00 PM PDT 24
Finished Apr 28 02:02:15 PM PDT 24
Peak memory 241416 kb
Host smart-ae5f67ce-7940-4ea3-9d4c-6d921a449c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67720119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.67720119
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.965529766
Short name T349
Test name
Test status
Simulation time 3480476271 ps
CPU time 38.32 seconds
Started Apr 28 02:02:06 PM PDT 24
Finished Apr 28 02:02:45 PM PDT 24
Peak memory 248064 kb
Host smart-bb36200f-9d7b-4851-a27f-a11faa398566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965529766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.
965529766
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.462989693
Short name T916
Test name
Test status
Simulation time 17276903102 ps
CPU time 47.92 seconds
Started Apr 28 02:02:06 PM PDT 24
Finished Apr 28 02:02:54 PM PDT 24
Peak memory 242168 kb
Host smart-036de1dd-457a-48c4-8bc6-19a016300c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462989693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.462989693
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.239246741
Short name T531
Test name
Test status
Simulation time 220123472 ps
CPU time 2.06 seconds
Started Apr 28 02:02:13 PM PDT 24
Finished Apr 28 02:02:15 PM PDT 24
Peak memory 240088 kb
Host smart-7f17ddb5-cc42-4658-bcb6-8a47479f4534
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239246741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.239246741
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.197100537
Short name T213
Test name
Test status
Simulation time 636057181 ps
CPU time 8.43 seconds
Started Apr 28 02:02:11 PM PDT 24
Finished Apr 28 02:02:20 PM PDT 24
Peak memory 241312 kb
Host smart-95001c8b-c653-45cf-a037-4879f5246736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197100537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.197100537
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.3272861539
Short name T939
Test name
Test status
Simulation time 575046870 ps
CPU time 15.23 seconds
Started Apr 28 02:02:10 PM PDT 24
Finished Apr 28 02:02:25 PM PDT 24
Peak memory 241584 kb
Host smart-bc056945-8bf6-456f-bc84-02b77b124d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272861539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.3272861539
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.3505675362
Short name T644
Test name
Test status
Simulation time 3843497113 ps
CPU time 11.42 seconds
Started Apr 28 02:02:05 PM PDT 24
Finished Apr 28 02:02:17 PM PDT 24
Peak memory 241736 kb
Host smart-55bc7701-d300-4ada-bce9-fe7c6c7918ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505675362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3505675362
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.4010877939
Short name T736
Test name
Test status
Simulation time 2224242458 ps
CPU time 4.98 seconds
Started Apr 28 02:02:04 PM PDT 24
Finished Apr 28 02:02:09 PM PDT 24
Peak memory 241840 kb
Host smart-1b55a2c9-272e-410f-adc9-64624c286d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010877939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.4010877939
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.17156530
Short name T880
Test name
Test status
Simulation time 3460947282 ps
CPU time 24.07 seconds
Started Apr 28 02:02:09 PM PDT 24
Finished Apr 28 02:02:33 PM PDT 24
Peak memory 241588 kb
Host smart-8a912375-9a1c-4188-8d42-f7a0985f4292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17156530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.17156530
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.3138619352
Short name T440
Test name
Test status
Simulation time 2087236429 ps
CPU time 25.59 seconds
Started Apr 28 02:02:14 PM PDT 24
Finished Apr 28 02:02:39 PM PDT 24
Peak memory 247968 kb
Host smart-800682b0-b188-451d-b9da-d3cd299991d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138619352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.3138619352
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.1504454191
Short name T344
Test name
Test status
Simulation time 1700926206 ps
CPU time 14.11 seconds
Started Apr 28 02:02:05 PM PDT 24
Finished Apr 28 02:02:20 PM PDT 24
Peak memory 241352 kb
Host smart-ffd90206-8013-47c8-939a-a738221e2ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504454191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1504454191
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.1549477833
Short name T609
Test name
Test status
Simulation time 3008497252 ps
CPU time 26.35 seconds
Started Apr 28 02:02:06 PM PDT 24
Finished Apr 28 02:02:33 PM PDT 24
Peak memory 241388 kb
Host smart-b13585f5-5360-461f-af5e-cddac3728384
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1549477833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1549477833
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.1093244659
Short name T1109
Test name
Test status
Simulation time 205122557 ps
CPU time 5.78 seconds
Started Apr 28 02:02:08 PM PDT 24
Finished Apr 28 02:02:14 PM PDT 24
Peak memory 241296 kb
Host smart-8afabff5-e0f1-40da-b5db-70eb0e90b91f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093244659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.1093244659
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.1475869964
Short name T474
Test name
Test status
Simulation time 409512902 ps
CPU time 5.61 seconds
Started Apr 28 02:02:05 PM PDT 24
Finished Apr 28 02:02:11 PM PDT 24
Peak memory 241440 kb
Host smart-8a05fda5-7452-4f66-b13b-f2b13cd55a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475869964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.1475869964
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.2022210865
Short name T728
Test name
Test status
Simulation time 11902726813 ps
CPU time 76.46 seconds
Started Apr 28 02:02:09 PM PDT 24
Finished Apr 28 02:03:26 PM PDT 24
Peak memory 243452 kb
Host smart-5eafee09-1709-4510-9da6-c21f9bb48a20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022210865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.2022210865
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.2465844621
Short name T468
Test name
Test status
Simulation time 34885019288 ps
CPU time 1072.35 seconds
Started Apr 28 02:02:09 PM PDT 24
Finished Apr 28 02:20:02 PM PDT 24
Peak memory 412132 kb
Host smart-821257bb-b6c3-4d6f-a880-d9fda745eea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465844621 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.2465844621
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.2295182547
Short name T920
Test name
Test status
Simulation time 1904656819 ps
CPU time 5.26 seconds
Started Apr 28 02:02:10 PM PDT 24
Finished Apr 28 02:02:15 PM PDT 24
Peak memory 241264 kb
Host smart-f03cbadc-86a2-4a39-87c2-5040e6f6e5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295182547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.2295182547
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.2593857990
Short name T102
Test name
Test status
Simulation time 137658544 ps
CPU time 1.89 seconds
Started Apr 28 02:02:21 PM PDT 24
Finished Apr 28 02:02:23 PM PDT 24
Peak memory 239712 kb
Host smart-84cdd37c-118b-4266-8267-04cc4bbce091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593857990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.2593857990
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.1754493632
Short name T1129
Test name
Test status
Simulation time 3539389261 ps
CPU time 8.09 seconds
Started Apr 28 02:02:15 PM PDT 24
Finished Apr 28 02:02:24 PM PDT 24
Peak memory 241584 kb
Host smart-99582d96-d18e-4b86-af86-e4c5670aa6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754493632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.1754493632
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.187388315
Short name T864
Test name
Test status
Simulation time 882139954 ps
CPU time 14.29 seconds
Started Apr 28 02:02:16 PM PDT 24
Finished Apr 28 02:02:30 PM PDT 24
Peak memory 241236 kb
Host smart-395894b8-3a2d-4c11-a5c3-643c284e4055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187388315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.187388315
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.3584516996
Short name T476
Test name
Test status
Simulation time 507474108 ps
CPU time 8.39 seconds
Started Apr 28 02:02:16 PM PDT 24
Finished Apr 28 02:02:24 PM PDT 24
Peak memory 241160 kb
Host smart-3b6c7012-3274-4cdd-bab9-22fec6823845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584516996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.3584516996
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.3827322265
Short name T449
Test name
Test status
Simulation time 604034067 ps
CPU time 4.68 seconds
Started Apr 28 02:02:15 PM PDT 24
Finished Apr 28 02:02:20 PM PDT 24
Peak memory 241712 kb
Host smart-df63db1b-c87f-4d71-9367-4659ef5bde27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827322265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.3827322265
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.1105766680
Short name T702
Test name
Test status
Simulation time 3787092927 ps
CPU time 52.68 seconds
Started Apr 28 02:02:14 PM PDT 24
Finished Apr 28 02:03:07 PM PDT 24
Peak memory 264468 kb
Host smart-896974b1-149a-47d6-a5a1-7a1f4637ea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105766680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.1105766680
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.3784810458
Short name T1008
Test name
Test status
Simulation time 751340099 ps
CPU time 27.31 seconds
Started Apr 28 02:02:15 PM PDT 24
Finished Apr 28 02:02:43 PM PDT 24
Peak memory 241680 kb
Host smart-5b647ed0-5834-45bf-8b26-f0c4f210a2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784810458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.3784810458
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.2509664752
Short name T143
Test name
Test status
Simulation time 1397798934 ps
CPU time 4.96 seconds
Started Apr 28 02:02:17 PM PDT 24
Finished Apr 28 02:02:22 PM PDT 24
Peak memory 241176 kb
Host smart-41e4ac6c-0db8-4e08-b800-e13638f8ab17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509664752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.2509664752
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.4260091463
Short name T607
Test name
Test status
Simulation time 954569403 ps
CPU time 8.11 seconds
Started Apr 28 02:02:16 PM PDT 24
Finished Apr 28 02:02:25 PM PDT 24
Peak memory 247940 kb
Host smart-a1fcdc35-64ee-4990-9127-f7a385522682
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260091463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.4260091463
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.139369271
Short name T1056
Test name
Test status
Simulation time 163892122 ps
CPU time 4.79 seconds
Started Apr 28 02:02:19 PM PDT 24
Finished Apr 28 02:02:24 PM PDT 24
Peak memory 241352 kb
Host smart-8cfbf697-2db6-4580-b68e-6b34dd5bb046
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139369271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.139369271
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.2461970533
Short name T539
Test name
Test status
Simulation time 2327198448 ps
CPU time 6.92 seconds
Started Apr 28 02:02:18 PM PDT 24
Finished Apr 28 02:02:25 PM PDT 24
Peak memory 241464 kb
Host smart-9ccbc271-0f0a-4dbe-ac43-b404e49b8f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461970533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.2461970533
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.3950842177
Short name T847
Test name
Test status
Simulation time 4541885338 ps
CPU time 7.76 seconds
Started Apr 28 02:02:19 PM PDT 24
Finished Apr 28 02:02:27 PM PDT 24
Peak memory 241548 kb
Host smart-bc733f28-830b-4bf7-b912-67c8161d6de7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950842177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.3950842177
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.3577479067
Short name T257
Test name
Test status
Simulation time 354556648664 ps
CPU time 1462.79 seconds
Started Apr 28 02:02:19 PM PDT 24
Finished Apr 28 02:26:42 PM PDT 24
Peak memory 344228 kb
Host smart-a92a5d8a-f0f6-4993-b44b-051e162618bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577479067 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.3577479067
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.4138281059
Short name T964
Test name
Test status
Simulation time 2725676464 ps
CPU time 18.66 seconds
Started Apr 28 02:02:25 PM PDT 24
Finished Apr 28 02:02:44 PM PDT 24
Peak memory 248048 kb
Host smart-36c43875-5ed3-43ad-80e9-8380c1f7d1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138281059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.4138281059
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.1876778815
Short name T720
Test name
Test status
Simulation time 221844796 ps
CPU time 1.77 seconds
Started Apr 28 02:02:31 PM PDT 24
Finished Apr 28 02:02:33 PM PDT 24
Peak memory 239828 kb
Host smart-5e36d38c-f166-48a7-b0ec-b7742cf04de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876778815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.1876778815
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.1549997555
Short name T130
Test name
Test status
Simulation time 1687517046 ps
CPU time 21.67 seconds
Started Apr 28 02:02:26 PM PDT 24
Finished Apr 28 02:02:48 PM PDT 24
Peak memory 241948 kb
Host smart-b610d1c0-f302-4c1d-adc9-8f9992519867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549997555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.1549997555
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.3063063398
Short name T3
Test name
Test status
Simulation time 1448350268 ps
CPU time 27.62 seconds
Started Apr 28 02:02:25 PM PDT 24
Finished Apr 28 02:02:53 PM PDT 24
Peak memory 241584 kb
Host smart-ab8b7714-3b70-4eb5-b405-ff46048a1779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063063398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.3063063398
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.1322171575
Short name T961
Test name
Test status
Simulation time 1449823082 ps
CPU time 28.45 seconds
Started Apr 28 02:02:27 PM PDT 24
Finished Apr 28 02:02:56 PM PDT 24
Peak memory 241508 kb
Host smart-5fb43f10-1489-4d11-a996-4ae0da9b45a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322171575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.1322171575
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.3826742314
Short name T954
Test name
Test status
Simulation time 191252210 ps
CPU time 4.63 seconds
Started Apr 28 02:02:22 PM PDT 24
Finished Apr 28 02:02:27 PM PDT 24
Peak memory 241368 kb
Host smart-3bd42c74-b75b-4e5d-b61a-56697a037f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826742314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.3826742314
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.3308233635
Short name T951
Test name
Test status
Simulation time 1244930918 ps
CPU time 13.35 seconds
Started Apr 28 02:02:25 PM PDT 24
Finished Apr 28 02:02:39 PM PDT 24
Peak memory 241688 kb
Host smart-15726318-39c7-442e-b5b4-69e0c864ce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308233635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.3308233635
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.255076657
Short name T541
Test name
Test status
Simulation time 274818016 ps
CPU time 6.7 seconds
Started Apr 28 02:02:23 PM PDT 24
Finished Apr 28 02:02:30 PM PDT 24
Peak memory 241272 kb
Host smart-72f8d005-dbd8-42aa-a24a-1ad0a52c511d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255076657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.255076657
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.2671134068
Short name T345
Test name
Test status
Simulation time 250707737 ps
CPU time 11.02 seconds
Started Apr 28 02:02:19 PM PDT 24
Finished Apr 28 02:02:31 PM PDT 24
Peak memory 241584 kb
Host smart-fbbd0593-0644-4443-af7d-9bbdf789ea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671134068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.2671134068
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.923360852
Short name T717
Test name
Test status
Simulation time 188560703 ps
CPU time 5.93 seconds
Started Apr 28 02:02:24 PM PDT 24
Finished Apr 28 02:02:30 PM PDT 24
Peak memory 241328 kb
Host smart-9d8e7a3f-cafa-4952-8d35-d3cceb87d18b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=923360852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.923360852
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.773980057
Short name T649
Test name
Test status
Simulation time 2875953886 ps
CPU time 5.61 seconds
Started Apr 28 02:02:21 PM PDT 24
Finished Apr 28 02:02:27 PM PDT 24
Peak memory 241680 kb
Host smart-d98b992f-46e5-420a-b399-e8d0ae6e200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773980057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.773980057
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.3327382931
Short name T810
Test name
Test status
Simulation time 32850500241 ps
CPU time 304.14 seconds
Started Apr 28 02:02:27 PM PDT 24
Finished Apr 28 02:07:32 PM PDT 24
Peak memory 282360 kb
Host smart-b1f52679-0d9a-4cb7-9e34-35f5deb39405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327382931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.3327382931
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.3174798395
Short name T507
Test name
Test status
Simulation time 212818834040 ps
CPU time 1270.05 seconds
Started Apr 28 02:02:26 PM PDT 24
Finished Apr 28 02:23:37 PM PDT 24
Peak memory 304640 kb
Host smart-324b1f0e-62d7-455d-b1b2-ca476bee2dd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174798395 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.3174798395
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.2405479807
Short name T516
Test name
Test status
Simulation time 16731744918 ps
CPU time 24.64 seconds
Started Apr 28 02:02:27 PM PDT 24
Finished Apr 28 02:02:52 PM PDT 24
Peak memory 241808 kb
Host smart-9af12754-16e6-45ce-a6aa-39269b279215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405479807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.2405479807
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.4004194610
Short name T852
Test name
Test status
Simulation time 131073674 ps
CPU time 2.22 seconds
Started Apr 28 02:02:39 PM PDT 24
Finished Apr 28 02:02:42 PM PDT 24
Peak memory 240220 kb
Host smart-dee1c8a9-9541-4417-ae2d-e3af7e5c6288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004194610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.4004194610
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.1236490738
Short name T61
Test name
Test status
Simulation time 1882452623 ps
CPU time 36.94 seconds
Started Apr 28 02:02:31 PM PDT 24
Finished Apr 28 02:03:08 PM PDT 24
Peak memory 247976 kb
Host smart-ad108354-2014-4b5e-bd09-56f8bd737e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236490738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.1236490738
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.301833420
Short name T475
Test name
Test status
Simulation time 3421705260 ps
CPU time 14.51 seconds
Started Apr 28 02:02:31 PM PDT 24
Finished Apr 28 02:02:46 PM PDT 24
Peak memory 241400 kb
Host smart-aa0db0db-6fc7-47fb-bdc3-7d8b45db8ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301833420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.301833420
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.2050960692
Short name T1159
Test name
Test status
Simulation time 776531891 ps
CPU time 4.45 seconds
Started Apr 28 02:02:30 PM PDT 24
Finished Apr 28 02:02:35 PM PDT 24
Peak memory 241592 kb
Host smart-e732c4a0-7105-4b7b-abec-5a10f4f88f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050960692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.2050960692
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.2682858353
Short name T131
Test name
Test status
Simulation time 306080852 ps
CPU time 4.05 seconds
Started Apr 28 02:02:32 PM PDT 24
Finished Apr 28 02:02:36 PM PDT 24
Peak memory 241668 kb
Host smart-98a68863-374e-4d40-b0f5-94339f4f7de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682858353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.2682858353
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.4227113948
Short name T1127
Test name
Test status
Simulation time 1772493348 ps
CPU time 25.06 seconds
Started Apr 28 02:02:29 PM PDT 24
Finished Apr 28 02:02:55 PM PDT 24
Peak memory 247980 kb
Host smart-629db4b0-673c-46bb-96db-e6212a759a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227113948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.4227113948
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.1471882757
Short name T1170
Test name
Test status
Simulation time 5956705258 ps
CPU time 20.97 seconds
Started Apr 28 02:02:36 PM PDT 24
Finished Apr 28 02:02:58 PM PDT 24
Peak memory 242404 kb
Host smart-70589a0d-a2c5-47a6-9c04-ba8c7091da6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471882757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.1471882757
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.2875684062
Short name T144
Test name
Test status
Simulation time 550406371 ps
CPU time 6.89 seconds
Started Apr 28 02:02:29 PM PDT 24
Finished Apr 28 02:02:36 PM PDT 24
Peak memory 241256 kb
Host smart-565254c2-9c55-49e0-bfe1-2824dfe17823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875684062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.2875684062
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.161586603
Short name T724
Test name
Test status
Simulation time 1036296094 ps
CPU time 15.26 seconds
Started Apr 28 02:02:31 PM PDT 24
Finished Apr 28 02:02:46 PM PDT 24
Peak memory 241324 kb
Host smart-fa545e6d-2307-4c51-8c2a-d746bfdece3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=161586603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.161586603
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.2490617960
Short name T1028
Test name
Test status
Simulation time 2468474975 ps
CPU time 8.89 seconds
Started Apr 28 02:02:35 PM PDT 24
Finished Apr 28 02:02:45 PM PDT 24
Peak memory 241408 kb
Host smart-4f49a7e8-7521-4b19-a091-df7d408c8067
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490617960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2490617960
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.2860545610
Short name T863
Test name
Test status
Simulation time 428963256 ps
CPU time 10.3 seconds
Started Apr 28 02:02:29 PM PDT 24
Finished Apr 28 02:02:39 PM PDT 24
Peak memory 241476 kb
Host smart-6434d9ad-dcb5-49e0-9522-559325456ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860545610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.2860545610
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.3448511968
Short name T842
Test name
Test status
Simulation time 3157087342 ps
CPU time 60.76 seconds
Started Apr 28 02:02:38 PM PDT 24
Finished Apr 28 02:03:39 PM PDT 24
Peak memory 243684 kb
Host smart-f07df13a-aaaa-4f48-afde-bb5efbf7e8ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448511968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.3448511968
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.1259240263
Short name T1069
Test name
Test status
Simulation time 153883440536 ps
CPU time 442.66 seconds
Started Apr 28 02:02:39 PM PDT 24
Finished Apr 28 02:10:02 PM PDT 24
Peak memory 281000 kb
Host smart-7ff09799-ff87-480f-af1c-e67bed03ed4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259240263 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.1259240263
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.989570089
Short name T896
Test name
Test status
Simulation time 1697429485 ps
CPU time 12.88 seconds
Started Apr 28 02:02:38 PM PDT 24
Finished Apr 28 02:02:51 PM PDT 24
Peak memory 247964 kb
Host smart-58f731c2-3738-476a-bedf-9c22676f3e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989570089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.989570089
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.2647841088
Short name T692
Test name
Test status
Simulation time 77109291 ps
CPU time 2.03 seconds
Started Apr 28 02:03:01 PM PDT 24
Finished Apr 28 02:03:04 PM PDT 24
Peak memory 240088 kb
Host smart-25d2fb8d-989d-4671-a116-43b407d14801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647841088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.2647841088
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.1418765960
Short name T48
Test name
Test status
Simulation time 2299806931 ps
CPU time 17.97 seconds
Started Apr 28 02:03:04 PM PDT 24
Finished Apr 28 02:03:23 PM PDT 24
Peak memory 241632 kb
Host smart-66d4fd20-fb9a-43f6-a30d-f1e5eb8daa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418765960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.1418765960
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.1446703331
Short name T446
Test name
Test status
Simulation time 358522837 ps
CPU time 7.73 seconds
Started Apr 28 02:03:01 PM PDT 24
Finished Apr 28 02:03:10 PM PDT 24
Peak memory 241404 kb
Host smart-a17791b8-6203-4b33-9cd1-6170cec22c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446703331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.1446703331
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.2943300739
Short name T1061
Test name
Test status
Simulation time 6854790295 ps
CPU time 17.78 seconds
Started Apr 28 02:03:04 PM PDT 24
Finished Apr 28 02:03:22 PM PDT 24
Peak memory 242244 kb
Host smart-e774bbc0-3523-4c35-82cd-6cc0c5e153b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943300739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.2943300739
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.2352690297
Short name T672
Test name
Test status
Simulation time 113813217 ps
CPU time 4.38 seconds
Started Apr 28 02:02:35 PM PDT 24
Finished Apr 28 02:02:40 PM PDT 24
Peak memory 241164 kb
Host smart-f0b79dcf-aa44-476a-9e36-dab139e8cbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352690297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2352690297
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.1198750097
Short name T523
Test name
Test status
Simulation time 1534223479 ps
CPU time 18.48 seconds
Started Apr 28 02:02:59 PM PDT 24
Finished Apr 28 02:03:18 PM PDT 24
Peak memory 241508 kb
Host smart-73b8bca5-9a98-4aa9-9754-0f0988bffd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198750097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.1198750097
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.1414376703
Short name T1064
Test name
Test status
Simulation time 240833862 ps
CPU time 5.87 seconds
Started Apr 28 02:03:00 PM PDT 24
Finished Apr 28 02:03:07 PM PDT 24
Peak memory 241696 kb
Host smart-1d2ad458-6e1d-41ec-b2f1-e03f4f716b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414376703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1414376703
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.1398884620
Short name T889
Test name
Test status
Simulation time 3738632772 ps
CPU time 7.8 seconds
Started Apr 28 02:03:00 PM PDT 24
Finished Apr 28 02:03:08 PM PDT 24
Peak memory 241444 kb
Host smart-b3b901e1-5b41-4f70-8fb7-a609239fe27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398884620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1398884620
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.3565667448
Short name T103
Test name
Test status
Simulation time 434984551 ps
CPU time 10.4 seconds
Started Apr 28 02:02:37 PM PDT 24
Finished Apr 28 02:02:48 PM PDT 24
Peak memory 241312 kb
Host smart-44631887-bd76-49f9-adb1-455f40c52a11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3565667448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3565667448
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.2800126202
Short name T804
Test name
Test status
Simulation time 352510659 ps
CPU time 6.12 seconds
Started Apr 28 02:03:02 PM PDT 24
Finished Apr 28 02:03:08 PM PDT 24
Peak memory 241264 kb
Host smart-205c63ad-e1d7-4baf-9e84-ca3553abc041
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2800126202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2800126202
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.927952957
Short name T559
Test name
Test status
Simulation time 689549684 ps
CPU time 11.23 seconds
Started Apr 28 02:02:35 PM PDT 24
Finished Apr 28 02:02:46 PM PDT 24
Peak memory 241488 kb
Host smart-b42aded1-65dc-44c9-9df8-011923b20f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927952957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.927952957
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.2896629805
Short name T895
Test name
Test status
Simulation time 122666701596 ps
CPU time 222.93 seconds
Started Apr 28 02:03:00 PM PDT 24
Finished Apr 28 02:06:43 PM PDT 24
Peak memory 258212 kb
Host smart-ae217de2-9ba9-4493-aaab-f448d22a353e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896629805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.2896629805
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.1027824087
Short name T388
Test name
Test status
Simulation time 106914636981 ps
CPU time 384.21 seconds
Started Apr 28 02:03:01 PM PDT 24
Finished Apr 28 02:09:25 PM PDT 24
Peak memory 264604 kb
Host smart-2b0d2808-1981-4f90-a80f-ba88f7cbaff0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027824087 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.1027824087
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.829162667
Short name T447
Test name
Test status
Simulation time 6782555837 ps
CPU time 45.58 seconds
Started Apr 28 02:03:00 PM PDT 24
Finished Apr 28 02:03:46 PM PDT 24
Peak memory 242472 kb
Host smart-5f87fc19-e8b4-429b-80d3-64acc3a64812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829162667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.829162667
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.1173485524
Short name T784
Test name
Test status
Simulation time 263638266 ps
CPU time 1.94 seconds
Started Apr 28 02:03:07 PM PDT 24
Finished Apr 28 02:03:10 PM PDT 24
Peak memory 239996 kb
Host smart-8824371e-b51a-453f-a203-0df79c9c6a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173485524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.1173485524
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.3216376366
Short name T93
Test name
Test status
Simulation time 2405280383 ps
CPU time 24.5 seconds
Started Apr 28 02:03:01 PM PDT 24
Finished Apr 28 02:03:27 PM PDT 24
Peak memory 241952 kb
Host smart-28fc72dc-b46b-48e7-8dfb-6cc346c919a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216376366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3216376366
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.3088243230
Short name T812
Test name
Test status
Simulation time 3814461207 ps
CPU time 37.62 seconds
Started Apr 28 02:03:01 PM PDT 24
Finished Apr 28 02:03:39 PM PDT 24
Peak memory 246320 kb
Host smart-003045f0-6a23-4785-8970-fc7443f60c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088243230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.3088243230
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.3239972897
Short name T865
Test name
Test status
Simulation time 864486247 ps
CPU time 13.87 seconds
Started Apr 28 02:03:02 PM PDT 24
Finished Apr 28 02:03:16 PM PDT 24
Peak memory 241408 kb
Host smart-f56ef44d-d754-4fb7-b4cb-0a1f01f4c16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239972897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.3239972897
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.383867858
Short name T430
Test name
Test status
Simulation time 2664285357 ps
CPU time 5.47 seconds
Started Apr 28 02:03:02 PM PDT 24
Finished Apr 28 02:03:08 PM PDT 24
Peak memory 241516 kb
Host smart-47722d6d-e3ac-4fa1-95fd-443b4d91d38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383867858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.383867858
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.2370781746
Short name T726
Test name
Test status
Simulation time 688208498 ps
CPU time 15.95 seconds
Started Apr 28 02:03:03 PM PDT 24
Finished Apr 28 02:03:19 PM PDT 24
Peak memory 241932 kb
Host smart-238dff58-5851-4e4e-a546-56812f0ee32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370781746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.2370781746
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.3917876237
Short name T435
Test name
Test status
Simulation time 2432948194 ps
CPU time 20.02 seconds
Started Apr 28 02:03:02 PM PDT 24
Finished Apr 28 02:03:22 PM PDT 24
Peak memory 241500 kb
Host smart-ae45aa08-c476-4735-bd21-6d07e67758c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917876237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.3917876237
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.3367222890
Short name T587
Test name
Test status
Simulation time 439727188 ps
CPU time 7.01 seconds
Started Apr 28 02:02:59 PM PDT 24
Finished Apr 28 02:03:07 PM PDT 24
Peak memory 241592 kb
Host smart-0e396837-8eac-414d-9273-b755e65bfded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367222890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.3367222890
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.3424177598
Short name T1053
Test name
Test status
Simulation time 340950425 ps
CPU time 5.17 seconds
Started Apr 28 02:03:01 PM PDT 24
Finished Apr 28 02:03:07 PM PDT 24
Peak memory 241392 kb
Host smart-5acbd2c8-539a-43f8-ab56-c2df5a16a88a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3424177598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.3424177598
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.3104736282
Short name T642
Test name
Test status
Simulation time 422574895 ps
CPU time 5.19 seconds
Started Apr 28 02:02:59 PM PDT 24
Finished Apr 28 02:03:05 PM PDT 24
Peak memory 241696 kb
Host smart-c47d8eeb-d9b6-4b1d-85a6-04e4eead1908
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3104736282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.3104736282
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.1914891446
Short name T483
Test name
Test status
Simulation time 758901138 ps
CPU time 6.03 seconds
Started Apr 28 02:03:02 PM PDT 24
Finished Apr 28 02:03:09 PM PDT 24
Peak memory 241356 kb
Host smart-152fc200-9d34-4195-9072-dc8d9cd394b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914891446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1914891446
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.4139417198
Short name T840
Test name
Test status
Simulation time 40193144019 ps
CPU time 224.79 seconds
Started Apr 28 02:03:10 PM PDT 24
Finished Apr 28 02:06:56 PM PDT 24
Peak memory 248164 kb
Host smart-269e6942-6b1d-4e25-a9fb-81b785ba80fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139417198 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.4139417198
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.2156049026
Short name T1160
Test name
Test status
Simulation time 117555971 ps
CPU time 3.2 seconds
Started Apr 28 02:03:03 PM PDT 24
Finished Apr 28 02:03:07 PM PDT 24
Peak memory 241596 kb
Host smart-10ff2046-58f1-40fd-ac3b-ac6a77f1096a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156049026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.2156049026
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.845883682
Short name T1074
Test name
Test status
Simulation time 61893332 ps
CPU time 1.82 seconds
Started Apr 28 02:03:13 PM PDT 24
Finished Apr 28 02:03:15 PM PDT 24
Peak memory 240140 kb
Host smart-223b3779-b51c-43a2-b2bd-895f08428428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845883682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.845883682
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.2279080105
Short name T112
Test name
Test status
Simulation time 2671135830 ps
CPU time 25.45 seconds
Started Apr 28 02:03:08 PM PDT 24
Finished Apr 28 02:03:35 PM PDT 24
Peak memory 241720 kb
Host smart-4adf4f8c-ce75-462b-a75e-9c62d744c1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279080105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.2279080105
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.2867281008
Short name T553
Test name
Test status
Simulation time 284891528 ps
CPU time 14.27 seconds
Started Apr 28 02:03:06 PM PDT 24
Finished Apr 28 02:03:21 PM PDT 24
Peak memory 241416 kb
Host smart-6be40541-c0b2-4ca3-8c82-8f2495c4da99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867281008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.2867281008
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.4287704870
Short name T913
Test name
Test status
Simulation time 13118973126 ps
CPU time 24.67 seconds
Started Apr 28 02:03:09 PM PDT 24
Finished Apr 28 02:03:34 PM PDT 24
Peak memory 241500 kb
Host smart-3effd797-173b-4599-9a12-bb670a8dc4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287704870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.4287704870
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.617843286
Short name T777
Test name
Test status
Simulation time 112902862 ps
CPU time 4.41 seconds
Started Apr 28 02:03:08 PM PDT 24
Finished Apr 28 02:03:14 PM PDT 24
Peak memory 241448 kb
Host smart-9d0da4c3-6479-4797-98d1-265366fc6edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617843286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.617843286
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.2651590405
Short name T289
Test name
Test status
Simulation time 1710549914 ps
CPU time 39.24 seconds
Started Apr 28 02:03:06 PM PDT 24
Finished Apr 28 02:03:45 PM PDT 24
Peak memory 260452 kb
Host smart-62081106-7def-4912-87d9-05a4cba742f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651590405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2651590405
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.2791555299
Short name T775
Test name
Test status
Simulation time 5960892921 ps
CPU time 16.92 seconds
Started Apr 28 02:03:08 PM PDT 24
Finished Apr 28 02:03:25 PM PDT 24
Peak memory 242136 kb
Host smart-49609543-0678-4f0e-a794-3861155946cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791555299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.2791555299
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.1568085858
Short name T522
Test name
Test status
Simulation time 2488728300 ps
CPU time 7.85 seconds
Started Apr 28 02:03:06 PM PDT 24
Finished Apr 28 02:03:14 PM PDT 24
Peak memory 241564 kb
Host smart-a4e91034-e6e7-4ef8-a97a-3a5061cce1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568085858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.1568085858
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.49889477
Short name T498
Test name
Test status
Simulation time 802011393 ps
CPU time 16.79 seconds
Started Apr 28 02:03:10 PM PDT 24
Finished Apr 28 02:03:27 PM PDT 24
Peak memory 241276 kb
Host smart-a9958bcc-a672-4f18-a967-af615d51c7a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49889477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.49889477
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.141088314
Short name T834
Test name
Test status
Simulation time 4777695876 ps
CPU time 16.38 seconds
Started Apr 28 02:03:11 PM PDT 24
Finished Apr 28 02:03:28 PM PDT 24
Peak memory 241404 kb
Host smart-3397426a-819e-4733-87d4-772e02dc1e4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141088314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.141088314
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.1087878999
Short name T445
Test name
Test status
Simulation time 546088134 ps
CPU time 10 seconds
Started Apr 28 02:03:09 PM PDT 24
Finished Apr 28 02:03:20 PM PDT 24
Peak memory 241720 kb
Host smart-e6d6c011-b409-44a3-be97-001d5710c13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087878999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.1087878999
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.477887257
Short name T351
Test name
Test status
Simulation time 18500322403 ps
CPU time 185.84 seconds
Started Apr 28 02:03:19 PM PDT 24
Finished Apr 28 02:06:25 PM PDT 24
Peak memory 280624 kb
Host smart-553b1d14-b357-4a80-8856-e5f04acfc8b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477887257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.
477887257
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3405541531
Short name T688
Test name
Test status
Simulation time 62334984806 ps
CPU time 1165.07 seconds
Started Apr 28 02:03:08 PM PDT 24
Finished Apr 28 02:22:35 PM PDT 24
Peak memory 302128 kb
Host smart-38b177bc-bcce-4f3f-9aa5-4d915cf589ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405541531 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.3405541531
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.2181109634
Short name T1013
Test name
Test status
Simulation time 1855811794 ps
CPU time 26.37 seconds
Started Apr 28 02:03:09 PM PDT 24
Finished Apr 28 02:03:36 PM PDT 24
Peak memory 241348 kb
Host smart-126a27b6-898f-43ec-9364-b2bb70ac1854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181109634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.2181109634
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.2498010502
Short name T719
Test name
Test status
Simulation time 175728365 ps
CPU time 1.78 seconds
Started Apr 28 02:03:10 PM PDT 24
Finished Apr 28 02:03:12 PM PDT 24
Peak memory 239908 kb
Host smart-b0b508a7-6116-4d5c-88bd-b051a459f5a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498010502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.2498010502
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.3554564976
Short name T1190
Test name
Test status
Simulation time 448041838 ps
CPU time 8.05 seconds
Started Apr 28 02:03:13 PM PDT 24
Finished Apr 28 02:03:22 PM PDT 24
Peak memory 247968 kb
Host smart-5fb45702-be20-44ef-aaf2-a849a084ff9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554564976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.3554564976
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.847378196
Short name T136
Test name
Test status
Simulation time 313605759 ps
CPU time 6.87 seconds
Started Apr 28 02:03:13 PM PDT 24
Finished Apr 28 02:03:20 PM PDT 24
Peak memory 241404 kb
Host smart-2ecca887-68ef-43d3-a531-887b38b4b4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847378196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.847378196
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.21716381
Short name T204
Test name
Test status
Simulation time 4412221101 ps
CPU time 26.98 seconds
Started Apr 28 02:03:08 PM PDT 24
Finished Apr 28 02:03:36 PM PDT 24
Peak memory 241364 kb
Host smart-582a5ee8-f1fc-4309-91cb-bb7712fe17c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21716381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.21716381
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.3126887409
Short name T582
Test name
Test status
Simulation time 142867473 ps
CPU time 3.65 seconds
Started Apr 28 02:03:10 PM PDT 24
Finished Apr 28 02:03:14 PM PDT 24
Peak memory 241344 kb
Host smart-d766502e-f562-447d-9e50-5d2558e74a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126887409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.3126887409
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.1765307413
Short name T1039
Test name
Test status
Simulation time 2030135852 ps
CPU time 33.02 seconds
Started Apr 28 02:03:13 PM PDT 24
Finished Apr 28 02:03:46 PM PDT 24
Peak memory 248060 kb
Host smart-6f30940a-8a8f-4f6e-8b08-f7a8a0e90ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765307413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.1765307413
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.1472707400
Short name T1168
Test name
Test status
Simulation time 394407233 ps
CPU time 9 seconds
Started Apr 28 02:03:19 PM PDT 24
Finished Apr 28 02:03:29 PM PDT 24
Peak memory 247964 kb
Host smart-7460e9c7-39c8-4194-923b-2c691bfe02c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472707400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.1472707400
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.3894459570
Short name T624
Test name
Test status
Simulation time 339159712 ps
CPU time 9.45 seconds
Started Apr 28 02:03:19 PM PDT 24
Finished Apr 28 02:03:29 PM PDT 24
Peak memory 241192 kb
Host smart-6cf48927-8138-4f54-96dc-91f85d466a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894459570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3894459570
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.2165944029
Short name T807
Test name
Test status
Simulation time 632921387 ps
CPU time 5.31 seconds
Started Apr 28 02:03:07 PM PDT 24
Finished Apr 28 02:03:13 PM PDT 24
Peak memory 247316 kb
Host smart-35674add-4b24-4a70-9908-540fdfc52be7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165944029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.2165944029
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.1292968910
Short name T372
Test name
Test status
Simulation time 551431675 ps
CPU time 5.06 seconds
Started Apr 28 02:03:07 PM PDT 24
Finished Apr 28 02:03:12 PM PDT 24
Peak memory 241188 kb
Host smart-e0a8ddc7-dcd6-4de7-9d12-6bb1fd096aa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292968910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.1292968910
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.790481455
Short name T711
Test name
Test status
Simulation time 916724083 ps
CPU time 11.81 seconds
Started Apr 28 02:03:08 PM PDT 24
Finished Apr 28 02:03:21 PM PDT 24
Peak memory 241228 kb
Host smart-2c801975-16c6-4bd1-82b5-3eb8b4ad302c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790481455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.790481455
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.3367959050
Short name T548
Test name
Test status
Simulation time 15891235784 ps
CPU time 139.75 seconds
Started Apr 28 02:03:19 PM PDT 24
Finished Apr 28 02:05:39 PM PDT 24
Peak memory 241892 kb
Host smart-1157a50c-8516-446a-b3d1-db764042f78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367959050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.3367959050
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.2274429854
Short name T772
Test name
Test status
Simulation time 232633795 ps
CPU time 1.82 seconds
Started Apr 28 01:57:46 PM PDT 24
Finished Apr 28 01:57:48 PM PDT 24
Peak memory 239828 kb
Host smart-8f2b2f60-ff95-4151-872a-50ebd641e206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274429854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2274429854
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.963426692
Short name T893
Test name
Test status
Simulation time 1896659497 ps
CPU time 21.37 seconds
Started Apr 28 01:57:40 PM PDT 24
Finished Apr 28 01:58:02 PM PDT 24
Peak memory 241736 kb
Host smart-9b1b0379-2ff7-4027-ada3-e126684cb2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963426692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.963426692
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.1734247688
Short name T615
Test name
Test status
Simulation time 590797271 ps
CPU time 7.69 seconds
Started Apr 28 01:57:40 PM PDT 24
Finished Apr 28 01:57:49 PM PDT 24
Peak memory 247984 kb
Host smart-e38bd0c5-f128-4236-85e4-8c484da29bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734247688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.1734247688
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.1290397933
Short name T573
Test name
Test status
Simulation time 328731297 ps
CPU time 14.52 seconds
Started Apr 28 01:57:41 PM PDT 24
Finished Apr 28 01:57:56 PM PDT 24
Peak memory 241456 kb
Host smart-5324e112-7b9a-46a4-9711-9890d852d7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290397933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1290397933
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.2901625045
Short name T883
Test name
Test status
Simulation time 2502628213 ps
CPU time 24.76 seconds
Started Apr 28 01:57:43 PM PDT 24
Finished Apr 28 01:58:08 PM PDT 24
Peak memory 241424 kb
Host smart-ebc1cf24-cbe8-4d24-b165-ce740343853c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901625045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.2901625045
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.279485420
Short name T740
Test name
Test status
Simulation time 1439764665 ps
CPU time 3.64 seconds
Started Apr 28 01:57:40 PM PDT 24
Finished Apr 28 01:57:44 PM PDT 24
Peak memory 241384 kb
Host smart-6259fe15-18f8-450d-90c7-2098a5030995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279485420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.279485420
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.3518021422
Short name T1175
Test name
Test status
Simulation time 1708760485 ps
CPU time 24.57 seconds
Started Apr 28 01:57:41 PM PDT 24
Finished Apr 28 01:58:06 PM PDT 24
Peak memory 248084 kb
Host smart-0668e6b9-2774-488e-8106-0a6162132a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518021422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.3518021422
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.27331101
Short name T841
Test name
Test status
Simulation time 795160023 ps
CPU time 16.37 seconds
Started Apr 28 01:57:40 PM PDT 24
Finished Apr 28 01:57:57 PM PDT 24
Peak memory 241240 kb
Host smart-f28a510d-6b1f-4faf-8119-f96310ba1242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27331101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.27331101
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.3543145678
Short name T1073
Test name
Test status
Simulation time 2012910973 ps
CPU time 19.99 seconds
Started Apr 28 01:57:41 PM PDT 24
Finished Apr 28 01:58:02 PM PDT 24
Peak memory 241372 kb
Host smart-b998420e-6b24-4276-8693-12c72d04eaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543145678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.3543145678
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.795572966
Short name T469
Test name
Test status
Simulation time 646460703 ps
CPU time 22.74 seconds
Started Apr 28 01:57:40 PM PDT 24
Finished Apr 28 01:58:03 PM PDT 24
Peak memory 241644 kb
Host smart-c47d83d2-f59c-483e-84db-ffc20e4ef33e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795572966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.795572966
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.1591690342
Short name T110
Test name
Test status
Simulation time 170787421 ps
CPU time 4.69 seconds
Started Apr 28 01:57:40 PM PDT 24
Finished Apr 28 01:57:46 PM PDT 24
Peak memory 241156 kb
Host smart-ffc3d2ca-9642-4952-bb6c-48625c8a8802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591690342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.1591690342
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.676579425
Short name T613
Test name
Test status
Simulation time 1380141208 ps
CPU time 7.73 seconds
Started Apr 28 01:57:40 PM PDT 24
Finished Apr 28 01:57:49 PM PDT 24
Peak memory 247884 kb
Host smart-5fe8260a-a71b-458c-8176-2e8593eee2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676579425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.676579425
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.1007114880
Short name T930
Test name
Test status
Simulation time 18439885348 ps
CPU time 120.45 seconds
Started Apr 28 01:57:45 PM PDT 24
Finished Apr 28 01:59:45 PM PDT 24
Peak memory 243932 kb
Host smart-5b494127-ee12-446f-82ff-fb66001fedbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007114880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
1007114880
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.4030229963
Short name T276
Test name
Test status
Simulation time 456225627752 ps
CPU time 1406.62 seconds
Started Apr 28 01:57:41 PM PDT 24
Finished Apr 28 02:21:09 PM PDT 24
Peak memory 301644 kb
Host smart-d631d316-f7c8-4b11-8635-b0b46a38aa68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030229963 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.4030229963
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.1209582953
Short name T945
Test name
Test status
Simulation time 455909355 ps
CPU time 8.13 seconds
Started Apr 28 01:57:41 PM PDT 24
Finished Apr 28 01:57:50 PM PDT 24
Peak memory 241568 kb
Host smart-756580a5-8464-4885-a88b-56bf7e841c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209582953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.1209582953
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.4227928387
Short name T993
Test name
Test status
Simulation time 2345865952 ps
CPU time 4.79 seconds
Started Apr 28 02:03:19 PM PDT 24
Finished Apr 28 02:03:25 PM PDT 24
Peak memory 241884 kb
Host smart-754fd627-5629-4be1-a00d-93bafd581148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227928387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.4227928387
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.3412871469
Short name T264
Test name
Test status
Simulation time 500571120 ps
CPU time 7.56 seconds
Started Apr 28 02:03:18 PM PDT 24
Finished Apr 28 02:03:26 PM PDT 24
Peak memory 241260 kb
Host smart-31a19280-b380-438a-a0b5-f9af60844a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412871469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.3412871469
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.3803985242
Short name T890
Test name
Test status
Simulation time 83726305366 ps
CPU time 666.95 seconds
Started Apr 28 02:03:20 PM PDT 24
Finished Apr 28 02:14:28 PM PDT 24
Peak memory 277872 kb
Host smart-444754d8-03c9-4bef-b3a2-446a2041f733
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803985242 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.3803985242
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.414304551
Short name T113
Test name
Test status
Simulation time 256458187 ps
CPU time 3.61 seconds
Started Apr 28 02:03:20 PM PDT 24
Finished Apr 28 02:03:25 PM PDT 24
Peak memory 241396 kb
Host smart-72439b62-f16c-43cb-9ff8-d646ebd00dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414304551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.414304551
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.3001461240
Short name T450
Test name
Test status
Simulation time 144643759 ps
CPU time 5.32 seconds
Started Apr 28 02:03:05 PM PDT 24
Finished Apr 28 02:03:11 PM PDT 24
Peak memory 241572 kb
Host smart-b38b8575-e7ea-498e-ac42-4b3986eaf196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001461240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3001461240
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.1786775635
Short name T83
Test name
Test status
Simulation time 461967039 ps
CPU time 3.78 seconds
Started Apr 28 02:03:09 PM PDT 24
Finished Apr 28 02:03:14 PM PDT 24
Peak memory 241256 kb
Host smart-c9c4efe1-cde0-4f14-b9ff-839de49c4faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786775635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.1786775635
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.3078686556
Short name T715
Test name
Test status
Simulation time 686979764 ps
CPU time 5.63 seconds
Started Apr 28 02:03:19 PM PDT 24
Finished Apr 28 02:03:26 PM PDT 24
Peak memory 248028 kb
Host smart-7d705306-d9da-409e-ba10-ed0e37547729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078686556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.3078686556
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.3489763773
Short name T331
Test name
Test status
Simulation time 226053917918 ps
CPU time 2813.57 seconds
Started Apr 28 02:03:08 PM PDT 24
Finished Apr 28 02:50:03 PM PDT 24
Peak memory 532916 kb
Host smart-ae81d9a7-9162-4ef4-aa96-b6c8c7ce8c90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489763773 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.3489763773
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.502274741
Short name T737
Test name
Test status
Simulation time 249463974 ps
CPU time 3.44 seconds
Started Apr 28 02:03:11 PM PDT 24
Finished Apr 28 02:03:15 PM PDT 24
Peak memory 241312 kb
Host smart-6b7ab33f-1941-4ab2-90a0-379cec266b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502274741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.502274741
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.3217837669
Short name T851
Test name
Test status
Simulation time 632504686 ps
CPU time 7.94 seconds
Started Apr 28 02:03:12 PM PDT 24
Finished Apr 28 02:03:20 PM PDT 24
Peak memory 241204 kb
Host smart-e50c1bf1-9811-4f05-ae59-6844bae5f0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217837669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.3217837669
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.347920743
Short name T698
Test name
Test status
Simulation time 261127724 ps
CPU time 3.77 seconds
Started Apr 28 02:03:21 PM PDT 24
Finished Apr 28 02:03:25 PM PDT 24
Peak memory 241364 kb
Host smart-b3eafafe-b6a5-4e4a-83e0-74eb6ea667f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347920743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.347920743
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.593067962
Short name T295
Test name
Test status
Simulation time 257640909 ps
CPU time 6.45 seconds
Started Apr 28 02:03:13 PM PDT 24
Finished Apr 28 02:03:21 PM PDT 24
Peak memory 241324 kb
Host smart-d4e954a1-63fb-4438-9da5-9f93bba4af85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593067962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.593067962
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.316376219
Short name T899
Test name
Test status
Simulation time 494304927314 ps
CPU time 937.38 seconds
Started Apr 28 02:03:09 PM PDT 24
Finished Apr 28 02:18:47 PM PDT 24
Peak memory 394024 kb
Host smart-e0211044-e7a5-4a68-8b20-02f1bef2d42f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316376219 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.316376219
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.3819478089
Short name T1071
Test name
Test status
Simulation time 166238693 ps
CPU time 4.14 seconds
Started Apr 28 02:03:12 PM PDT 24
Finished Apr 28 02:03:17 PM PDT 24
Peak memory 241436 kb
Host smart-46724767-a016-4f2d-80a4-b594258b2141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819478089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.3819478089
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.1055467025
Short name T986
Test name
Test status
Simulation time 2594834938 ps
CPU time 8.49 seconds
Started Apr 28 02:03:13 PM PDT 24
Finished Apr 28 02:03:22 PM PDT 24
Peak memory 241784 kb
Host smart-f5551a41-47f5-4eaa-a54f-766e3319cd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055467025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.1055467025
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.3040744432
Short name T23
Test name
Test status
Simulation time 158361397416 ps
CPU time 1237.91 seconds
Started Apr 28 02:03:20 PM PDT 24
Finished Apr 28 02:23:59 PM PDT 24
Peak memory 296480 kb
Host smart-db61c776-4703-4c96-a016-a6dc3e44fa31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040744432 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.3040744432
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.2963350752
Short name T982
Test name
Test status
Simulation time 1526082556 ps
CPU time 4.49 seconds
Started Apr 28 02:03:20 PM PDT 24
Finished Apr 28 02:03:26 PM PDT 24
Peak memory 241328 kb
Host smart-d8fe746f-c1d0-43c2-a08a-2945a23b23fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963350752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.2963350752
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.3977628425
Short name T908
Test name
Test status
Simulation time 2030019098 ps
CPU time 6.07 seconds
Started Apr 28 02:03:14 PM PDT 24
Finished Apr 28 02:03:20 PM PDT 24
Peak memory 241120 kb
Host smart-a3223614-ac17-4970-bfac-7c1f3cae8a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977628425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.3977628425
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.3096195439
Short name T336
Test name
Test status
Simulation time 123629427805 ps
CPU time 1499.12 seconds
Started Apr 28 02:03:20 PM PDT 24
Finished Apr 28 02:28:21 PM PDT 24
Peak memory 266740 kb
Host smart-febe7139-8035-4a4b-b49f-9d85617de924
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096195439 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.3096195439
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.3047325752
Short name T879
Test name
Test status
Simulation time 172098959 ps
CPU time 3.84 seconds
Started Apr 28 02:03:13 PM PDT 24
Finished Apr 28 02:03:18 PM PDT 24
Peak memory 241728 kb
Host smart-ba8c75ba-f356-4001-9ef6-75c306d946c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047325752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.3047325752
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.3160137762
Short name T407
Test name
Test status
Simulation time 271432126 ps
CPU time 3.63 seconds
Started Apr 28 02:03:20 PM PDT 24
Finished Apr 28 02:03:24 PM PDT 24
Peak memory 241800 kb
Host smart-b51c0b89-1cb9-4b22-b382-00637209a3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160137762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.3160137762
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.2750093240
Short name T117
Test name
Test status
Simulation time 273487600268 ps
CPU time 1416.78 seconds
Started Apr 28 02:03:13 PM PDT 24
Finished Apr 28 02:26:51 PM PDT 24
Peak memory 433108 kb
Host smart-1caaaaf5-e38e-42cd-951c-659fdadf15a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750093240 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.2750093240
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.3371809397
Short name T1102
Test name
Test status
Simulation time 3703942836 ps
CPU time 11.26 seconds
Started Apr 28 02:03:13 PM PDT 24
Finished Apr 28 02:03:25 PM PDT 24
Peak memory 241392 kb
Host smart-0c1c0f59-97bd-49b8-bc15-0f07df49413b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371809397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.3371809397
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.991231398
Short name T1091
Test name
Test status
Simulation time 58826678614 ps
CPU time 792.88 seconds
Started Apr 28 02:03:18 PM PDT 24
Finished Apr 28 02:16:31 PM PDT 24
Peak memory 316060 kb
Host smart-2d3fb606-21cd-41cf-9c66-5adad6d5646d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991231398 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.991231398
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.1478143735
Short name T1080
Test name
Test status
Simulation time 2895956069 ps
CPU time 6.56 seconds
Started Apr 28 02:03:18 PM PDT 24
Finished Apr 28 02:03:26 PM PDT 24
Peak memory 241484 kb
Host smart-c5755c99-f6e3-4248-8aa5-3b38b2b88139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478143735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.1478143735
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.1348051461
Short name T936
Test name
Test status
Simulation time 186912786 ps
CPU time 6.13 seconds
Started Apr 28 02:03:26 PM PDT 24
Finished Apr 28 02:03:32 PM PDT 24
Peak memory 241412 kb
Host smart-ab197fc9-a7f9-4e5a-bb19-1c60f61f2439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348051461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.1348051461
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.2169516598
Short name T20
Test name
Test status
Simulation time 31504977630 ps
CPU time 783.02 seconds
Started Apr 28 02:03:18 PM PDT 24
Finished Apr 28 02:16:22 PM PDT 24
Peak memory 330140 kb
Host smart-d205364c-c7fd-4ba5-bd4c-825dcebc4609
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169516598 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.2169516598
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.1680102905
Short name T591
Test name
Test status
Simulation time 64678304 ps
CPU time 1.67 seconds
Started Apr 28 01:57:54 PM PDT 24
Finished Apr 28 01:57:56 PM PDT 24
Peak memory 239988 kb
Host smart-43645212-7859-40d1-be45-a0898cf96b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680102905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.1680102905
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.2044388615
Short name T437
Test name
Test status
Simulation time 939513490 ps
CPU time 8.19 seconds
Started Apr 28 01:57:44 PM PDT 24
Finished Apr 28 01:57:52 PM PDT 24
Peak memory 241388 kb
Host smart-b244fe9e-578d-46c9-9d77-e705b16704d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044388615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.2044388615
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.2903488219
Short name T849
Test name
Test status
Simulation time 436019256 ps
CPU time 9.87 seconds
Started Apr 28 01:57:50 PM PDT 24
Finished Apr 28 01:58:00 PM PDT 24
Peak memory 247988 kb
Host smart-5825bd68-003e-4efd-a276-1d089869ac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903488219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.2903488219
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.3684924667
Short name T666
Test name
Test status
Simulation time 351689183 ps
CPU time 18.91 seconds
Started Apr 28 01:57:44 PM PDT 24
Finished Apr 28 01:58:03 PM PDT 24
Peak memory 241260 kb
Host smart-e3875299-2db2-4562-bf32-5f80295b092b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684924667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.3684924667
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.2710967631
Short name T179
Test name
Test status
Simulation time 827830556 ps
CPU time 26.78 seconds
Started Apr 28 01:57:43 PM PDT 24
Finished Apr 28 01:58:10 PM PDT 24
Peak memory 241704 kb
Host smart-be79336d-efa3-4693-a3ef-4cb748bebcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710967631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.2710967631
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.2431042705
Short name T1151
Test name
Test status
Simulation time 191294015 ps
CPU time 3.28 seconds
Started Apr 28 01:57:46 PM PDT 24
Finished Apr 28 01:57:50 PM PDT 24
Peak memory 241264 kb
Host smart-ee2ec44e-42ea-4757-845f-9edb06b7a585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431042705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.2431042705
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.3247605697
Short name T1133
Test name
Test status
Simulation time 3334312247 ps
CPU time 35.46 seconds
Started Apr 28 01:57:54 PM PDT 24
Finished Apr 28 01:58:30 PM PDT 24
Peak memory 246864 kb
Host smart-6bb0f123-79f4-4410-8686-596b8c891c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247605697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.3247605697
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.1450282930
Short name T686
Test name
Test status
Simulation time 928480319 ps
CPU time 18.19 seconds
Started Apr 28 01:57:54 PM PDT 24
Finished Apr 28 01:58:13 PM PDT 24
Peak memory 241644 kb
Host smart-64dded6f-178e-4830-ac3c-62f4c039a99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450282930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.1450282930
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.3333909991
Short name T149
Test name
Test status
Simulation time 314866368 ps
CPU time 6.03 seconds
Started Apr 28 01:57:44 PM PDT 24
Finished Apr 28 01:57:51 PM PDT 24
Peak memory 241148 kb
Host smart-5fa718df-252f-4c85-b007-1b203460201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333909991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.3333909991
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.259513423
Short name T1014
Test name
Test status
Simulation time 632940647 ps
CPU time 5.37 seconds
Started Apr 28 01:57:44 PM PDT 24
Finished Apr 28 01:57:50 PM PDT 24
Peak memory 241152 kb
Host smart-65108c0f-d7e6-4a5f-a8ba-d3c5a92cd725
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=259513423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.259513423
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.1892610198
Short name T365
Test name
Test status
Simulation time 502695942 ps
CPU time 6.85 seconds
Started Apr 28 01:57:51 PM PDT 24
Finished Apr 28 01:57:58 PM PDT 24
Peak memory 248000 kb
Host smart-2914c23f-7be1-40d5-8efc-0727f6f9cc20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892610198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.1892610198
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.205459390
Short name T521
Test name
Test status
Simulation time 3617858416 ps
CPU time 9.24 seconds
Started Apr 28 01:57:43 PM PDT 24
Finished Apr 28 01:57:53 PM PDT 24
Peak memory 241700 kb
Host smart-d8492721-7956-45ab-b637-5a1bce77b328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205459390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.205459390
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.2671409103
Short name T605
Test name
Test status
Simulation time 7943851102 ps
CPU time 55.65 seconds
Started Apr 28 01:57:50 PM PDT 24
Finished Apr 28 01:58:46 PM PDT 24
Peak memory 245384 kb
Host smart-5c198b59-8d7a-42ce-9536-0347b6f449fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671409103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
2671409103
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.4095132340
Short name T1020
Test name
Test status
Simulation time 862768498 ps
CPU time 17.53 seconds
Started Apr 28 01:57:50 PM PDT 24
Finished Apr 28 01:58:08 PM PDT 24
Peak memory 241312 kb
Host smart-d64a33d8-2214-46d2-9830-8027b0d7da41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095132340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.4095132340
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.2873217354
Short name T634
Test name
Test status
Simulation time 160338413 ps
CPU time 3.14 seconds
Started Apr 28 02:03:18 PM PDT 24
Finished Apr 28 02:03:22 PM PDT 24
Peak memory 241344 kb
Host smart-62922c35-da6c-4403-99c9-b6cd6f967afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873217354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.2873217354
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.2360056040
Short name T2
Test name
Test status
Simulation time 437377737 ps
CPU time 9.5 seconds
Started Apr 28 02:03:18 PM PDT 24
Finished Apr 28 02:03:29 PM PDT 24
Peak memory 241724 kb
Host smart-1415e90a-9d2a-4ad6-91e7-d2d78e4c41e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360056040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.2360056040
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.1823031700
Short name T1036
Test name
Test status
Simulation time 25857407552 ps
CPU time 692.35 seconds
Started Apr 28 02:03:25 PM PDT 24
Finished Apr 28 02:14:58 PM PDT 24
Peak memory 260072 kb
Host smart-d594e0f7-5e03-4d54-8034-d7fe69bec4f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823031700 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.1823031700
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.355039866
Short name T506
Test name
Test status
Simulation time 204134107 ps
CPU time 3.36 seconds
Started Apr 28 02:03:22 PM PDT 24
Finished Apr 28 02:03:26 PM PDT 24
Peak memory 241632 kb
Host smart-f6b43853-2026-4f81-9a7f-a92268ed35b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355039866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.355039866
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.3433118202
Short name T542
Test name
Test status
Simulation time 99113545 ps
CPU time 3.57 seconds
Started Apr 28 02:03:24 PM PDT 24
Finished Apr 28 02:03:29 PM PDT 24
Peak memory 241392 kb
Host smart-bff0ced0-316a-468a-ab06-b819242e04c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433118202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3433118202
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.3660419964
Short name T278
Test name
Test status
Simulation time 66826579928 ps
CPU time 348.45 seconds
Started Apr 28 02:03:23 PM PDT 24
Finished Apr 28 02:09:12 PM PDT 24
Peak memory 269616 kb
Host smart-d4ee8eaa-00bb-4e97-a2e8-38579268ec7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660419964 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.3660419964
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.867392050
Short name T652
Test name
Test status
Simulation time 1554974068 ps
CPU time 4.5 seconds
Started Apr 28 02:03:24 PM PDT 24
Finished Apr 28 02:03:30 PM PDT 24
Peak memory 241736 kb
Host smart-88e5de13-5820-403f-9840-a035fb85b604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867392050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.867392050
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.336708993
Short name T540
Test name
Test status
Simulation time 193650513 ps
CPU time 4.46 seconds
Started Apr 28 02:03:29 PM PDT 24
Finished Apr 28 02:03:34 PM PDT 24
Peak memory 241116 kb
Host smart-624051a0-2e68-483b-ad8d-c8171c04ed84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336708993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.336708993
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.1686096144
Short name T396
Test name
Test status
Simulation time 97644510794 ps
CPU time 795.61 seconds
Started Apr 28 02:03:28 PM PDT 24
Finished Apr 28 02:16:44 PM PDT 24
Peak memory 289620 kb
Host smart-8b6406e2-f560-4697-95d7-caec5773423c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686096144 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.1686096144
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.3456936137
Short name T39
Test name
Test status
Simulation time 663175240 ps
CPU time 4.31 seconds
Started Apr 28 02:03:24 PM PDT 24
Finished Apr 28 02:03:28 PM PDT 24
Peak memory 241784 kb
Host smart-15140599-94bf-4480-bb69-e885e55eca5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456936137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.3456936137
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.3829257518
Short name T133
Test name
Test status
Simulation time 144148048 ps
CPU time 3.53 seconds
Started Apr 28 02:03:24 PM PDT 24
Finished Apr 28 02:03:28 PM PDT 24
Peak memory 241568 kb
Host smart-7f3920a4-190b-42a8-968a-3a3abde054ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829257518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.3829257518
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.2248272926
Short name T1146
Test name
Test status
Simulation time 25325083998 ps
CPU time 730.72 seconds
Started Apr 28 02:03:29 PM PDT 24
Finished Apr 28 02:15:40 PM PDT 24
Peak memory 248024 kb
Host smart-38704e7f-a8ea-432a-9eda-01dd05f913c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248272926 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.2248272926
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.1427387826
Short name T80
Test name
Test status
Simulation time 242368579 ps
CPU time 3.39 seconds
Started Apr 28 02:03:33 PM PDT 24
Finished Apr 28 02:03:37 PM PDT 24
Peak memory 241708 kb
Host smart-4bb13f46-dca9-4457-8221-673dd134b51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427387826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.1427387826
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.3957995724
Short name T1016
Test name
Test status
Simulation time 1919064879 ps
CPU time 8.44 seconds
Started Apr 28 02:03:30 PM PDT 24
Finished Apr 28 02:03:39 PM PDT 24
Peak memory 241112 kb
Host smart-fdc9a1c5-ca68-4933-8663-3401b24dfffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957995724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.3957995724
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.3007909908
Short name T925
Test name
Test status
Simulation time 87002557967 ps
CPU time 1089.21 seconds
Started Apr 28 02:03:34 PM PDT 24
Finished Apr 28 02:21:43 PM PDT 24
Peak memory 272792 kb
Host smart-d3157e4c-0cc8-4999-86d4-84623bbeb788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007909908 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.3007909908
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.2475385837
Short name T418
Test name
Test status
Simulation time 678518121 ps
CPU time 4.92 seconds
Started Apr 28 02:03:29 PM PDT 24
Finished Apr 28 02:03:35 PM PDT 24
Peak memory 241356 kb
Host smart-8cef9345-ca69-4210-92c2-22e5501ce274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475385837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.2475385837
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.2738476705
Short name T207
Test name
Test status
Simulation time 183854541 ps
CPU time 5.64 seconds
Started Apr 28 02:03:30 PM PDT 24
Finished Apr 28 02:03:36 PM PDT 24
Peak memory 241652 kb
Host smart-8da1cefd-54de-448f-88b7-3958cc0b9d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738476705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.2738476705
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.1850490209
Short name T69
Test name
Test status
Simulation time 166637762 ps
CPU time 5.07 seconds
Started Apr 28 02:03:29 PM PDT 24
Finished Apr 28 02:03:35 PM PDT 24
Peak memory 241328 kb
Host smart-177d1763-f121-46cf-b43d-bff630eff97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850490209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.1850490209
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.1132853976
Short name T462
Test name
Test status
Simulation time 251899417 ps
CPU time 5.44 seconds
Started Apr 28 02:03:29 PM PDT 24
Finished Apr 28 02:03:35 PM PDT 24
Peak memory 241156 kb
Host smart-c06ca72e-e3e6-4c8f-a398-cf8bdeee8180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132853976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.1132853976
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.3045376261
Short name T100
Test name
Test status
Simulation time 542249248510 ps
CPU time 2216.09 seconds
Started Apr 28 02:03:36 PM PDT 24
Finished Apr 28 02:40:33 PM PDT 24
Peak memory 392984 kb
Host smart-2690fe91-ac93-487b-bb1d-7e72acee71cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045376261 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.3045376261
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.2856941907
Short name T191
Test name
Test status
Simulation time 473954671 ps
CPU time 4.03 seconds
Started Apr 28 02:03:34 PM PDT 24
Finished Apr 28 02:03:39 PM PDT 24
Peak memory 241352 kb
Host smart-6cd33b17-5eaa-426a-b826-4c70c91ca756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856941907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.2856941907
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.2971334593
Short name T211
Test name
Test status
Simulation time 608143692 ps
CPU time 15.53 seconds
Started Apr 28 02:03:38 PM PDT 24
Finished Apr 28 02:03:54 PM PDT 24
Peak memory 241248 kb
Host smart-d64f9052-51f7-4dfe-9a76-d227e9c9b5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971334593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2971334593
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.326412930
Short name T1149
Test name
Test status
Simulation time 110048870 ps
CPU time 3.9 seconds
Started Apr 28 02:03:43 PM PDT 24
Finished Apr 28 02:03:47 PM PDT 24
Peak memory 241352 kb
Host smart-b4bd6a0a-6e43-4f1d-84b9-8e8c204aa2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326412930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.326412930
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.2076066720
Short name T1178
Test name
Test status
Simulation time 1887111768 ps
CPU time 7.36 seconds
Started Apr 28 02:03:51 PM PDT 24
Finished Apr 28 02:03:58 PM PDT 24
Peak memory 241792 kb
Host smart-561e41c2-f728-4cce-8011-f63a87ff002b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076066720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.2076066720
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.2184125442
Short name T1126
Test name
Test status
Simulation time 142831402 ps
CPU time 3.84 seconds
Started Apr 28 02:03:42 PM PDT 24
Finished Apr 28 02:03:46 PM PDT 24
Peak memory 241336 kb
Host smart-3415d7e0-c8c5-441e-955d-12d19c261ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184125442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.2184125442
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.3175516364
Short name T785
Test name
Test status
Simulation time 344011384 ps
CPU time 9.48 seconds
Started Apr 28 02:03:45 PM PDT 24
Finished Apr 28 02:03:55 PM PDT 24
Peak memory 241264 kb
Host smart-9b39187f-4d3a-4c38-b571-22578b39a6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175516364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.3175516364
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.3292513601
Short name T145
Test name
Test status
Simulation time 224982048857 ps
CPU time 3732 seconds
Started Apr 28 02:03:42 PM PDT 24
Finished Apr 28 03:05:55 PM PDT 24
Peak memory 654860 kb
Host smart-4dca1e8d-b237-4d24-9ca7-903ddb0e6270
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292513601 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.3292513601
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.315627247
Short name T465
Test name
Test status
Simulation time 148211863 ps
CPU time 2.2 seconds
Started Apr 28 01:58:11 PM PDT 24
Finished Apr 28 01:58:14 PM PDT 24
Peak memory 239800 kb
Host smart-7dda2b1f-683c-4f2e-93fb-af5c168dbf5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315627247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.315627247
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.650772469
Short name T796
Test name
Test status
Simulation time 6653474988 ps
CPU time 54.33 seconds
Started Apr 28 01:57:54 PM PDT 24
Finished Apr 28 01:58:49 PM PDT 24
Peak memory 242584 kb
Host smart-34c7bd0b-4cc2-4a1f-b73a-0e12d8c7ade1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650772469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.650772469
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.2102722243
Short name T126
Test name
Test status
Simulation time 931207168 ps
CPU time 20.1 seconds
Started Apr 28 01:57:55 PM PDT 24
Finished Apr 28 01:58:16 PM PDT 24
Peak memory 248036 kb
Host smart-19bc2c73-3d36-4109-9167-ce216617363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102722243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.2102722243
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.3116550522
Short name T241
Test name
Test status
Simulation time 10189532410 ps
CPU time 22.82 seconds
Started Apr 28 01:57:54 PM PDT 24
Finished Apr 28 01:58:18 PM PDT 24
Peak memory 241652 kb
Host smart-4775190c-15a4-4da1-b244-b46d4e750f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116550522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.3116550522
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.3949814847
Short name T929
Test name
Test status
Simulation time 617922447 ps
CPU time 13.8 seconds
Started Apr 28 01:57:53 PM PDT 24
Finished Apr 28 01:58:07 PM PDT 24
Peak memory 241792 kb
Host smart-cf1b3a58-9141-4662-a64f-8ce758c8f538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949814847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.3949814847
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.4200704279
Short name T1021
Test name
Test status
Simulation time 468046981 ps
CPU time 5.24 seconds
Started Apr 28 01:57:52 PM PDT 24
Finished Apr 28 01:57:57 PM PDT 24
Peak memory 241364 kb
Host smart-0368f0d9-d1e1-4516-a29e-04615673c01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200704279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.4200704279
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.1396229888
Short name T214
Test name
Test status
Simulation time 1182510385 ps
CPU time 17.65 seconds
Started Apr 28 01:57:53 PM PDT 24
Finished Apr 28 01:58:11 PM PDT 24
Peak memory 243068 kb
Host smart-a79ca27b-f4a4-476f-affe-b3d90b597537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396229888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.1396229888
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.2583029660
Short name T1156
Test name
Test status
Simulation time 772603871 ps
CPU time 5.67 seconds
Started Apr 28 01:57:52 PM PDT 24
Finished Apr 28 01:57:58 PM PDT 24
Peak memory 241368 kb
Host smart-53258ff0-93ae-4b4d-9ec6-02d901d8d15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583029660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.2583029660
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.2764672556
Short name T554
Test name
Test status
Simulation time 338850118 ps
CPU time 20.72 seconds
Started Apr 28 01:57:50 PM PDT 24
Finished Apr 28 01:58:11 PM PDT 24
Peak memory 241324 kb
Host smart-27b341dd-334b-4729-ba5f-6ba94e4ca9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764672556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.2764672556
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.474659991
Short name T186
Test name
Test status
Simulation time 339419125 ps
CPU time 10.62 seconds
Started Apr 28 01:58:01 PM PDT 24
Finished Apr 28 01:58:12 PM PDT 24
Peak memory 241336 kb
Host smart-32f0773b-be83-42c3-a52c-5042f20b9206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474659991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.474659991
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.3845377158
Short name T648
Test name
Test status
Simulation time 550424231 ps
CPU time 10.09 seconds
Started Apr 28 01:57:54 PM PDT 24
Finished Apr 28 01:58:04 PM PDT 24
Peak memory 241328 kb
Host smart-03ed71a4-27a2-4555-8417-0acb7e6f080a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3845377158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.3845377158
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.2653049599
Short name T429
Test name
Test status
Simulation time 442175171 ps
CPU time 6.33 seconds
Started Apr 28 01:57:50 PM PDT 24
Finished Apr 28 01:57:57 PM PDT 24
Peak memory 241620 kb
Host smart-0cca99a7-c879-4a00-90fa-cc7c8eb29390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653049599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.2653049599
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.932833495
Short name T1058
Test name
Test status
Simulation time 4372619167 ps
CPU time 31.72 seconds
Started Apr 28 01:58:01 PM PDT 24
Finished Apr 28 01:58:33 PM PDT 24
Peak memory 243064 kb
Host smart-5d35ca97-4947-4bc8-9aae-f20a60840947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932833495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.932833495
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.1317239596
Short name T394
Test name
Test status
Simulation time 64925239425 ps
CPU time 397.75 seconds
Started Apr 28 01:58:09 PM PDT 24
Finished Apr 28 02:04:47 PM PDT 24
Peak memory 275100 kb
Host smart-252596f9-9084-45de-874c-9b2d8aeb0578
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317239596 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.1317239596
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.4017879500
Short name T661
Test name
Test status
Simulation time 167603924 ps
CPU time 6.39 seconds
Started Apr 28 01:57:52 PM PDT 24
Finished Apr 28 01:57:59 PM PDT 24
Peak memory 241320 kb
Host smart-090538bf-40d8-47d9-90c8-5afb7138906a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017879500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.4017879500
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.1236235293
Short name T989
Test name
Test status
Simulation time 146142625 ps
CPU time 3.81 seconds
Started Apr 28 02:03:41 PM PDT 24
Finished Apr 28 02:03:45 PM PDT 24
Peak memory 241756 kb
Host smart-73645345-0b45-432d-bc78-a1e882dcf5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236235293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.1236235293
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.2749416776
Short name T1046
Test name
Test status
Simulation time 4306008543 ps
CPU time 23.69 seconds
Started Apr 28 02:03:40 PM PDT 24
Finished Apr 28 02:04:04 PM PDT 24
Peak memory 241432 kb
Host smart-8e837716-ddaa-4f54-a026-92cc6a0199d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749416776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.2749416776
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.2282980294
Short name T172
Test name
Test status
Simulation time 262388851 ps
CPU time 3.62 seconds
Started Apr 28 02:03:43 PM PDT 24
Finished Apr 28 02:03:47 PM PDT 24
Peak memory 241276 kb
Host smart-e213f9f8-70ef-45bf-b4be-0311e0493076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282980294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.2282980294
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.2370646552
Short name T1128
Test name
Test status
Simulation time 1924389052 ps
CPU time 21.71 seconds
Started Apr 28 02:03:44 PM PDT 24
Finished Apr 28 02:04:06 PM PDT 24
Peak memory 241732 kb
Host smart-a43d0a25-52d5-4cf2-9e07-4e18bd5eb1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370646552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2370646552
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.4254892175
Short name T286
Test name
Test status
Simulation time 198891043346 ps
CPU time 1973.33 seconds
Started Apr 28 02:03:41 PM PDT 24
Finished Apr 28 02:36:35 PM PDT 24
Peak memory 440904 kb
Host smart-b1999213-1288-4eeb-851f-9b7325ff0cb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254892175 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.4254892175
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.1324352595
Short name T910
Test name
Test status
Simulation time 150720195 ps
CPU time 4.26 seconds
Started Apr 28 02:03:45 PM PDT 24
Finished Apr 28 02:03:50 PM PDT 24
Peak memory 241632 kb
Host smart-d16cb1e3-c1ea-4bbf-a1b5-2eea8e092a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324352595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.1324352595
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.2530757261
Short name T127
Test name
Test status
Simulation time 330309203 ps
CPU time 6.42 seconds
Started Apr 28 02:03:54 PM PDT 24
Finished Apr 28 02:04:01 PM PDT 24
Peak memory 241428 kb
Host smart-9e067b3d-0526-4203-9f7a-6f7d33d9d9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530757261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.2530757261
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.2186646206
Short name T251
Test name
Test status
Simulation time 1111879363666 ps
CPU time 2186.64 seconds
Started Apr 28 02:03:46 PM PDT 24
Finished Apr 28 02:40:14 PM PDT 24
Peak memory 395588 kb
Host smart-f3cc2d26-d7c2-4984-be22-acb7445a9526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186646206 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.2186646206
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.627725187
Short name T817
Test name
Test status
Simulation time 199842709 ps
CPU time 3.78 seconds
Started Apr 28 02:03:45 PM PDT 24
Finished Apr 28 02:03:49 PM PDT 24
Peak memory 241752 kb
Host smart-e56d7eba-cccc-4973-9d69-26ab3baf5ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627725187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.627725187
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.3314819990
Short name T762
Test name
Test status
Simulation time 2192480056 ps
CPU time 6.29 seconds
Started Apr 28 02:03:54 PM PDT 24
Finished Apr 28 02:04:01 PM PDT 24
Peak memory 241452 kb
Host smart-5a8c125a-3024-4065-91e7-570a6f0ca7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314819990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.3314819990
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.2005477435
Short name T1122
Test name
Test status
Simulation time 109394989246 ps
CPU time 2018 seconds
Started Apr 28 02:03:45 PM PDT 24
Finished Apr 28 02:37:24 PM PDT 24
Peak memory 272484 kb
Host smart-131ed5ce-4c39-4408-b6ad-105445db98ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005477435 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.2005477435
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.585365756
Short name T855
Test name
Test status
Simulation time 143856928 ps
CPU time 3.95 seconds
Started Apr 28 02:03:54 PM PDT 24
Finished Apr 28 02:03:58 PM PDT 24
Peak memory 241284 kb
Host smart-3ac731a5-fc17-49a3-a666-0a53d87a6f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585365756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.585365756
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.1354531971
Short name T1005
Test name
Test status
Simulation time 728596610 ps
CPU time 8.98 seconds
Started Apr 28 02:03:49 PM PDT 24
Finished Apr 28 02:03:58 PM PDT 24
Peak memory 241288 kb
Host smart-0db0a09b-9b35-4b23-86a0-a05484e59ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354531971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1354531971
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.3829918041
Short name T453
Test name
Test status
Simulation time 28492994356 ps
CPU time 653.25 seconds
Started Apr 28 02:03:46 PM PDT 24
Finished Apr 28 02:14:40 PM PDT 24
Peak memory 257468 kb
Host smart-b08cc75f-a4d7-42ae-805b-69e2b60a1be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829918041 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.3829918041
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.3968066864
Short name T433
Test name
Test status
Simulation time 637148887 ps
CPU time 5.01 seconds
Started Apr 28 02:03:49 PM PDT 24
Finished Apr 28 02:03:54 PM PDT 24
Peak memory 241684 kb
Host smart-5f3cb22c-f03b-4e46-b31d-afaae83cac06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968066864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3968066864
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.390771634
Short name T691
Test name
Test status
Simulation time 166569997 ps
CPU time 4.35 seconds
Started Apr 28 02:03:47 PM PDT 24
Finished Apr 28 02:03:51 PM PDT 24
Peak memory 241428 kb
Host smart-007f2bbe-17fb-40bf-a1d9-adf5b4aab136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390771634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.390771634
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.2209556156
Short name T574
Test name
Test status
Simulation time 611393317 ps
CPU time 4.1 seconds
Started Apr 28 02:03:52 PM PDT 24
Finished Apr 28 02:03:56 PM PDT 24
Peak memory 241636 kb
Host smart-ec55f5fb-75ba-4905-be2c-bd63b1551ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209556156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.2209556156
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.912597376
Short name T923
Test name
Test status
Simulation time 241188301 ps
CPU time 6.49 seconds
Started Apr 28 02:03:53 PM PDT 24
Finished Apr 28 02:04:00 PM PDT 24
Peak memory 241344 kb
Host smart-b47fa06c-4547-41a2-bb99-0146ebd862ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912597376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.912597376
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.2644530992
Short name T275
Test name
Test status
Simulation time 41372019816 ps
CPU time 843.62 seconds
Started Apr 28 02:03:54 PM PDT 24
Finished Apr 28 02:17:58 PM PDT 24
Peak memory 325908 kb
Host smart-e995c57d-24b5-43e6-89d5-1f2849a7830a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644530992 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.2644530992
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.460431617
Short name T443
Test name
Test status
Simulation time 260969574 ps
CPU time 5.11 seconds
Started Apr 28 02:03:51 PM PDT 24
Finished Apr 28 02:03:56 PM PDT 24
Peak memory 241696 kb
Host smart-5abf6740-90ee-4cff-bcc2-7d3cdd06c1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460431617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.460431617
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.1047823095
Short name T152
Test name
Test status
Simulation time 479735504 ps
CPU time 12.08 seconds
Started Apr 28 02:03:51 PM PDT 24
Finished Apr 28 02:04:03 PM PDT 24
Peak memory 242008 kb
Host smart-3121c676-ddaf-44b1-a9a2-6563426ecb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047823095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.1047823095
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.3075493495
Short name T1027
Test name
Test status
Simulation time 790594268917 ps
CPU time 1640.94 seconds
Started Apr 28 02:03:55 PM PDT 24
Finished Apr 28 02:31:17 PM PDT 24
Peak memory 469328 kb
Host smart-5419d897-1e5a-421c-a7ed-7b9c852bbf2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075493495 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.3075493495
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.834922182
Short name T836
Test name
Test status
Simulation time 107961669 ps
CPU time 2.96 seconds
Started Apr 28 02:03:54 PM PDT 24
Finished Apr 28 02:03:57 PM PDT 24
Peak memory 241372 kb
Host smart-394be636-3bed-4d0f-bc23-159bca49cf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834922182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.834922182
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.3543553246
Short name T689
Test name
Test status
Simulation time 414585536 ps
CPU time 9.44 seconds
Started Apr 28 02:03:51 PM PDT 24
Finished Apr 28 02:04:01 PM PDT 24
Peak memory 241280 kb
Host smart-0b1d2c90-2ae0-442b-9bfd-b99ac50dd2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543553246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.3543553246
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.2361059281
Short name T334
Test name
Test status
Simulation time 58954461449 ps
CPU time 1185.69 seconds
Started Apr 28 02:03:53 PM PDT 24
Finished Apr 28 02:23:39 PM PDT 24
Peak memory 292532 kb
Host smart-71b873dc-571d-4007-8f57-5a89cd2c4436
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361059281 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.2361059281
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.902895135
Short name T192
Test name
Test status
Simulation time 166980945 ps
CPU time 3.79 seconds
Started Apr 28 02:03:52 PM PDT 24
Finished Apr 28 02:03:57 PM PDT 24
Peak memory 241408 kb
Host smart-2d572972-1da4-43c3-b626-074de015efe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902895135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.902895135
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.3664468921
Short name T738
Test name
Test status
Simulation time 4938457928 ps
CPU time 25.42 seconds
Started Apr 28 02:03:59 PM PDT 24
Finished Apr 28 02:04:25 PM PDT 24
Peak memory 241244 kb
Host smart-886cefb0-d44a-407d-99f1-2656b862cb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664468921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.3664468921
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2555539659
Short name T482
Test name
Test status
Simulation time 57979196038 ps
CPU time 417.57 seconds
Started Apr 28 02:03:59 PM PDT 24
Finished Apr 28 02:10:57 PM PDT 24
Peak memory 264560 kb
Host smart-a6992e07-1b22-4d26-b059-65f7e128512b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555539659 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.2555539659
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.950718982
Short name T512
Test name
Test status
Simulation time 68555930 ps
CPU time 2.02 seconds
Started Apr 28 01:58:10 PM PDT 24
Finished Apr 28 01:58:13 PM PDT 24
Peak memory 239920 kb
Host smart-c944c57d-610f-451b-a26f-64e232e6cc13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950718982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.950718982
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.2796614450
Short name T89
Test name
Test status
Simulation time 3600279832 ps
CPU time 37.63 seconds
Started Apr 28 01:58:04 PM PDT 24
Finished Apr 28 01:58:42 PM PDT 24
Peak memory 241596 kb
Host smart-17e838d5-7266-4395-bda3-c9951fc1413f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796614450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2796614450
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.3315515182
Short name T98
Test name
Test status
Simulation time 491967182 ps
CPU time 16.67 seconds
Started Apr 28 01:58:03 PM PDT 24
Finished Apr 28 01:58:20 PM PDT 24
Peak memory 241080 kb
Host smart-16f886d2-1338-4305-938b-1bd57e680c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315515182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.3315515182
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.4089074286
Short name T544
Test name
Test status
Simulation time 720090582 ps
CPU time 8.35 seconds
Started Apr 28 01:58:04 PM PDT 24
Finished Apr 28 01:58:13 PM PDT 24
Peak memory 241272 kb
Host smart-2faed994-4fb7-4733-be55-4999f3ef9258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089074286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.4089074286
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.3514325267
Short name T171
Test name
Test status
Simulation time 303388406 ps
CPU time 3.21 seconds
Started Apr 28 01:58:00 PM PDT 24
Finished Apr 28 01:58:03 PM PDT 24
Peak memory 241720 kb
Host smart-5daf8d46-2649-4f6e-875a-b8989df9d6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514325267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.3514325267
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.443500043
Short name T892
Test name
Test status
Simulation time 8909602129 ps
CPU time 8.85 seconds
Started Apr 28 01:58:12 PM PDT 24
Finished Apr 28 01:58:21 PM PDT 24
Peak memory 241828 kb
Host smart-d7a3d588-4957-42b3-bf64-7042ac484667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443500043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.443500043
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.3992453622
Short name T845
Test name
Test status
Simulation time 4396366568 ps
CPU time 26.33 seconds
Started Apr 28 01:58:08 PM PDT 24
Finished Apr 28 01:58:34 PM PDT 24
Peak memory 241704 kb
Host smart-10139abe-77a7-4d85-9a0a-3c532524254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992453622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.3992453622
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.2887209745
Short name T663
Test name
Test status
Simulation time 456502960 ps
CPU time 9.57 seconds
Started Apr 28 01:58:03 PM PDT 24
Finished Apr 28 01:58:13 PM PDT 24
Peak memory 241344 kb
Host smart-1ad99215-38fa-4417-9e06-6f7f3219934b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887209745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.2887209745
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.169363289
Short name T811
Test name
Test status
Simulation time 4052412997 ps
CPU time 10.89 seconds
Started Apr 28 01:57:58 PM PDT 24
Finished Apr 28 01:58:09 PM PDT 24
Peak memory 248040 kb
Host smart-edabaa39-e27a-492f-b09a-691479f9349a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169363289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.169363289
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.221582252
Short name T1171
Test name
Test status
Simulation time 24435390618 ps
CPU time 181.1 seconds
Started Apr 28 01:58:14 PM PDT 24
Finished Apr 28 02:01:16 PM PDT 24
Peak memory 259312 kb
Host smart-7d39b120-c0a0-4fb3-b2cf-62dfa079061b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221582252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.221582252
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.22030033
Short name T279
Test name
Test status
Simulation time 89459741080 ps
CPU time 1049.84 seconds
Started Apr 28 01:58:12 PM PDT 24
Finished Apr 28 02:15:42 PM PDT 24
Peak memory 313352 kb
Host smart-2169f892-d094-457a-90a4-9e2f90f24265
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22030033 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.22030033
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.1235719763
Short name T439
Test name
Test status
Simulation time 10855695668 ps
CPU time 20.72 seconds
Started Apr 28 01:58:07 PM PDT 24
Finished Apr 28 01:58:28 PM PDT 24
Peak memory 242008 kb
Host smart-5f284b74-9627-48ee-ae4c-e9d2d2140d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235719763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.1235719763
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.2613156053
Short name T183
Test name
Test status
Simulation time 177747858 ps
CPU time 4.12 seconds
Started Apr 28 02:03:57 PM PDT 24
Finished Apr 28 02:04:01 PM PDT 24
Peak memory 241288 kb
Host smart-2dc10911-41af-4f2b-8ef8-ff7bceb49ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613156053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.2613156053
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.3805960820
Short name T397
Test name
Test status
Simulation time 205140441 ps
CPU time 8.82 seconds
Started Apr 28 02:04:00 PM PDT 24
Finished Apr 28 02:04:09 PM PDT 24
Peak memory 241652 kb
Host smart-f003d6e2-874c-42e2-870d-cae08fad9a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805960820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.3805960820
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.3643770521
Short name T282
Test name
Test status
Simulation time 192899266318 ps
CPU time 509.2 seconds
Started Apr 28 02:04:01 PM PDT 24
Finished Apr 28 02:12:30 PM PDT 24
Peak memory 304996 kb
Host smart-670fed06-6614-44c3-bdae-46ec10db6d68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643770521 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.3643770521
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.114289828
Short name T1112
Test name
Test status
Simulation time 326048653 ps
CPU time 4.75 seconds
Started Apr 28 02:03:58 PM PDT 24
Finished Apr 28 02:04:03 PM PDT 24
Peak memory 241716 kb
Host smart-9c250c95-3232-4d31-bbd5-72476a3f692d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114289828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.114289828
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.3747245756
Short name T878
Test name
Test status
Simulation time 345333379 ps
CPU time 8.95 seconds
Started Apr 28 02:03:58 PM PDT 24
Finished Apr 28 02:04:07 PM PDT 24
Peak memory 241224 kb
Host smart-d980dce4-67fd-42f7-bbe8-f8a79e3953e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747245756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.3747245756
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.3070782723
Short name T338
Test name
Test status
Simulation time 91282379507 ps
CPU time 1725.31 seconds
Started Apr 28 02:04:02 PM PDT 24
Finished Apr 28 02:32:48 PM PDT 24
Peak memory 554880 kb
Host smart-c2c72333-baad-4a51-8ce3-9c64f456bb49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070782723 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.3070782723
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.846860023
Short name T656
Test name
Test status
Simulation time 580215140 ps
CPU time 4.46 seconds
Started Apr 28 02:04:02 PM PDT 24
Finished Apr 28 02:04:07 PM PDT 24
Peak memory 241700 kb
Host smart-baeed525-f027-4a0b-9cc4-c23a6afcaa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846860023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.846860023
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.181038396
Short name T420
Test name
Test status
Simulation time 2489113899 ps
CPU time 5.24 seconds
Started Apr 28 02:03:59 PM PDT 24
Finished Apr 28 02:04:05 PM PDT 24
Peak memory 241768 kb
Host smart-4d05c065-13ce-48ce-b434-4da00c883aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181038396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.181038396
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.3115656793
Short name T1048
Test name
Test status
Simulation time 194832467 ps
CPU time 4.82 seconds
Started Apr 28 02:03:59 PM PDT 24
Finished Apr 28 02:04:05 PM PDT 24
Peak memory 241192 kb
Host smart-d5ff81f9-94c8-4fab-92c3-9128a6b36d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115656793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3115656793
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.243635729
Short name T616
Test name
Test status
Simulation time 624301490075 ps
CPU time 1325.78 seconds
Started Apr 28 02:03:58 PM PDT 24
Finished Apr 28 02:26:05 PM PDT 24
Peak memory 329276 kb
Host smart-dee680c7-42c5-4e31-897c-2917d778a5c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243635729 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.243635729
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.3854649377
Short name T872
Test name
Test status
Simulation time 302477626 ps
CPU time 4.49 seconds
Started Apr 28 02:03:58 PM PDT 24
Finished Apr 28 02:04:02 PM PDT 24
Peak memory 241328 kb
Host smart-6827dc65-9bd8-4870-ab16-764777422e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854649377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.3854649377
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.3565282646
Short name T427
Test name
Test status
Simulation time 409239174 ps
CPU time 5.66 seconds
Started Apr 28 02:04:01 PM PDT 24
Finished Apr 28 02:04:07 PM PDT 24
Peak memory 241396 kb
Host smart-6a47a014-223d-44f4-8e0e-f0169a5bba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565282646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3565282646
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.26167563
Short name T339
Test name
Test status
Simulation time 447588117696 ps
CPU time 764.37 seconds
Started Apr 28 02:03:57 PM PDT 24
Finished Apr 28 02:16:42 PM PDT 24
Peak memory 293424 kb
Host smart-8b1925fa-d808-4b36-bdee-a10beb86728c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26167563 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.26167563
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.2942351018
Short name T739
Test name
Test status
Simulation time 2123742207 ps
CPU time 4.45 seconds
Started Apr 28 02:04:02 PM PDT 24
Finished Apr 28 02:04:07 PM PDT 24
Peak memory 241372 kb
Host smart-777c2695-987c-49b3-bdeb-d1af3c80db6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942351018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2942351018
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.3859190525
Short name T101
Test name
Test status
Simulation time 222081183 ps
CPU time 5.13 seconds
Started Apr 28 02:03:58 PM PDT 24
Finished Apr 28 02:04:04 PM PDT 24
Peak memory 241380 kb
Host smart-934fac02-c1fb-4da4-98c5-e926fadb1baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859190525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.3859190525
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.1062415087
Short name T254
Test name
Test status
Simulation time 11612333361 ps
CPU time 153.14 seconds
Started Apr 28 02:04:04 PM PDT 24
Finished Apr 28 02:06:38 PM PDT 24
Peak memory 256760 kb
Host smart-1ba194a5-603b-45bf-a77d-f5a8c21c9a6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062415087 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.1062415087
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.1873372764
Short name T682
Test name
Test status
Simulation time 1591247290 ps
CPU time 4.24 seconds
Started Apr 28 02:04:03 PM PDT 24
Finished Apr 28 02:04:08 PM PDT 24
Peak memory 241364 kb
Host smart-921a7ff3-4c5d-4834-9f42-a39186f0ea98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873372764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.1873372764
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.3582355775
Short name T5
Test name
Test status
Simulation time 344936426 ps
CPU time 9.3 seconds
Started Apr 28 02:04:03 PM PDT 24
Finished Apr 28 02:04:12 PM PDT 24
Peak memory 241532 kb
Host smart-48b9c6d5-461a-4cc4-a9b6-82cfd0e2c436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582355775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.3582355775
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.1777018318
Short name T971
Test name
Test status
Simulation time 27851629440 ps
CPU time 374.78 seconds
Started Apr 28 02:04:03 PM PDT 24
Finished Apr 28 02:10:18 PM PDT 24
Peak memory 256368 kb
Host smart-116c18d1-80f3-4123-8149-29576ac1511c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777018318 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.1777018318
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.948388416
Short name T1079
Test name
Test status
Simulation time 154874083 ps
CPU time 3.72 seconds
Started Apr 28 02:04:09 PM PDT 24
Finished Apr 28 02:04:13 PM PDT 24
Peak memory 241328 kb
Host smart-4f4fa56a-ee7d-4ab8-869e-21d55028cf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948388416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.948388416
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.1780807724
Short name T801
Test name
Test status
Simulation time 876730477 ps
CPU time 12.22 seconds
Started Apr 28 02:04:05 PM PDT 24
Finished Apr 28 02:04:17 PM PDT 24
Peak memory 241684 kb
Host smart-18318d51-760c-4c7d-9d2c-fcfdc68b7c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780807724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.1780807724
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.3034006555
Short name T255
Test name
Test status
Simulation time 165161370172 ps
CPU time 3840.56 seconds
Started Apr 28 02:04:05 PM PDT 24
Finished Apr 28 03:08:07 PM PDT 24
Peak memory 307784 kb
Host smart-6d17215a-92b7-4a01-98c8-c4eb57175f57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034006555 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.3034006555
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.3213921938
Short name T814
Test name
Test status
Simulation time 450689389 ps
CPU time 4.28 seconds
Started Apr 28 02:04:09 PM PDT 24
Finished Apr 28 02:04:14 PM PDT 24
Peak memory 241500 kb
Host smart-2690b39d-aeac-4e9c-b086-ca46bac11251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213921938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.3213921938
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.1320990996
Short name T140
Test name
Test status
Simulation time 266348769 ps
CPU time 6.81 seconds
Started Apr 28 02:04:02 PM PDT 24
Finished Apr 28 02:04:10 PM PDT 24
Peak memory 241456 kb
Host smart-45396fa8-a8c6-4364-ba7a-a6ed5900606b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320990996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.1320990996
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.4139786160
Short name T340
Test name
Test status
Simulation time 329959741005 ps
CPU time 783.5 seconds
Started Apr 28 02:04:04 PM PDT 24
Finished Apr 28 02:17:08 PM PDT 24
Peak memory 354852 kb
Host smart-c49c9deb-be05-4b79-b8b5-48b4a7167f31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139786160 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.4139786160
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.2778704391
Short name T597
Test name
Test status
Simulation time 546553567 ps
CPU time 4.68 seconds
Started Apr 28 02:04:04 PM PDT 24
Finished Apr 28 02:04:09 PM PDT 24
Peak memory 241260 kb
Host smart-f61f28e6-2377-4dcb-8c00-03e898b8479f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778704391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.2778704391
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.1630282482
Short name T850
Test name
Test status
Simulation time 2949222026 ps
CPU time 21.87 seconds
Started Apr 28 02:04:03 PM PDT 24
Finished Apr 28 02:04:25 PM PDT 24
Peak memory 241560 kb
Host smart-55b36fc2-1326-486e-b1ca-49266dfaddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630282482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.1630282482
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.1098783729
Short name T1116
Test name
Test status
Simulation time 117823089 ps
CPU time 2.01 seconds
Started Apr 28 01:58:22 PM PDT 24
Finished Apr 28 01:58:24 PM PDT 24
Peak memory 239816 kb
Host smart-b2bf06e9-2a23-47e4-8e54-3cb907dffeff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098783729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.1098783729
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.3507080180
Short name T576
Test name
Test status
Simulation time 989238958 ps
CPU time 6.33 seconds
Started Apr 28 01:58:14 PM PDT 24
Finished Apr 28 01:58:20 PM PDT 24
Peak memory 241752 kb
Host smart-291c90ab-1a3e-46b6-9af3-6f577e58e4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507080180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.3507080180
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.2312072448
Short name T118
Test name
Test status
Simulation time 13990039412 ps
CPU time 25.94 seconds
Started Apr 28 01:58:21 PM PDT 24
Finished Apr 28 01:58:47 PM PDT 24
Peak memory 241912 kb
Host smart-df1ebc65-27f3-4236-86a3-882b19cdb598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312072448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2312072448
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.1865399868
Short name T456
Test name
Test status
Simulation time 933602894 ps
CPU time 32.23 seconds
Started Apr 28 01:58:18 PM PDT 24
Finished Apr 28 01:58:51 PM PDT 24
Peak memory 242424 kb
Host smart-26553e33-8bd8-4239-9e03-e560a7450737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865399868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.1865399868
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.694925784
Short name T111
Test name
Test status
Simulation time 934401495 ps
CPU time 18.01 seconds
Started Apr 28 01:58:15 PM PDT 24
Finished Apr 28 01:58:34 PM PDT 24
Peak memory 241600 kb
Host smart-da4fbf85-f1dd-4597-9fcf-236666220cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694925784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.694925784
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.3858219938
Short name T190
Test name
Test status
Simulation time 103806922 ps
CPU time 3.28 seconds
Started Apr 28 01:58:13 PM PDT 24
Finished Apr 28 01:58:17 PM PDT 24
Peak memory 241644 kb
Host smart-ccb318ca-1230-4463-965a-0b126759be02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858219938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.3858219938
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.3141936162
Short name T1066
Test name
Test status
Simulation time 1010964589 ps
CPU time 25.09 seconds
Started Apr 28 01:58:17 PM PDT 24
Finished Apr 28 01:58:43 PM PDT 24
Peak memory 241692 kb
Host smart-c70123a8-ed30-4319-b144-4cd597a3d9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141936162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.3141936162
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.1143434550
Short name T868
Test name
Test status
Simulation time 2426517683 ps
CPU time 16.77 seconds
Started Apr 28 01:58:17 PM PDT 24
Finished Apr 28 01:58:35 PM PDT 24
Peak memory 241332 kb
Host smart-7562f677-01c6-4412-b068-31b06dc03f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143434550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.1143434550
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.2075186862
Short name T1152
Test name
Test status
Simulation time 2174947510 ps
CPU time 27.86 seconds
Started Apr 28 01:58:13 PM PDT 24
Finished Apr 28 01:58:41 PM PDT 24
Peak memory 241876 kb
Host smart-06c7181a-d9f0-4872-b629-b25531c10823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075186862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.2075186862
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.3473592963
Short name T458
Test name
Test status
Simulation time 522250053 ps
CPU time 13.62 seconds
Started Apr 28 01:58:11 PM PDT 24
Finished Apr 28 01:58:25 PM PDT 24
Peak memory 241300 kb
Host smart-71e92526-947d-4340-b7a4-2f6b3e6f8f18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3473592963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3473592963
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.878486905
Short name T1024
Test name
Test status
Simulation time 4129422760 ps
CPU time 10.31 seconds
Started Apr 28 01:58:18 PM PDT 24
Finished Apr 28 01:58:29 PM PDT 24
Peak memory 241780 kb
Host smart-ef947b76-dc60-40ab-a997-31acd6c9e382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=878486905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.878486905
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.930610985
Short name T1003
Test name
Test status
Simulation time 1046441184 ps
CPU time 11.48 seconds
Started Apr 28 01:58:13 PM PDT 24
Finished Apr 28 01:58:25 PM PDT 24
Peak memory 241572 kb
Host smart-d18695d5-fcb1-4317-a1c0-bc4732befc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930610985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.930610985
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.1695477505
Short name T281
Test name
Test status
Simulation time 8079947462 ps
CPU time 137.31 seconds
Started Apr 28 01:58:23 PM PDT 24
Finished Apr 28 02:00:41 PM PDT 24
Peak memory 256348 kb
Host smart-426d53bc-1b12-483f-aaf6-ab3704c94020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695477505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
1695477505
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.3687042841
Short name T259
Test name
Test status
Simulation time 73507210867 ps
CPU time 627.17 seconds
Started Apr 28 01:58:21 PM PDT 24
Finished Apr 28 02:08:49 PM PDT 24
Peak memory 292812 kb
Host smart-154fae03-524e-4f9b-a8e9-0ad32c44771d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687042841 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.3687042841
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.2369972450
Short name T477
Test name
Test status
Simulation time 527908317 ps
CPU time 15.13 seconds
Started Apr 28 01:58:17 PM PDT 24
Finished Apr 28 01:58:32 PM PDT 24
Peak memory 241296 kb
Host smart-dcfe02b8-a7c5-4fd2-8540-26cd51fd5522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369972450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.2369972450
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.2528682587
Short name T907
Test name
Test status
Simulation time 127538908 ps
CPU time 3.78 seconds
Started Apr 28 02:04:02 PM PDT 24
Finished Apr 28 02:04:07 PM PDT 24
Peak memory 241484 kb
Host smart-076b2512-fdb7-49e7-b4b5-b55e4ffc713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528682587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.2528682587
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.4216980800
Short name T252
Test name
Test status
Simulation time 112352599659 ps
CPU time 1361.63 seconds
Started Apr 28 02:04:02 PM PDT 24
Finished Apr 28 02:26:44 PM PDT 24
Peak memory 279060 kb
Host smart-6eedaca1-0512-4b6d-b531-26c356ebc9bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216980800 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.4216980800
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.521977152
Short name T972
Test name
Test status
Simulation time 325117404 ps
CPU time 3.53 seconds
Started Apr 28 02:04:03 PM PDT 24
Finished Apr 28 02:04:07 PM PDT 24
Peak memory 241636 kb
Host smart-6ffb4faa-0428-4532-b4e7-d35d63b3550f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521977152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.521977152
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.268392211
Short name T803
Test name
Test status
Simulation time 248826137 ps
CPU time 10.81 seconds
Started Apr 28 02:04:09 PM PDT 24
Finished Apr 28 02:04:20 PM PDT 24
Peak memory 241268 kb
Host smart-60e4e911-3625-44fa-b126-2570834270f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268392211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.268392211
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.2373759495
Short name T794
Test name
Test status
Simulation time 904516839579 ps
CPU time 1264.92 seconds
Started Apr 28 02:04:09 PM PDT 24
Finished Apr 28 02:25:14 PM PDT 24
Peak memory 286788 kb
Host smart-8475d158-5802-4511-94b2-bb5bdb4e5e72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373759495 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.2373759495
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.4149025434
Short name T1138
Test name
Test status
Simulation time 527074619 ps
CPU time 4.08 seconds
Started Apr 28 02:04:10 PM PDT 24
Finished Apr 28 02:04:14 PM PDT 24
Peak memory 241280 kb
Host smart-9beb19b0-35cc-4f83-acd7-c1ef7e75363f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149025434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.4149025434
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.1609054336
Short name T935
Test name
Test status
Simulation time 118794075 ps
CPU time 3.63 seconds
Started Apr 28 02:04:13 PM PDT 24
Finished Apr 28 02:04:17 PM PDT 24
Peak memory 241164 kb
Host smart-b60d3958-8dba-404f-bd66-a8308e7f13cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609054336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.1609054336
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.786727606
Short name T57
Test name
Test status
Simulation time 492208512 ps
CPU time 5.09 seconds
Started Apr 28 02:04:15 PM PDT 24
Finished Apr 28 02:04:20 PM PDT 24
Peak memory 241660 kb
Host smart-b2a6fb2e-1350-46ca-82e9-290e787f7b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786727606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.786727606
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.1145027642
Short name T236
Test name
Test status
Simulation time 126676961 ps
CPU time 4.97 seconds
Started Apr 28 02:04:08 PM PDT 24
Finished Apr 28 02:04:13 PM PDT 24
Peak memory 241680 kb
Host smart-d6dbbe94-f561-4e13-87b0-efdbc0be1d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145027642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.1145027642
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.2939655500
Short name T162
Test name
Test status
Simulation time 365633688 ps
CPU time 3.66 seconds
Started Apr 28 02:04:10 PM PDT 24
Finished Apr 28 02:04:14 PM PDT 24
Peak memory 241636 kb
Host smart-9491a3ac-6a92-42f0-9496-2386d62216b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939655500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.2939655500
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.99777865
Short name T1163
Test name
Test status
Simulation time 1213459415 ps
CPU time 11.08 seconds
Started Apr 28 02:04:09 PM PDT 24
Finished Apr 28 02:04:21 PM PDT 24
Peak memory 241184 kb
Host smart-3807a93f-34fb-4e46-a7f9-9d208353498a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99777865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.99777865
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.1548839380
Short name T1173
Test name
Test status
Simulation time 80848463556 ps
CPU time 552.38 seconds
Started Apr 28 02:04:10 PM PDT 24
Finished Apr 28 02:13:22 PM PDT 24
Peak memory 248792 kb
Host smart-3671432e-66a3-46c6-bc6b-6cbfab3e1563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548839380 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.1548839380
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.3304954629
Short name T404
Test name
Test status
Simulation time 725599221 ps
CPU time 4.59 seconds
Started Apr 28 02:04:09 PM PDT 24
Finished Apr 28 02:04:14 PM PDT 24
Peak memory 241436 kb
Host smart-7f0ca1ef-e101-476f-ad47-8de0a594c7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304954629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3304954629
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.3884699141
Short name T231
Test name
Test status
Simulation time 460187928 ps
CPU time 12.8 seconds
Started Apr 28 02:04:11 PM PDT 24
Finished Apr 28 02:04:24 PM PDT 24
Peak memory 241536 kb
Host smart-489179d8-2b34-4568-b10d-8cae8087483b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884699141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.3884699141
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.1030404249
Short name T799
Test name
Test status
Simulation time 35757158117 ps
CPU time 401.2 seconds
Started Apr 28 02:04:08 PM PDT 24
Finished Apr 28 02:10:50 PM PDT 24
Peak memory 264656 kb
Host smart-e13267d3-b482-4498-a925-c506e5e626f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030404249 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.1030404249
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.2749886192
Short name T646
Test name
Test status
Simulation time 1638274355 ps
CPU time 4.84 seconds
Started Apr 28 02:04:10 PM PDT 24
Finished Apr 28 02:04:15 PM PDT 24
Peak memory 241292 kb
Host smart-7856af6c-3e16-4773-b469-e771dbb59e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749886192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2749886192
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.1831714558
Short name T461
Test name
Test status
Simulation time 173428011 ps
CPU time 7.24 seconds
Started Apr 28 02:04:18 PM PDT 24
Finished Apr 28 02:04:26 PM PDT 24
Peak memory 241320 kb
Host smart-5019c4dc-faf8-4cd8-8cfc-1d5774abb911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831714558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.1831714558
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.441546635
Short name T1095
Test name
Test status
Simulation time 333671613973 ps
CPU time 643.19 seconds
Started Apr 28 02:04:15 PM PDT 24
Finished Apr 28 02:14:58 PM PDT 24
Peak memory 262988 kb
Host smart-c194c652-d863-4d16-9e0a-b54b2792a749
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441546635 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.441546635
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.3227897719
Short name T992
Test name
Test status
Simulation time 320523817 ps
CPU time 3.97 seconds
Started Apr 28 02:04:17 PM PDT 24
Finished Apr 28 02:04:21 PM PDT 24
Peak memory 241288 kb
Host smart-941b5b23-c2b6-4024-9bce-983750ed9a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227897719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.3227897719
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.1760513508
Short name T210
Test name
Test status
Simulation time 310199222 ps
CPU time 8.91 seconds
Started Apr 28 02:04:14 PM PDT 24
Finished Apr 28 02:04:24 PM PDT 24
Peak memory 241604 kb
Host smart-045f2a53-4e87-4306-996d-a12707ed38de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760513508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.1760513508
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.1493943591
Short name T385
Test name
Test status
Simulation time 151245772711 ps
CPU time 344.48 seconds
Started Apr 28 02:04:15 PM PDT 24
Finished Apr 28 02:10:00 PM PDT 24
Peak memory 259080 kb
Host smart-83f06c69-980c-42ad-b187-9e387213d4da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493943591 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.1493943591
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.20772861
Short name T757
Test name
Test status
Simulation time 485074094 ps
CPU time 3.94 seconds
Started Apr 28 02:04:14 PM PDT 24
Finished Apr 28 02:04:18 PM PDT 24
Peak memory 241364 kb
Host smart-bad43324-b076-4b53-80f2-a6833af81195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20772861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.20772861
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.3706911340
Short name T1090
Test name
Test status
Simulation time 438862138 ps
CPU time 7.47 seconds
Started Apr 28 02:04:17 PM PDT 24
Finished Apr 28 02:04:25 PM PDT 24
Peak memory 241768 kb
Host smart-0608a88f-ce55-4205-8e7b-4afd58314dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706911340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.3706911340
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.3127315595
Short name T341
Test name
Test status
Simulation time 30884187633 ps
CPU time 509.66 seconds
Started Apr 28 02:04:16 PM PDT 24
Finished Apr 28 02:12:46 PM PDT 24
Peak memory 256316 kb
Host smart-21ac1244-416c-4f5b-8e94-6a213e2a98b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127315595 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.3127315595
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.10510550
Short name T322
Test name
Test status
Simulation time 123779831 ps
CPU time 3.4 seconds
Started Apr 28 02:04:21 PM PDT 24
Finished Apr 28 02:04:24 PM PDT 24
Peak memory 241320 kb
Host smart-f1fe13d2-225f-4d23-be28-3ae41fb2b116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10510550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.10510550
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.718309295
Short name T250
Test name
Test status
Simulation time 973812812 ps
CPU time 25.27 seconds
Started Apr 28 02:04:19 PM PDT 24
Finished Apr 28 02:04:45 PM PDT 24
Peak memory 241424 kb
Host smart-dd8aa7ee-78d1-4ce6-9408-6fa27e296700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718309295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.718309295
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest
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