Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
creator_sw_cfg_lock	2	0	2	100.00	100	1	1	2
hw_cfg0_lock	2	0	2	100.00	100	1	1	2
hw_cfg1_lock	2	0	2	100.00	100	1	1	2
lc_esc	2	0	2	100.00	100	1	1	2
owner_sw_cfg_lock	2	0	2	100.00	100	1	1	2
rot_creator_auth_codesign_lock	2	0	2	100.00	100	1	1	2
rot_creator_auth_state_lock	2	0	2	100.00	100	1	1	2
secret0_lock	2	0	2	100.00	100	1	1	2
secret1_lock	2	0	2	100.00	100	1	1	2
secret2_lock	2	0	2	100.00	100	1	1	2
vendor_test_lock	2	0	2	100.00	100	1	1	2

Summary for Variable creator_sw_cfg_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for creator_sw_cfg_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7746

1

T1

15

T2

4

T3

4

auto[1]

4794

1

T1

4

T5

12

T14

11

---

Summary for Variable hw_cfg0_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_cfg0_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7723

1

T1

3

T2

4

T3

3

auto[1]

4817

1

T1

16

T3

1

T5

12

---

Summary for Variable hw_cfg1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_cfg1_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7570

1

T1

11

T2

4

T3

3

auto[1]

4970

1

T1

8

T3

1

T5

12

---

Summary for Variable lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12503

1

T1

19

T2

4

T3

4

auto[1]

37

1

T70

1

T214

1

T76

1

---

Summary for Variable owner_sw_cfg_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for owner_sw_cfg_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9369

1

T1

19

T2

4

T3

4

auto[1]

3171

1

T15

20

T90

2

T173

2

---

Summary for Variable rot_creator_auth_codesign_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rot_creator_auth_codesign_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7794

1

T1

7

T2

4

T3

4

auto[1]

4746

1

T1

12

T5

10

T14

11

---

Summary for Variable rot_creator_auth_state_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rot_creator_auth_state_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10509

1

T1

7

T2

4

T3

4

auto[1]

2031

1

T1

12

T5

12

T14

11

---

Summary for Variable secret0_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret0_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7568

1

T1

9

T2

3

T3

3

auto[1]

4972

1

T1

10

T2

1

T3

1

---

Summary for Variable secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret1_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7596

1

T1

3

T2

4

T3

3

auto[1]

4944

1

T1

16

T3

1

T5

10

---

Summary for Variable secret2_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret2_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8968

1

T1

9

T2

4

T3

3

auto[1]

3572

1

T1

10

T3

1

T5

12

---

Summary for Variable vendor_test_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for vendor_test_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7690

1

T1

15

T2

4

T3

4

auto[1]

4850

1

T1

4

T5

12

T14

11