Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
flash_addr_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
flash_addr_req_during_lc_esc	2	0	2	100.00	100	1	1	0
flash_addr_req_during_otbn_req	2	0	2	100.00	100	1	1	2
flash_addr_req_during_otp_idle	2	0	2	100.00	100	1	1	2
flash_addr_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
flash_addr_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable flash_addr_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10977

1

T2

4

T4

5

T5

10

auto[1]

2371

1

T2

4

T4

5

T5

2

---

Summary for Variable flash_addr_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for flash_addr_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

13312

1

T2

8

T4

10

T5

12

lc_esc_on

36

1

T202

1

T244

1

T378

1

---

Summary for Variable flash_addr_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12413

1

T2

8

T4

10

T5

11

auto[1]

935

1

T5

1

T25

7

T8

5

---

Summary for Variable flash_addr_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1774

1

T4

9

T5

1

T25

9

auto[1]

11574

1

T2

8

T4

1

T5

11

---

Summary for Variable flash_addr_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12497

1

T2

8

T4

10

T5

12

auto[1]

851

1

T25

7

T8

11

T19

3

---

Summary for Variable flash_addr_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12976

1

T2

8

T4

10

T5

11

auto[1]

372

1

T5

1

T25

2

T19

3