Summary for Variable flash_index
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for flash_index
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| il |
0 |
Illegal |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| flash_addr_key |
6785 |
1 |
|
|
T1 |
1 |
|
T4 |
90 |
|
T5 |
3 |
| flash_data_key |
6751 |
1 |
|
|
T1 |
1 |
|
T4 |
82 |
|
T5 |
3 |
Summary for Variable secret1_lock
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret1_lock
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8369 |
1 |
|
|
T4 |
38 |
|
T8 |
2 |
|
T9 |
2 |
| auto[1] |
5167 |
1 |
|
|
T1 |
2 |
|
T4 |
134 |
|
T5 |
6 |
Summary for Cross flash_req_lock_cross
Samples crossed: flash_index secret1_lock
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for flash_req_lock_cross
Bins
| flash_index | secret1_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| flash_addr_key |
auto[0] |
4202 |
1 |
|
|
T4 |
20 |
|
T8 |
1 |
|
T9 |
1 |
| flash_addr_key |
auto[1] |
2583 |
1 |
|
|
T1 |
1 |
|
T4 |
70 |
|
T5 |
3 |
| flash_data_key |
auto[0] |
4167 |
1 |
|
|
T4 |
18 |
|
T8 |
1 |
|
T9 |
1 |
| flash_data_key |
auto[1] |
2584 |
1 |
|
|
T1 |
1 |
|
T4 |
64 |
|
T5 |
3 |