Summary for Variable flash_index
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for flash_index
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| il |
0 |
Illegal |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| flash_addr_key |
6157 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T5 |
9 |
| flash_data_key |
6166 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T5 |
9 |
Summary for Variable secret1_lock
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret1_lock
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7124 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T5 |
18 |
| auto[1] |
5199 |
1 |
|
|
T3 |
4 |
|
T9 |
16 |
|
T11 |
6 |
Summary for Cross flash_req_lock_cross
Samples crossed: flash_index secret1_lock
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for flash_req_lock_cross
Bins
| flash_index | secret1_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| flash_addr_key |
auto[0] |
3568 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
9 |
| flash_addr_key |
auto[1] |
2589 |
1 |
|
|
T3 |
2 |
|
T9 |
8 |
|
T11 |
3 |
| flash_data_key |
auto[0] |
3556 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
9 |
| flash_data_key |
auto[1] |
2610 |
1 |
|
|
T3 |
2 |
|
T9 |
8 |
|
T11 |
3 |