Summary for Variable keymgr_rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for keymgr_rd_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3802 |
1 |
|
|
T1 |
2 |
|
T3 |
5 |
|
T5 |
11 |
| auto[1] |
2511 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
3 |
Summary for Variable secret2_lock
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret2_lock
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4372 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
4 |
| auto[1] |
1941 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T9 |
9 |
Summary for Cross keymgr_output_conditions
Samples crossed: keymgr_rd_en secret2_lock
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for keymgr_output_conditions
Bins
| keymgr_rd_en | secret2_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
2615 |
1 |
|
|
T1 |
2 |
|
T3 |
4 |
|
T5 |
11 |
| auto[0] |
auto[1] |
1187 |
1 |
|
|
T3 |
1 |
|
T9 |
4 |
|
T11 |
2 |
| auto[1] |
auto[0] |
1757 |
1 |
|
|
T2 |
1 |
|
T5 |
3 |
|
T8 |
1 |
| auto[1] |
auto[1] |
754 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T9 |
5 |