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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.86 93.81 96.18 95.65 91.65 97.10 96.34 93.28


Total test records in report: 1319
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T1256 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.686283932 Aug 01 06:29:16 PM PDT 24 Aug 01 06:29:18 PM PDT 24 42490364 ps
T1257 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3461740329 Aug 01 06:29:16 PM PDT 24 Aug 01 06:29:18 PM PDT 24 73844426 ps
T1258 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1519423349 Aug 01 06:28:28 PM PDT 24 Aug 01 06:28:42 PM PDT 24 10276018781 ps
T1259 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.1746753766 Aug 01 06:29:15 PM PDT 24 Aug 01 06:29:16 PM PDT 24 139672120 ps
T1260 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1164716005 Aug 01 06:28:40 PM PDT 24 Aug 01 06:28:47 PM PDT 24 163521258 ps
T1261 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2465434689 Aug 01 06:28:56 PM PDT 24 Aug 01 06:28:58 PM PDT 24 89910056 ps
T1262 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1185503330 Aug 01 06:29:19 PM PDT 24 Aug 01 06:29:24 PM PDT 24 1657071541 ps
T1263 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.928454222 Aug 01 06:28:52 PM PDT 24 Aug 01 06:28:54 PM PDT 24 68213378 ps
T1264 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.4160452749 Aug 01 06:28:42 PM PDT 24 Aug 01 06:28:46 PM PDT 24 1291718716 ps
T1265 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2046323599 Aug 01 06:29:15 PM PDT 24 Aug 01 06:29:17 PM PDT 24 143901846 ps
T1266 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.736017446 Aug 01 06:29:02 PM PDT 24 Aug 01 06:29:06 PM PDT 24 1109384697 ps
T1267 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.108288526 Aug 01 06:28:34 PM PDT 24 Aug 01 06:28:41 PM PDT 24 1850556623 ps
T1268 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.407663907 Aug 01 06:28:51 PM PDT 24 Aug 01 06:28:53 PM PDT 24 85171205 ps
T1269 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2408400035 Aug 01 06:29:15 PM PDT 24 Aug 01 06:29:16 PM PDT 24 81407411 ps
T1270 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2450850538 Aug 01 06:28:54 PM PDT 24 Aug 01 06:28:56 PM PDT 24 72598903 ps
T1271 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1900179429 Aug 01 06:29:01 PM PDT 24 Aug 01 06:29:03 PM PDT 24 44182035 ps
T263 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1968186346 Aug 01 06:28:53 PM PDT 24 Aug 01 06:29:04 PM PDT 24 645616105 ps
T1272 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.692509010 Aug 01 06:28:53 PM PDT 24 Aug 01 06:28:56 PM PDT 24 64046707 ps
T1273 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2865346546 Aug 01 06:28:32 PM PDT 24 Aug 01 06:28:42 PM PDT 24 626127428 ps
T1274 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1932399400 Aug 01 06:28:43 PM PDT 24 Aug 01 06:28:44 PM PDT 24 46842560 ps
T1275 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3662146453 Aug 01 06:29:01 PM PDT 24 Aug 01 06:29:07 PM PDT 24 156517161 ps
T1276 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2867733539 Aug 01 06:29:02 PM PDT 24 Aug 01 06:29:05 PM PDT 24 109885391 ps
T1277 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.234795505 Aug 01 06:28:52 PM PDT 24 Aug 01 06:28:56 PM PDT 24 161951358 ps
T1278 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3760215357 Aug 01 06:29:17 PM PDT 24 Aug 01 06:29:19 PM PDT 24 43318329 ps
T1279 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3773812406 Aug 01 06:29:04 PM PDT 24 Aug 01 06:29:08 PM PDT 24 70935418 ps
T306 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1531538356 Aug 01 06:28:26 PM PDT 24 Aug 01 06:28:32 PM PDT 24 147463691 ps
T1280 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3788807453 Aug 01 06:28:42 PM PDT 24 Aug 01 06:28:44 PM PDT 24 121971083 ps
T307 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.209543782 Aug 01 06:29:04 PM PDT 24 Aug 01 06:29:06 PM PDT 24 177449731 ps
T1281 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1447358020 Aug 01 06:28:59 PM PDT 24 Aug 01 06:29:23 PM PDT 24 4544422148 ps
T1282 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.377690261 Aug 01 06:28:44 PM PDT 24 Aug 01 06:29:05 PM PDT 24 4001888994 ps
T1283 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.1574681773 Aug 01 06:29:16 PM PDT 24 Aug 01 06:29:18 PM PDT 24 515117108 ps
T1284 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2582903544 Aug 01 06:29:17 PM PDT 24 Aug 01 06:29:19 PM PDT 24 550669639 ps
T1285 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1501520167 Aug 01 06:28:28 PM PDT 24 Aug 01 06:28:34 PM PDT 24 184085729 ps
T1286 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.3390141658 Aug 01 06:28:41 PM PDT 24 Aug 01 06:28:43 PM PDT 24 88773158 ps
T1287 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2561991761 Aug 01 06:28:31 PM PDT 24 Aug 01 06:28:34 PM PDT 24 91730632 ps
T350 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2781717440 Aug 01 06:28:59 PM PDT 24 Aug 01 06:29:17 PM PDT 24 2561997806 ps
T1288 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2474427361 Aug 01 06:28:42 PM PDT 24 Aug 01 06:28:47 PM PDT 24 118184746 ps
T1289 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1281543662 Aug 01 06:29:18 PM PDT 24 Aug 01 06:29:20 PM PDT 24 73974098 ps
T1290 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3250740737 Aug 01 06:28:54 PM PDT 24 Aug 01 06:28:56 PM PDT 24 105462295 ps
T1291 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1689819555 Aug 01 06:28:33 PM PDT 24 Aug 01 06:28:35 PM PDT 24 143053755 ps
T1292 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1286544954 Aug 01 06:28:54 PM PDT 24 Aug 01 06:29:00 PM PDT 24 1629965659 ps
T1293 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3728095450 Aug 01 06:28:31 PM PDT 24 Aug 01 06:28:33 PM PDT 24 74326049 ps
T1294 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2092868632 Aug 01 06:29:01 PM PDT 24 Aug 01 06:29:04 PM PDT 24 164304119 ps
T1295 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.2619172767 Aug 01 06:28:46 PM PDT 24 Aug 01 06:28:48 PM PDT 24 698883144 ps
T1296 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2913015289 Aug 01 06:28:54 PM PDT 24 Aug 01 06:28:58 PM PDT 24 207091070 ps
T1297 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1264566218 Aug 01 06:28:33 PM PDT 24 Aug 01 06:28:35 PM PDT 24 37096774 ps
T1298 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.1770518371 Aug 01 06:28:32 PM PDT 24 Aug 01 06:28:34 PM PDT 24 141291838 ps
T1299 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3329079879 Aug 01 06:28:42 PM PDT 24 Aug 01 06:28:45 PM PDT 24 103746885 ps
T1300 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2829545393 Aug 01 06:28:43 PM PDT 24 Aug 01 06:28:49 PM PDT 24 141139148 ps
T1301 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.2494693352 Aug 01 06:29:15 PM PDT 24 Aug 01 06:29:17 PM PDT 24 111095769 ps
T1302 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.387015850 Aug 01 06:28:55 PM PDT 24 Aug 01 06:28:56 PM PDT 24 43215465 ps
T1303 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2266982770 Aug 01 06:28:52 PM PDT 24 Aug 01 06:28:56 PM PDT 24 166480555 ps
T353 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1465957862 Aug 01 06:28:54 PM PDT 24 Aug 01 06:29:05 PM PDT 24 645707841 ps
T1304 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2090761283 Aug 01 06:29:15 PM PDT 24 Aug 01 06:29:17 PM PDT 24 77175457 ps
T1305 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3342766820 Aug 01 06:28:32 PM PDT 24 Aug 01 06:28:34 PM PDT 24 544716315 ps
T1306 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3388772013 Aug 01 06:28:32 PM PDT 24 Aug 01 06:28:35 PM PDT 24 202934986 ps
T1307 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1433097292 Aug 01 06:28:34 PM PDT 24 Aug 01 06:28:35 PM PDT 24 134594491 ps
T1308 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1349970158 Aug 01 06:28:33 PM PDT 24 Aug 01 06:28:35 PM PDT 24 45647686 ps
T1309 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.87002725 Aug 01 06:28:54 PM PDT 24 Aug 01 06:28:55 PM PDT 24 137874411 ps
T1310 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3678958959 Aug 01 06:28:34 PM PDT 24 Aug 01 06:28:37 PM PDT 24 1034427597 ps
T1311 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.1521034279 Aug 01 06:29:16 PM PDT 24 Aug 01 06:29:17 PM PDT 24 38789800 ps
T1312 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.485151014 Aug 01 06:29:17 PM PDT 24 Aug 01 06:29:19 PM PDT 24 73632196 ps
T1313 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1545422059 Aug 01 06:29:01 PM PDT 24 Aug 01 06:29:05 PM PDT 24 234862328 ps
T1314 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3709897321 Aug 01 06:28:30 PM PDT 24 Aug 01 06:28:31 PM PDT 24 79035031 ps
T1315 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1560830384 Aug 01 06:28:52 PM PDT 24 Aug 01 06:28:54 PM PDT 24 600335380 ps
T1316 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.421025480 Aug 01 06:29:15 PM PDT 24 Aug 01 06:29:17 PM PDT 24 79326303 ps
T1317 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.278394903 Aug 01 06:28:30 PM PDT 24 Aug 01 06:28:33 PM PDT 24 379667009 ps
T1318 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.584887868 Aug 01 06:29:05 PM PDT 24 Aug 01 06:29:10 PM PDT 24 77343048 ps
T1319 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.292523536 Aug 01 06:28:33 PM PDT 24 Aug 01 06:28:43 PM PDT 24 631407008 ps

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.1003176886
Short name T2
Test name
Test status
Simulation time 66863445294 ps
CPU time 1553.41 seconds
Started Aug 01 06:01:56 PM PDT 24
Finished Aug 01 06:27:50 PM PDT 24
Peak memory 265116 kb
Host smart-62b8f08e-8bb3-41d0-843c-235a91b0a8bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003176886 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.1003176886
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.2503405649
Short name T12
Test name
Test status
Simulation time 18693152497 ps
CPU time 137.11 seconds
Started Aug 01 06:00:42 PM PDT 24
Finished Aug 01 06:03:13 PM PDT 24
Peak memory 256684 kb
Host smart-ae8f44e4-17c9-4b54-9b94-3a31db139dc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503405649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.2503405649
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.3019099003
Short name T59
Test name
Test status
Simulation time 154080171162 ps
CPU time 360.15 seconds
Started Aug 01 05:58:48 PM PDT 24
Finished Aug 01 06:04:49 PM PDT 24
Peak memory 265016 kb
Host smart-b79e4e76-f141-4e69-ba39-306469167fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019099003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.3019099003
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.3558075326
Short name T56
Test name
Test status
Simulation time 31915513026 ps
CPU time 205.79 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:04:21 PM PDT 24
Peak memory 248592 kb
Host smart-17e7db47-ade0-4086-98c6-17acecbb5695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558075326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.3558075326
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.3872068740
Short name T19
Test name
Test status
Simulation time 10523511060 ps
CPU time 192.67 seconds
Started Aug 01 05:57:58 PM PDT 24
Finished Aug 01 06:01:11 PM PDT 24
Peak memory 266088 kb
Host smart-2da121bd-a613-4d9a-a560-7d8766af5c63
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872068740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3872068740
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.1565622598
Short name T36
Test name
Test status
Simulation time 20102212195 ps
CPU time 36.98 seconds
Started Aug 01 06:00:41 PM PDT 24
Finished Aug 01 06:01:33 PM PDT 24
Peak memory 243396 kb
Host smart-fa7e0b60-8acf-4543-8537-1e8e78a6204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565622598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.1565622598
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.2731748084
Short name T1
Test name
Test status
Simulation time 11584066296 ps
CPU time 81.24 seconds
Started Aug 01 05:59:43 PM PDT 24
Finished Aug 01 06:01:05 PM PDT 24
Peak memory 248372 kb
Host smart-87ba4f5f-36ab-429d-a975-9247481bb62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731748084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.2731748084
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.1658854241
Short name T60
Test name
Test status
Simulation time 201187432 ps
CPU time 3.59 seconds
Started Aug 01 06:02:07 PM PDT 24
Finished Aug 01 06:02:11 PM PDT 24
Peak memory 242216 kb
Host smart-7e96a1df-c192-40c3-8066-68669fd40463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658854241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.1658854241
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.1340416317
Short name T91
Test name
Test status
Simulation time 13778761137 ps
CPU time 148.04 seconds
Started Aug 01 05:59:48 PM PDT 24
Finished Aug 01 06:02:17 PM PDT 24
Peak memory 256872 kb
Host smart-a08c8200-4daf-41f8-8647-c7691548c647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340416317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.1340416317
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.1200267681
Short name T22
Test name
Test status
Simulation time 117057296 ps
CPU time 3.47 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 242036 kb
Host smart-0e2e66a0-0cc5-4c3e-ba2e-19519a7abe1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200267681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1200267681
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3656999015
Short name T257
Test name
Test status
Simulation time 1942265348 ps
CPU time 22.42 seconds
Started Aug 01 06:28:54 PM PDT 24
Finished Aug 01 06:29:16 PM PDT 24
Peak memory 243860 kb
Host smart-ec87992c-87b7-40cd-befd-5b6551c1fda0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656999015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.3656999015
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.1308863010
Short name T323
Test name
Test status
Simulation time 480867750160 ps
CPU time 930.32 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:17:16 PM PDT 24
Peak memory 311596 kb
Host smart-96ad5334-9f2a-45eb-ae18-d127d8aefad8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308863010 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.1308863010
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.3504005255
Short name T34
Test name
Test status
Simulation time 273726883 ps
CPU time 4.2 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:48 PM PDT 24
Peak memory 241944 kb
Host smart-543539c1-f789-4b3d-b899-004b6def96c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504005255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.3504005255
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.1064168286
Short name T209
Test name
Test status
Simulation time 1992156041 ps
CPU time 43.3 seconds
Started Aug 01 05:58:03 PM PDT 24
Finished Aug 01 05:58:46 PM PDT 24
Peak memory 249628 kb
Host smart-76ab9480-8ab2-4786-9142-cd558da05012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064168286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.1064168286
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.3526076625
Short name T64
Test name
Test status
Simulation time 4396824363 ps
CPU time 23.57 seconds
Started Aug 01 06:00:21 PM PDT 24
Finished Aug 01 06:01:19 PM PDT 24
Peak memory 244032 kb
Host smart-835d1b95-cd6a-4a1f-8073-264a232ea7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526076625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.3526076625
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.3867306100
Short name T105
Test name
Test status
Simulation time 317513157 ps
CPU time 4.36 seconds
Started Aug 01 06:01:56 PM PDT 24
Finished Aug 01 06:02:01 PM PDT 24
Peak memory 242176 kb
Host smart-80404cb4-2551-48e3-82b9-acbcd83737a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867306100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3867306100
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.1443706398
Short name T150
Test name
Test status
Simulation time 62540679226 ps
CPU time 178.72 seconds
Started Aug 01 05:59:21 PM PDT 24
Finished Aug 01 06:02:20 PM PDT 24
Peak memory 264988 kb
Host smart-382df833-ebaf-48c8-aec0-93adf4fb318a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443706398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.1443706398
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.3689305272
Short name T391
Test name
Test status
Simulation time 402700975 ps
CPU time 5.3 seconds
Started Aug 01 05:58:40 PM PDT 24
Finished Aug 01 05:58:46 PM PDT 24
Peak memory 242080 kb
Host smart-363c74a2-5a2a-49ca-aad5-06dd17b43c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689305272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.3689305272
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.1994200207
Short name T61
Test name
Test status
Simulation time 20375065729 ps
CPU time 246.56 seconds
Started Aug 01 05:59:21 PM PDT 24
Finished Aug 01 06:03:27 PM PDT 24
Peak memory 280540 kb
Host smart-0fe40a39-6ed7-4293-8318-4beb21dbbfbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994200207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.1994200207
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.771525883
Short name T9
Test name
Test status
Simulation time 476007264 ps
CPU time 5.11 seconds
Started Aug 01 06:02:47 PM PDT 24
Finished Aug 01 06:02:53 PM PDT 24
Peak memory 241960 kb
Host smart-5bdda0cc-2055-43a3-8357-1a5463501aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771525883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.771525883
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.1831829857
Short name T191
Test name
Test status
Simulation time 66826990 ps
CPU time 1.89 seconds
Started Aug 01 05:57:48 PM PDT 24
Finished Aug 01 05:57:50 PM PDT 24
Peak memory 240596 kb
Host smart-0bf95c02-9b48-4b6f-9c68-88b422d5a973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831829857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.1831829857
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.989007849
Short name T217
Test name
Test status
Simulation time 1953408674 ps
CPU time 44.62 seconds
Started Aug 01 05:58:37 PM PDT 24
Finished Aug 01 05:59:22 PM PDT 24
Peak memory 248592 kb
Host smart-462d6ae6-2bfb-4d9c-b1f6-ea7bf5dac962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989007849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.989007849
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.3932293794
Short name T111
Test name
Test status
Simulation time 448817859 ps
CPU time 4.51 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:02 PM PDT 24
Peak memory 242136 kb
Host smart-f555251e-3318-40b1-b017-46c5d37ca93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932293794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.3932293794
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.4112001254
Short name T262
Test name
Test status
Simulation time 41710389 ps
CPU time 1.59 seconds
Started Aug 01 06:29:04 PM PDT 24
Finished Aug 01 06:29:05 PM PDT 24
Peak memory 240556 kb
Host smart-2def4b95-8e9c-4a18-83de-b11faa41a68e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112001254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.4112001254
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.1575754030
Short name T45
Test name
Test status
Simulation time 150892975 ps
CPU time 4.64 seconds
Started Aug 01 06:02:59 PM PDT 24
Finished Aug 01 06:03:03 PM PDT 24
Peak memory 241948 kb
Host smart-153a7472-8cf6-4fd0-9aca-da43ccf48fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575754030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1575754030
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.1896053958
Short name T205
Test name
Test status
Simulation time 698118501 ps
CPU time 5.71 seconds
Started Aug 01 06:02:45 PM PDT 24
Finished Aug 01 06:02:51 PM PDT 24
Peak memory 241980 kb
Host smart-34147010-a07b-4bd7-a956-d8acd1ed990b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896053958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.1896053958
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.676238938
Short name T14
Test name
Test status
Simulation time 35920404944 ps
CPU time 115.3 seconds
Started Aug 01 05:58:28 PM PDT 24
Finished Aug 01 06:00:23 PM PDT 24
Peak memory 249388 kb
Host smart-17772087-4858-4e44-be6f-af66c33b778c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676238938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.
676238938
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.4091009014
Short name T133
Test name
Test status
Simulation time 67489754408 ps
CPU time 1704.77 seconds
Started Aug 01 05:58:54 PM PDT 24
Finished Aug 01 06:27:19 PM PDT 24
Peak memory 273220 kb
Host smart-65a4f1d5-6bea-4cfa-ba29-508beed9601f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091009014 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.4091009014
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.3843058799
Short name T179
Test name
Test status
Simulation time 123947935 ps
CPU time 3.2 seconds
Started Aug 01 06:02:31 PM PDT 24
Finished Aug 01 06:02:34 PM PDT 24
Peak memory 242356 kb
Host smart-f5f947d3-ae84-4965-bfb9-b6a4c6053ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843058799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3843058799
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.4065097011
Short name T27
Test name
Test status
Simulation time 305967727 ps
CPU time 5.46 seconds
Started Aug 01 06:03:06 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 241912 kb
Host smart-7e2cdf54-5e97-4719-8445-c12f9bfb5e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065097011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.4065097011
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.163291685
Short name T33
Test name
Test status
Simulation time 672781747 ps
CPU time 5.42 seconds
Started Aug 01 06:03:01 PM PDT 24
Finished Aug 01 06:03:07 PM PDT 24
Peak memory 242124 kb
Host smart-73d5d017-5af4-44c3-ac7c-aeffc51e435a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163291685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.163291685
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.705599099
Short name T693
Test name
Test status
Simulation time 294890305 ps
CPU time 3.64 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:02:59 PM PDT 24
Peak memory 242196 kb
Host smart-c1b3d4a5-aca8-4159-97f0-a9c857196de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705599099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.705599099
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.2072250404
Short name T35
Test name
Test status
Simulation time 103010738 ps
CPU time 4.04 seconds
Started Aug 01 06:02:32 PM PDT 24
Finished Aug 01 06:02:36 PM PDT 24
Peak memory 241768 kb
Host smart-fe646fb7-ee45-45c4-981d-66a365696889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072250404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.2072250404
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.1256819105
Short name T183
Test name
Test status
Simulation time 211634350 ps
CPU time 3.92 seconds
Started Aug 01 06:02:57 PM PDT 24
Finished Aug 01 06:03:01 PM PDT 24
Peak memory 241972 kb
Host smart-d8d8b99d-753a-4416-adf0-560064dcfd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256819105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.1256819105
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.1067300678
Short name T240
Test name
Test status
Simulation time 144838036404 ps
CPU time 369.55 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:07:05 PM PDT 24
Peak memory 284708 kb
Host smart-02c829e8-0a34-4fa1-8090-0a2e0bff57c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067300678 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.1067300678
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.1722833591
Short name T68
Test name
Test status
Simulation time 9168755365 ps
CPU time 27.5 seconds
Started Aug 01 06:00:38 PM PDT 24
Finished Aug 01 06:01:23 PM PDT 24
Peak memory 244736 kb
Host smart-bc257f47-d742-46df-9b09-b3892919ecd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722833591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.1722833591
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.836299479
Short name T136
Test name
Test status
Simulation time 257040543 ps
CPU time 5.78 seconds
Started Aug 01 06:02:11 PM PDT 24
Finished Aug 01 06:02:17 PM PDT 24
Peak memory 241788 kb
Host smart-578806c1-782a-4956-8ba8-4b7988f5414d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836299479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.836299479
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.81777852
Short name T151
Test name
Test status
Simulation time 106047569848 ps
CPU time 212.63 seconds
Started Aug 01 06:00:59 PM PDT 24
Finished Aug 01 06:04:32 PM PDT 24
Peak memory 259332 kb
Host smart-8f77d5c1-64e3-439c-a9ce-3483961b2313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81777852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.81777852
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.3668106608
Short name T142
Test name
Test status
Simulation time 243035458 ps
CPU time 4.73 seconds
Started Aug 01 06:02:33 PM PDT 24
Finished Aug 01 06:02:38 PM PDT 24
Peak memory 241904 kb
Host smart-c2210acd-0616-481f-9ff0-8d4b01d3018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668106608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3668106608
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.1309021752
Short name T906
Test name
Test status
Simulation time 460712709 ps
CPU time 6.97 seconds
Started Aug 01 06:00:06 PM PDT 24
Finished Aug 01 06:01:02 PM PDT 24
Peak memory 241760 kb
Host smart-0dee4531-3d8e-4124-b45b-d99c64f0509e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309021752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.1309021752
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.1362234568
Short name T71
Test name
Test status
Simulation time 175524209 ps
CPU time 4.32 seconds
Started Aug 01 06:02:22 PM PDT 24
Finished Aug 01 06:02:27 PM PDT 24
Peak memory 242256 kb
Host smart-1cfebf86-31f8-431a-af72-524d4f87b8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362234568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.1362234568
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.2153932961
Short name T23
Test name
Test status
Simulation time 6324776074 ps
CPU time 12.82 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 05:58:52 PM PDT 24
Peak memory 243052 kb
Host smart-237cc5ca-d0ad-4037-a08a-536a173b2caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153932961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.2153932961
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.1812739154
Short name T237
Test name
Test status
Simulation time 157635479364 ps
CPU time 1639.06 seconds
Started Aug 01 06:01:44 PM PDT 24
Finished Aug 01 06:29:03 PM PDT 24
Peak memory 576456 kb
Host smart-fa91b5d6-732c-410b-a791-0dd4cff7e5fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812739154 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.1812739154
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.118937179
Short name T78
Test name
Test status
Simulation time 157324699 ps
CPU time 4.37 seconds
Started Aug 01 05:58:52 PM PDT 24
Finished Aug 01 05:58:56 PM PDT 24
Peak memory 241988 kb
Host smart-4bf57267-d3e5-4650-8a35-945ce635ecef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118937179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.118937179
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.1214336910
Short name T137
Test name
Test status
Simulation time 1663059036 ps
CPU time 4.51 seconds
Started Aug 01 06:02:18 PM PDT 24
Finished Aug 01 06:02:23 PM PDT 24
Peak memory 242060 kb
Host smart-096d8390-fb9a-45c9-9056-f2d84fd59691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214336910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.1214336910
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.221884411
Short name T1090
Test name
Test status
Simulation time 135399943 ps
CPU time 6.93 seconds
Started Aug 01 06:02:19 PM PDT 24
Finished Aug 01 06:02:26 PM PDT 24
Peak memory 242312 kb
Host smart-4e6b52b2-98c3-4e28-95f0-e8fc97036ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221884411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.221884411
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.668914532
Short name T119
Test name
Test status
Simulation time 138532208 ps
CPU time 6.32 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:50 PM PDT 24
Peak memory 242108 kb
Host smart-8d08ee87-658c-4981-b0ef-90134866d175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668914532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.668914532
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.3890803866
Short name T57
Test name
Test status
Simulation time 1318829008 ps
CPU time 21.79 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:03:05 PM PDT 24
Peak memory 241948 kb
Host smart-f73b4f5d-8800-44f8-af60-b297f8dc7681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890803866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3890803866
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.3265566149
Short name T236
Test name
Test status
Simulation time 1248240833 ps
CPU time 8.64 seconds
Started Aug 01 06:02:59 PM PDT 24
Finished Aug 01 06:03:07 PM PDT 24
Peak memory 241860 kb
Host smart-2ab09ad8-fa2c-4083-9b26-5dadae6f5dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265566149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.3265566149
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.2860270336
Short name T204
Test name
Test status
Simulation time 19566630679 ps
CPU time 127.67 seconds
Started Aug 01 06:01:20 PM PDT 24
Finished Aug 01 06:03:28 PM PDT 24
Peak memory 256796 kb
Host smart-d052e52f-4190-4d46-a79e-00ba5b557af3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860270336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.2860270336
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.342205199
Short name T140
Test name
Test status
Simulation time 594394465 ps
CPU time 5.01 seconds
Started Aug 01 06:01:46 PM PDT 24
Finished Aug 01 06:01:51 PM PDT 24
Peak memory 241736 kb
Host smart-a2c0912f-a8bf-47aa-9ca9-53ace06b471c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342205199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.342205199
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3467791940
Short name T352
Test name
Test status
Simulation time 3670813613 ps
CPU time 21.7 seconds
Started Aug 01 06:28:41 PM PDT 24
Finished Aug 01 06:29:02 PM PDT 24
Peak memory 244612 kb
Host smart-b1afb16c-54e4-4215-af1f-ee26fcc76297
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467791940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.3467791940
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.2549507218
Short name T370
Test name
Test status
Simulation time 246737369 ps
CPU time 8.7 seconds
Started Aug 01 06:00:20 PM PDT 24
Finished Aug 01 06:01:04 PM PDT 24
Peak memory 248460 kb
Host smart-e84d6c6f-1622-49f1-9b16-1f12b0f9eb40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549507218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.2549507218
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.1433267061
Short name T72
Test name
Test status
Simulation time 21799499469 ps
CPU time 36.16 seconds
Started Aug 01 05:58:49 PM PDT 24
Finished Aug 01 05:59:25 PM PDT 24
Peak memory 248712 kb
Host smart-019c43b5-3130-476e-addd-e7346b5cb99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433267061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1433267061
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.4209948043
Short name T334
Test name
Test status
Simulation time 191156609842 ps
CPU time 248.36 seconds
Started Aug 01 05:59:01 PM PDT 24
Finished Aug 01 06:03:10 PM PDT 24
Peak memory 263424 kb
Host smart-529f5990-48f4-414a-b8aa-d785303d16fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209948043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.4209948043
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2209227938
Short name T261
Test name
Test status
Simulation time 1835716588 ps
CPU time 9.3 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:24 PM PDT 24
Peak memory 243624 kb
Host smart-20b42183-1a99-46e5-a8ba-ebb0ad2a6e83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209227938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.2209227938
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.3294911640
Short name T41
Test name
Test status
Simulation time 1017002168 ps
CPU time 13.18 seconds
Started Aug 01 05:58:29 PM PDT 24
Finished Aug 01 05:58:43 PM PDT 24
Peak memory 242384 kb
Host smart-1d3cc1e4-530d-4c3f-8e93-f941015e41ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294911640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.3294911640
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.1771144178
Short name T6
Test name
Test status
Simulation time 613038394 ps
CPU time 13.67 seconds
Started Aug 01 05:57:58 PM PDT 24
Finished Aug 01 05:58:12 PM PDT 24
Peak memory 242068 kb
Host smart-e9f83f0b-8693-458d-ad11-c46134f7b878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771144178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.1771144178
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2973736969
Short name T264
Test name
Test status
Simulation time 1412829039 ps
CPU time 18.53 seconds
Started Aug 01 06:29:03 PM PDT 24
Finished Aug 01 06:29:22 PM PDT 24
Peak memory 238888 kb
Host smart-26fa3d22-061a-4867-9ebf-eb75caa62ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973736969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.2973736969
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.4169655016
Short name T717
Test name
Test status
Simulation time 13016019680 ps
CPU time 163.88 seconds
Started Aug 01 05:59:02 PM PDT 24
Finished Aug 01 06:01:46 PM PDT 24
Peak memory 247388 kb
Host smart-d70ba951-8fc9-42cd-bded-0c2d70318483
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169655016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.4169655016
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.4061739334
Short name T366
Test name
Test status
Simulation time 412169865 ps
CPU time 7.8 seconds
Started Aug 01 05:59:52 PM PDT 24
Finished Aug 01 06:00:00 PM PDT 24
Peak memory 242028 kb
Host smart-7e850e79-597a-475f-a68b-c6995ac4ad81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061739334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.4061739334
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.209543782
Short name T307
Test name
Test status
Simulation time 177449731 ps
CPU time 1.88 seconds
Started Aug 01 06:29:04 PM PDT 24
Finished Aug 01 06:29:06 PM PDT 24
Peak memory 241180 kb
Host smart-7674ee4a-b509-4beb-ac72-cc362bab29a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209543782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.209543782
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.2709385268
Short name T624
Test name
Test status
Simulation time 25681845532 ps
CPU time 304.97 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:07:02 PM PDT 24
Peak memory 275824 kb
Host smart-231e4621-1a0d-458b-93fd-ea93db900316
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709385268 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.2709385268
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.2246429463
Short name T110
Test name
Test status
Simulation time 601143102 ps
CPU time 15.74 seconds
Started Aug 01 05:58:38 PM PDT 24
Finished Aug 01 05:58:54 PM PDT 24
Peak memory 242468 kb
Host smart-d93a0d7f-3d6a-4230-86c7-f665b9987610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246429463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.2246429463
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.2932363766
Short name T49
Test name
Test status
Simulation time 6574404287 ps
CPU time 64.19 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:01:59 PM PDT 24
Peak memory 248608 kb
Host smart-e4bda03c-2819-4e1c-aa2d-4f443c747952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932363766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.2932363766
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.322757663
Short name T117
Test name
Test status
Simulation time 262664008 ps
CPU time 4.34 seconds
Started Aug 01 06:02:12 PM PDT 24
Finished Aug 01 06:02:17 PM PDT 24
Peak memory 241948 kb
Host smart-4ee0ceba-f0c7-44e4-bf1f-cb2836936870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322757663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.322757663
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.602718028
Short name T218
Test name
Test status
Simulation time 344245971 ps
CPU time 3.63 seconds
Started Aug 01 06:02:11 PM PDT 24
Finished Aug 01 06:02:15 PM PDT 24
Peak memory 242180 kb
Host smart-61a7f2df-f013-4260-9ae0-e2a8a7fcdd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602718028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.602718028
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2712299364
Short name T348
Test name
Test status
Simulation time 1306381598 ps
CPU time 11.17 seconds
Started Aug 01 06:28:54 PM PDT 24
Finished Aug 01 06:29:05 PM PDT 24
Peak memory 243476 kb
Host smart-165352f0-fb78-4ec3-af42-d83ab18d6a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712299364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.2712299364
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.363999540
Short name T3
Test name
Test status
Simulation time 337300225 ps
CPU time 3.66 seconds
Started Aug 01 05:58:50 PM PDT 24
Finished Aug 01 05:58:54 PM PDT 24
Peak memory 248260 kb
Host smart-e0aef7b8-020e-4740-b235-bbbcf9a3d6d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=363999540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.363999540
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.4229221522
Short name T274
Test name
Test status
Simulation time 75170789578 ps
CPU time 1396.35 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:25:14 PM PDT 24
Peak memory 273356 kb
Host smart-41ec8428-1a15-4891-8797-073011be45af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229221522 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.4229221522
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.513856288
Short name T62
Test name
Test status
Simulation time 450918929 ps
CPU time 4.12 seconds
Started Aug 01 06:03:18 PM PDT 24
Finished Aug 01 06:03:23 PM PDT 24
Peak memory 242120 kb
Host smart-162f3ff3-dd16-4b92-b729-212df45999cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513856288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.513856288
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.2374393777
Short name T157
Test name
Test status
Simulation time 180596480 ps
CPU time 1.72 seconds
Started Aug 01 05:57:48 PM PDT 24
Finished Aug 01 05:57:50 PM PDT 24
Peak memory 240220 kb
Host smart-8ee09c60-b254-4f1d-85df-af70c356cf3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2374393777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.2374393777
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1968186346
Short name T263
Test name
Test status
Simulation time 645616105 ps
CPU time 11.03 seconds
Started Aug 01 06:28:53 PM PDT 24
Finished Aug 01 06:29:04 PM PDT 24
Peak memory 238748 kb
Host smart-8ea5da12-bca1-4d4e-8788-53c0c281f822
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968186346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.1968186346
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.1639580264
Short name T131
Test name
Test status
Simulation time 1042305103 ps
CPU time 18.93 seconds
Started Aug 01 05:58:28 PM PDT 24
Finished Aug 01 05:58:47 PM PDT 24
Peak memory 242252 kb
Host smart-a3846b2c-42b4-4adb-a117-152fbd21c58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639580264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1639580264
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.2430825534
Short name T90
Test name
Test status
Simulation time 35480111517 ps
CPU time 182.16 seconds
Started Aug 01 06:00:04 PM PDT 24
Finished Aug 01 06:03:58 PM PDT 24
Peak memory 265044 kb
Host smart-b698b0a7-c137-48b1-88cf-8c56dc9b46fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430825534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.2430825534
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2675156684
Short name T295
Test name
Test status
Simulation time 56788136 ps
CPU time 3.12 seconds
Started Aug 01 06:28:26 PM PDT 24
Finished Aug 01 06:28:29 PM PDT 24
Peak memory 238788 kb
Host smart-5c869cb6-eb6e-4a41-8259-120c2746913c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675156684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.2675156684
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1531538356
Short name T306
Test name
Test status
Simulation time 147463691 ps
CPU time 5.97 seconds
Started Aug 01 06:28:26 PM PDT 24
Finished Aug 01 06:28:32 PM PDT 24
Peak memory 238800 kb
Host smart-217541ef-14cd-4950-868a-d3c784dfcc5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531538356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.1531538356
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.999700665
Short name T304
Test name
Test status
Simulation time 134345428 ps
CPU time 1.88 seconds
Started Aug 01 06:28:25 PM PDT 24
Finished Aug 01 06:28:27 PM PDT 24
Peak memory 238808 kb
Host smart-8d52b9bc-07af-4cd3-9586-c589a498e945
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999700665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_re
set.999700665
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3600146224
Short name T1248
Test name
Test status
Simulation time 65460469 ps
CPU time 2.23 seconds
Started Aug 01 06:28:34 PM PDT 24
Finished Aug 01 06:28:36 PM PDT 24
Peak memory 245972 kb
Host smart-e82c957a-0495-4290-9491-2f0f8c826a69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600146224 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.3600146224
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1417188425
Short name T1207
Test name
Test status
Simulation time 68630202 ps
CPU time 1.54 seconds
Started Aug 01 06:28:26 PM PDT 24
Finished Aug 01 06:28:28 PM PDT 24
Peak memory 241016 kb
Host smart-c0866c68-6eef-4cfb-8bff-1abc009bdbf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417188425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1417188425
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.990156958
Short name T1202
Test name
Test status
Simulation time 567454475 ps
CPU time 1.72 seconds
Started Aug 01 06:28:27 PM PDT 24
Finished Aug 01 06:28:29 PM PDT 24
Peak memory 229816 kb
Host smart-8406054e-f3bd-4e60-b3c6-69702e89f49c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990156958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.990156958
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1588425718
Short name T1197
Test name
Test status
Simulation time 38058447 ps
CPU time 1.43 seconds
Started Aug 01 06:28:27 PM PDT 24
Finished Aug 01 06:28:29 PM PDT 24
Peak memory 229608 kb
Host smart-3edcc3ec-a4a4-493f-ae74-dd06d77093c7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588425718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.1588425718
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3278107699
Short name T1214
Test name
Test status
Simulation time 132563034 ps
CPU time 1.46 seconds
Started Aug 01 06:28:27 PM PDT 24
Finished Aug 01 06:28:29 PM PDT 24
Peak memory 229772 kb
Host smart-a8bb859c-20c7-447d-ab5a-a410d952ba9e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278107699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.3278107699
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.3485601842
Short name T311
Test name
Test status
Simulation time 140500585 ps
CPU time 2.32 seconds
Started Aug 01 06:28:28 PM PDT 24
Finished Aug 01 06:28:30 PM PDT 24
Peak memory 238812 kb
Host smart-d1e32b36-5c54-46ae-9837-d459619991a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485601842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.3485601842
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1501520167
Short name T1285
Test name
Test status
Simulation time 184085729 ps
CPU time 5.52 seconds
Started Aug 01 06:28:28 PM PDT 24
Finished Aug 01 06:28:34 PM PDT 24
Peak memory 246112 kb
Host smart-eb22b0a1-4eb5-4084-aa32-71d54c530936
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501520167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.1501520167
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1519423349
Short name T1258
Test name
Test status
Simulation time 10276018781 ps
CPU time 13.89 seconds
Started Aug 01 06:28:28 PM PDT 24
Finished Aug 01 06:28:42 PM PDT 24
Peak memory 244220 kb
Host smart-47480a67-8865-4a3f-b965-d20b7200b13c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519423349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.1519423349
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.4023047888
Short name T303
Test name
Test status
Simulation time 287177344 ps
CPU time 6.09 seconds
Started Aug 01 06:28:33 PM PDT 24
Finished Aug 01 06:28:39 PM PDT 24
Peak memory 238824 kb
Host smart-9398b466-bcff-45e7-b857-894fd70e00e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023047888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.4023047888
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.918443744
Short name T1213
Test name
Test status
Simulation time 741547927 ps
CPU time 5.63 seconds
Started Aug 01 06:28:30 PM PDT 24
Finished Aug 01 06:28:36 PM PDT 24
Peak memory 238780 kb
Host smart-94330700-5852-4764-a071-5631c4bf32b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918443744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_b
ash.918443744
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3340203996
Short name T302
Test name
Test status
Simulation time 65780085 ps
CPU time 1.73 seconds
Started Aug 01 06:28:34 PM PDT 24
Finished Aug 01 06:28:36 PM PDT 24
Peak memory 240416 kb
Host smart-7f3a48f5-32c4-4ee6-85d4-1c729008be99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340203996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.3340203996
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.691695810
Short name T1215
Test name
Test status
Simulation time 109965242 ps
CPU time 3.6 seconds
Started Aug 01 06:28:30 PM PDT 24
Finished Aug 01 06:28:33 PM PDT 24
Peak memory 247036 kb
Host smart-7fa9143c-f199-4098-b7a1-a010ebabfb36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691695810 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.691695810
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1689819555
Short name T1291
Test name
Test status
Simulation time 143053755 ps
CPU time 1.75 seconds
Started Aug 01 06:28:33 PM PDT 24
Finished Aug 01 06:28:35 PM PDT 24
Peak memory 240568 kb
Host smart-de322228-efda-4c04-ac7a-56a5646369fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689819555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1689819555
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3342766820
Short name T1305
Test name
Test status
Simulation time 544716315 ps
CPU time 1.37 seconds
Started Aug 01 06:28:32 PM PDT 24
Finished Aug 01 06:28:34 PM PDT 24
Peak memory 230196 kb
Host smart-9ebe90f9-a33c-42ca-b000-fd92d97a5e4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342766820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3342766820
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.1992501742
Short name T1216
Test name
Test status
Simulation time 128235122 ps
CPU time 1.32 seconds
Started Aug 01 06:28:29 PM PDT 24
Finished Aug 01 06:28:31 PM PDT 24
Peak memory 229884 kb
Host smart-67450905-402b-4785-8fe5-69456fa5e064
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992501742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.1992501742
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1433097292
Short name T1307
Test name
Test status
Simulation time 134594491 ps
CPU time 1.36 seconds
Started Aug 01 06:28:34 PM PDT 24
Finished Aug 01 06:28:35 PM PDT 24
Peak memory 230096 kb
Host smart-079da2a1-dfbc-41f9-8aa6-6f7ce4ec8d89
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433097292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.1433097292
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2561991761
Short name T1287
Test name
Test status
Simulation time 91730632 ps
CPU time 2.46 seconds
Started Aug 01 06:28:31 PM PDT 24
Finished Aug 01 06:28:34 PM PDT 24
Peak memory 238796 kb
Host smart-10fe6aad-03da-406a-ab50-115c0c5e25ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561991761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.2561991761
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.172981445
Short name T1243
Test name
Test status
Simulation time 119974590 ps
CPU time 5.15 seconds
Started Aug 01 06:28:35 PM PDT 24
Finished Aug 01 06:28:41 PM PDT 24
Peak memory 238896 kb
Host smart-a0a14ae3-7abb-4c1c-97dc-fb5a1b58c807
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172981445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.172981445
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2616057839
Short name T349
Test name
Test status
Simulation time 696308899 ps
CPU time 10.95 seconds
Started Aug 01 06:28:31 PM PDT 24
Finished Aug 01 06:28:42 PM PDT 24
Peak memory 238820 kb
Host smart-d7c10cac-3673-41e7-ba6c-89419d823ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616057839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.2616057839
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2450850538
Short name T1270
Test name
Test status
Simulation time 72598903 ps
CPU time 2.11 seconds
Started Aug 01 06:28:54 PM PDT 24
Finished Aug 01 06:28:56 PM PDT 24
Peak memory 244252 kb
Host smart-1f1a9e77-10eb-458f-8501-508aca1ef7c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450850538 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.2450850538
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1560830384
Short name T1315
Test name
Test status
Simulation time 600335380 ps
CPU time 1.83 seconds
Started Aug 01 06:28:52 PM PDT 24
Finished Aug 01 06:28:54 PM PDT 24
Peak memory 238780 kb
Host smart-ce647252-9fc7-4fd2-bed4-5a576ffe7c33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560830384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.1560830384
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3250740737
Short name T1290
Test name
Test status
Simulation time 105462295 ps
CPU time 1.62 seconds
Started Aug 01 06:28:54 PM PDT 24
Finished Aug 01 06:28:56 PM PDT 24
Peak memory 230108 kb
Host smart-3f5fcdb6-9ebf-47e0-b45f-98c7a7605053
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250740737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.3250740737
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1038596960
Short name T318
Test name
Test status
Simulation time 64310147 ps
CPU time 2.13 seconds
Started Aug 01 06:28:54 PM PDT 24
Finished Aug 01 06:28:56 PM PDT 24
Peak memory 241996 kb
Host smart-41702847-9e2c-4b63-900e-76acdda87062
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038596960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.1038596960
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.400129636
Short name T1201
Test name
Test status
Simulation time 561419991 ps
CPU time 7.2 seconds
Started Aug 01 06:28:53 PM PDT 24
Finished Aug 01 06:29:00 PM PDT 24
Peak memory 246124 kb
Host smart-cd741d7a-8b16-4c07-9129-d161574f861c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400129636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.400129636
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.928454222
Short name T1263
Test name
Test status
Simulation time 68213378 ps
CPU time 2 seconds
Started Aug 01 06:28:52 PM PDT 24
Finished Aug 01 06:28:54 PM PDT 24
Peak memory 244868 kb
Host smart-a5a4ce4c-3bff-4758-95f8-3669879857a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928454222 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.928454222
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3638283746
Short name T298
Test name
Test status
Simulation time 55908838 ps
CPU time 1.56 seconds
Started Aug 01 06:28:54 PM PDT 24
Finished Aug 01 06:28:56 PM PDT 24
Peak memory 238792 kb
Host smart-13107fca-e1ca-45cd-a6d3-0d180ce12e67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638283746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.3638283746
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2587939517
Short name T1211
Test name
Test status
Simulation time 117697314 ps
CPU time 1.42 seconds
Started Aug 01 06:29:01 PM PDT 24
Finished Aug 01 06:29:03 PM PDT 24
Peak memory 229912 kb
Host smart-0bbb4487-cf95-4473-98c7-e711eddd9846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587939517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2587939517
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.692509010
Short name T1272
Test name
Test status
Simulation time 64046707 ps
CPU time 2.26 seconds
Started Aug 01 06:28:53 PM PDT 24
Finished Aug 01 06:28:56 PM PDT 24
Peak memory 238660 kb
Host smart-2edd45f4-1625-418f-b844-3baa113e0ef5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692509010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_c
trl_same_csr_outstanding.692509010
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1286544954
Short name T1292
Test name
Test status
Simulation time 1629965659 ps
CPU time 6.64 seconds
Started Aug 01 06:28:54 PM PDT 24
Finished Aug 01 06:29:00 PM PDT 24
Peak memory 246156 kb
Host smart-8eb0f700-7be9-4bdd-b720-3ea174848d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286544954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.1286544954
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2867733539
Short name T1276
Test name
Test status
Simulation time 109885391 ps
CPU time 3.21 seconds
Started Aug 01 06:29:02 PM PDT 24
Finished Aug 01 06:29:05 PM PDT 24
Peak memory 246308 kb
Host smart-3d3f37a3-c78e-4a76-b750-dca0de10595c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867733539 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.2867733539
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.654496216
Short name T1254
Test name
Test status
Simulation time 72931751 ps
CPU time 1.7 seconds
Started Aug 01 06:29:02 PM PDT 24
Finished Aug 01 06:29:04 PM PDT 24
Peak memory 241408 kb
Host smart-f8117e7c-be29-4d86-a115-cf3b6cfb02ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654496216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.654496216
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.387015850
Short name T1302
Test name
Test status
Simulation time 43215465 ps
CPU time 1.56 seconds
Started Aug 01 06:28:55 PM PDT 24
Finished Aug 01 06:28:56 PM PDT 24
Peak memory 229856 kb
Host smart-f6769c6f-b198-4d07-b6dc-33c979168548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387015850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.387015850
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1545422059
Short name T1313
Test name
Test status
Simulation time 234862328 ps
CPU time 3.54 seconds
Started Aug 01 06:29:01 PM PDT 24
Finished Aug 01 06:29:05 PM PDT 24
Peak memory 238796 kb
Host smart-88e1efd1-a49e-4010-9d64-46d0bdaf459c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545422059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.1545422059
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3136830273
Short name T1253
Test name
Test status
Simulation time 472234490 ps
CPU time 5.44 seconds
Started Aug 01 06:28:53 PM PDT 24
Finished Aug 01 06:28:58 PM PDT 24
Peak memory 246888 kb
Host smart-48d5500a-3e21-4181-a084-60caab66ce16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136830273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3136830273
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2781717440
Short name T350
Test name
Test status
Simulation time 2561997806 ps
CPU time 18.11 seconds
Started Aug 01 06:28:59 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 244316 kb
Host smart-237c5b17-6dbd-48fd-abbd-c4e28f649600
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781717440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.2781717440
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.443451329
Short name T1235
Test name
Test status
Simulation time 428700126 ps
CPU time 2.99 seconds
Started Aug 01 06:29:01 PM PDT 24
Finished Aug 01 06:29:04 PM PDT 24
Peak memory 247044 kb
Host smart-ba0106ed-f1d9-4d34-b5c1-19b251fcfdee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443451329 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.443451329
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3703222459
Short name T296
Test name
Test status
Simulation time 598068803 ps
CPU time 1.94 seconds
Started Aug 01 06:28:51 PM PDT 24
Finished Aug 01 06:28:53 PM PDT 24
Peak memory 238768 kb
Host smart-74515f16-77a6-4ca2-8aae-25459971cb52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703222459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.3703222459
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2465434689
Short name T1261
Test name
Test status
Simulation time 89910056 ps
CPU time 1.41 seconds
Started Aug 01 06:28:56 PM PDT 24
Finished Aug 01 06:28:58 PM PDT 24
Peak memory 229872 kb
Host smart-d9c39eb9-dd02-44e8-910b-1a87b0e35528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465434689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.2465434689
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1775627586
Short name T315
Test name
Test status
Simulation time 84244724 ps
CPU time 2.81 seconds
Started Aug 01 06:28:57 PM PDT 24
Finished Aug 01 06:29:00 PM PDT 24
Peak memory 238788 kb
Host smart-7b1a7057-d995-4e61-b1bb-6586d338d1d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775627586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.1775627586
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3662146453
Short name T1275
Test name
Test status
Simulation time 156517161 ps
CPU time 5.64 seconds
Started Aug 01 06:29:01 PM PDT 24
Finished Aug 01 06:29:07 PM PDT 24
Peak memory 246900 kb
Host smart-f59bdcc9-3815-4d3c-9ee5-15f2f9f3beed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662146453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3662146453
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1447358020
Short name T1281
Test name
Test status
Simulation time 4544422148 ps
CPU time 23.12 seconds
Started Aug 01 06:28:59 PM PDT 24
Finished Aug 01 06:29:23 PM PDT 24
Peak memory 238880 kb
Host smart-f6eed47d-e690-46f8-b4f5-bc232807b4c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447358020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.1447358020
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2266982770
Short name T1303
Test name
Test status
Simulation time 166480555 ps
CPU time 3.57 seconds
Started Aug 01 06:28:52 PM PDT 24
Finished Aug 01 06:28:56 PM PDT 24
Peak memory 247080 kb
Host smart-26114134-75a5-468c-affd-f7b532e6d012
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266982770 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.2266982770
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.87002725
Short name T1309
Test name
Test status
Simulation time 137874411 ps
CPU time 1.51 seconds
Started Aug 01 06:28:54 PM PDT 24
Finished Aug 01 06:28:55 PM PDT 24
Peak memory 240612 kb
Host smart-e0213702-bfd1-480d-b149-6a47c6bea731
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87002725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.87002725
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1900179429
Short name T1271
Test name
Test status
Simulation time 44182035 ps
CPU time 1.45 seconds
Started Aug 01 06:29:01 PM PDT 24
Finished Aug 01 06:29:03 PM PDT 24
Peak memory 229936 kb
Host smart-cd058a9f-0367-4764-bc85-38c048b3aae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900179429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.1900179429
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2020855792
Short name T316
Test name
Test status
Simulation time 133186324 ps
CPU time 3.52 seconds
Started Aug 01 06:29:02 PM PDT 24
Finished Aug 01 06:29:05 PM PDT 24
Peak memory 238744 kb
Host smart-682651d6-3e72-4040-aa9b-5d5acfbd6362
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020855792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.2020855792
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1091289228
Short name T1219
Test name
Test status
Simulation time 188704460 ps
CPU time 4.77 seconds
Started Aug 01 06:28:53 PM PDT 24
Finished Aug 01 06:28:58 PM PDT 24
Peak memory 245860 kb
Host smart-55f0850b-4226-47ca-bc5e-26132fa17d49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091289228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.1091289228
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3393564180
Short name T1220
Test name
Test status
Simulation time 406128672 ps
CPU time 2.61 seconds
Started Aug 01 06:29:06 PM PDT 24
Finished Aug 01 06:29:09 PM PDT 24
Peak memory 246876 kb
Host smart-2770f766-f313-49d6-8a69-d2011687d15a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393564180 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.3393564180
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.4249073922
Short name T1225
Test name
Test status
Simulation time 41249384 ps
CPU time 1.53 seconds
Started Aug 01 06:29:03 PM PDT 24
Finished Aug 01 06:29:05 PM PDT 24
Peak memory 230180 kb
Host smart-d134dba0-f961-4f8f-abee-6bab122c6adb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249073922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.4249073922
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.736017446
Short name T1266
Test name
Test status
Simulation time 1109384697 ps
CPU time 3.72 seconds
Started Aug 01 06:29:02 PM PDT 24
Finished Aug 01 06:29:06 PM PDT 24
Peak memory 241816 kb
Host smart-347775f4-294e-4a17-9678-dcde2a1ce5b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736017446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_c
trl_same_csr_outstanding.736017446
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.234795505
Short name T1277
Test name
Test status
Simulation time 161951358 ps
CPU time 3.33 seconds
Started Aug 01 06:28:52 PM PDT 24
Finished Aug 01 06:28:56 PM PDT 24
Peak memory 245712 kb
Host smart-ca90d73c-e7dd-40a8-a2e7-ef577d449098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234795505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.234795505
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1698279232
Short name T1204
Test name
Test status
Simulation time 103371979 ps
CPU time 3.4 seconds
Started Aug 01 06:29:06 PM PDT 24
Finished Aug 01 06:29:09 PM PDT 24
Peak memory 247060 kb
Host smart-5b914c4f-e95e-450a-a956-c47e4e697079
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698279232 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.1698279232
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3168162457
Short name T1194
Test name
Test status
Simulation time 40093658 ps
CPU time 1.43 seconds
Started Aug 01 06:29:03 PM PDT 24
Finished Aug 01 06:29:05 PM PDT 24
Peak memory 229976 kb
Host smart-a0706997-4125-4c8e-8170-8e660f9ccd7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168162457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3168162457
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3663196521
Short name T319
Test name
Test status
Simulation time 237734014 ps
CPU time 2.46 seconds
Started Aug 01 06:29:04 PM PDT 24
Finished Aug 01 06:29:06 PM PDT 24
Peak memory 241828 kb
Host smart-cdd4801b-20ca-4427-aaad-0b99dfe6735b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663196521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.3663196521
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3811372016
Short name T1245
Test name
Test status
Simulation time 758404429 ps
CPU time 7.36 seconds
Started Aug 01 06:29:04 PM PDT 24
Finished Aug 01 06:29:12 PM PDT 24
Peak memory 246276 kb
Host smart-a58fa55c-aa8b-45d3-8fab-797d8094c3b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811372016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.3811372016
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2075987843
Short name T354
Test name
Test status
Simulation time 658788643 ps
CPU time 10.55 seconds
Started Aug 01 06:29:03 PM PDT 24
Finished Aug 01 06:29:14 PM PDT 24
Peak memory 243656 kb
Host smart-bd839b7e-a9e7-4661-82de-06d9086577e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075987843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.2075987843
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3944013155
Short name T1209
Test name
Test status
Simulation time 1637668713 ps
CPU time 3.92 seconds
Started Aug 01 06:29:03 PM PDT 24
Finished Aug 01 06:29:07 PM PDT 24
Peak memory 246928 kb
Host smart-684cf421-75bb-476e-a857-b138ae9b6bb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944013155 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.3944013155
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3289661929
Short name T1224
Test name
Test status
Simulation time 151950711 ps
CPU time 1.66 seconds
Started Aug 01 06:29:03 PM PDT 24
Finished Aug 01 06:29:05 PM PDT 24
Peak memory 238744 kb
Host smart-e2d6abc0-38c9-48ae-a03b-6c6e3d37874f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289661929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3289661929
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2321653485
Short name T1247
Test name
Test status
Simulation time 122200510 ps
CPU time 1.37 seconds
Started Aug 01 06:29:14 PM PDT 24
Finished Aug 01 06:29:15 PM PDT 24
Peak memory 230180 kb
Host smart-46c0b247-3d9b-414c-852c-cbdd61a5b2d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321653485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.2321653485
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1678132376
Short name T1223
Test name
Test status
Simulation time 317387720 ps
CPU time 3.19 seconds
Started Aug 01 06:29:06 PM PDT 24
Finished Aug 01 06:29:10 PM PDT 24
Peak memory 238736 kb
Host smart-d56e0490-890d-429e-b04c-3801ab3ab1fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678132376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.1678132376
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3773812406
Short name T1279
Test name
Test status
Simulation time 70935418 ps
CPU time 3.15 seconds
Started Aug 01 06:29:04 PM PDT 24
Finished Aug 01 06:29:08 PM PDT 24
Peak memory 238852 kb
Host smart-700da7f6-0c5a-47cc-a9c3-e677ddcc8454
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773812406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.3773812406
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3113577376
Short name T351
Test name
Test status
Simulation time 1580642356 ps
CPU time 20.32 seconds
Started Aug 01 06:29:03 PM PDT 24
Finished Aug 01 06:29:23 PM PDT 24
Peak memory 244796 kb
Host smart-9c47f3fa-885d-4c3d-8046-c337a852f3dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113577376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.3113577376
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1185503330
Short name T1262
Test name
Test status
Simulation time 1657071541 ps
CPU time 4.78 seconds
Started Aug 01 06:29:19 PM PDT 24
Finished Aug 01 06:29:24 PM PDT 24
Peak memory 247044 kb
Host smart-5b2816aa-572f-44e9-b3ad-731ec88cf08d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185503330 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.1185503330
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1429219287
Short name T314
Test name
Test status
Simulation time 76360429 ps
CPU time 1.66 seconds
Started Aug 01 06:29:14 PM PDT 24
Finished Aug 01 06:29:16 PM PDT 24
Peak memory 240476 kb
Host smart-f480a836-3d75-4cdf-bff7-218fa91d1903
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429219287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.1429219287
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1281543662
Short name T1289
Test name
Test status
Simulation time 73974098 ps
CPU time 1.55 seconds
Started Aug 01 06:29:18 PM PDT 24
Finished Aug 01 06:29:20 PM PDT 24
Peak memory 229868 kb
Host smart-c56b7b87-7296-42b8-83f8-a48e2a2d4715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281543662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.1281543662
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1404963091
Short name T317
Test name
Test status
Simulation time 854674473 ps
CPU time 2.67 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 238760 kb
Host smart-6e0016db-f934-4c26-bdf8-e57975345164
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404963091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.1404963091
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.584887868
Short name T1318
Test name
Test status
Simulation time 77343048 ps
CPU time 5.07 seconds
Started Aug 01 06:29:05 PM PDT 24
Finished Aug 01 06:29:10 PM PDT 24
Peak memory 238896 kb
Host smart-eba877b5-a47e-460d-8b10-3a9f0d32d109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584887868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.584887868
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1111349529
Short name T355
Test name
Test status
Simulation time 1981593740 ps
CPU time 23.57 seconds
Started Aug 01 06:29:05 PM PDT 24
Finished Aug 01 06:29:29 PM PDT 24
Peak memory 244052 kb
Host smart-88fe71a7-6523-4dd1-bd3c-ef215310b96d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111349529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.1111349529
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3121630657
Short name T1230
Test name
Test status
Simulation time 229902243 ps
CPU time 3.77 seconds
Started Aug 01 06:29:19 PM PDT 24
Finished Aug 01 06:29:23 PM PDT 24
Peak memory 247036 kb
Host smart-760c8099-b6bd-4b63-8505-f47f8d926a99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121630657 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.3121630657
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.367724382
Short name T301
Test name
Test status
Simulation time 676332365 ps
CPU time 2.09 seconds
Started Aug 01 06:29:17 PM PDT 24
Finished Aug 01 06:29:19 PM PDT 24
Peak memory 241332 kb
Host smart-598846a5-ed1c-4b54-a293-39f5e6e73891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367724382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.367724382
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.421025480
Short name T1316
Test name
Test status
Simulation time 79326303 ps
CPU time 1.54 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 229888 kb
Host smart-3cc407ff-efef-42b1-aadb-d46cd5aae1d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421025480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.421025480
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3708100031
Short name T1241
Test name
Test status
Simulation time 64375316 ps
CPU time 2.19 seconds
Started Aug 01 06:29:16 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 238748 kb
Host smart-c62ad6a8-c61d-4566-b3fc-6c9d21ffbee7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708100031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.3708100031
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.521223157
Short name T1193
Test name
Test status
Simulation time 144897611 ps
CPU time 6.04 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:22 PM PDT 24
Peak memory 245932 kb
Host smart-a32f4055-8fd2-4686-a812-6b4872821fc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521223157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.521223157
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.2784075855
Short name T300
Test name
Test status
Simulation time 1207828006 ps
CPU time 4.63 seconds
Started Aug 01 06:28:32 PM PDT 24
Finished Aug 01 06:28:37 PM PDT 24
Peak memory 238716 kb
Host smart-6a8c4ba3-dbf3-45db-a8cf-987e16150243
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784075855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.2784075855
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.848262315
Short name T299
Test name
Test status
Simulation time 8082300625 ps
CPU time 12.45 seconds
Started Aug 01 06:28:29 PM PDT 24
Finished Aug 01 06:28:42 PM PDT 24
Peak memory 238864 kb
Host smart-aa37d456-df9a-4949-b1ec-d6aea98acfb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848262315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_b
ash.848262315
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2105584086
Short name T297
Test name
Test status
Simulation time 75118023 ps
CPU time 2.06 seconds
Started Aug 01 06:28:34 PM PDT 24
Finished Aug 01 06:28:36 PM PDT 24
Peak memory 240328 kb
Host smart-2fe33a90-3007-476f-83e1-7ebdd20cb58d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105584086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.2105584086
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3728095450
Short name T1293
Test name
Test status
Simulation time 74326049 ps
CPU time 2.03 seconds
Started Aug 01 06:28:31 PM PDT 24
Finished Aug 01 06:28:33 PM PDT 24
Peak memory 244152 kb
Host smart-7ed9dd2b-8184-4bba-8c98-7cc2780b6583
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728095450 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.3728095450
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.118530972
Short name T310
Test name
Test status
Simulation time 140630321 ps
CPU time 1.69 seconds
Started Aug 01 06:28:32 PM PDT 24
Finished Aug 01 06:28:34 PM PDT 24
Peak memory 238780 kb
Host smart-d96f0c00-34f2-4c7c-af0e-78467ac128d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118530972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.118530972
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.1770518371
Short name T1298
Test name
Test status
Simulation time 141291838 ps
CPU time 1.5 seconds
Started Aug 01 06:28:32 PM PDT 24
Finished Aug 01 06:28:34 PM PDT 24
Peak memory 230604 kb
Host smart-7003b02b-7938-492e-bed5-12c6e3254334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770518371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.1770518371
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1349970158
Short name T1308
Test name
Test status
Simulation time 45647686 ps
CPU time 1.33 seconds
Started Aug 01 06:28:33 PM PDT 24
Finished Aug 01 06:28:35 PM PDT 24
Peak memory 230408 kb
Host smart-5ca9bca7-42b5-412c-a8c2-211cd453ac90
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349970158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.1349970158
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2283913844
Short name T1195
Test name
Test status
Simulation time 68668166 ps
CPU time 1.38 seconds
Started Aug 01 06:28:30 PM PDT 24
Finished Aug 01 06:28:31 PM PDT 24
Peak memory 229664 kb
Host smart-552219ea-b236-41aa-bd70-bdc8783b53cb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283913844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.2283913844
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.341622390
Short name T260
Test name
Test status
Simulation time 68824493 ps
CPU time 2.28 seconds
Started Aug 01 06:28:33 PM PDT 24
Finished Aug 01 06:28:35 PM PDT 24
Peak memory 238768 kb
Host smart-98226635-61d8-44ab-804e-5b3e4b85cd6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341622390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ct
rl_same_csr_outstanding.341622390
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.1504417380
Short name T1233
Test name
Test status
Simulation time 2810820767 ps
CPU time 7.19 seconds
Started Aug 01 06:28:33 PM PDT 24
Finished Aug 01 06:28:41 PM PDT 24
Peak memory 238936 kb
Host smart-e143bfe2-2671-437f-a9d9-e809c7029e19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504417380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.1504417380
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1729232798
Short name T258
Test name
Test status
Simulation time 18813707471 ps
CPU time 44.75 seconds
Started Aug 01 06:28:33 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 244500 kb
Host smart-4b59a167-11dc-4346-8d24-c3d474375840
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729232798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.1729232798
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.86387385
Short name T1227
Test name
Test status
Simulation time 526356128 ps
CPU time 1.47 seconds
Started Aug 01 06:29:14 PM PDT 24
Finished Aug 01 06:29:16 PM PDT 24
Peak memory 230600 kb
Host smart-bd19a03d-7b78-4046-b842-7f025466d694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86387385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.86387385
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.1521034279
Short name T1311
Test name
Test status
Simulation time 38789800 ps
CPU time 1.49 seconds
Started Aug 01 06:29:16 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 230644 kb
Host smart-3f057935-ba01-4142-8feb-3dc4012a5867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521034279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.1521034279
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2286247179
Short name T1192
Test name
Test status
Simulation time 78599208 ps
CPU time 1.37 seconds
Started Aug 01 06:29:14 PM PDT 24
Finished Aug 01 06:29:15 PM PDT 24
Peak memory 229864 kb
Host smart-347fb234-f684-474f-bceb-27e3856f4bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286247179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.2286247179
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2571998121
Short name T1196
Test name
Test status
Simulation time 78929709 ps
CPU time 1.51 seconds
Started Aug 01 06:29:14 PM PDT 24
Finished Aug 01 06:29:16 PM PDT 24
Peak memory 229904 kb
Host smart-1e3aa81c-ce0a-49c0-a072-1af5ec1b1e5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571998121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.2571998121
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2582903544
Short name T1284
Test name
Test status
Simulation time 550669639 ps
CPU time 1.94 seconds
Started Aug 01 06:29:17 PM PDT 24
Finished Aug 01 06:29:19 PM PDT 24
Peak memory 229804 kb
Host smart-c1372d83-fd9b-4fd5-9134-de476f9ae132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582903544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2582903544
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1403445047
Short name T1238
Test name
Test status
Simulation time 43040943 ps
CPU time 1.42 seconds
Started Aug 01 06:29:14 PM PDT 24
Finished Aug 01 06:29:16 PM PDT 24
Peak memory 229852 kb
Host smart-e83bc713-2c30-4149-a5ad-c2cf69bd8658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403445047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1403445047
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.1574681773
Short name T1283
Test name
Test status
Simulation time 515117108 ps
CPU time 1.96 seconds
Started Aug 01 06:29:16 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 229836 kb
Host smart-790fd09c-6c70-4bc8-864d-b79e5a762785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574681773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1574681773
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.4165384414
Short name T1242
Test name
Test status
Simulation time 61483389 ps
CPU time 1.42 seconds
Started Aug 01 06:29:16 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 230164 kb
Host smart-ea982408-b83b-43f9-b9d0-1c9a836480d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165384414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.4165384414
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.3987572054
Short name T1221
Test name
Test status
Simulation time 42874884 ps
CPU time 1.43 seconds
Started Aug 01 06:29:16 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 230612 kb
Host smart-9d14090c-0e2e-4bbe-afd9-b0958f419c1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987572054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.3987572054
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2408400035
Short name T1269
Test name
Test status
Simulation time 81407411 ps
CPU time 1.41 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:16 PM PDT 24
Peak memory 230064 kb
Host smart-628b0cb3-920d-4e68-a2cd-95a1383d28fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408400035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2408400035
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.106494588
Short name T280
Test name
Test status
Simulation time 255885919 ps
CPU time 3.7 seconds
Started Aug 01 06:28:32 PM PDT 24
Finished Aug 01 06:28:36 PM PDT 24
Peak memory 238744 kb
Host smart-a33e418a-2d13-4eb5-a276-f0e3819ac230
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106494588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alias
ing.106494588
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3998117523
Short name T259
Test name
Test status
Simulation time 6790750894 ps
CPU time 19.13 seconds
Started Aug 01 06:28:33 PM PDT 24
Finished Aug 01 06:28:52 PM PDT 24
Peak memory 240568 kb
Host smart-9e33ad21-d432-4e9d-821e-8ffff15a1bc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998117523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.3998117523
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3678958959
Short name T1310
Test name
Test status
Simulation time 1034427597 ps
CPU time 2.49 seconds
Started Aug 01 06:28:34 PM PDT 24
Finished Aug 01 06:28:37 PM PDT 24
Peak memory 238828 kb
Host smart-ca21e113-25cb-4a4e-92d1-1ebf9b2795f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678958959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.3678958959
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.278394903
Short name T1317
Test name
Test status
Simulation time 379667009 ps
CPU time 3.11 seconds
Started Aug 01 06:28:30 PM PDT 24
Finished Aug 01 06:28:33 PM PDT 24
Peak memory 247020 kb
Host smart-e7cf3e41-cde0-426c-9544-d46a93b53003
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278394903 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.278394903
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.1127710776
Short name T305
Test name
Test status
Simulation time 143822021 ps
CPU time 1.8 seconds
Started Aug 01 06:28:32 PM PDT 24
Finished Aug 01 06:28:34 PM PDT 24
Peak memory 240568 kb
Host smart-bae86ff2-31a5-4bd7-a4cf-97db1705b480
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127710776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.1127710776
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3709897321
Short name T1314
Test name
Test status
Simulation time 79035031 ps
CPU time 1.34 seconds
Started Aug 01 06:28:30 PM PDT 24
Finished Aug 01 06:28:31 PM PDT 24
Peak memory 230548 kb
Host smart-1d0d8760-9472-4431-bcee-386dc26fc1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709897321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.3709897321
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1264566218
Short name T1297
Test name
Test status
Simulation time 37096774 ps
CPU time 1.39 seconds
Started Aug 01 06:28:33 PM PDT 24
Finished Aug 01 06:28:35 PM PDT 24
Peak memory 229588 kb
Host smart-4da1f444-b16a-457e-9ad4-aa7a863bc621
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264566218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.1264566218
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2429303303
Short name T1228
Test name
Test status
Simulation time 39742728 ps
CPU time 1.36 seconds
Started Aug 01 06:28:34 PM PDT 24
Finished Aug 01 06:28:35 PM PDT 24
Peak memory 229636 kb
Host smart-6f78478e-18a5-4e6b-b205-3658a6f0419b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429303303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.2429303303
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.108288526
Short name T1267
Test name
Test status
Simulation time 1850556623 ps
CPU time 6.75 seconds
Started Aug 01 06:28:34 PM PDT 24
Finished Aug 01 06:28:41 PM PDT 24
Peak memory 238804 kb
Host smart-cd614bb9-5742-41e7-b55f-b5bb651e7a31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108288526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ct
rl_same_csr_outstanding.108288526
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3388772013
Short name T1306
Test name
Test status
Simulation time 202934986 ps
CPU time 3.01 seconds
Started Aug 01 06:28:32 PM PDT 24
Finished Aug 01 06:28:35 PM PDT 24
Peak memory 245560 kb
Host smart-90392654-9233-46e0-a981-c036f8941f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388772013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.3388772013
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.292523536
Short name T1319
Test name
Test status
Simulation time 631407008 ps
CPU time 10.06 seconds
Started Aug 01 06:28:33 PM PDT 24
Finished Aug 01 06:28:43 PM PDT 24
Peak memory 243468 kb
Host smart-9131a0bc-daa5-4e7b-90a5-049f56741148
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292523536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_int
g_err.292523536
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1325784991
Short name T1217
Test name
Test status
Simulation time 568225990 ps
CPU time 1.95 seconds
Started Aug 01 06:29:18 PM PDT 24
Finished Aug 01 06:29:20 PM PDT 24
Peak memory 229848 kb
Host smart-ba42bdd9-52dc-40cc-af12-e3d2245a998a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325784991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1325784991
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.85094454
Short name T1239
Test name
Test status
Simulation time 144443498 ps
CPU time 1.44 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 230580 kb
Host smart-7b053268-9275-41f9-a7e5-13de832ed980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85094454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.85094454
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.661747482
Short name T1249
Test name
Test status
Simulation time 63201609 ps
CPU time 1.51 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:16 PM PDT 24
Peak memory 229788 kb
Host smart-5f35834f-8cde-42f6-bc40-06718158dc09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661747482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.661747482
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.3801938431
Short name T1200
Test name
Test status
Simulation time 36210701 ps
CPU time 1.35 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 229868 kb
Host smart-25655cb0-d486-43b0-b004-45e990503484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801938431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.3801938431
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2126538764
Short name T1252
Test name
Test status
Simulation time 73999809 ps
CPU time 1.54 seconds
Started Aug 01 06:29:18 PM PDT 24
Finished Aug 01 06:29:20 PM PDT 24
Peak memory 229920 kb
Host smart-804130eb-bfd0-42d2-9a2d-b025a6aac9f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126538764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.2126538764
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.1746753766
Short name T1259
Test name
Test status
Simulation time 139672120 ps
CPU time 1.48 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:16 PM PDT 24
Peak memory 230612 kb
Host smart-398862c7-a342-42df-b3e7-14c83cc9e2ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746753766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.1746753766
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.2494693352
Short name T1301
Test name
Test status
Simulation time 111095769 ps
CPU time 1.48 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 230564 kb
Host smart-0bc7ce68-cbc8-4423-a598-aeb96bfd3c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494693352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.2494693352
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2762597338
Short name T1190
Test name
Test status
Simulation time 129782051 ps
CPU time 1.37 seconds
Started Aug 01 06:29:16 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 230196 kb
Host smart-e7608ca7-271c-4110-a6bc-88e37f18f4e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762597338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.2762597338
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.686283932
Short name T1256
Test name
Test status
Simulation time 42490364 ps
CPU time 1.42 seconds
Started Aug 01 06:29:16 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 229816 kb
Host smart-88a3cbc7-b455-4055-9811-545003fcfbde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686283932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.686283932
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.1965184286
Short name T1208
Test name
Test status
Simulation time 576062763 ps
CPU time 1.87 seconds
Started Aug 01 06:29:17 PM PDT 24
Finished Aug 01 06:29:19 PM PDT 24
Peak memory 229852 kb
Host smart-ba463461-84d6-4b32-9067-7398d0805a51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965184286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.1965184286
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1164716005
Short name T1260
Test name
Test status
Simulation time 163521258 ps
CPU time 6 seconds
Started Aug 01 06:28:40 PM PDT 24
Finished Aug 01 06:28:47 PM PDT 24
Peak memory 238804 kb
Host smart-f0ea9a5c-2814-4d30-93fb-f3320acb00e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164716005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.1164716005
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1296565006
Short name T279
Test name
Test status
Simulation time 390287625 ps
CPU time 8.53 seconds
Started Aug 01 06:28:44 PM PDT 24
Finished Aug 01 06:28:52 PM PDT 24
Peak memory 238716 kb
Host smart-da6559e1-4dd3-43e5-a063-769c572bbbdb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296565006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.1296565006
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3239847975
Short name T1255
Test name
Test status
Simulation time 186699475 ps
CPU time 2.41 seconds
Started Aug 01 06:28:41 PM PDT 24
Finished Aug 01 06:28:44 PM PDT 24
Peak memory 240664 kb
Host smart-4fbd1a89-3d40-436e-87d5-28e2652ff736
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239847975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.3239847975
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.2909797692
Short name T1205
Test name
Test status
Simulation time 67982347 ps
CPU time 1.89 seconds
Started Aug 01 06:28:40 PM PDT 24
Finished Aug 01 06:28:42 PM PDT 24
Peak memory 244512 kb
Host smart-bb9e246a-9bec-41df-a50d-f47c78b69c71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909797692 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.2909797692
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.217832129
Short name T308
Test name
Test status
Simulation time 117968389 ps
CPU time 1.79 seconds
Started Aug 01 06:28:42 PM PDT 24
Finished Aug 01 06:28:44 PM PDT 24
Peak memory 241120 kb
Host smart-9570112b-f3f9-4b26-a4ec-2371ac7768d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217832129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.217832129
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.158052883
Short name T1203
Test name
Test status
Simulation time 89703731 ps
CPU time 1.37 seconds
Started Aug 01 06:28:44 PM PDT 24
Finished Aug 01 06:28:46 PM PDT 24
Peak memory 229856 kb
Host smart-fcd74d03-d128-45d6-903f-be12742b17b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158052883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.158052883
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3311110136
Short name T1212
Test name
Test status
Simulation time 52638970 ps
CPU time 1.36 seconds
Started Aug 01 06:28:42 PM PDT 24
Finished Aug 01 06:28:44 PM PDT 24
Peak memory 230344 kb
Host smart-02c422ac-5832-4efb-aa29-7edaf4615c14
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311110136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.3311110136
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2767580744
Short name T1198
Test name
Test status
Simulation time 528495523 ps
CPU time 1.48 seconds
Started Aug 01 06:28:41 PM PDT 24
Finished Aug 01 06:28:43 PM PDT 24
Peak memory 230184 kb
Host smart-b468813e-ada7-453c-a0e0-231213bf3a13
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767580744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.2767580744
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3788807453
Short name T1280
Test name
Test status
Simulation time 121971083 ps
CPU time 2.46 seconds
Started Aug 01 06:28:42 PM PDT 24
Finished Aug 01 06:28:44 PM PDT 24
Peak memory 238756 kb
Host smart-f0028c87-bcde-4b94-8aa1-d3ee8f8559af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788807453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.3788807453
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3037104387
Short name T1222
Test name
Test status
Simulation time 1169474179 ps
CPU time 6.59 seconds
Started Aug 01 06:28:29 PM PDT 24
Finished Aug 01 06:28:36 PM PDT 24
Peak memory 246116 kb
Host smart-4a6c9e91-4520-404d-8d3f-29249fbc8efb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037104387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3037104387
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2865346546
Short name T1273
Test name
Test status
Simulation time 626127428 ps
CPU time 9.47 seconds
Started Aug 01 06:28:32 PM PDT 24
Finished Aug 01 06:28:42 PM PDT 24
Peak memory 238852 kb
Host smart-af44acf5-d766-4201-95f6-04f996512235
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865346546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.2865346546
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2046323599
Short name T1265
Test name
Test status
Simulation time 143901846 ps
CPU time 1.45 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 229864 kb
Host smart-23f02322-5675-4bdf-ad91-1039b2a0df09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046323599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2046323599
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.1987124509
Short name T1199
Test name
Test status
Simulation time 80662543 ps
CPU time 1.39 seconds
Started Aug 01 06:29:17 PM PDT 24
Finished Aug 01 06:29:19 PM PDT 24
Peak memory 229908 kb
Host smart-40d57d42-10ca-4974-864d-cf7613c8ee6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987124509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.1987124509
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2090761283
Short name T1304
Test name
Test status
Simulation time 77175457 ps
CPU time 1.31 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 230612 kb
Host smart-4bcee95d-6ded-448a-9b7b-4f28bcedadbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090761283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2090761283
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3760215357
Short name T1278
Test name
Test status
Simulation time 43318329 ps
CPU time 1.46 seconds
Started Aug 01 06:29:17 PM PDT 24
Finished Aug 01 06:29:19 PM PDT 24
Peak memory 230228 kb
Host smart-834320c5-0f71-4e0e-826e-54491064e2bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760215357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3760215357
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.485151014
Short name T1312
Test name
Test status
Simulation time 73632196 ps
CPU time 1.51 seconds
Started Aug 01 06:29:17 PM PDT 24
Finished Aug 01 06:29:19 PM PDT 24
Peak memory 230212 kb
Host smart-7f5d486d-85e9-4f9b-96a4-139b9893b230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485151014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.485151014
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.1583232974
Short name T1232
Test name
Test status
Simulation time 52454176 ps
CPU time 1.4 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 230132 kb
Host smart-343ae79b-eafb-4637-b7db-4a5fc6ca4f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583232974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.1583232974
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2655454154
Short name T1244
Test name
Test status
Simulation time 130464288 ps
CPU time 1.41 seconds
Started Aug 01 06:29:17 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 230588 kb
Host smart-cea1ba9b-dceb-4f98-b37c-b5736e40411a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655454154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2655454154
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.521096886
Short name T1206
Test name
Test status
Simulation time 39520789 ps
CPU time 1.45 seconds
Started Aug 01 06:29:16 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 229848 kb
Host smart-90430b80-ee58-4b94-840e-98208d08e2b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521096886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.521096886
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.1862112345
Short name T1231
Test name
Test status
Simulation time 43285222 ps
CPU time 1.43 seconds
Started Aug 01 06:29:15 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 229908 kb
Host smart-72eba90f-7c18-4e65-8cc7-90ff46ef05da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862112345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.1862112345
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3461740329
Short name T1257
Test name
Test status
Simulation time 73844426 ps
CPU time 1.49 seconds
Started Aug 01 06:29:16 PM PDT 24
Finished Aug 01 06:29:18 PM PDT 24
Peak memory 230220 kb
Host smart-50a729c9-cc87-4941-aa60-822f0cc3cadc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461740329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3461740329
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2705174756
Short name T1251
Test name
Test status
Simulation time 249736196 ps
CPU time 3.21 seconds
Started Aug 01 06:28:42 PM PDT 24
Finished Aug 01 06:28:45 PM PDT 24
Peak memory 247048 kb
Host smart-50645ddd-a53c-45f3-b504-92516987e929
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705174756 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.2705174756
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.2619172767
Short name T1295
Test name
Test status
Simulation time 698883144 ps
CPU time 1.94 seconds
Started Aug 01 06:28:46 PM PDT 24
Finished Aug 01 06:28:48 PM PDT 24
Peak memory 240924 kb
Host smart-e048c6ab-4980-4942-bf16-cecc9617ef10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619172767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.2619172767
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.100015163
Short name T1226
Test name
Test status
Simulation time 69435254 ps
CPU time 1.44 seconds
Started Aug 01 06:28:44 PM PDT 24
Finished Aug 01 06:28:46 PM PDT 24
Peak memory 230188 kb
Host smart-a8dfd5de-ee14-49eb-80dc-8245d5080106
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100015163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.100015163
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3329079879
Short name T1299
Test name
Test status
Simulation time 103746885 ps
CPU time 3.31 seconds
Started Aug 01 06:28:42 PM PDT 24
Finished Aug 01 06:28:45 PM PDT 24
Peak memory 242008 kb
Host smart-b78203ab-0faa-4caf-bf4e-7c51d9d59d9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329079879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.3329079879
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2474427361
Short name T1288
Test name
Test status
Simulation time 118184746 ps
CPU time 5.14 seconds
Started Aug 01 06:28:42 PM PDT 24
Finished Aug 01 06:28:47 PM PDT 24
Peak memory 245904 kb
Host smart-b9b4bb8f-0366-47a8-8839-e32be77781fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474427361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.2474427361
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.277575293
Short name T256
Test name
Test status
Simulation time 18975660483 ps
CPU time 36.18 seconds
Started Aug 01 06:28:41 PM PDT 24
Finished Aug 01 06:29:17 PM PDT 24
Peak memory 244444 kb
Host smart-d72c9482-23eb-4706-9abe-3021c7fc619a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277575293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_int
g_err.277575293
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1348102285
Short name T1246
Test name
Test status
Simulation time 269650990 ps
CPU time 2.25 seconds
Started Aug 01 06:28:46 PM PDT 24
Finished Aug 01 06:28:48 PM PDT 24
Peak memory 244380 kb
Host smart-82483300-1263-4f15-b1dd-4152aaff1a5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348102285 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.1348102285
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.3649949420
Short name T313
Test name
Test status
Simulation time 157541951 ps
CPU time 1.56 seconds
Started Aug 01 06:28:42 PM PDT 24
Finished Aug 01 06:28:43 PM PDT 24
Peak memory 238844 kb
Host smart-addc0170-2b8e-418d-a27e-b74e0bd0a6ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649949420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.3649949420
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.3390141658
Short name T1286
Test name
Test status
Simulation time 88773158 ps
CPU time 1.41 seconds
Started Aug 01 06:28:41 PM PDT 24
Finished Aug 01 06:28:43 PM PDT 24
Peak memory 230596 kb
Host smart-4e98db88-3533-40c9-a1b9-3b6f4f894d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390141658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.3390141658
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1180305403
Short name T1229
Test name
Test status
Simulation time 96938339 ps
CPU time 3.06 seconds
Started Aug 01 06:28:42 PM PDT 24
Finished Aug 01 06:28:45 PM PDT 24
Peak memory 238748 kb
Host smart-bc41b332-e5c9-4f2f-acf5-31863cc0755e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180305403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.1180305403
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.533372468
Short name T1191
Test name
Test status
Simulation time 85233033 ps
CPU time 3.67 seconds
Started Aug 01 06:28:42 PM PDT 24
Finished Aug 01 06:28:46 PM PDT 24
Peak memory 245668 kb
Host smart-c701ead3-7617-4879-a9c6-6b8988370bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533372468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.533372468
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2838888959
Short name T356
Test name
Test status
Simulation time 20204416691 ps
CPU time 26.32 seconds
Started Aug 01 06:28:44 PM PDT 24
Finished Aug 01 06:29:10 PM PDT 24
Peak memory 245528 kb
Host smart-24615d54-979a-405e-beea-33bf8ca0652e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838888959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.2838888959
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1932399400
Short name T1274
Test name
Test status
Simulation time 46842560 ps
CPU time 1.71 seconds
Started Aug 01 06:28:43 PM PDT 24
Finished Aug 01 06:28:44 PM PDT 24
Peak memory 238784 kb
Host smart-e22bf6e2-f2db-4f76-9c5b-e23296211454
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932399400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.1932399400
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.103947715
Short name T1250
Test name
Test status
Simulation time 84368252 ps
CPU time 1.36 seconds
Started Aug 01 06:28:41 PM PDT 24
Finished Aug 01 06:28:43 PM PDT 24
Peak memory 229836 kb
Host smart-62a97fd1-eac0-404b-bac8-5d80bf4725e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103947715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.103947715
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.4160452749
Short name T1264
Test name
Test status
Simulation time 1291718716 ps
CPU time 3.89 seconds
Started Aug 01 06:28:42 PM PDT 24
Finished Aug 01 06:28:46 PM PDT 24
Peak memory 242016 kb
Host smart-7aa7c14a-8dc0-44b7-a038-79a464e60bab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160452749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.4160452749
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3933421736
Short name T1234
Test name
Test status
Simulation time 246597820 ps
CPU time 4.11 seconds
Started Aug 01 06:28:42 PM PDT 24
Finished Aug 01 06:28:46 PM PDT 24
Peak memory 245524 kb
Host smart-50d59a58-9c6f-44fb-b24a-165e1cbe0f87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933421736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3933421736
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.377690261
Short name T1282
Test name
Test status
Simulation time 4001888994 ps
CPU time 21.13 seconds
Started Aug 01 06:28:44 PM PDT 24
Finished Aug 01 06:29:05 PM PDT 24
Peak memory 238852 kb
Host smart-dba24e6c-8b00-42ba-b9af-dcecf0f40305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377690261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_int
g_err.377690261
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3910803260
Short name T1237
Test name
Test status
Simulation time 196380042 ps
CPU time 3.83 seconds
Started Aug 01 06:28:55 PM PDT 24
Finished Aug 01 06:28:59 PM PDT 24
Peak memory 247080 kb
Host smart-8a3e3c8b-b5f1-4cf5-8351-a828437db964
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910803260 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.3910803260
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.407663907
Short name T1268
Test name
Test status
Simulation time 85171205 ps
CPU time 1.84 seconds
Started Aug 01 06:28:51 PM PDT 24
Finished Aug 01 06:28:53 PM PDT 24
Peak memory 238788 kb
Host smart-500db519-5ee7-46b2-920d-ba6da7305bc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407663907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.407663907
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.388417938
Short name T1240
Test name
Test status
Simulation time 142232779 ps
CPU time 1.46 seconds
Started Aug 01 06:28:42 PM PDT 24
Finished Aug 01 06:28:43 PM PDT 24
Peak memory 230580 kb
Host smart-cc521348-b340-47e9-b981-ad56e1d4019d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388417938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.388417938
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2092868632
Short name T1294
Test name
Test status
Simulation time 164304119 ps
CPU time 3.03 seconds
Started Aug 01 06:29:01 PM PDT 24
Finished Aug 01 06:29:04 PM PDT 24
Peak memory 238840 kb
Host smart-0b5a9543-7ae6-44fb-9db9-cebbc47ea242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092868632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.2092868632
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2829545393
Short name T1300
Test name
Test status
Simulation time 141139148 ps
CPU time 6.02 seconds
Started Aug 01 06:28:43 PM PDT 24
Finished Aug 01 06:28:49 PM PDT 24
Peak memory 246380 kb
Host smart-f6c93df0-ae32-4000-b72b-0f04929fc459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829545393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.2829545393
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2913015289
Short name T1296
Test name
Test status
Simulation time 207091070 ps
CPU time 3.22 seconds
Started Aug 01 06:28:54 PM PDT 24
Finished Aug 01 06:28:58 PM PDT 24
Peak memory 247068 kb
Host smart-707121cf-5509-470f-9a9a-f04617330b58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913015289 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.2913015289
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1400932493
Short name T312
Test name
Test status
Simulation time 51080963 ps
CPU time 1.87 seconds
Started Aug 01 06:28:53 PM PDT 24
Finished Aug 01 06:28:55 PM PDT 24
Peak memory 238792 kb
Host smart-d9ba571a-06bc-4594-8c54-71db7ae4806d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400932493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1400932493
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.569126798
Short name T1218
Test name
Test status
Simulation time 53842991 ps
CPU time 1.39 seconds
Started Aug 01 06:28:54 PM PDT 24
Finished Aug 01 06:28:55 PM PDT 24
Peak memory 230580 kb
Host smart-3b05ac60-3cc7-497c-a329-03e8a0c4a30c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569126798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.569126798
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3881797621
Short name T1236
Test name
Test status
Simulation time 1578948191 ps
CPU time 3.52 seconds
Started Aug 01 06:28:55 PM PDT 24
Finished Aug 01 06:28:58 PM PDT 24
Peak memory 238712 kb
Host smart-b3a2273f-ee07-4db1-986b-5695a7fc1c01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881797621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.3881797621
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1876993015
Short name T1210
Test name
Test status
Simulation time 176957165 ps
CPU time 7.43 seconds
Started Aug 01 06:28:54 PM PDT 24
Finished Aug 01 06:29:02 PM PDT 24
Peak memory 247104 kb
Host smart-f514a156-1133-448c-8537-4ebb817b0fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876993015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.1876993015
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1465957862
Short name T353
Test name
Test status
Simulation time 645707841 ps
CPU time 11.04 seconds
Started Aug 01 06:28:54 PM PDT 24
Finished Aug 01 06:29:05 PM PDT 24
Peak memory 243528 kb
Host smart-89a32033-294b-4ff5-8d7e-98611128f327
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465957862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.1465957862
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.114109503
Short name T1141
Test name
Test status
Simulation time 45793356 ps
CPU time 1.63 seconds
Started Aug 01 05:57:42 PM PDT 24
Finished Aug 01 05:57:44 PM PDT 24
Peak memory 240688 kb
Host smart-14bd40e9-e3fb-4ac7-a6a6-c0387fc99eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114109503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.114109503
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.237707464
Short name T880
Test name
Test status
Simulation time 2576985779 ps
CPU time 50.73 seconds
Started Aug 01 05:57:42 PM PDT 24
Finished Aug 01 05:58:32 PM PDT 24
Peak memory 242536 kb
Host smart-421c0af7-c168-44ce-8d08-a525f209c5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237707464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.237707464
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.400156443
Short name T63
Test name
Test status
Simulation time 310294252 ps
CPU time 7.41 seconds
Started Aug 01 05:57:45 PM PDT 24
Finished Aug 01 05:57:52 PM PDT 24
Peak memory 242000 kb
Host smart-a07127e1-aaca-48c2-a31d-ed6673990190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400156443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.400156443
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.662398311
Short name T1010
Test name
Test status
Simulation time 3683409153 ps
CPU time 37.65 seconds
Started Aug 01 05:57:46 PM PDT 24
Finished Aug 01 05:58:24 PM PDT 24
Peak memory 247204 kb
Host smart-5104d991-a033-4ffb-a054-7709bd27029c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662398311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.662398311
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.3813905338
Short name T777
Test name
Test status
Simulation time 2551101115 ps
CPU time 13.55 seconds
Started Aug 01 05:57:43 PM PDT 24
Finished Aug 01 05:57:57 PM PDT 24
Peak memory 242296 kb
Host smart-dae9baa2-2651-45e3-b190-08de9a34808d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813905338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3813905338
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.1586125588
Short name T1124
Test name
Test status
Simulation time 287313412 ps
CPU time 3.62 seconds
Started Aug 01 05:57:45 PM PDT 24
Finished Aug 01 05:57:49 PM PDT 24
Peak memory 242216 kb
Host smart-be21289f-fd64-4356-9fb1-6c63f7a96fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586125588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.1586125588
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.3205039045
Short name T389
Test name
Test status
Simulation time 6975628255 ps
CPU time 11.45 seconds
Started Aug 01 05:57:43 PM PDT 24
Finished Aug 01 05:57:55 PM PDT 24
Peak memory 240516 kb
Host smart-d3d7105a-92c3-4eda-8fef-9893e2f3ce15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205039045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.3205039045
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.172579698
Short name T453
Test name
Test status
Simulation time 7391751222 ps
CPU time 21.15 seconds
Started Aug 01 05:57:46 PM PDT 24
Finished Aug 01 05:58:07 PM PDT 24
Peak memory 242792 kb
Host smart-5636f30d-0c56-484c-8b60-2fe1f69805b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172579698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.172579698
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.2512912292
Short name T520
Test name
Test status
Simulation time 3663791980 ps
CPU time 52.4 seconds
Started Aug 01 05:57:46 PM PDT 24
Finished Aug 01 05:58:39 PM PDT 24
Peak memory 242172 kb
Host smart-02252c3a-6b2f-4775-9680-bd3a37fe6d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512912292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.2512912292
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.1327766886
Short name T342
Test name
Test status
Simulation time 527819706 ps
CPU time 6.4 seconds
Started Aug 01 05:57:44 PM PDT 24
Finished Aug 01 05:57:50 PM PDT 24
Peak memory 241984 kb
Host smart-2b504ff6-8ba2-48b3-9a12-741c16d04c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327766886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.1327766886
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.3850939241
Short name T615
Test name
Test status
Simulation time 660036661 ps
CPU time 6.51 seconds
Started Aug 01 05:57:45 PM PDT 24
Finished Aug 01 05:57:51 PM PDT 24
Peak memory 242000 kb
Host smart-d9b3390d-2741-477c-ad5d-ff9cb005fec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3850939241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.3850939241
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.1295277427
Short name T287
Test name
Test status
Simulation time 2396412269 ps
CPU time 22.43 seconds
Started Aug 01 05:57:47 PM PDT 24
Finished Aug 01 05:58:09 PM PDT 24
Peak memory 241528 kb
Host smart-9702d930-9be0-4352-bb01-d5e346176a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295277427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1295277427
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.3368375267
Short name T368
Test name
Test status
Simulation time 695507990 ps
CPU time 6 seconds
Started Aug 01 05:57:45 PM PDT 24
Finished Aug 01 05:57:51 PM PDT 24
Peak memory 242168 kb
Host smart-7098ec55-7c2e-43ec-a7ec-6c9d0a5cc85f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368375267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.3368375267
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.2425121590
Short name T17
Test name
Test status
Simulation time 37135767857 ps
CPU time 209.68 seconds
Started Aug 01 05:57:47 PM PDT 24
Finished Aug 01 06:01:17 PM PDT 24
Peak memory 265196 kb
Host smart-33680da0-6873-4442-85a0-cd5315f92932
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425121590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.2425121590
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.989232470
Short name T1147
Test name
Test status
Simulation time 4814062551 ps
CPU time 17.3 seconds
Started Aug 01 05:57:43 PM PDT 24
Finished Aug 01 05:58:00 PM PDT 24
Peak memory 241872 kb
Host smart-f26de40d-5df3-4a9d-81dc-80835e1a3951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989232470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.989232470
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.1049399732
Short name T559
Test name
Test status
Simulation time 26048293956 ps
CPU time 94.87 seconds
Started Aug 01 05:57:42 PM PDT 24
Finished Aug 01 05:59:17 PM PDT 24
Peak memory 248544 kb
Host smart-87637c7e-86ef-4f3f-b7a1-24c034eb6e5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049399732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
1049399732
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.3276685112
Short name T327
Test name
Test status
Simulation time 86835126586 ps
CPU time 491.22 seconds
Started Aug 01 05:57:38 PM PDT 24
Finished Aug 01 06:05:49 PM PDT 24
Peak memory 299948 kb
Host smart-7382dca9-fc3f-420b-b8e1-57cbbb69e1f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276685112 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.3276685112
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.3958118548
Short name T265
Test name
Test status
Simulation time 12469529606 ps
CPU time 42.42 seconds
Started Aug 01 05:57:44 PM PDT 24
Finished Aug 01 05:58:26 PM PDT 24
Peak memory 243756 kb
Host smart-a895222d-1b8f-4bea-bb9b-ba1f971bad14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958118548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.3958118548
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.19214385
Short name T879
Test name
Test status
Simulation time 1660999320 ps
CPU time 24.26 seconds
Started Aug 01 05:57:45 PM PDT 24
Finished Aug 01 05:58:10 PM PDT 24
Peak memory 242044 kb
Host smart-8cad0c20-580c-46d2-a430-2b44da7b1eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19214385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.19214385
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.2341411073
Short name T24
Test name
Test status
Simulation time 3150956660 ps
CPU time 22.53 seconds
Started Aug 01 05:57:48 PM PDT 24
Finished Aug 01 05:58:10 PM PDT 24
Peak memory 242292 kb
Host smart-d603a2c0-b9c5-4dc4-9b71-58292f9308d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341411073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.2341411073
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.1708149532
Short name T1078
Test name
Test status
Simulation time 3031866757 ps
CPU time 29.09 seconds
Started Aug 01 05:57:45 PM PDT 24
Finished Aug 01 05:58:14 PM PDT 24
Peak memory 243820 kb
Host smart-29e21c69-a325-4061-a085-640d249309cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708149532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.1708149532
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.1226232802
Short name T605
Test name
Test status
Simulation time 364961443 ps
CPU time 3.53 seconds
Started Aug 01 05:57:43 PM PDT 24
Finished Aug 01 05:57:47 PM PDT 24
Peak memory 241936 kb
Host smart-e0a50d15-1d13-4213-bafa-255ae070f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226232802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.1226232802
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.1544492116
Short name T409
Test name
Test status
Simulation time 406167296 ps
CPU time 4.86 seconds
Started Aug 01 05:57:45 PM PDT 24
Finished Aug 01 05:57:50 PM PDT 24
Peak memory 242044 kb
Host smart-0075712b-f88b-4850-8e52-0d19ec8d0051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544492116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.1544492116
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.2055975189
Short name T285
Test name
Test status
Simulation time 4456098558 ps
CPU time 34.84 seconds
Started Aug 01 05:57:42 PM PDT 24
Finished Aug 01 05:58:17 PM PDT 24
Peak memory 253960 kb
Host smart-9e9d66f6-d832-4b91-b1a7-428234df5d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055975189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.2055975189
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.3280576826
Short name T194
Test name
Test status
Simulation time 5308218377 ps
CPU time 10.65 seconds
Started Aug 01 05:57:43 PM PDT 24
Finished Aug 01 05:57:54 PM PDT 24
Peak memory 243112 kb
Host smart-c1110ab1-6d45-4206-8dbb-086516880d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280576826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.3280576826
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.2330431723
Short name T982
Test name
Test status
Simulation time 210536938 ps
CPU time 3.72 seconds
Started Aug 01 05:57:45 PM PDT 24
Finished Aug 01 05:57:49 PM PDT 24
Peak memory 241936 kb
Host smart-7793646e-34d8-426a-8e89-717e8add79db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330431723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.2330431723
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.4117324569
Short name T485
Test name
Test status
Simulation time 843733666 ps
CPU time 23.52 seconds
Started Aug 01 05:57:44 PM PDT 24
Finished Aug 01 05:58:08 PM PDT 24
Peak memory 242320 kb
Host smart-6fa825f2-d69d-4c67-a7e8-de208e73c198
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117324569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.4117324569
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.3031931604
Short name T1046
Test name
Test status
Simulation time 2961013155 ps
CPU time 5.9 seconds
Started Aug 01 05:57:38 PM PDT 24
Finished Aug 01 05:57:44 PM PDT 24
Peak memory 241960 kb
Host smart-8206d946-d4df-4a44-9bbe-f35f98748f7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031931604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3031931604
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.3835663244
Short name T18
Test name
Test status
Simulation time 14202035877 ps
CPU time 178.19 seconds
Started Aug 01 05:57:43 PM PDT 24
Finished Aug 01 06:00:41 PM PDT 24
Peak memory 266072 kb
Host smart-a51e31ad-ed33-4f43-95db-94cf3130e2e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835663244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3835663244
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.2069195770
Short name T888
Test name
Test status
Simulation time 423543052 ps
CPU time 5.54 seconds
Started Aug 01 05:57:45 PM PDT 24
Finished Aug 01 05:57:51 PM PDT 24
Peak memory 241884 kb
Host smart-3012e404-429d-4f69-afdb-b6baf1d49abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069195770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.2069195770
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.2523758416
Short name T985
Test name
Test status
Simulation time 60100807978 ps
CPU time 275.12 seconds
Started Aug 01 05:57:54 PM PDT 24
Finished Aug 01 06:02:29 PM PDT 24
Peak memory 281360 kb
Host smart-7b6c7587-abed-455f-8140-f4a21cdf9f21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523758416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
2523758416
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.2891079194
Short name T1118
Test name
Test status
Simulation time 86660021899 ps
CPU time 651.02 seconds
Started Aug 01 05:57:47 PM PDT 24
Finished Aug 01 06:08:38 PM PDT 24
Peak memory 349264 kb
Host smart-57320a97-474c-47c9-b43a-e36d81aff99f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891079194 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.2891079194
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.2055381982
Short name T1116
Test name
Test status
Simulation time 736229919 ps
CPU time 23.51 seconds
Started Aug 01 05:57:48 PM PDT 24
Finished Aug 01 05:58:12 PM PDT 24
Peak memory 242160 kb
Host smart-2d755462-290c-42a8-b112-4633ae11f3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055381982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.2055381982
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.2425587061
Short name T1047
Test name
Test status
Simulation time 155619060 ps
CPU time 1.99 seconds
Started Aug 01 05:58:26 PM PDT 24
Finished Aug 01 05:58:28 PM PDT 24
Peak memory 240352 kb
Host smart-43543b62-1c23-432e-acfb-b8df7b5a2927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425587061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.2425587061
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.426525309
Short name T73
Test name
Test status
Simulation time 521703089 ps
CPU time 15.81 seconds
Started Aug 01 05:58:26 PM PDT 24
Finished Aug 01 05:58:42 PM PDT 24
Peak memory 242388 kb
Host smart-1a468a70-7b4c-4ff9-aeac-2ac03eaaaadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426525309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.426525309
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.2238974229
Short name T565
Test name
Test status
Simulation time 176814042 ps
CPU time 8.46 seconds
Started Aug 01 05:58:29 PM PDT 24
Finished Aug 01 05:58:38 PM PDT 24
Peak memory 242220 kb
Host smart-8b7ca694-7edf-47ed-a476-3509d7db3682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238974229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.2238974229
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.2282770773
Short name T922
Test name
Test status
Simulation time 1221817982 ps
CPU time 25.41 seconds
Started Aug 01 05:58:19 PM PDT 24
Finished Aug 01 05:58:45 PM PDT 24
Peak memory 241984 kb
Host smart-a616a76c-1392-4c5e-94de-0274436b7a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282770773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2282770773
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.2491820183
Short name T887
Test name
Test status
Simulation time 292527880 ps
CPU time 4.03 seconds
Started Aug 01 05:58:16 PM PDT 24
Finished Aug 01 05:58:21 PM PDT 24
Peak memory 242352 kb
Host smart-59c3b5f6-9127-4595-9678-27172b59fb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491820183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.2491820183
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.704539508
Short name T434
Test name
Test status
Simulation time 14823350191 ps
CPU time 37.21 seconds
Started Aug 01 05:58:27 PM PDT 24
Finished Aug 01 05:59:05 PM PDT 24
Peak memory 248152 kb
Host smart-203bc4fa-a187-4b3c-af76-51fa4afda633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704539508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.704539508
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.1773679625
Short name T593
Test name
Test status
Simulation time 4410460481 ps
CPU time 15.32 seconds
Started Aug 01 05:58:28 PM PDT 24
Finished Aug 01 05:58:43 PM PDT 24
Peak memory 242044 kb
Host smart-36f4a955-6399-43bd-ba61-98ebf789e2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773679625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.1773679625
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.1135515316
Short name T143
Test name
Test status
Simulation time 3287951569 ps
CPU time 6.65 seconds
Started Aug 01 05:58:20 PM PDT 24
Finished Aug 01 05:58:27 PM PDT 24
Peak memory 242212 kb
Host smart-9f5bf751-48ae-48a2-bc62-2a892f555d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135515316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.1135515316
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.4119866583
Short name T411
Test name
Test status
Simulation time 740365836 ps
CPU time 8.89 seconds
Started Aug 01 05:58:15 PM PDT 24
Finished Aug 01 05:58:24 PM PDT 24
Peak memory 242260 kb
Host smart-4a121674-4d85-4aaf-a4af-67f5207ef43f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4119866583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.4119866583
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.2451555259
Short name T519
Test name
Test status
Simulation time 1786195111 ps
CPU time 5.07 seconds
Started Aug 01 05:58:26 PM PDT 24
Finished Aug 01 05:58:31 PM PDT 24
Peak memory 248436 kb
Host smart-4614edd4-bc61-49a3-b308-28301337a8ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451555259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.2451555259
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.757912389
Short name T1032
Test name
Test status
Simulation time 1161680647 ps
CPU time 7.12 seconds
Started Aug 01 05:58:15 PM PDT 24
Finished Aug 01 05:58:23 PM PDT 24
Peak memory 241844 kb
Host smart-3e9feaba-98b1-4c19-adb7-76957a9ddb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757912389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.757912389
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.2796303735
Short name T322
Test name
Test status
Simulation time 370837418545 ps
CPU time 2769.69 seconds
Started Aug 01 05:58:27 PM PDT 24
Finished Aug 01 06:44:37 PM PDT 24
Peak memory 548360 kb
Host smart-d852e52d-6c81-40d0-ac83-6c79b5ff56c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796303735 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.2796303735
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.1625728567
Short name T929
Test name
Test status
Simulation time 616543974 ps
CPU time 18.64 seconds
Started Aug 01 05:58:33 PM PDT 24
Finished Aug 01 05:58:52 PM PDT 24
Peak memory 242424 kb
Host smart-6ca5f619-b7ad-473f-8658-afa8ae20c775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625728567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.1625728567
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.4261287502
Short name T683
Test name
Test status
Simulation time 267434882 ps
CPU time 4.3 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:01 PM PDT 24
Peak memory 241940 kb
Host smart-e6fc25f3-b696-492c-9d94-3e6f0f444976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261287502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.4261287502
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.2916169549
Short name T707
Test name
Test status
Simulation time 94447610 ps
CPU time 3.6 seconds
Started Aug 01 06:01:58 PM PDT 24
Finished Aug 01 06:02:01 PM PDT 24
Peak memory 242364 kb
Host smart-e6431e44-a38d-4973-b64f-2bf0be9f84ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916169549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.2916169549
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.156781890
Short name T1025
Test name
Test status
Simulation time 106635568 ps
CPU time 3.69 seconds
Started Aug 01 06:01:56 PM PDT 24
Finished Aug 01 06:02:00 PM PDT 24
Peak memory 242288 kb
Host smart-91fc9fa2-25f3-4ec3-9c87-d3f7398bbe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156781890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.156781890
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.3885217841
Short name T838
Test name
Test status
Simulation time 275923263 ps
CPU time 4.18 seconds
Started Aug 01 06:01:55 PM PDT 24
Finished Aug 01 06:01:59 PM PDT 24
Peak memory 242100 kb
Host smart-19d57268-6ffa-4fa7-bf05-66b3db601ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885217841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.3885217841
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.2086304444
Short name T1180
Test name
Test status
Simulation time 845400845 ps
CPU time 8.54 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:05 PM PDT 24
Peak memory 242200 kb
Host smart-11effe3d-c9b6-466a-957e-1f51184472c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086304444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2086304444
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.2587112834
Short name T828
Test name
Test status
Simulation time 140036878 ps
CPU time 3.44 seconds
Started Aug 01 06:02:00 PM PDT 24
Finished Aug 01 06:02:04 PM PDT 24
Peak memory 242000 kb
Host smart-a274734f-c432-4d89-9340-165fb8c30862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587112834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.2587112834
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.2616024940
Short name T747
Test name
Test status
Simulation time 247215843 ps
CPU time 5.68 seconds
Started Aug 01 06:01:56 PM PDT 24
Finished Aug 01 06:02:02 PM PDT 24
Peak memory 242380 kb
Host smart-7ab21eb3-4bb7-49e9-b1fc-adc648675149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616024940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.2616024940
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.1588304914
Short name T833
Test name
Test status
Simulation time 102292142 ps
CPU time 3.48 seconds
Started Aug 01 06:02:00 PM PDT 24
Finished Aug 01 06:02:04 PM PDT 24
Peak memory 242076 kb
Host smart-9510a61e-8cd5-45fa-a0eb-2b501592a34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588304914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.1588304914
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.183384991
Short name T1072
Test name
Test status
Simulation time 218367789 ps
CPU time 5.08 seconds
Started Aug 01 06:02:08 PM PDT 24
Finished Aug 01 06:02:13 PM PDT 24
Peak memory 241952 kb
Host smart-2306b012-f0b1-481c-a2c5-537be3cb9df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183384991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.183384991
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.4095742877
Short name T835
Test name
Test status
Simulation time 1442704746 ps
CPU time 3.49 seconds
Started Aug 01 06:02:08 PM PDT 24
Finished Aug 01 06:02:11 PM PDT 24
Peak memory 242088 kb
Host smart-bf374eae-e3b4-4ced-be32-df1946ab4ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095742877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.4095742877
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.1324972409
Short name T289
Test name
Test status
Simulation time 749502016 ps
CPU time 7.15 seconds
Started Aug 01 06:02:06 PM PDT 24
Finished Aug 01 06:02:14 PM PDT 24
Peak memory 242252 kb
Host smart-03ce8034-fb79-42a7-9820-7e65e4aea8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324972409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.1324972409
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.2181369603
Short name T186
Test name
Test status
Simulation time 232498967 ps
CPU time 3.4 seconds
Started Aug 01 06:02:11 PM PDT 24
Finished Aug 01 06:02:15 PM PDT 24
Peak memory 242076 kb
Host smart-a312ffb8-10b1-4102-8c2b-57e80c28868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181369603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.2181369603
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.4175294006
Short name T822
Test name
Test status
Simulation time 5845425829 ps
CPU time 17.19 seconds
Started Aug 01 06:02:08 PM PDT 24
Finished Aug 01 06:02:25 PM PDT 24
Peak memory 242076 kb
Host smart-0e4c2395-6acf-4c6a-9a3f-8fb9389090a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175294006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.4175294006
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.2138960235
Short name T648
Test name
Test status
Simulation time 158047391 ps
CPU time 3.96 seconds
Started Aug 01 06:02:07 PM PDT 24
Finished Aug 01 06:02:12 PM PDT 24
Peak memory 247024 kb
Host smart-54928d95-fbd2-485d-b831-1a85caac808e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138960235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.2138960235
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.3667789621
Short name T699
Test name
Test status
Simulation time 179709600 ps
CPU time 4.96 seconds
Started Aug 01 06:02:07 PM PDT 24
Finished Aug 01 06:02:12 PM PDT 24
Peak memory 242028 kb
Host smart-5785d058-c9c6-4f2f-8c6c-bf3e135641dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667789621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3667789621
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.1699727580
Short name T114
Test name
Test status
Simulation time 136560727 ps
CPU time 4.03 seconds
Started Aug 01 06:02:07 PM PDT 24
Finished Aug 01 06:02:12 PM PDT 24
Peak memory 246328 kb
Host smart-e4ad2605-9f6b-4059-9ab8-cf4ddd4c8929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699727580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.1699727580
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.1848353813
Short name T911
Test name
Test status
Simulation time 512244400 ps
CPU time 4.87 seconds
Started Aug 01 06:02:11 PM PDT 24
Finished Aug 01 06:02:16 PM PDT 24
Peak memory 242248 kb
Host smart-7ccd35b8-d2e7-410c-8a6a-aa31723a36c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848353813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.1848353813
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.770165145
Short name T282
Test name
Test status
Simulation time 491389895 ps
CPU time 3.72 seconds
Started Aug 01 06:02:07 PM PDT 24
Finished Aug 01 06:02:11 PM PDT 24
Peak memory 246612 kb
Host smart-f2ce7156-2480-4a26-a330-6411d5d251b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770165145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.770165145
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.2746755974
Short name T820
Test name
Test status
Simulation time 76150159 ps
CPU time 2.07 seconds
Started Aug 01 05:58:29 PM PDT 24
Finished Aug 01 05:58:31 PM PDT 24
Peak memory 240644 kb
Host smart-2503dc72-6a84-4129-b752-b79007725820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746755974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.2746755974
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.2775916304
Short name T1120
Test name
Test status
Simulation time 2221092204 ps
CPU time 18.55 seconds
Started Aug 01 05:58:27 PM PDT 24
Finished Aug 01 05:58:46 PM PDT 24
Peak memory 242356 kb
Host smart-3e9e12ae-2255-447f-8211-8e418d768113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775916304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.2775916304
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.1178625683
Short name T734
Test name
Test status
Simulation time 162659498 ps
CPU time 4.26 seconds
Started Aug 01 05:58:29 PM PDT 24
Finished Aug 01 05:58:34 PM PDT 24
Peak memory 241928 kb
Host smart-a56f1eb7-5daf-4edf-8f5c-e5e6f98ce6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178625683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.1178625683
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.2778894888
Short name T1142
Test name
Test status
Simulation time 475282407 ps
CPU time 8.53 seconds
Started Aug 01 05:58:28 PM PDT 24
Finished Aug 01 05:58:37 PM PDT 24
Peak memory 248492 kb
Host smart-d8cdba90-14c2-4ef3-9c48-227446fa6f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778894888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.2778894888
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.1341336103
Short name T230
Test name
Test status
Simulation time 993954764 ps
CPU time 10.42 seconds
Started Aug 01 05:58:30 PM PDT 24
Finished Aug 01 05:58:41 PM PDT 24
Peak memory 242328 kb
Host smart-36a982a9-97bb-4f8c-9dfe-a76ebae8cfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341336103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.1341336103
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.2958453806
Short name T643
Test name
Test status
Simulation time 340783504 ps
CPU time 20.98 seconds
Started Aug 01 05:58:27 PM PDT 24
Finished Aug 01 05:58:48 PM PDT 24
Peak memory 242468 kb
Host smart-af043b36-aa80-47cd-8b36-327bb652b667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958453806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.2958453806
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.623910086
Short name T957
Test name
Test status
Simulation time 1397244492 ps
CPU time 21.73 seconds
Started Aug 01 05:58:26 PM PDT 24
Finished Aug 01 05:58:48 PM PDT 24
Peak memory 242336 kb
Host smart-62e46ff4-1239-4d4c-bd18-a5127c13c429
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=623910086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.623910086
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.4287883130
Short name T364
Test name
Test status
Simulation time 491211989 ps
CPU time 5.47 seconds
Started Aug 01 05:58:27 PM PDT 24
Finished Aug 01 05:58:33 PM PDT 24
Peak memory 241936 kb
Host smart-ccf5a979-d56c-4bbe-8279-cea7f6b7d588
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4287883130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.4287883130
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.1627081911
Short name T267
Test name
Test status
Simulation time 3698701078 ps
CPU time 5.7 seconds
Started Aug 01 05:58:27 PM PDT 24
Finished Aug 01 05:58:33 PM PDT 24
Peak memory 248500 kb
Host smart-4f070205-33e2-4a8e-9d1e-fc6f70943f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627081911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.1627081911
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.995011452
Short name T198
Test name
Test status
Simulation time 34789698014 ps
CPU time 214.58 seconds
Started Aug 01 05:58:28 PM PDT 24
Finished Aug 01 06:02:03 PM PDT 24
Peak memory 274292 kb
Host smart-fcde5d0e-a2de-4b9f-8427-589d0ca99317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995011452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.
995011452
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.3841158294
Short name T15
Test name
Test status
Simulation time 124257917541 ps
CPU time 1040.1 seconds
Started Aug 01 05:58:25 PM PDT 24
Finished Aug 01 06:15:46 PM PDT 24
Peak memory 359772 kb
Host smart-b67750c3-be9c-4c39-bf73-05d4b6ea1c02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841158294 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.3841158294
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.6134233
Short name T471
Test name
Test status
Simulation time 1668005758 ps
CPU time 15.93 seconds
Started Aug 01 05:58:26 PM PDT 24
Finished Aug 01 05:58:42 PM PDT 24
Peak memory 242324 kb
Host smart-beeaf7ae-920a-48a5-9bf3-d02a78e3b7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6134233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.6134233
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.1436524972
Short name T531
Test name
Test status
Simulation time 707654473 ps
CPU time 5.55 seconds
Started Aug 01 06:02:06 PM PDT 24
Finished Aug 01 06:02:11 PM PDT 24
Peak memory 241964 kb
Host smart-3d3caad6-3902-4988-aed1-d9863a00d3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436524972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.1436524972
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.2090653189
Short name T669
Test name
Test status
Simulation time 302312452 ps
CPU time 4.37 seconds
Started Aug 01 06:02:07 PM PDT 24
Finished Aug 01 06:02:12 PM PDT 24
Peak memory 242172 kb
Host smart-82e29f74-e0f8-4077-9bfa-f74405061df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090653189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.2090653189
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.3548734317
Short name T375
Test name
Test status
Simulation time 3357474899 ps
CPU time 28.69 seconds
Started Aug 01 06:02:08 PM PDT 24
Finished Aug 01 06:02:37 PM PDT 24
Peak memory 242280 kb
Host smart-9a222dba-f772-448f-918e-67b84dae4150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548734317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.3548734317
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.3689372783
Short name T169
Test name
Test status
Simulation time 108355760 ps
CPU time 3.26 seconds
Started Aug 01 06:02:04 PM PDT 24
Finished Aug 01 06:02:08 PM PDT 24
Peak memory 242132 kb
Host smart-681c1462-ffd9-4799-ab5a-ec25612c5d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689372783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.3689372783
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.309147425
Short name T1112
Test name
Test status
Simulation time 265117934 ps
CPU time 5.96 seconds
Started Aug 01 06:02:07 PM PDT 24
Finished Aug 01 06:02:13 PM PDT 24
Peak memory 241808 kb
Host smart-02c85249-59c4-4d03-a22d-9ef22f1968b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309147425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.309147425
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.2281161603
Short name T1179
Test name
Test status
Simulation time 468316523 ps
CPU time 5.84 seconds
Started Aug 01 06:02:07 PM PDT 24
Finished Aug 01 06:02:13 PM PDT 24
Peak memory 242228 kb
Host smart-b001c737-8d53-430b-b55e-453b28ceb925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281161603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.2281161603
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.2223497308
Short name T226
Test name
Test status
Simulation time 299612983 ps
CPU time 7.58 seconds
Started Aug 01 06:02:08 PM PDT 24
Finished Aug 01 06:02:16 PM PDT 24
Peak memory 241684 kb
Host smart-e7ee9eb1-7a63-42b0-bc00-65480800e75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223497308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2223497308
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.3244948133
Short name T543
Test name
Test status
Simulation time 609133645 ps
CPU time 3.99 seconds
Started Aug 01 06:02:10 PM PDT 24
Finished Aug 01 06:02:14 PM PDT 24
Peak memory 242180 kb
Host smart-a4233b6c-8250-455b-bcab-6a9e51fe65b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244948133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.3244948133
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.1988594498
Short name T641
Test name
Test status
Simulation time 365983891 ps
CPU time 7.14 seconds
Started Aug 01 06:02:11 PM PDT 24
Finished Aug 01 06:02:18 PM PDT 24
Peak memory 241816 kb
Host smart-4dcc0e1d-bfb6-4748-8f88-7044527dc20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988594498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.1988594498
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.1720977177
Short name T66
Test name
Test status
Simulation time 110539592 ps
CPU time 3.97 seconds
Started Aug 01 06:02:11 PM PDT 24
Finished Aug 01 06:02:15 PM PDT 24
Peak memory 241972 kb
Host smart-184c4085-37cf-47ea-a9dc-c62a6a6c17e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720977177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.1720977177
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.2132922924
Short name T431
Test name
Test status
Simulation time 4739303224 ps
CPU time 16.73 seconds
Started Aug 01 06:02:07 PM PDT 24
Finished Aug 01 06:02:24 PM PDT 24
Peak memory 241892 kb
Host smart-7a361c0c-b217-48d3-b850-30ad44a1c647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132922924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.2132922924
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.1532378236
Short name T1026
Test name
Test status
Simulation time 444414854 ps
CPU time 3.45 seconds
Started Aug 01 06:02:10 PM PDT 24
Finished Aug 01 06:02:13 PM PDT 24
Peak memory 247944 kb
Host smart-0adc3799-02f7-44ec-8ac3-df564d660d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532378236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.1532378236
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.2406981852
Short name T174
Test name
Test status
Simulation time 483246740 ps
CPU time 4.85 seconds
Started Aug 01 06:02:05 PM PDT 24
Finished Aug 01 06:02:10 PM PDT 24
Peak memory 242396 kb
Host smart-2691aefc-e326-41a3-8282-097bcf649282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406981852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.2406981852
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.3537839944
Short name T1099
Test name
Test status
Simulation time 599306386 ps
CPU time 4.93 seconds
Started Aug 01 06:02:07 PM PDT 24
Finished Aug 01 06:02:12 PM PDT 24
Peak memory 241684 kb
Host smart-0f74a759-b1b5-48e3-86d3-d0743269e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537839944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3537839944
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.3843423628
Short name T1158
Test name
Test status
Simulation time 115060260 ps
CPU time 3.78 seconds
Started Aug 01 06:02:07 PM PDT 24
Finished Aug 01 06:02:11 PM PDT 24
Peak memory 241952 kb
Host smart-aa8aef89-559d-43d8-a315-4798868787d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843423628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.3843423628
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.3388340541
Short name T465
Test name
Test status
Simulation time 3335273756 ps
CPU time 11.01 seconds
Started Aug 01 06:02:05 PM PDT 24
Finished Aug 01 06:02:17 PM PDT 24
Peak memory 242412 kb
Host smart-a59e46c1-56f1-4a59-bfb9-5c6ea00d85b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388340541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.3388340541
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.3462616974
Short name T786
Test name
Test status
Simulation time 486122656 ps
CPU time 5.08 seconds
Started Aug 01 06:02:12 PM PDT 24
Finished Aug 01 06:02:17 PM PDT 24
Peak memory 242032 kb
Host smart-69b96c38-5f76-4965-bdc1-5e38bcdaf4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462616974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.3462616974
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.111653068
Short name T917
Test name
Test status
Simulation time 2114097519 ps
CPU time 21.55 seconds
Started Aug 01 06:02:09 PM PDT 24
Finished Aug 01 06:02:31 PM PDT 24
Peak memory 241928 kb
Host smart-64b377eb-b51e-4de7-8ba7-72ffa9903791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111653068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.111653068
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.1926321043
Short name T94
Test name
Test status
Simulation time 196501479 ps
CPU time 2.08 seconds
Started Aug 01 05:58:32 PM PDT 24
Finished Aug 01 05:58:34 PM PDT 24
Peak memory 240208 kb
Host smart-4e79d40f-2737-4c8e-b56a-c22f2ad4d8a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926321043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1926321043
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.2768789712
Short name T32
Test name
Test status
Simulation time 2985258298 ps
CPU time 17.68 seconds
Started Aug 01 05:58:27 PM PDT 24
Finished Aug 01 05:58:45 PM PDT 24
Peak memory 248708 kb
Host smart-23b502ea-b3cf-40d1-adcf-6a03c3e9384f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768789712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.2768789712
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.1248110515
Short name T686
Test name
Test status
Simulation time 854411140 ps
CPU time 21.73 seconds
Started Aug 01 05:58:27 PM PDT 24
Finished Aug 01 05:58:49 PM PDT 24
Peak memory 242328 kb
Host smart-0330c807-8959-44a3-8885-31d08d0887a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248110515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.1248110515
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.3051842324
Short name T413
Test name
Test status
Simulation time 416099757 ps
CPU time 8.93 seconds
Started Aug 01 05:58:27 PM PDT 24
Finished Aug 01 05:58:36 PM PDT 24
Peak memory 248540 kb
Host smart-3a19aa51-12ae-40ba-86c6-4f2667792073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051842324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.3051842324
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.1734039240
Short name T805
Test name
Test status
Simulation time 1953071140 ps
CPU time 4.35 seconds
Started Aug 01 05:58:26 PM PDT 24
Finished Aug 01 05:58:30 PM PDT 24
Peak memory 241972 kb
Host smart-710c067e-a4e0-4984-bfb0-1ffbab820e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734039240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1734039240
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.1007098913
Short name T798
Test name
Test status
Simulation time 11446557625 ps
CPU time 29.76 seconds
Started Aug 01 05:58:26 PM PDT 24
Finished Aug 01 05:58:56 PM PDT 24
Peak memory 246024 kb
Host smart-85123546-f0d3-4eae-8445-954f0d0ecf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007098913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.1007098913
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.3276875458
Short name T5
Test name
Test status
Simulation time 1624250484 ps
CPU time 14.75 seconds
Started Aug 01 05:58:29 PM PDT 24
Finished Aug 01 05:58:44 PM PDT 24
Peak memory 242124 kb
Host smart-2e4e27c0-1f04-4aae-93a7-36c70910e659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276875458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.3276875458
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.488712653
Short name T770
Test name
Test status
Simulation time 82082427 ps
CPU time 3.17 seconds
Started Aug 01 05:58:32 PM PDT 24
Finished Aug 01 05:58:35 PM PDT 24
Peak memory 242156 kb
Host smart-b01474b6-3285-4a7a-a82c-e79fc5e0864a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488712653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.488712653
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.2571658601
Short name T1087
Test name
Test status
Simulation time 704409290 ps
CPU time 8.65 seconds
Started Aug 01 05:58:29 PM PDT 24
Finished Aug 01 05:58:37 PM PDT 24
Peak memory 241912 kb
Host smart-da44fe19-5e0f-4230-b064-cec5ff4b6737
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2571658601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.2571658601
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.3954661975
Short name T1136
Test name
Test status
Simulation time 451870368 ps
CPU time 4.56 seconds
Started Aug 01 05:58:27 PM PDT 24
Finished Aug 01 05:58:32 PM PDT 24
Peak memory 241848 kb
Host smart-043d67bb-5b3b-4c4f-9bfd-bd6be6083228
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3954661975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.3954661975
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.3010217900
Short name T975
Test name
Test status
Simulation time 197002583 ps
CPU time 4.24 seconds
Started Aug 01 05:58:28 PM PDT 24
Finished Aug 01 05:58:32 PM PDT 24
Peak memory 248400 kb
Host smart-d91a0f75-ad96-4cae-95f3-9b920f0e0bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010217900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.3010217900
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.1076827047
Short name T346
Test name
Test status
Simulation time 11816535093 ps
CPU time 169.3 seconds
Started Aug 01 05:58:30 PM PDT 24
Finished Aug 01 06:01:19 PM PDT 24
Peak memory 264200 kb
Host smart-b6b9c19c-84cf-496d-8052-3ca1da807fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076827047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.1076827047
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.1415988397
Short name T324
Test name
Test status
Simulation time 116059637794 ps
CPU time 2954.13 seconds
Started Aug 01 05:58:30 PM PDT 24
Finished Aug 01 06:47:44 PM PDT 24
Peak memory 332332 kb
Host smart-f40c295e-8c22-463e-b679-09d227cd1abb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415988397 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.1415988397
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.3869282128
Short name T580
Test name
Test status
Simulation time 359500384 ps
CPU time 11.64 seconds
Started Aug 01 05:58:29 PM PDT 24
Finished Aug 01 05:58:40 PM PDT 24
Peak memory 242220 kb
Host smart-51cff034-3551-42df-a8f8-35529e562780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869282128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.3869282128
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.333536866
Short name T815
Test name
Test status
Simulation time 152477884 ps
CPU time 4.08 seconds
Started Aug 01 06:02:08 PM PDT 24
Finished Aug 01 06:02:13 PM PDT 24
Peak memory 241912 kb
Host smart-8cf59a3d-65f4-4163-a646-d6758ac8a4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333536866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.333536866
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.3056168906
Short name T325
Test name
Test status
Simulation time 227064514 ps
CPU time 5.62 seconds
Started Aug 01 06:02:11 PM PDT 24
Finished Aug 01 06:02:17 PM PDT 24
Peak memory 242224 kb
Host smart-16786864-3a54-4a09-b66d-a93b3f2bfde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056168906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.3056168906
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.4210577834
Short name T796
Test name
Test status
Simulation time 446794840 ps
CPU time 4.12 seconds
Started Aug 01 06:02:06 PM PDT 24
Finished Aug 01 06:02:11 PM PDT 24
Peak memory 242200 kb
Host smart-fd507bc7-8978-46ee-bd98-45e6b8e1430e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210577834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.4210577834
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.3718986625
Short name T662
Test name
Test status
Simulation time 353029762 ps
CPU time 9.4 seconds
Started Aug 01 06:02:06 PM PDT 24
Finished Aug 01 06:02:15 PM PDT 24
Peak memory 241916 kb
Host smart-0ccc35ee-0e80-40b9-811c-820cc388e96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718986625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3718986625
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.3881874413
Short name T46
Test name
Test status
Simulation time 131232707 ps
CPU time 4.7 seconds
Started Aug 01 06:02:06 PM PDT 24
Finished Aug 01 06:02:11 PM PDT 24
Peak memory 242256 kb
Host smart-b63888b2-5683-4569-8ac4-86c8b7d27c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881874413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.3881874413
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.1299667121
Short name T95
Test name
Test status
Simulation time 460766472 ps
CPU time 4.21 seconds
Started Aug 01 06:02:06 PM PDT 24
Finished Aug 01 06:02:10 PM PDT 24
Peak memory 241692 kb
Host smart-34b7cf7e-716d-4b9f-8619-a62763f0d1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299667121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.1299667121
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.861284984
Short name T840
Test name
Test status
Simulation time 137590675 ps
CPU time 4.59 seconds
Started Aug 01 06:02:06 PM PDT 24
Finished Aug 01 06:02:11 PM PDT 24
Peak memory 242148 kb
Host smart-018f2f4c-e52b-4680-9b7c-2fcd398ad601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861284984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.861284984
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.2994920265
Short name T448
Test name
Test status
Simulation time 119973599 ps
CPU time 5.69 seconds
Started Aug 01 06:02:11 PM PDT 24
Finished Aug 01 06:02:17 PM PDT 24
Peak memory 241832 kb
Host smart-2ef70a7b-ea04-401e-96fd-975f00c12e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994920265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.2994920265
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.271487479
Short name T124
Test name
Test status
Simulation time 133620753 ps
CPU time 4.14 seconds
Started Aug 01 06:02:06 PM PDT 24
Finished Aug 01 06:02:11 PM PDT 24
Peak memory 241940 kb
Host smart-c91d107e-a45f-4dd4-9eaa-26f3bab2544f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271487479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.271487479
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.732539493
Short name T343
Test name
Test status
Simulation time 1261935939 ps
CPU time 16.72 seconds
Started Aug 01 06:02:08 PM PDT 24
Finished Aug 01 06:02:25 PM PDT 24
Peak memory 241904 kb
Host smart-51133dc0-b0e1-4e83-b93f-b3385d26a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732539493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.732539493
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.3924411516
Short name T912
Test name
Test status
Simulation time 508249150 ps
CPU time 3.46 seconds
Started Aug 01 06:02:06 PM PDT 24
Finished Aug 01 06:02:10 PM PDT 24
Peak memory 242164 kb
Host smart-bcf7027e-c284-417e-aec6-834b0caecfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924411516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.3924411516
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.298688968
Short name T479
Test name
Test status
Simulation time 2283820254 ps
CPU time 5.43 seconds
Started Aug 01 06:02:08 PM PDT 24
Finished Aug 01 06:02:14 PM PDT 24
Peak memory 241768 kb
Host smart-679a3d34-ff87-4efa-99bb-a46c0da8e2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298688968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.298688968
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.343955896
Short name T902
Test name
Test status
Simulation time 119348960 ps
CPU time 4.99 seconds
Started Aug 01 06:02:09 PM PDT 24
Finished Aug 01 06:02:14 PM PDT 24
Peak memory 242284 kb
Host smart-01338876-6989-4c97-9461-a076fcf2c406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343955896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.343955896
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.996455134
Short name T141
Test name
Test status
Simulation time 1117441344 ps
CPU time 10.49 seconds
Started Aug 01 06:02:10 PM PDT 24
Finished Aug 01 06:02:21 PM PDT 24
Peak memory 241896 kb
Host smart-493245c8-d9d8-467f-89b2-5e46fe744d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996455134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.996455134
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.4093479437
Short name T188
Test name
Test status
Simulation time 1759301942 ps
CPU time 5.8 seconds
Started Aug 01 06:02:08 PM PDT 24
Finished Aug 01 06:02:14 PM PDT 24
Peak memory 242160 kb
Host smart-a0ce239c-cea6-4b5e-b56d-7d8a102bc4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093479437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.4093479437
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.1578562458
Short name T190
Test name
Test status
Simulation time 848866855 ps
CPU time 19.37 seconds
Started Aug 01 06:02:10 PM PDT 24
Finished Aug 01 06:02:30 PM PDT 24
Peak memory 241992 kb
Host smart-0326b4c5-2be0-4c37-851a-0d21fcb4eaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578562458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.1578562458
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.1481741461
Short name T677
Test name
Test status
Simulation time 907025424 ps
CPU time 28.87 seconds
Started Aug 01 06:02:06 PM PDT 24
Finished Aug 01 06:02:35 PM PDT 24
Peak memory 241788 kb
Host smart-25e925bb-9221-4b50-83dd-ffd764c02de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481741461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.1481741461
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.4216761484
Short name T635
Test name
Test status
Simulation time 2392204754 ps
CPU time 4.43 seconds
Started Aug 01 06:02:09 PM PDT 24
Finished Aug 01 06:02:14 PM PDT 24
Peak memory 242240 kb
Host smart-2d475ba0-c8c2-4f9a-aa3a-a1dfe4bf620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216761484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.4216761484
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.3861816203
Short name T148
Test name
Test status
Simulation time 2638698693 ps
CPU time 4.61 seconds
Started Aug 01 06:02:27 PM PDT 24
Finished Aug 01 06:02:32 PM PDT 24
Peak memory 242396 kb
Host smart-0ec6a93a-e21e-48b7-8aad-eb5d4747fba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861816203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.3861816203
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.2970458169
Short name T691
Test name
Test status
Simulation time 894875545 ps
CPU time 2.73 seconds
Started Aug 01 05:58:37 PM PDT 24
Finished Aug 01 05:58:40 PM PDT 24
Peak memory 240756 kb
Host smart-da4f3c2d-9765-4ac6-b89d-fe654f28ba18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970458169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.2970458169
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.852291953
Short name T13
Test name
Test status
Simulation time 233043040 ps
CPU time 12.67 seconds
Started Aug 01 05:58:29 PM PDT 24
Finished Aug 01 05:58:42 PM PDT 24
Peak memory 241908 kb
Host smart-df7cb7bc-a486-4a9c-8e74-a478e7dc8403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852291953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.852291953
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.2831755478
Short name T481
Test name
Test status
Simulation time 25557875874 ps
CPU time 49 seconds
Started Aug 01 05:58:26 PM PDT 24
Finished Aug 01 05:59:15 PM PDT 24
Peak memory 243128 kb
Host smart-34793a1f-2840-414a-ac8e-12c4aaaa75c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831755478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.2831755478
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.1170540384
Short name T538
Test name
Test status
Simulation time 171832832 ps
CPU time 4.44 seconds
Started Aug 01 05:58:26 PM PDT 24
Finished Aug 01 05:58:31 PM PDT 24
Peak memory 241952 kb
Host smart-f2bd4db2-7e7c-49cc-80c4-a69f9ba19090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170540384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.1170540384
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.64728595
Short name T1031
Test name
Test status
Simulation time 899728294 ps
CPU time 28.13 seconds
Started Aug 01 05:58:42 PM PDT 24
Finished Aug 01 05:59:11 PM PDT 24
Peak memory 245344 kb
Host smart-6cecef73-de81-485d-aa6b-5a5d026e4036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64728595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.64728595
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.1257902366
Short name T97
Test name
Test status
Simulation time 1488305184 ps
CPU time 10.67 seconds
Started Aug 01 05:58:40 PM PDT 24
Finished Aug 01 05:58:51 PM PDT 24
Peak memory 242300 kb
Host smart-df9d62fc-a4e6-4ec2-a1f5-7b8684062120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257902366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.1257902366
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.288030490
Short name T291
Test name
Test status
Simulation time 395516858 ps
CPU time 9.97 seconds
Started Aug 01 05:58:29 PM PDT 24
Finished Aug 01 05:58:39 PM PDT 24
Peak memory 241744 kb
Host smart-d124b135-f9d7-4993-91ce-052ee7623ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288030490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.288030490
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.1489320681
Short name T436
Test name
Test status
Simulation time 1997339060 ps
CPU time 16.22 seconds
Started Aug 01 05:58:28 PM PDT 24
Finished Aug 01 05:58:45 PM PDT 24
Peak memory 241924 kb
Host smart-896cb0c3-f6cc-4ebd-b391-0ac960eb9a6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489320681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.1489320681
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.731215336
Short name T551
Test name
Test status
Simulation time 444228074 ps
CPU time 4.4 seconds
Started Aug 01 05:58:40 PM PDT 24
Finished Aug 01 05:58:45 PM PDT 24
Peak memory 241880 kb
Host smart-a7fa7f7a-c386-402b-8fb7-68521a9da3fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731215336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.731215336
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.3984635932
Short name T877
Test name
Test status
Simulation time 540612406 ps
CPU time 4.64 seconds
Started Aug 01 05:58:28 PM PDT 24
Finished Aug 01 05:58:33 PM PDT 24
Peak memory 242008 kb
Host smart-45f82408-578e-4f6b-bb95-713346ef6ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984635932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.3984635932
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.3402788136
Short name T829
Test name
Test status
Simulation time 8724950939 ps
CPU time 81.69 seconds
Started Aug 01 05:58:38 PM PDT 24
Finished Aug 01 06:00:00 PM PDT 24
Peak memory 248352 kb
Host smart-9b343e00-7297-4e51-82e5-2129ce46f803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402788136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.3402788136
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.3728409336
Short name T272
Test name
Test status
Simulation time 67539401936 ps
CPU time 1287.36 seconds
Started Aug 01 05:58:38 PM PDT 24
Finished Aug 01 06:20:06 PM PDT 24
Peak memory 542448 kb
Host smart-9ddd4639-7389-4b61-bd39-9f2668347e78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728409336 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.3728409336
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.170690504
Short name T560
Test name
Test status
Simulation time 155540108 ps
CPU time 4.4 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 05:58:44 PM PDT 24
Peak memory 241772 kb
Host smart-34baa117-1242-4c4d-9cc1-319164b58a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170690504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.170690504
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.4008663039
Short name T907
Test name
Test status
Simulation time 1953681901 ps
CPU time 6.3 seconds
Started Aug 01 06:02:18 PM PDT 24
Finished Aug 01 06:02:25 PM PDT 24
Peak memory 241964 kb
Host smart-9a51830b-0371-4f80-b35b-34caf58250a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008663039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.4008663039
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.3671133298
Short name T602
Test name
Test status
Simulation time 210694505 ps
CPU time 2.87 seconds
Started Aug 01 06:02:23 PM PDT 24
Finished Aug 01 06:02:26 PM PDT 24
Peak memory 242280 kb
Host smart-3c8e4b17-fa25-4ef5-ace3-0de9d268114a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671133298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3671133298
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.3905778808
Short name T20
Test name
Test status
Simulation time 116328531 ps
CPU time 4.17 seconds
Started Aug 01 06:02:21 PM PDT 24
Finished Aug 01 06:02:25 PM PDT 24
Peak memory 242228 kb
Host smart-9baed598-15ae-497f-ba81-c33820dc199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905778808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.3905778808
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.1480036992
Short name T961
Test name
Test status
Simulation time 10603817620 ps
CPU time 26.4 seconds
Started Aug 01 06:02:17 PM PDT 24
Finished Aug 01 06:02:44 PM PDT 24
Peak memory 241856 kb
Host smart-5ad89cfa-6e13-4b61-abf5-c3c84d237e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480036992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.1480036992
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.2673617836
Short name T505
Test name
Test status
Simulation time 404689529 ps
CPU time 4.54 seconds
Started Aug 01 06:02:18 PM PDT 24
Finished Aug 01 06:02:23 PM PDT 24
Peak memory 242064 kb
Host smart-2c334e16-9321-4f89-b3ee-23fb9eaa4686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673617836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.2673617836
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.398572785
Short name T821
Test name
Test status
Simulation time 137505025 ps
CPU time 4.95 seconds
Started Aug 01 06:02:15 PM PDT 24
Finished Aug 01 06:02:20 PM PDT 24
Peak memory 241928 kb
Host smart-89bbecb5-e60e-4fa9-9c42-5e6c888a36cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398572785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.398572785
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.4230633066
Short name T521
Test name
Test status
Simulation time 1441259285 ps
CPU time 11.64 seconds
Started Aug 01 06:02:21 PM PDT 24
Finished Aug 01 06:02:32 PM PDT 24
Peak memory 241692 kb
Host smart-90a6b904-842d-4b71-bb5b-147b1fa22786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230633066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.4230633066
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.3475912748
Short name T812
Test name
Test status
Simulation time 363419797 ps
CPU time 4.16 seconds
Started Aug 01 06:02:17 PM PDT 24
Finished Aug 01 06:02:22 PM PDT 24
Peak memory 241828 kb
Host smart-98fa1cee-4cb5-445b-a28e-d65c0e7bd9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475912748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.3475912748
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.2508228974
Short name T253
Test name
Test status
Simulation time 414004365 ps
CPU time 9.02 seconds
Started Aug 01 06:02:19 PM PDT 24
Finished Aug 01 06:02:28 PM PDT 24
Peak memory 241916 kb
Host smart-7a5d6614-cd4a-416f-97ac-83daf0c9f8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508228974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2508228974
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.2891502386
Short name T115
Test name
Test status
Simulation time 1930820748 ps
CPU time 5.53 seconds
Started Aug 01 06:02:19 PM PDT 24
Finished Aug 01 06:02:25 PM PDT 24
Peak memory 241844 kb
Host smart-07e0920c-4b09-4d1a-88f7-1ebc89292114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891502386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.2891502386
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.2331749300
Short name T474
Test name
Test status
Simulation time 515750928 ps
CPU time 3.89 seconds
Started Aug 01 06:02:18 PM PDT 24
Finished Aug 01 06:02:22 PM PDT 24
Peak memory 241960 kb
Host smart-ae939f00-fd68-461d-a84b-6bfca87bf41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331749300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.2331749300
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.106488434
Short name T843
Test name
Test status
Simulation time 401355635 ps
CPU time 4.08 seconds
Started Aug 01 06:02:28 PM PDT 24
Finished Aug 01 06:02:32 PM PDT 24
Peak memory 242336 kb
Host smart-db18c720-dcec-448a-80fc-afd09500c710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106488434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.106488434
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.1183079255
Short name T626
Test name
Test status
Simulation time 1860868626 ps
CPU time 7.32 seconds
Started Aug 01 06:02:20 PM PDT 24
Finished Aug 01 06:02:27 PM PDT 24
Peak memory 242496 kb
Host smart-78500c2a-b9b8-4f7e-be53-5d9c16e90ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183079255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1183079255
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.1357084924
Short name T1066
Test name
Test status
Simulation time 585893171 ps
CPU time 5.01 seconds
Started Aug 01 06:02:28 PM PDT 24
Finished Aug 01 06:02:33 PM PDT 24
Peak memory 241912 kb
Host smart-f29482a4-4245-4337-a5f3-9726b529af71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357084924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.1357084924
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.1350288854
Short name T818
Test name
Test status
Simulation time 2532285068 ps
CPU time 7.85 seconds
Started Aug 01 06:02:27 PM PDT 24
Finished Aug 01 06:02:35 PM PDT 24
Peak memory 241952 kb
Host smart-3ec2dd88-8351-4fcb-99fa-069b89587742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350288854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1350288854
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.3291588689
Short name T75
Test name
Test status
Simulation time 170198213 ps
CPU time 4.52 seconds
Started Aug 01 06:02:22 PM PDT 24
Finished Aug 01 06:02:27 PM PDT 24
Peak memory 242168 kb
Host smart-8e124f20-c963-47fc-963b-ad85cfdf02d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291588689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.3291588689
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.1479991541
Short name T1150
Test name
Test status
Simulation time 4795655169 ps
CPU time 12.79 seconds
Started Aug 01 06:02:18 PM PDT 24
Finished Aug 01 06:02:31 PM PDT 24
Peak memory 241852 kb
Host smart-7b91d93d-6acd-4adb-8791-fe6bb9cbe38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479991541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.1479991541
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2420763852
Short name T1149
Test name
Test status
Simulation time 2234822006 ps
CPU time 7.26 seconds
Started Aug 01 06:02:19 PM PDT 24
Finished Aug 01 06:02:26 PM PDT 24
Peak memory 242144 kb
Host smart-8e6d1fdb-02bd-4465-a4ea-c0bb747a64a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420763852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2420763852
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.1995649009
Short name T567
Test name
Test status
Simulation time 523951262 ps
CPU time 12.1 seconds
Started Aug 01 06:02:17 PM PDT 24
Finished Aug 01 06:02:29 PM PDT 24
Peak memory 241812 kb
Host smart-e02811cd-cfcf-4fe5-8608-8af74f09deec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995649009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.1995649009
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.2370995301
Short name T616
Test name
Test status
Simulation time 41865199 ps
CPU time 1.56 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 05:58:42 PM PDT 24
Peak memory 240168 kb
Host smart-51160ee4-1bce-4431-b11f-aee72f4cfbcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370995301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.2370995301
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.576674247
Short name T1084
Test name
Test status
Simulation time 679272833 ps
CPU time 16.18 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 05:58:56 PM PDT 24
Peak memory 241872 kb
Host smart-a898b6e1-91d4-466a-b245-d6f934f4c3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576674247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.576674247
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.1776211001
Short name T589
Test name
Test status
Simulation time 11518251213 ps
CPU time 28.67 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 05:59:09 PM PDT 24
Peak memory 243336 kb
Host smart-f540874d-23f5-4889-831f-a44d4e6928c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776211001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.1776211001
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.2992935726
Short name T816
Test name
Test status
Simulation time 14295006682 ps
CPU time 29.93 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 05:59:10 PM PDT 24
Peak memory 243336 kb
Host smart-c2a32f4c-300f-4a8e-bace-a967dd5bd47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992935726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.2992935726
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.41426531
Short name T450
Test name
Test status
Simulation time 99359606 ps
CPU time 3.88 seconds
Started Aug 01 05:58:38 PM PDT 24
Finished Aug 01 05:58:42 PM PDT 24
Peak memory 241860 kb
Host smart-850ed545-5d9a-4afe-98d5-69db2c9d1c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41426531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.41426531
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.2944828589
Short name T1016
Test name
Test status
Simulation time 1289445780 ps
CPU time 19.6 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 05:59:00 PM PDT 24
Peak memory 241936 kb
Host smart-43b2e93e-d90c-43aa-a509-d868fe715835
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944828589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.2944828589
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.2954272975
Short name T1020
Test name
Test status
Simulation time 502793448 ps
CPU time 8.4 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 05:58:48 PM PDT 24
Peak memory 242048 kb
Host smart-e964a957-a90a-4db3-8ef0-00b1c151c86f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2954272975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.2954272975
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.3349953828
Short name T336
Test name
Test status
Simulation time 562518190 ps
CPU time 11.6 seconds
Started Aug 01 05:58:37 PM PDT 24
Finished Aug 01 05:58:49 PM PDT 24
Peak memory 241860 kb
Host smart-2b038ec6-778b-4ac2-8e20-220764973799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349953828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.3349953828
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.514290114
Short name T1174
Test name
Test status
Simulation time 11104883877 ps
CPU time 63.61 seconds
Started Aug 01 05:58:38 PM PDT 24
Finished Aug 01 05:59:42 PM PDT 24
Peak memory 243852 kb
Host smart-0cf9197e-fa5e-4393-9ee2-d81a95b06738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514290114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.
514290114
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.4022885088
Short name T827
Test name
Test status
Simulation time 39014532052 ps
CPU time 520.63 seconds
Started Aug 01 05:58:40 PM PDT 24
Finished Aug 01 06:07:21 PM PDT 24
Peak memory 256820 kb
Host smart-7e1b1fa2-28dc-4c21-a64d-3f8d7d897273
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022885088 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.4022885088
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.2024630235
Short name T526
Test name
Test status
Simulation time 422139280 ps
CPU time 7.38 seconds
Started Aug 01 05:58:37 PM PDT 24
Finished Aug 01 05:58:44 PM PDT 24
Peak memory 248580 kb
Host smart-fff83659-8fcc-4c1a-b9c9-308b53fa2231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024630235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.2024630235
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.504718921
Short name T627
Test name
Test status
Simulation time 1606581531 ps
CPU time 5.21 seconds
Started Aug 01 06:02:21 PM PDT 24
Finished Aug 01 06:02:26 PM PDT 24
Peak memory 242060 kb
Host smart-c39aba2a-cfed-4df8-9b98-25a609697b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504718921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.504718921
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.943127496
Short name T853
Test name
Test status
Simulation time 298974515 ps
CPU time 6.46 seconds
Started Aug 01 06:02:23 PM PDT 24
Finished Aug 01 06:02:30 PM PDT 24
Peak memory 242288 kb
Host smart-cff4023a-6582-4425-98b7-acbf84407489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943127496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.943127496
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.591472980
Short name T563
Test name
Test status
Simulation time 511798479 ps
CPU time 5.94 seconds
Started Aug 01 06:02:19 PM PDT 24
Finished Aug 01 06:02:25 PM PDT 24
Peak memory 242228 kb
Host smart-26e83618-3061-48d3-9369-3dad657dac39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591472980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.591472980
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.3082758035
Short name T609
Test name
Test status
Simulation time 221373779 ps
CPU time 4.48 seconds
Started Aug 01 06:02:21 PM PDT 24
Finished Aug 01 06:02:26 PM PDT 24
Peak memory 242132 kb
Host smart-e76d4183-c908-4289-b7e8-26904ac064fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082758035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.3082758035
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.3059676543
Short name T783
Test name
Test status
Simulation time 239829284 ps
CPU time 3.78 seconds
Started Aug 01 06:02:23 PM PDT 24
Finished Aug 01 06:02:27 PM PDT 24
Peak memory 242172 kb
Host smart-4276d1d7-51bc-40e0-969c-e77d792f4f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059676543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3059676543
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.3170306806
Short name T160
Test name
Test status
Simulation time 233263904 ps
CPU time 3.84 seconds
Started Aug 01 06:02:19 PM PDT 24
Finished Aug 01 06:02:24 PM PDT 24
Peak memory 242264 kb
Host smart-d58f5227-5855-4511-89a1-86571aeefa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170306806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3170306806
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.3107019083
Short name T541
Test name
Test status
Simulation time 4397548384 ps
CPU time 11.13 seconds
Started Aug 01 06:02:19 PM PDT 24
Finished Aug 01 06:02:31 PM PDT 24
Peak memory 242056 kb
Host smart-c5cf4e4f-2977-4fff-be5a-8d08cce024de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107019083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3107019083
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.3971882745
Short name T553
Test name
Test status
Simulation time 3322278224 ps
CPU time 25.1 seconds
Started Aug 01 06:02:21 PM PDT 24
Finished Aug 01 06:02:47 PM PDT 24
Peak memory 241972 kb
Host smart-96052b2c-b7bd-4d5a-9251-2239dd510e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971882745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.3971882745
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.4268502941
Short name T161
Test name
Test status
Simulation time 566696124 ps
CPU time 4.47 seconds
Started Aug 01 06:02:19 PM PDT 24
Finished Aug 01 06:02:23 PM PDT 24
Peak memory 242432 kb
Host smart-b345edcf-459b-4b1e-87b0-a089d3ae1e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268502941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.4268502941
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.381889771
Short name T395
Test name
Test status
Simulation time 563076899 ps
CPU time 7.78 seconds
Started Aug 01 06:02:19 PM PDT 24
Finished Aug 01 06:02:27 PM PDT 24
Peak memory 241760 kb
Host smart-9198ab54-c144-46b1-a9d9-9cce3da08caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381889771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.381889771
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.1914307913
Short name T1097
Test name
Test status
Simulation time 144159102 ps
CPU time 3.85 seconds
Started Aug 01 06:02:19 PM PDT 24
Finished Aug 01 06:02:23 PM PDT 24
Peak memory 242064 kb
Host smart-6cb13199-c639-41da-b93e-806d11bf655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914307913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.1914307913
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.1917684838
Short name T525
Test name
Test status
Simulation time 126889303 ps
CPU time 4.01 seconds
Started Aug 01 06:02:18 PM PDT 24
Finished Aug 01 06:02:22 PM PDT 24
Peak memory 241868 kb
Host smart-8ffe6194-998e-4d61-921f-34fe073d48c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917684838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.1917684838
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.3672574245
Short name T990
Test name
Test status
Simulation time 219039363 ps
CPU time 4.31 seconds
Started Aug 01 06:02:19 PM PDT 24
Finished Aug 01 06:02:23 PM PDT 24
Peak memory 242420 kb
Host smart-f0a5051a-bbed-4bb9-8bfc-7dbd489c4041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672574245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.3672574245
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.2631928275
Short name T758
Test name
Test status
Simulation time 123297448 ps
CPU time 3.25 seconds
Started Aug 01 06:02:19 PM PDT 24
Finished Aug 01 06:02:23 PM PDT 24
Peak memory 241864 kb
Host smart-3c47ec7a-d13c-4be1-87da-02c62079e5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631928275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.2631928275
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.2484052512
Short name T26
Test name
Test status
Simulation time 1700855066 ps
CPU time 4.17 seconds
Started Aug 01 06:02:20 PM PDT 24
Finished Aug 01 06:02:24 PM PDT 24
Peak memory 242136 kb
Host smart-0dc65eb5-d068-45e1-8ded-5508653fdb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484052512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.2484052512
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.1872646395
Short name T651
Test name
Test status
Simulation time 165620457 ps
CPU time 7.08 seconds
Started Aug 01 06:02:31 PM PDT 24
Finished Aug 01 06:02:38 PM PDT 24
Peak memory 242044 kb
Host smart-803aa343-26d6-4acc-9b6c-d4c99c13469b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872646395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.1872646395
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.2029578031
Short name T1146
Test name
Test status
Simulation time 2762878221 ps
CPU time 7 seconds
Started Aug 01 06:02:30 PM PDT 24
Finished Aug 01 06:02:37 PM PDT 24
Peak memory 241908 kb
Host smart-2a342401-febc-42eb-a6e1-86325904cc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029578031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.2029578031
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.1153203286
Short name T938
Test name
Test status
Simulation time 532361404 ps
CPU time 6.19 seconds
Started Aug 01 06:02:32 PM PDT 24
Finished Aug 01 06:02:39 PM PDT 24
Peak memory 242000 kb
Host smart-85198315-8dcd-4d9d-afe0-be6290db9325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153203286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1153203286
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.1899503429
Short name T901
Test name
Test status
Simulation time 475220768 ps
CPU time 3.62 seconds
Started Aug 01 05:58:48 PM PDT 24
Finished Aug 01 05:58:52 PM PDT 24
Peak memory 240776 kb
Host smart-34f5e418-ae0e-4309-9c7e-4fcb17b52cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899503429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.1899503429
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.720381983
Short name T564
Test name
Test status
Simulation time 1614330065 ps
CPU time 18.36 seconds
Started Aug 01 05:58:38 PM PDT 24
Finished Aug 01 05:58:56 PM PDT 24
Peak memory 248652 kb
Host smart-993de7c1-9780-40a8-84cc-55000ae94d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720381983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.720381983
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.3975148629
Short name T347
Test name
Test status
Simulation time 251383278 ps
CPU time 14.87 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 05:58:54 PM PDT 24
Peak memory 242216 kb
Host smart-5e551b9c-02a8-4d33-89ff-5e6d2af94476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975148629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.3975148629
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.258990284
Short name T406
Test name
Test status
Simulation time 690490371 ps
CPU time 15.68 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 05:58:56 PM PDT 24
Peak memory 242188 kb
Host smart-2f1ac61c-b427-49d2-91c9-36e1b7f18c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258990284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.258990284
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.3755674015
Short name T844
Test name
Test status
Simulation time 154669739 ps
CPU time 4.07 seconds
Started Aug 01 05:58:36 PM PDT 24
Finished Aug 01 05:58:41 PM PDT 24
Peak memory 242192 kb
Host smart-084f958f-e75a-4f08-a7ce-0078643c69e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755674015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.3755674015
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.2662076890
Short name T446
Test name
Test status
Simulation time 8480792906 ps
CPU time 27.54 seconds
Started Aug 01 05:58:40 PM PDT 24
Finished Aug 01 05:59:08 PM PDT 24
Peak memory 242700 kb
Host smart-d89fa655-a38c-4506-aba5-51ba702d23ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662076890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.2662076890
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.2456715966
Short name T679
Test name
Test status
Simulation time 1556655599 ps
CPU time 35.84 seconds
Started Aug 01 05:58:36 PM PDT 24
Finished Aug 01 05:59:12 PM PDT 24
Peak memory 248628 kb
Host smart-109bb8b7-f3e2-4a99-8ec5-9d09c3de2f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456715966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.2456715966
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.1166473653
Short name T152
Test name
Test status
Simulation time 2623828749 ps
CPU time 5 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 05:58:45 PM PDT 24
Peak memory 242296 kb
Host smart-36fd824d-5912-48b4-90d7-b3dfe4b5ac45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166473653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.1166473653
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.991426138
Short name T379
Test name
Test status
Simulation time 588587029 ps
CPU time 15.1 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 05:58:54 PM PDT 24
Peak memory 242132 kb
Host smart-a99f6887-d1a7-46dd-b146-8996081b7494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991426138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.991426138
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.1517190017
Short name T586
Test name
Test status
Simulation time 108329848 ps
CPU time 4.13 seconds
Started Aug 01 05:58:38 PM PDT 24
Finished Aug 01 05:58:42 PM PDT 24
Peak memory 242012 kb
Host smart-a4943dee-5975-47cb-ab2a-cbd9256bc3f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1517190017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.1517190017
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.3700373301
Short name T898
Test name
Test status
Simulation time 394960813 ps
CPU time 8.39 seconds
Started Aug 01 05:58:38 PM PDT 24
Finished Aug 01 05:58:47 PM PDT 24
Peak memory 242328 kb
Host smart-784800d1-2868-4098-b3ea-7d504b877fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700373301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.3700373301
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.54934627
Short name T763
Test name
Test status
Simulation time 40396981978 ps
CPU time 109.85 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 06:00:29 PM PDT 24
Peak memory 249628 kb
Host smart-044271ab-b802-41fc-a572-b7c1b2e4e1a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54934627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.54934627
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.2680672282
Short name T170
Test name
Test status
Simulation time 50287955555 ps
CPU time 1146.66 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 06:17:47 PM PDT 24
Peak memory 288752 kb
Host smart-9e00bf00-105d-48f8-9cea-c2d88b26cd2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680672282 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.2680672282
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.2260300211
Short name T1028
Test name
Test status
Simulation time 808480121 ps
CPU time 6.66 seconds
Started Aug 01 05:58:39 PM PDT 24
Finished Aug 01 05:58:47 PM PDT 24
Peak memory 242284 kb
Host smart-ba8f2ed4-ef01-43fc-aec0-8240c2912b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260300211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.2260300211
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.252862205
Short name T484
Test name
Test status
Simulation time 1629294522 ps
CPU time 5.95 seconds
Started Aug 01 06:02:34 PM PDT 24
Finished Aug 01 06:02:40 PM PDT 24
Peak memory 241988 kb
Host smart-3c0a88af-2f33-4456-a7c7-a4df04b51920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252862205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.252862205
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.2336584921
Short name T490
Test name
Test status
Simulation time 516869393 ps
CPU time 15.5 seconds
Started Aug 01 06:02:33 PM PDT 24
Finished Aug 01 06:02:49 PM PDT 24
Peak memory 241996 kb
Host smart-507129af-2409-4ee1-938e-c247edb1f483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336584921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.2336584921
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.2134421659
Short name T894
Test name
Test status
Simulation time 253475067 ps
CPU time 3.86 seconds
Started Aug 01 06:02:33 PM PDT 24
Finished Aug 01 06:02:37 PM PDT 24
Peak memory 242104 kb
Host smart-b62a7fd4-f9b7-4051-97de-a3bbb1d8e72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134421659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.2134421659
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.2482991009
Short name T1003
Test name
Test status
Simulation time 1196072386 ps
CPU time 4.07 seconds
Started Aug 01 06:02:31 PM PDT 24
Finished Aug 01 06:02:36 PM PDT 24
Peak memory 241892 kb
Host smart-961ec958-b742-4c78-930e-b1974b28d617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482991009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.2482991009
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.308313845
Short name T454
Test name
Test status
Simulation time 306409715 ps
CPU time 4.15 seconds
Started Aug 01 06:02:34 PM PDT 24
Finished Aug 01 06:02:38 PM PDT 24
Peak memory 241944 kb
Host smart-8601937a-d978-45c4-b218-b0e4c86c14d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308313845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.308313845
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.999889916
Short name T1098
Test name
Test status
Simulation time 3006810927 ps
CPU time 7.6 seconds
Started Aug 01 06:02:33 PM PDT 24
Finished Aug 01 06:02:40 PM PDT 24
Peak memory 242016 kb
Host smart-adba67bc-2baa-4fbc-99b5-6a5a732607e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999889916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.999889916
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.3543105140
Short name T608
Test name
Test status
Simulation time 427578752 ps
CPU time 4.47 seconds
Started Aug 01 06:02:33 PM PDT 24
Finished Aug 01 06:02:37 PM PDT 24
Peak memory 242404 kb
Host smart-c714f4b8-ba43-4b9c-9da5-152a5637d14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543105140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.3543105140
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.1520840499
Short name T542
Test name
Test status
Simulation time 184859393 ps
CPU time 8.57 seconds
Started Aug 01 06:02:33 PM PDT 24
Finished Aug 01 06:02:42 PM PDT 24
Peak memory 241948 kb
Host smart-5367f160-1e05-4918-9549-a896b933d58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520840499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.1520840499
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.469852273
Short name T533
Test name
Test status
Simulation time 198799020 ps
CPU time 4.59 seconds
Started Aug 01 06:02:33 PM PDT 24
Finished Aug 01 06:02:38 PM PDT 24
Peak memory 242204 kb
Host smart-81604a44-1b0b-408b-9d4d-449d8b10804f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469852273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.469852273
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.3165645314
Short name T1059
Test name
Test status
Simulation time 426751229 ps
CPU time 6.6 seconds
Started Aug 01 06:02:31 PM PDT 24
Finished Aug 01 06:02:38 PM PDT 24
Peak memory 242228 kb
Host smart-6ac2d084-7d9b-4986-9f1b-8268fba8c328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165645314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.3165645314
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.3633231922
Short name T508
Test name
Test status
Simulation time 183390731 ps
CPU time 4.83 seconds
Started Aug 01 06:02:33 PM PDT 24
Finished Aug 01 06:02:38 PM PDT 24
Peak memory 241952 kb
Host smart-b4514bb5-87b8-41b3-b02d-b3dd81bb6583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633231922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.3633231922
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.3251685802
Short name T727
Test name
Test status
Simulation time 3181108303 ps
CPU time 8.72 seconds
Started Aug 01 06:02:33 PM PDT 24
Finished Aug 01 06:02:42 PM PDT 24
Peak memory 242016 kb
Host smart-9bd6b59f-9ea4-4bcf-8386-12d1d0a8baa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251685802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3251685802
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.3839324865
Short name T962
Test name
Test status
Simulation time 175423935 ps
CPU time 3.71 seconds
Started Aug 01 06:02:32 PM PDT 24
Finished Aug 01 06:02:36 PM PDT 24
Peak memory 242192 kb
Host smart-91df58e3-e0fa-4e15-ae07-f8d0343c00b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839324865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3839324865
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.1497511692
Short name T341
Test name
Test status
Simulation time 2018686123 ps
CPU time 6.76 seconds
Started Aug 01 06:02:30 PM PDT 24
Finished Aug 01 06:02:37 PM PDT 24
Peak memory 241848 kb
Host smart-7301f38b-fbe4-4185-ae26-40390f5294be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497511692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.1497511692
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.2800015364
Short name T530
Test name
Test status
Simulation time 2081488593 ps
CPU time 6.3 seconds
Started Aug 01 06:02:31 PM PDT 24
Finished Aug 01 06:02:37 PM PDT 24
Peak memory 241968 kb
Host smart-a9d0ef9e-1185-4612-8c0c-b65188ea37d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800015364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.2800015364
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.2832774208
Short name T622
Test name
Test status
Simulation time 657664596 ps
CPU time 11.49 seconds
Started Aug 01 06:02:32 PM PDT 24
Finished Aug 01 06:02:44 PM PDT 24
Peak memory 242188 kb
Host smart-e0eaba4b-321c-4b18-92a2-9bb694333acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832774208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.2832774208
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.3630671415
Short name T1168
Test name
Test status
Simulation time 140412665 ps
CPU time 5.12 seconds
Started Aug 01 06:02:31 PM PDT 24
Finished Aug 01 06:02:36 PM PDT 24
Peak memory 242124 kb
Host smart-56d14afa-4642-4c5f-a6ce-afdafdc8bf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630671415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.3630671415
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.2133060989
Short name T373
Test name
Test status
Simulation time 201979585 ps
CPU time 6.2 seconds
Started Aug 01 06:02:31 PM PDT 24
Finished Aug 01 06:02:37 PM PDT 24
Peak memory 241940 kb
Host smart-a1402cff-ba5d-4abb-830b-20b6c7d78b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133060989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.2133060989
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.2823607237
Short name T184
Test name
Test status
Simulation time 180978855 ps
CPU time 3.93 seconds
Started Aug 01 06:02:32 PM PDT 24
Finished Aug 01 06:02:36 PM PDT 24
Peak memory 242316 kb
Host smart-cadb4174-638a-4b76-9569-97e290f94867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823607237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2823607237
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.2720008357
Short name T577
Test name
Test status
Simulation time 369588202 ps
CPU time 12.51 seconds
Started Aug 01 06:02:32 PM PDT 24
Finished Aug 01 06:02:44 PM PDT 24
Peak memory 241844 kb
Host smart-12e2fb36-d8cd-4ae1-ab19-fe32e647c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720008357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.2720008357
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.3450773295
Short name T866
Test name
Test status
Simulation time 110999779 ps
CPU time 1.69 seconds
Started Aug 01 05:58:50 PM PDT 24
Finished Aug 01 05:58:52 PM PDT 24
Peak memory 240316 kb
Host smart-0e5a4de8-1dd5-4b22-be62-4928381973e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450773295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.3450773295
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.1258553729
Short name T891
Test name
Test status
Simulation time 5254787144 ps
CPU time 9.39 seconds
Started Aug 01 05:58:49 PM PDT 24
Finished Aug 01 05:58:59 PM PDT 24
Peak memory 248624 kb
Host smart-b60bde90-c470-413f-a8c0-05fb8e3f60c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258553729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.1258553729
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.2991685455
Short name T344
Test name
Test status
Simulation time 623729884 ps
CPU time 16.31 seconds
Started Aug 01 05:58:50 PM PDT 24
Finished Aug 01 05:59:06 PM PDT 24
Peak memory 242172 kb
Host smart-1e53bf02-336b-4d8d-8657-574147953973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991685455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.2991685455
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.948255847
Short name T656
Test name
Test status
Simulation time 5975157399 ps
CPU time 46.25 seconds
Started Aug 01 05:58:48 PM PDT 24
Finished Aug 01 05:59:34 PM PDT 24
Peak memory 242292 kb
Host smart-041c3d91-254e-4883-9e8c-452ea1f186f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948255847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.948255847
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.1509093171
Short name T753
Test name
Test status
Simulation time 257460552 ps
CPU time 3.5 seconds
Started Aug 01 05:58:50 PM PDT 24
Finished Aug 01 05:58:53 PM PDT 24
Peak memory 242256 kb
Host smart-b53c4f83-5d9a-49f8-b70c-5583a16542a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509093171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.1509093171
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.2505554030
Short name T166
Test name
Test status
Simulation time 899773695 ps
CPU time 27.14 seconds
Started Aug 01 05:58:48 PM PDT 24
Finished Aug 01 05:59:15 PM PDT 24
Peak memory 246276 kb
Host smart-57b5c784-22bd-434f-b93c-f82a000e7572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505554030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.2505554030
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.4151647261
Short name T992
Test name
Test status
Simulation time 2539797501 ps
CPU time 20.85 seconds
Started Aug 01 05:58:49 PM PDT 24
Finished Aug 01 05:59:10 PM PDT 24
Peak memory 242460 kb
Host smart-de903e76-57e8-4ec0-819f-fc6d7d8c7b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151647261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.4151647261
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.569743796
Short name T398
Test name
Test status
Simulation time 142204892 ps
CPU time 6.47 seconds
Started Aug 01 05:58:49 PM PDT 24
Finished Aug 01 05:58:56 PM PDT 24
Peak memory 242056 kb
Host smart-70c6a1df-bf31-42f6-9fd2-d663c7ec9b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569743796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.569743796
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.3453163302
Short name T613
Test name
Test status
Simulation time 1196162035 ps
CPU time 23.44 seconds
Started Aug 01 05:58:49 PM PDT 24
Finished Aug 01 05:59:13 PM PDT 24
Peak memory 241948 kb
Host smart-77a846db-8abf-4a03-a0bb-5f90be10a544
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3453163302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.3453163302
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.1586578697
Short name T360
Test name
Test status
Simulation time 2933582158 ps
CPU time 11.12 seconds
Started Aug 01 05:58:51 PM PDT 24
Finished Aug 01 05:59:02 PM PDT 24
Peak memory 242240 kb
Host smart-cbe52f1d-ff13-4893-bfeb-18f98fc9e0e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1586578697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.1586578697
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.1522391980
Short name T396
Test name
Test status
Simulation time 379492626 ps
CPU time 8.48 seconds
Started Aug 01 05:58:55 PM PDT 24
Finished Aug 01 05:59:03 PM PDT 24
Peak memory 242252 kb
Host smart-9b06730f-f5cd-437b-9d02-a8a3cb04acb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522391980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.1522391980
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.1238309697
Short name T249
Test name
Test status
Simulation time 215810111386 ps
CPU time 1082.88 seconds
Started Aug 01 05:58:54 PM PDT 24
Finished Aug 01 06:16:57 PM PDT 24
Peak memory 286196 kb
Host smart-1f88d24c-e881-4103-9cfb-30c4fa53d171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238309697 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.1238309697
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.2509618869
Short name T382
Test name
Test status
Simulation time 3237875649 ps
CPU time 34.56 seconds
Started Aug 01 05:58:48 PM PDT 24
Finished Aug 01 05:59:23 PM PDT 24
Peak memory 242880 kb
Host smart-cf9312a8-efcf-4064-992c-82c47f8bbdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509618869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.2509618869
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.3279007773
Short name T1113
Test name
Test status
Simulation time 2583495972 ps
CPU time 6.18 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:49 PM PDT 24
Peak memory 241828 kb
Host smart-2e23ec65-d1b8-4a9b-bc66-e35c6dbbbf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279007773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.3279007773
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.4000727475
Short name T497
Test name
Test status
Simulation time 130111137 ps
CPU time 4.79 seconds
Started Aug 01 06:02:46 PM PDT 24
Finished Aug 01 06:02:51 PM PDT 24
Peak memory 242420 kb
Host smart-16377222-cd72-475f-a07a-ac76ecae2db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000727475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.4000727475
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.1236232235
Short name T981
Test name
Test status
Simulation time 409268089 ps
CPU time 9.79 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:54 PM PDT 24
Peak memory 241860 kb
Host smart-22d34785-7ce0-49c5-9d5a-8242ddee3dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236232235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.1236232235
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.2321253643
Short name T546
Test name
Test status
Simulation time 2223619609 ps
CPU time 4.85 seconds
Started Aug 01 06:02:46 PM PDT 24
Finished Aug 01 06:02:50 PM PDT 24
Peak memory 242248 kb
Host smart-d689b6d4-3fd4-47a9-920d-ae613afc3fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321253643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.2321253643
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.3447374583
Short name T858
Test name
Test status
Simulation time 490314489 ps
CPU time 5.67 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:50 PM PDT 24
Peak memory 242044 kb
Host smart-08d804b0-f992-46cc-8d9a-a942bf72642a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447374583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.3447374583
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.3050176995
Short name T944
Test name
Test status
Simulation time 97514420 ps
CPU time 3.5 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:48 PM PDT 24
Peak memory 241964 kb
Host smart-63417a0b-6b65-48e7-b1b5-a5522a753eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050176995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.3050176995
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.1401841303
Short name T596
Test name
Test status
Simulation time 1685576725 ps
CPU time 4.3 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:48 PM PDT 24
Peak memory 241844 kb
Host smart-a811cdea-f190-4d71-bc94-26756cf4ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401841303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.1401841303
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.632557571
Short name T781
Test name
Test status
Simulation time 481147181 ps
CPU time 4.11 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:48 PM PDT 24
Peak memory 242128 kb
Host smart-17da3bb7-747b-42b2-9d27-19b2d3639540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632557571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.632557571
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.3263588260
Short name T819
Test name
Test status
Simulation time 1700590695 ps
CPU time 5.56 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:49 PM PDT 24
Peak memory 241976 kb
Host smart-71f8fd74-2573-4333-ab12-5e7ac1b7d4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263588260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3263588260
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.1658687727
Short name T1036
Test name
Test status
Simulation time 98995144 ps
CPU time 3.83 seconds
Started Aug 01 06:02:46 PM PDT 24
Finished Aug 01 06:02:50 PM PDT 24
Peak memory 242000 kb
Host smart-7c80cb03-147f-43ac-a68a-3e4a9bb10b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658687727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.1658687727
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.1132386512
Short name T442
Test name
Test status
Simulation time 237498799 ps
CPU time 3.31 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:46 PM PDT 24
Peak memory 242312 kb
Host smart-1056540f-6a77-4975-8ed2-27809e1687dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132386512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.1132386512
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.1208299304
Short name T666
Test name
Test status
Simulation time 163392748 ps
CPU time 3.7 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:47 PM PDT 24
Peak memory 242128 kb
Host smart-30b7326d-8804-443d-809d-b5144094df38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208299304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.1208299304
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.1705063165
Short name T863
Test name
Test status
Simulation time 816902249 ps
CPU time 6 seconds
Started Aug 01 06:02:47 PM PDT 24
Finished Aug 01 06:02:53 PM PDT 24
Peak memory 242232 kb
Host smart-fd8fc9fe-69eb-4d7f-8a6f-c52ad1c69e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705063165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.1705063165
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.1474170890
Short name T764
Test name
Test status
Simulation time 112277946 ps
CPU time 3.3 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:47 PM PDT 24
Peak memory 242184 kb
Host smart-b9751b9d-9911-43a2-a289-febfcb349362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474170890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1474170890
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.3889472726
Short name T583
Test name
Test status
Simulation time 296010711 ps
CPU time 4.91 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:48 PM PDT 24
Peak memory 241804 kb
Host smart-4523f4f1-74ab-4047-a94d-3f0d4cfade4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889472726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.3889472726
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.2219494574
Short name T1093
Test name
Test status
Simulation time 2139263900 ps
CPU time 5.35 seconds
Started Aug 01 06:02:45 PM PDT 24
Finished Aug 01 06:02:50 PM PDT 24
Peak memory 242056 kb
Host smart-534415eb-3534-4cad-83d0-6be38ea4977e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219494574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.2219494574
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.1150138334
Short name T706
Test name
Test status
Simulation time 593881030 ps
CPU time 7.83 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:51 PM PDT 24
Peak memory 241996 kb
Host smart-0b2f2fd7-ed27-4713-9d5f-62fbdfcbc2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150138334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.1150138334
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.3886764065
Short name T1065
Test name
Test status
Simulation time 66648493 ps
CPU time 1.79 seconds
Started Aug 01 05:58:50 PM PDT 24
Finished Aug 01 05:58:52 PM PDT 24
Peak memory 240744 kb
Host smart-c9f22eed-5c9f-402a-bc59-06a5a5f6188f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886764065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.3886764065
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.2808330707
Short name T918
Test name
Test status
Simulation time 12786278831 ps
CPU time 27.12 seconds
Started Aug 01 05:58:48 PM PDT 24
Finished Aug 01 05:59:16 PM PDT 24
Peak memory 241848 kb
Host smart-0892faea-7eff-42af-99d6-b5117efd52f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808330707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.2808330707
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.1612704903
Short name T773
Test name
Test status
Simulation time 433883336 ps
CPU time 4.95 seconds
Started Aug 01 05:58:50 PM PDT 24
Finished Aug 01 05:58:55 PM PDT 24
Peak memory 242116 kb
Host smart-77146190-ab13-4340-b1fc-9a52cffeb52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612704903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.1612704903
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.3766102526
Short name T210
Test name
Test status
Simulation time 3056503923 ps
CPU time 49.51 seconds
Started Aug 01 05:58:52 PM PDT 24
Finished Aug 01 05:59:42 PM PDT 24
Peak memory 249524 kb
Host smart-f0278fea-1067-4cbf-9270-125b999cfe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766102526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3766102526
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.2460382573
Short name T1152
Test name
Test status
Simulation time 1922729206 ps
CPU time 22.19 seconds
Started Aug 01 05:58:52 PM PDT 24
Finished Aug 01 05:59:14 PM PDT 24
Peak memory 242132 kb
Host smart-01c907de-0c81-4da3-ae49-c599b54205df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460382573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.2460382573
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.772840522
Short name T940
Test name
Test status
Simulation time 207990032 ps
CPU time 4.85 seconds
Started Aug 01 05:58:55 PM PDT 24
Finished Aug 01 05:59:00 PM PDT 24
Peak memory 241824 kb
Host smart-bd882218-0329-43ed-a08b-0b84c66d0e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772840522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.772840522
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.3605989432
Short name T1161
Test name
Test status
Simulation time 1813601672 ps
CPU time 25.46 seconds
Started Aug 01 05:58:50 PM PDT 24
Finished Aug 01 05:59:15 PM PDT 24
Peak memory 242120 kb
Host smart-d30eb50a-02a5-44c1-a741-091a94a30ba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605989432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.3605989432
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.1366057232
Short name T489
Test name
Test status
Simulation time 356124957 ps
CPU time 5.2 seconds
Started Aug 01 05:58:52 PM PDT 24
Finished Aug 01 05:58:58 PM PDT 24
Peak memory 241908 kb
Host smart-8b75c747-c52c-4826-bcd5-a39305abee3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366057232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.1366057232
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.2442720499
Short name T1131
Test name
Test status
Simulation time 36304883308 ps
CPU time 508.52 seconds
Started Aug 01 05:58:50 PM PDT 24
Finished Aug 01 06:07:19 PM PDT 24
Peak memory 265044 kb
Host smart-757e3260-784a-4cf1-95a0-5af160ba5a90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442720499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.2442720499
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.2605681044
Short name T81
Test name
Test status
Simulation time 1511902549 ps
CPU time 21.11 seconds
Started Aug 01 05:58:51 PM PDT 24
Finished Aug 01 05:59:13 PM PDT 24
Peak memory 242660 kb
Host smart-5e503d5e-fd03-44fd-8bf1-7ce55f9e7424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605681044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.2605681044
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.1933429594
Short name T500
Test name
Test status
Simulation time 217946786 ps
CPU time 4.25 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:49 PM PDT 24
Peak memory 242180 kb
Host smart-48fc211f-93ba-49e7-8074-21808e61ca82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933429594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.1933429594
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.3720931694
Short name T135
Test name
Test status
Simulation time 138001130 ps
CPU time 7.02 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:51 PM PDT 24
Peak memory 241764 kb
Host smart-65024b5a-a6e1-4a87-802d-c5cdd352933f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720931694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.3720931694
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.2155990873
Short name T180
Test name
Test status
Simulation time 376107126 ps
CPU time 3.49 seconds
Started Aug 01 06:02:42 PM PDT 24
Finished Aug 01 06:02:45 PM PDT 24
Peak memory 242048 kb
Host smart-fddf29e2-460e-4532-8045-5fe781b04856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155990873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.2155990873
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.2508958755
Short name T515
Test name
Test status
Simulation time 277174870 ps
CPU time 6.67 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:51 PM PDT 24
Peak memory 242292 kb
Host smart-873c1ca0-dfc8-4efb-9b3a-da5f24906e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508958755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2508958755
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.3057651044
Short name T1024
Test name
Test status
Simulation time 438103517 ps
CPU time 3.43 seconds
Started Aug 01 06:02:45 PM PDT 24
Finished Aug 01 06:02:49 PM PDT 24
Peak memory 241880 kb
Host smart-d66e8815-9fc8-458b-af4e-9fca0a9a390f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057651044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.3057651044
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.3944561167
Short name T339
Test name
Test status
Simulation time 416899834 ps
CPU time 6.92 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:51 PM PDT 24
Peak memory 241780 kb
Host smart-7784c228-df96-4a02-87b6-9c6ed332a350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944561167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.3944561167
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.1409389547
Short name T178
Test name
Test status
Simulation time 160588449 ps
CPU time 4.64 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:49 PM PDT 24
Peak memory 242272 kb
Host smart-8de60309-eb54-4cb3-a2ed-b2025275670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409389547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.1409389547
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.3525189856
Short name T728
Test name
Test status
Simulation time 255483366 ps
CPU time 6.78 seconds
Started Aug 01 06:02:45 PM PDT 24
Finished Aug 01 06:02:52 PM PDT 24
Peak memory 241904 kb
Host smart-150eee52-544b-4b22-9a0d-c7ec7bc8c0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525189856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3525189856
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.3856215250
Short name T754
Test name
Test status
Simulation time 111349260 ps
CPU time 3.62 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:47 PM PDT 24
Peak memory 241960 kb
Host smart-e507ce64-4e89-47f0-b0f1-492e10494d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856215250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.3856215250
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.4111993045
Short name T998
Test name
Test status
Simulation time 342389884 ps
CPU time 4.82 seconds
Started Aug 01 06:02:46 PM PDT 24
Finished Aug 01 06:02:51 PM PDT 24
Peak memory 241732 kb
Host smart-3a14cfce-049b-449d-bc69-88111e9626df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111993045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.4111993045
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.3574035041
Short name T874
Test name
Test status
Simulation time 241399754 ps
CPU time 4.83 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:48 PM PDT 24
Peak memory 242192 kb
Host smart-7960a776-9b90-4ef2-a669-8c599b451b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574035041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.3574035041
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.220479999
Short name T337
Test name
Test status
Simulation time 1021893056 ps
CPU time 22.02 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:03:05 PM PDT 24
Peak memory 242200 kb
Host smart-a204d520-11cf-463b-8a8a-ac9bf7488351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220479999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.220479999
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.3812408521
Short name T28
Test name
Test status
Simulation time 151005711 ps
CPU time 3.82 seconds
Started Aug 01 06:03:19 PM PDT 24
Finished Aug 01 06:03:22 PM PDT 24
Peak memory 242176 kb
Host smart-513850f9-58b6-445a-a3fa-9e3b0f8a4ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812408521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3812408521
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.4040669376
Short name T799
Test name
Test status
Simulation time 2969615431 ps
CPU time 7.59 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:51 PM PDT 24
Peak memory 242280 kb
Host smart-37f4deb7-f33a-4d8d-af41-4dd588dbd7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040669376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.4040669376
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.1224282557
Short name T896
Test name
Test status
Simulation time 9385174821 ps
CPU time 29.97 seconds
Started Aug 01 06:02:46 PM PDT 24
Finished Aug 01 06:03:16 PM PDT 24
Peak memory 242032 kb
Host smart-1bb38acd-7e7d-4a4c-89a7-9cecfb048caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224282557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.1224282557
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.3730515348
Short name T21
Test name
Test status
Simulation time 335516235 ps
CPU time 4.47 seconds
Started Aug 01 06:02:46 PM PDT 24
Finished Aug 01 06:02:51 PM PDT 24
Peak memory 242004 kb
Host smart-ee3b3fe7-3d94-4b04-9592-7d818fff5c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730515348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.3730515348
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.2161548414
Short name T785
Test name
Test status
Simulation time 204720889 ps
CPU time 10.33 seconds
Started Aug 01 06:02:45 PM PDT 24
Finished Aug 01 06:02:55 PM PDT 24
Peak memory 241996 kb
Host smart-0aa36c9d-6a18-4175-afbe-3b2c858533d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161548414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.2161548414
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.4256577527
Short name T134
Test name
Test status
Simulation time 2123293543 ps
CPU time 7.32 seconds
Started Aug 01 06:02:45 PM PDT 24
Finished Aug 01 06:02:53 PM PDT 24
Peak memory 242296 kb
Host smart-08604eee-227a-41f6-845f-ae2042f6f4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256577527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.4256577527
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.4085067439
Short name T663
Test name
Test status
Simulation time 79667148 ps
CPU time 1.75 seconds
Started Aug 01 05:58:48 PM PDT 24
Finished Aug 01 05:58:49 PM PDT 24
Peak memory 240776 kb
Host smart-a950760a-a4ae-476b-8a4b-8b0e1074760a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085067439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.4085067439
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.2452844909
Short name T8
Test name
Test status
Simulation time 485977872 ps
CPU time 16 seconds
Started Aug 01 05:58:49 PM PDT 24
Finished Aug 01 05:59:05 PM PDT 24
Peak memory 242488 kb
Host smart-d7917428-6578-4533-bffc-cb74f0f1a393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452844909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.2452844909
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.3419341398
Short name T513
Test name
Test status
Simulation time 462126590 ps
CPU time 13.18 seconds
Started Aug 01 05:58:51 PM PDT 24
Finished Aug 01 05:59:04 PM PDT 24
Peak memory 241844 kb
Host smart-a074be86-652b-47ee-93b1-412ee07b9a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419341398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.3419341398
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.3607903076
Short name T197
Test name
Test status
Simulation time 2731221209 ps
CPU time 24.76 seconds
Started Aug 01 05:58:50 PM PDT 24
Finished Aug 01 05:59:14 PM PDT 24
Peak memory 242072 kb
Host smart-f8efe8aa-5207-4409-bd63-bc4cb28095e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607903076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.3607903076
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.2982986968
Short name T149
Test name
Test status
Simulation time 586422120 ps
CPU time 4.35 seconds
Started Aug 01 05:58:47 PM PDT 24
Finished Aug 01 05:58:52 PM PDT 24
Peak memory 242248 kb
Host smart-62b226b1-5236-4a20-a1d7-1a31fdd0b2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982986968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2982986968
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.306506626
Short name T510
Test name
Test status
Simulation time 12112428694 ps
CPU time 100.58 seconds
Started Aug 01 05:58:50 PM PDT 24
Finished Aug 01 06:00:31 PM PDT 24
Peak memory 242168 kb
Host smart-967dc827-51b7-4502-87df-70c2c3ce065c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306506626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.306506626
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.3229738862
Short name T466
Test name
Test status
Simulation time 918193486 ps
CPU time 17.51 seconds
Started Aug 01 05:58:53 PM PDT 24
Finished Aug 01 05:59:10 PM PDT 24
Peak memory 242592 kb
Host smart-891550c7-c727-4706-9a44-ca6e81e81ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229738862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.3229738862
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.2555941956
Short name T606
Test name
Test status
Simulation time 368999198 ps
CPU time 10.39 seconds
Started Aug 01 05:58:50 PM PDT 24
Finished Aug 01 05:59:01 PM PDT 24
Peak memory 241888 kb
Host smart-69cd9208-77bc-4a1a-a619-84c423dcb6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555941956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.2555941956
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.679819947
Short name T873
Test name
Test status
Simulation time 1147122596 ps
CPU time 23.15 seconds
Started Aug 01 05:58:55 PM PDT 24
Finished Aug 01 05:59:18 PM PDT 24
Peak memory 242040 kb
Host smart-69358681-25f6-4b53-b0d6-25aaa3d54e98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=679819947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.679819947
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.1505407179
Short name T358
Test name
Test status
Simulation time 4323071046 ps
CPU time 13.29 seconds
Started Aug 01 05:58:53 PM PDT 24
Finished Aug 01 05:59:06 PM PDT 24
Peak memory 241888 kb
Host smart-9403eb0b-7b20-4be8-b5af-d78c0cf11b0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505407179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1505407179
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.1428301366
Short name T1164
Test name
Test status
Simulation time 3923356165 ps
CPU time 12.99 seconds
Started Aug 01 05:58:53 PM PDT 24
Finished Aug 01 05:59:06 PM PDT 24
Peak memory 241988 kb
Host smart-bd3d68f4-2ac3-4f34-bc66-dc9e050a5ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428301366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.1428301366
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.3062739544
Short name T1023
Test name
Test status
Simulation time 34942590704 ps
CPU time 262.25 seconds
Started Aug 01 05:58:52 PM PDT 24
Finished Aug 01 06:03:14 PM PDT 24
Peak memory 264964 kb
Host smart-01043ba3-fd1b-4e89-8840-c396a75f86e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062739544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.3062739544
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.2156637395
Short name T130
Test name
Test status
Simulation time 99962833341 ps
CPU time 605.5 seconds
Started Aug 01 05:58:49 PM PDT 24
Finished Aug 01 06:08:55 PM PDT 24
Peak memory 265132 kb
Host smart-54df5a9a-de2d-489f-8455-1e6e8c6e905c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156637395 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.2156637395
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.1620247552
Short name T591
Test name
Test status
Simulation time 1852082885 ps
CPU time 25.49 seconds
Started Aug 01 05:58:48 PM PDT 24
Finished Aug 01 05:59:13 PM PDT 24
Peak memory 242704 kb
Host smart-15305ff1-7a3c-4d72-8fed-747509546bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620247552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.1620247552
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.1642702447
Short name T1068
Test name
Test status
Simulation time 299984371 ps
CPU time 4.14 seconds
Started Aug 01 06:02:47 PM PDT 24
Finished Aug 01 06:02:51 PM PDT 24
Peak memory 242144 kb
Host smart-d7d7242c-8198-4a6d-a212-77281c5ff04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642702447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.1642702447
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.2588974987
Short name T989
Test name
Test status
Simulation time 147646143 ps
CPU time 2.93 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:46 PM PDT 24
Peak memory 242312 kb
Host smart-ef14cbbb-9fd2-466a-a18a-78ce6a3ddf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588974987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.2588974987
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.4129182141
Short name T657
Test name
Test status
Simulation time 134461733 ps
CPU time 3.83 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:47 PM PDT 24
Peak memory 241964 kb
Host smart-367afcbd-75e5-42f1-8d91-5c28f70dcaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129182141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.4129182141
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.3083525860
Short name T970
Test name
Test status
Simulation time 6771725826 ps
CPU time 13.32 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:56 PM PDT 24
Peak memory 241896 kb
Host smart-5526a8c1-04d2-4194-931b-55efa5f4ef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083525860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.3083525860
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.1736035354
Short name T759
Test name
Test status
Simulation time 170876069 ps
CPU time 3.69 seconds
Started Aug 01 06:02:45 PM PDT 24
Finished Aug 01 06:02:49 PM PDT 24
Peak memory 241912 kb
Host smart-29ccf78e-965a-4a36-9502-c946a26c2bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736035354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.1736035354
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.4243156949
Short name T1132
Test name
Test status
Simulation time 321506108 ps
CPU time 3.64 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:46 PM PDT 24
Peak memory 241824 kb
Host smart-6bf1cb35-506d-4a49-8d9b-9355dd82134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243156949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.4243156949
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.3323160638
Short name T966
Test name
Test status
Simulation time 105560313 ps
CPU time 3.69 seconds
Started Aug 01 06:02:46 PM PDT 24
Finished Aug 01 06:02:50 PM PDT 24
Peak memory 241940 kb
Host smart-4a7e4141-283f-417e-85c4-30664efb2e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323160638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.3323160638
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.4175457604
Short name T1140
Test name
Test status
Simulation time 245829724 ps
CPU time 5.57 seconds
Started Aug 01 06:02:42 PM PDT 24
Finished Aug 01 06:02:48 PM PDT 24
Peak memory 242184 kb
Host smart-a7cefb30-1f0e-41d7-b19d-d871583777bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175457604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.4175457604
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.1746578516
Short name T77
Test name
Test status
Simulation time 164905538 ps
CPU time 3.82 seconds
Started Aug 01 06:02:42 PM PDT 24
Finished Aug 01 06:02:46 PM PDT 24
Peak memory 242196 kb
Host smart-19eb56b8-014a-4aa8-8982-c33732a48f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746578516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1746578516
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.3077500026
Short name T532
Test name
Test status
Simulation time 359265778 ps
CPU time 9.53 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:54 PM PDT 24
Peak memory 241964 kb
Host smart-54fd154b-a6f2-420f-997d-e4fa83533283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077500026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.3077500026
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.3854796370
Short name T107
Test name
Test status
Simulation time 149760806 ps
CPU time 3.71 seconds
Started Aug 01 06:02:43 PM PDT 24
Finished Aug 01 06:02:47 PM PDT 24
Peak memory 242000 kb
Host smart-fd4f5a42-bafa-4e00-aadd-3f2f0d87bc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854796370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.3854796370
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.3908949031
Short name T493
Test name
Test status
Simulation time 112162443 ps
CPU time 3.53 seconds
Started Aug 01 06:02:47 PM PDT 24
Finished Aug 01 06:02:50 PM PDT 24
Peak memory 242228 kb
Host smart-68729897-165e-4ff0-b18e-16f56108f7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908949031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.3908949031
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.4161764585
Short name T1165
Test name
Test status
Simulation time 280649746 ps
CPU time 7.61 seconds
Started Aug 01 06:02:45 PM PDT 24
Finished Aug 01 06:02:53 PM PDT 24
Peak memory 241984 kb
Host smart-9c420c80-810a-4c53-b372-7d7492b819a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161764585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.4161764585
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.2705832083
Short name T233
Test name
Test status
Simulation time 2293432034 ps
CPU time 19.51 seconds
Started Aug 01 06:02:46 PM PDT 24
Finished Aug 01 06:03:06 PM PDT 24
Peak memory 242136 kb
Host smart-6ebb3798-6ec4-4584-8d05-f663b56a6344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705832083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.2705832083
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.2783047107
Short name T585
Test name
Test status
Simulation time 2160748966 ps
CPU time 4.34 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:48 PM PDT 24
Peak memory 242244 kb
Host smart-3f1c9f4f-365c-42be-8026-26d69f4173a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783047107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.2783047107
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.2029248382
Short name T207
Test name
Test status
Simulation time 675605948 ps
CPU time 17.15 seconds
Started Aug 01 06:02:45 PM PDT 24
Finished Aug 01 06:03:02 PM PDT 24
Peak memory 242312 kb
Host smart-4b23905e-7ef4-46bc-ac80-05d00b216dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029248382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.2029248382
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.1163853138
Short name T817
Test name
Test status
Simulation time 183464010 ps
CPU time 4.78 seconds
Started Aug 01 06:02:46 PM PDT 24
Finished Aug 01 06:02:51 PM PDT 24
Peak memory 241904 kb
Host smart-68c69bf2-5791-493a-b192-7ce8f49a4c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163853138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.1163853138
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.3180792191
Short name T203
Test name
Test status
Simulation time 801128103 ps
CPU time 1.79 seconds
Started Aug 01 05:58:58 PM PDT 24
Finished Aug 01 05:59:00 PM PDT 24
Peak memory 240752 kb
Host smart-01b0c234-a98a-4d2b-a405-eb5cd416a736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180792191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.3180792191
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.2895602115
Short name T729
Test name
Test status
Simulation time 1479604468 ps
CPU time 3.43 seconds
Started Aug 01 05:59:00 PM PDT 24
Finished Aug 01 05:59:04 PM PDT 24
Peak memory 248424 kb
Host smart-865c8c9a-d67b-43a3-bec5-f09501be499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895602115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.2895602115
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.779461716
Short name T923
Test name
Test status
Simulation time 15048405750 ps
CPU time 49.39 seconds
Started Aug 01 05:58:58 PM PDT 24
Finished Aug 01 05:59:47 PM PDT 24
Peak memory 245128 kb
Host smart-b0b83933-fede-4f97-94c4-b69d0183c779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779461716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.779461716
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.604547381
Short name T437
Test name
Test status
Simulation time 2706924039 ps
CPU time 22.11 seconds
Started Aug 01 05:58:46 PM PDT 24
Finished Aug 01 05:59:08 PM PDT 24
Peak memory 242508 kb
Host smart-c164bde4-1ecd-4b26-95fb-f1edf940589e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604547381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.604547381
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.1499951543
Short name T697
Test name
Test status
Simulation time 1521967157 ps
CPU time 6.16 seconds
Started Aug 01 05:58:49 PM PDT 24
Finished Aug 01 05:58:55 PM PDT 24
Peak memory 242028 kb
Host smart-251d019d-0d8e-44c5-b682-22127af11aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499951543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.1499951543
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.2690206800
Short name T155
Test name
Test status
Simulation time 15619886227 ps
CPU time 36.82 seconds
Started Aug 01 05:58:58 PM PDT 24
Finished Aug 01 05:59:35 PM PDT 24
Peak memory 246276 kb
Host smart-2990dd7a-f9ab-4899-a77c-4f11c3525ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690206800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.2690206800
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.3783172118
Short name T387
Test name
Test status
Simulation time 859300384 ps
CPU time 14.81 seconds
Started Aug 01 05:58:59 PM PDT 24
Finished Aug 01 05:59:14 PM PDT 24
Peak memory 241856 kb
Host smart-18b10f70-b1b7-4125-8fb8-7f69a3e8462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783172118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.3783172118
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.4179858587
Short name T423
Test name
Test status
Simulation time 794865378 ps
CPU time 20.19 seconds
Started Aug 01 05:58:48 PM PDT 24
Finished Aug 01 05:59:09 PM PDT 24
Peak memory 242224 kb
Host smart-b68f1eea-11db-42ce-bda0-32ebface0ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179858587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.4179858587
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.1320169145
Short name T381
Test name
Test status
Simulation time 248836685 ps
CPU time 5.4 seconds
Started Aug 01 05:58:46 PM PDT 24
Finished Aug 01 05:58:52 PM PDT 24
Peak memory 241948 kb
Host smart-292a6100-ac6e-45f1-8c85-144e50f82789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320169145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.1320169145
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.1296662553
Short name T682
Test name
Test status
Simulation time 125438303 ps
CPU time 4.96 seconds
Started Aug 01 05:59:01 PM PDT 24
Finished Aug 01 05:59:06 PM PDT 24
Peak memory 241844 kb
Host smart-43b875eb-8a58-4518-8dee-fb092f9e3b2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296662553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.1296662553
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.2801130777
Short name T394
Test name
Test status
Simulation time 508430593 ps
CPU time 6.49 seconds
Started Aug 01 05:58:53 PM PDT 24
Finished Aug 01 05:59:00 PM PDT 24
Peak memory 242260 kb
Host smart-3d1e04cf-64dc-4fd3-b6f7-d0ac2c52616c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801130777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.2801130777
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.1852509104
Short name T16
Test name
Test status
Simulation time 147564754800 ps
CPU time 3081.22 seconds
Started Aug 01 05:59:01 PM PDT 24
Finished Aug 01 06:50:22 PM PDT 24
Peak memory 456640 kb
Host smart-4df862d6-e43a-4917-9637-60a30d6b9a38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852509104 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.1852509104
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.3496577603
Short name T195
Test name
Test status
Simulation time 15460156117 ps
CPU time 45.12 seconds
Started Aug 01 05:58:58 PM PDT 24
Finished Aug 01 05:59:44 PM PDT 24
Peak memory 248576 kb
Host smart-88372770-6568-4baa-987a-9f1d242e9ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496577603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3496577603
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.1545103319
Short name T958
Test name
Test status
Simulation time 290162086 ps
CPU time 3.97 seconds
Started Aug 01 06:02:44 PM PDT 24
Finished Aug 01 06:02:48 PM PDT 24
Peak memory 242108 kb
Host smart-f698bc67-e5a2-4b30-9fe6-14f3e314d5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545103319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1545103319
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.2872050887
Short name T599
Test name
Test status
Simulation time 340581451 ps
CPU time 9.66 seconds
Started Aug 01 06:02:46 PM PDT 24
Finished Aug 01 06:02:56 PM PDT 24
Peak memory 241848 kb
Host smart-67c391fb-72e6-486e-a083-fe7dc3aaf598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872050887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.2872050887
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.2314338884
Short name T87
Test name
Test status
Simulation time 1734276908 ps
CPU time 6.85 seconds
Started Aug 01 06:02:48 PM PDT 24
Finished Aug 01 06:02:55 PM PDT 24
Peak memory 241964 kb
Host smart-3fbdbe1e-c7ed-4b6a-9e3e-4cabcc757350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314338884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.2314338884
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.882012630
Short name T1013
Test name
Test status
Simulation time 197813849 ps
CPU time 3.46 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:02:58 PM PDT 24
Peak memory 241988 kb
Host smart-0fdf3fb3-1c0b-4186-a209-ba93d590b0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882012630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.882012630
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.2851950784
Short name T181
Test name
Test status
Simulation time 206332314 ps
CPU time 3.78 seconds
Started Aug 01 06:02:57 PM PDT 24
Finished Aug 01 06:03:01 PM PDT 24
Peak memory 242340 kb
Host smart-a1d7ddfb-66c4-4ff4-a236-64fbf17e1dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851950784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2851950784
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.2149368613
Short name T374
Test name
Test status
Simulation time 387872831 ps
CPU time 11.15 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:03:06 PM PDT 24
Peak memory 241896 kb
Host smart-4f79f180-00fa-4870-aed9-c81b86b4bd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149368613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.2149368613
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.1012338532
Short name T410
Test name
Test status
Simulation time 178354800 ps
CPU time 4.7 seconds
Started Aug 01 06:02:54 PM PDT 24
Finished Aug 01 06:02:59 PM PDT 24
Peak memory 242040 kb
Host smart-52886532-7047-4eba-a2ff-ec7b98646b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012338532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1012338532
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.2474115681
Short name T939
Test name
Test status
Simulation time 225601070 ps
CPU time 5.84 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:03:01 PM PDT 24
Peak memory 241888 kb
Host smart-a71c8b42-1eb8-490f-89a2-7a27d28ebc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474115681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.2474115681
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.32233123
Short name T885
Test name
Test status
Simulation time 182731002 ps
CPU time 4.02 seconds
Started Aug 01 06:02:59 PM PDT 24
Finished Aug 01 06:03:03 PM PDT 24
Peak memory 241968 kb
Host smart-d72bdb0d-d980-4da5-9fec-1f6c181e676c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32233123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.32233123
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.3297978886
Short name T556
Test name
Test status
Simulation time 256902543 ps
CPU time 14.72 seconds
Started Aug 01 06:02:59 PM PDT 24
Finished Aug 01 06:03:14 PM PDT 24
Peak memory 242316 kb
Host smart-9d70af9a-cc4d-4f96-aac4-868a7a8291ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297978886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.3297978886
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.986996652
Short name T631
Test name
Test status
Simulation time 274330629 ps
CPU time 3.75 seconds
Started Aug 01 06:02:56 PM PDT 24
Finished Aug 01 06:03:00 PM PDT 24
Peak memory 241800 kb
Host smart-d161f6ef-de36-4e20-bbee-6093ead20c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986996652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.986996652
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.2326006054
Short name T338
Test name
Test status
Simulation time 135192767 ps
CPU time 5.46 seconds
Started Aug 01 06:02:54 PM PDT 24
Finished Aug 01 06:03:00 PM PDT 24
Peak memory 241940 kb
Host smart-0e421cd2-9c8f-462c-86ec-262e5420c40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326006054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.2326006054
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.1546348969
Short name T495
Test name
Test status
Simulation time 1898256456 ps
CPU time 3.65 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:02:58 PM PDT 24
Peak memory 242320 kb
Host smart-5c015b96-6d10-463c-984a-091f40768a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546348969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.1546348969
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.2573396475
Short name T145
Test name
Test status
Simulation time 2074828695 ps
CPU time 7.84 seconds
Started Aug 01 06:02:56 PM PDT 24
Finished Aug 01 06:03:04 PM PDT 24
Peak memory 242048 kb
Host smart-3aa8c989-5a08-4136-a2ce-580f4ac8a9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573396475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.2573396475
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.1640317237
Short name T1134
Test name
Test status
Simulation time 330231035 ps
CPU time 5.36 seconds
Started Aug 01 06:02:57 PM PDT 24
Finished Aug 01 06:03:02 PM PDT 24
Peak memory 242088 kb
Host smart-25b7be17-b150-4491-82eb-de7eaaadeabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640317237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.1640317237
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.1380686521
Short name T644
Test name
Test status
Simulation time 97119767 ps
CPU time 3.62 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:02:59 PM PDT 24
Peak memory 242312 kb
Host smart-e6d72885-a6ab-437d-9ed2-741236f37651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380686521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1380686521
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.2610606648
Short name T540
Test name
Test status
Simulation time 394205893 ps
CPU time 4.1 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:02:59 PM PDT 24
Peak memory 241936 kb
Host smart-135f043a-4b9a-42ba-95e7-4b37a7f7063f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610606648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.2610606648
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.2972022525
Short name T488
Test name
Test status
Simulation time 125100275 ps
CPU time 4.01 seconds
Started Aug 01 06:02:57 PM PDT 24
Finished Aug 01 06:03:01 PM PDT 24
Peak memory 241960 kb
Host smart-5d2f3d58-03a4-4a54-8f45-ebd338da9a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972022525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2972022525
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.373218991
Short name T875
Test name
Test status
Simulation time 387190619 ps
CPU time 5.03 seconds
Started Aug 01 06:02:57 PM PDT 24
Finished Aug 01 06:03:02 PM PDT 24
Peak memory 242112 kb
Host smart-34944760-2cf8-4370-a840-c043aea4072f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373218991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.373218991
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.605267235
Short name T401
Test name
Test status
Simulation time 187794726 ps
CPU time 1.59 seconds
Started Aug 01 05:57:57 PM PDT 24
Finished Aug 01 05:57:59 PM PDT 24
Peak memory 240492 kb
Host smart-714001c4-0d7e-436f-8340-55bd16483928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605267235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.605267235
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.781516549
Short name T701
Test name
Test status
Simulation time 624602067 ps
CPU time 12.43 seconds
Started Aug 01 05:57:47 PM PDT 24
Finished Aug 01 05:58:00 PM PDT 24
Peak memory 248592 kb
Host smart-dba116d9-5397-4f16-b88a-d09e16f70cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781516549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.781516549
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.1323457152
Short name T1117
Test name
Test status
Simulation time 1830345659 ps
CPU time 32.83 seconds
Started Aug 01 05:57:57 PM PDT 24
Finished Aug 01 05:58:30 PM PDT 24
Peak memory 244376 kb
Host smart-0e28355f-3374-46f7-be67-f1bc3342d00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323457152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.1323457152
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.3217516217
Short name T231
Test name
Test status
Simulation time 539132934 ps
CPU time 12.33 seconds
Started Aug 01 05:57:54 PM PDT 24
Finished Aug 01 05:58:06 PM PDT 24
Peak memory 241912 kb
Host smart-d82b0e9f-16da-4b41-a264-37eb8498b0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217516217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.3217516217
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.3875038980
Short name T100
Test name
Test status
Simulation time 1089540490 ps
CPU time 7.55 seconds
Started Aug 01 05:57:52 PM PDT 24
Finished Aug 01 05:58:00 PM PDT 24
Peak memory 241988 kb
Host smart-47e6dd6b-3528-4ef7-829d-7b81226108de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875038980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.3875038980
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.1672784640
Short name T861
Test name
Test status
Simulation time 158884374 ps
CPU time 4.05 seconds
Started Aug 01 05:57:47 PM PDT 24
Finished Aug 01 05:57:51 PM PDT 24
Peak memory 241952 kb
Host smart-7dd3f835-b2c7-4d5e-b151-522ae77fc341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672784640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.1672784640
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.1093235417
Short name T1060
Test name
Test status
Simulation time 3520998865 ps
CPU time 7.81 seconds
Started Aug 01 05:57:49 PM PDT 24
Finished Aug 01 05:57:57 PM PDT 24
Peak memory 242124 kb
Host smart-30298956-8fee-4815-8bff-b3844039c624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093235417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.1093235417
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.2352117290
Short name T1069
Test name
Test status
Simulation time 5545519851 ps
CPU time 17.73 seconds
Started Aug 01 05:57:51 PM PDT 24
Finished Aug 01 05:58:09 PM PDT 24
Peak memory 248664 kb
Host smart-d339c867-2656-4994-97be-ba0eb4f49d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352117290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2352117290
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.2067068148
Short name T234
Test name
Test status
Simulation time 1879923367 ps
CPU time 19.22 seconds
Started Aug 01 05:57:50 PM PDT 24
Finished Aug 01 05:58:10 PM PDT 24
Peak memory 241916 kb
Host smart-5a875b57-a4f8-410c-8d9d-58cc52943602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067068148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2067068148
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.2044114580
Short name T1052
Test name
Test status
Simulation time 321089480 ps
CPU time 7.12 seconds
Started Aug 01 05:57:49 PM PDT 24
Finished Aug 01 05:57:57 PM PDT 24
Peak memory 241848 kb
Host smart-dd9b34b7-b0e3-4cf2-857c-ea073f2e752d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2044114580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.2044114580
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.3231007171
Short name T1163
Test name
Test status
Simulation time 3651869303 ps
CPU time 9.23 seconds
Started Aug 01 05:57:50 PM PDT 24
Finished Aug 01 05:58:00 PM PDT 24
Peak memory 242320 kb
Host smart-4f0f8266-02a7-4467-b4c3-0f2f6747223c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231007171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.3231007171
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.1638464432
Short name T225
Test name
Test status
Simulation time 10985257648 ps
CPU time 183.77 seconds
Started Aug 01 05:57:58 PM PDT 24
Finished Aug 01 06:01:02 PM PDT 24
Peak memory 278556 kb
Host smart-7269391a-e964-4bb3-863f-71a48d978242
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638464432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.1638464432
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.36642335
Short name T972
Test name
Test status
Simulation time 263819408 ps
CPU time 6.35 seconds
Started Aug 01 05:57:44 PM PDT 24
Finished Aug 01 05:57:51 PM PDT 24
Peak memory 241976 kb
Host smart-0741c048-327d-4c5f-846f-a3360a7466a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36642335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.36642335
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.512371828
Short name T1067
Test name
Test status
Simulation time 56928493731 ps
CPU time 145.27 seconds
Started Aug 01 05:57:52 PM PDT 24
Finished Aug 01 06:00:17 PM PDT 24
Peak memory 248576 kb
Host smart-19ade9f3-875c-4c72-81eb-1614856b0fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512371828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.512371828
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.3235639498
Short name T1122
Test name
Test status
Simulation time 120726488252 ps
CPU time 640.57 seconds
Started Aug 01 05:57:57 PM PDT 24
Finished Aug 01 06:08:37 PM PDT 24
Peak memory 256976 kb
Host smart-69775d3e-90bd-4a70-95b9-70f2649cb9ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235639498 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.3235639498
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.3494740389
Short name T227
Test name
Test status
Simulation time 2999694975 ps
CPU time 17.62 seconds
Started Aug 01 05:57:52 PM PDT 24
Finished Aug 01 05:58:10 PM PDT 24
Peak memory 242500 kb
Host smart-ebbe964d-d0d1-45d7-ae70-b8906e3d366b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494740389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.3494740389
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.1135631224
Short name T172
Test name
Test status
Simulation time 849368185 ps
CPU time 2.27 seconds
Started Aug 01 05:58:58 PM PDT 24
Finished Aug 01 05:59:01 PM PDT 24
Peak memory 240356 kb
Host smart-502da5c1-e111-4833-bc94-6fdc25e29d3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135631224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.1135631224
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.26611486
Short name T126
Test name
Test status
Simulation time 1283069449 ps
CPU time 25.36 seconds
Started Aug 01 05:59:00 PM PDT 24
Finished Aug 01 05:59:26 PM PDT 24
Peak memory 242976 kb
Host smart-2a52acb3-d5c6-4a2e-a0ee-c43e8a6ce825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26611486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.26611486
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.4159676380
Short name T736
Test name
Test status
Simulation time 6300805237 ps
CPU time 44.92 seconds
Started Aug 01 05:59:06 PM PDT 24
Finished Aug 01 05:59:51 PM PDT 24
Peak memory 255604 kb
Host smart-def7fe97-365e-400e-8ff8-7b2c93a88f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159676380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.4159676380
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.3058240574
Short name T652
Test name
Test status
Simulation time 2819238065 ps
CPU time 7.55 seconds
Started Aug 01 05:58:59 PM PDT 24
Finished Aug 01 05:59:07 PM PDT 24
Peak memory 242152 kb
Host smart-940abab8-2185-44e3-b4e1-5578a47ed194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058240574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3058240574
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.2886602280
Short name T120
Test name
Test status
Simulation time 335790355 ps
CPU time 4.3 seconds
Started Aug 01 05:58:59 PM PDT 24
Finished Aug 01 05:59:03 PM PDT 24
Peak memory 241860 kb
Host smart-15cf6074-3978-4f65-a2cd-f617c0dd2894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886602280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2886602280
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.1142879292
Short name T721
Test name
Test status
Simulation time 952205521 ps
CPU time 17.16 seconds
Started Aug 01 05:59:00 PM PDT 24
Finished Aug 01 05:59:17 PM PDT 24
Peak memory 243768 kb
Host smart-bb17a7c5-190b-4c65-84cc-6b5b8e3850ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142879292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.1142879292
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.1563812164
Short name T388
Test name
Test status
Simulation time 1415438525 ps
CPU time 30.57 seconds
Started Aug 01 05:58:58 PM PDT 24
Finished Aug 01 05:59:29 PM PDT 24
Peak memory 242532 kb
Host smart-af658566-c8f2-4c85-a1d3-44143124abb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563812164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.1563812164
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.2781234804
Short name T425
Test name
Test status
Simulation time 2006678102 ps
CPU time 7.27 seconds
Started Aug 01 05:59:00 PM PDT 24
Finished Aug 01 05:59:07 PM PDT 24
Peak memory 242392 kb
Host smart-fdc2c82d-a598-4de0-96c9-4d6f134762ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781234804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.2781234804
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.581182523
Short name T412
Test name
Test status
Simulation time 4320718711 ps
CPU time 13.72 seconds
Started Aug 01 05:58:59 PM PDT 24
Finished Aug 01 05:59:13 PM PDT 24
Peak memory 242380 kb
Host smart-6a27f7d5-cda1-48ae-a3ad-8c503ce26334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581182523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.581182523
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.2505044029
Short name T369
Test name
Test status
Simulation time 292123329 ps
CPU time 4.75 seconds
Started Aug 01 05:59:00 PM PDT 24
Finished Aug 01 05:59:05 PM PDT 24
Peak memory 242136 kb
Host smart-2c0d1b5f-c54d-43eb-a8ae-c126122de5b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505044029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.2505044029
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.778021645
Short name T309
Test name
Test status
Simulation time 710909886 ps
CPU time 6.58 seconds
Started Aug 01 05:58:58 PM PDT 24
Finished Aug 01 05:59:05 PM PDT 24
Peak memory 248380 kb
Host smart-5b80f2cb-b6a4-4831-89b2-1212c368edfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778021645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.778021645
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.2350144340
Short name T831
Test name
Test status
Simulation time 5281406174 ps
CPU time 92.01 seconds
Started Aug 01 05:59:01 PM PDT 24
Finished Aug 01 06:00:33 PM PDT 24
Peak memory 248792 kb
Host smart-f51a5e9c-34a9-4f4b-b1ea-0854cf055ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350144340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.2350144340
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.2726832419
Short name T1001
Test name
Test status
Simulation time 935816554 ps
CPU time 17.81 seconds
Started Aug 01 05:58:59 PM PDT 24
Finished Aug 01 05:59:17 PM PDT 24
Peak memory 242328 kb
Host smart-08fcda27-71a5-42e9-b017-2a72cdaea51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726832419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.2726832419
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.1145147834
Short name T550
Test name
Test status
Simulation time 439326782 ps
CPU time 5.09 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:03:00 PM PDT 24
Peak memory 242356 kb
Host smart-a5856d79-4f39-4183-a4e3-1e046477b0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145147834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.1145147834
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.1751720159
Short name T40
Test name
Test status
Simulation time 176013870 ps
CPU time 4.51 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:03:00 PM PDT 24
Peak memory 242068 kb
Host smart-d8e3bd84-5210-4ef7-8137-2832ba596867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751720159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.1751720159
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.3338304968
Short name T435
Test name
Test status
Simulation time 170695068 ps
CPU time 4.21 seconds
Started Aug 01 06:02:59 PM PDT 24
Finished Aug 01 06:03:04 PM PDT 24
Peak memory 242156 kb
Host smart-c9a83879-3e93-454c-8bc3-3899b8937112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338304968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.3338304968
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.216293077
Short name T587
Test name
Test status
Simulation time 303907747 ps
CPU time 4.69 seconds
Started Aug 01 06:02:58 PM PDT 24
Finished Aug 01 06:03:03 PM PDT 24
Peak memory 241868 kb
Host smart-544c92ae-2a4d-4ff8-967f-5a06d91ca193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216293077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.216293077
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.2222437686
Short name T1123
Test name
Test status
Simulation time 225907827 ps
CPU time 4.78 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:03:00 PM PDT 24
Peak memory 241956 kb
Host smart-e06b94b2-e136-4c2c-949c-7466910d774c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222437686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.2222437686
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.2447725257
Short name T800
Test name
Test status
Simulation time 116897255 ps
CPU time 3.87 seconds
Started Aug 01 06:03:00 PM PDT 24
Finished Aug 01 06:03:04 PM PDT 24
Peak memory 242084 kb
Host smart-736e949f-37cc-4576-8130-d93fc955de38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447725257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.2447725257
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.3963243505
Short name T1144
Test name
Test status
Simulation time 2717255107 ps
CPU time 5.7 seconds
Started Aug 01 06:02:56 PM PDT 24
Finished Aug 01 06:03:01 PM PDT 24
Peak memory 242072 kb
Host smart-34514acd-12a5-43ce-ac01-61c8b42d4ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963243505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.3963243505
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.1509170690
Short name T670
Test name
Test status
Simulation time 1935441981 ps
CPU time 5.47 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:03:00 PM PDT 24
Peak memory 241964 kb
Host smart-51db7a51-096c-416a-bfe5-25af2ffde3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509170690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.1509170690
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.3894348994
Short name T29
Test name
Test status
Simulation time 180509790 ps
CPU time 4.05 seconds
Started Aug 01 06:02:58 PM PDT 24
Finished Aug 01 06:03:02 PM PDT 24
Peak memory 242204 kb
Host smart-dacc486c-16a1-4008-9f5c-d89ab2102922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894348994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3894348994
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.3770715284
Short name T977
Test name
Test status
Simulation time 139072048 ps
CPU time 4.14 seconds
Started Aug 01 06:02:54 PM PDT 24
Finished Aug 01 06:02:58 PM PDT 24
Peak memory 242016 kb
Host smart-98721d64-44ec-4c5a-b171-dd8b98babd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770715284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3770715284
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.1222732332
Short name T422
Test name
Test status
Simulation time 132834154 ps
CPU time 1.82 seconds
Started Aug 01 05:59:05 PM PDT 24
Finished Aug 01 05:59:07 PM PDT 24
Peak memory 240928 kb
Host smart-ce627e74-32a8-4e15-884f-51f27fd419b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222732332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.1222732332
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.625556245
Short name T955
Test name
Test status
Simulation time 815518122 ps
CPU time 11.67 seconds
Started Aug 01 05:59:00 PM PDT 24
Finished Aug 01 05:59:11 PM PDT 24
Peak memory 242000 kb
Host smart-0ab2e28c-7e28-4f5b-9886-f559fd9f2dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625556245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.625556245
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.1772794906
Short name T943
Test name
Test status
Simulation time 421830193 ps
CPU time 19.14 seconds
Started Aug 01 05:59:08 PM PDT 24
Finished Aug 01 05:59:28 PM PDT 24
Peak memory 241808 kb
Host smart-c5f944bf-b6bc-4604-85d7-8c7214cabc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772794906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.1772794906
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.4264575276
Short name T452
Test name
Test status
Simulation time 451537123 ps
CPU time 9.87 seconds
Started Aug 01 05:58:59 PM PDT 24
Finished Aug 01 05:59:09 PM PDT 24
Peak memory 242240 kb
Host smart-8792cb13-a8a7-41ed-98c8-9f28813339c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264575276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.4264575276
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.932087371
Short name T187
Test name
Test status
Simulation time 232253953 ps
CPU time 3.82 seconds
Started Aug 01 05:58:59 PM PDT 24
Finished Aug 01 05:59:03 PM PDT 24
Peak memory 242152 kb
Host smart-ffd26940-3efa-4d95-89ba-8968fc6c2f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932087371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.932087371
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.3388302122
Short name T333
Test name
Test status
Simulation time 1000718057 ps
CPU time 21.03 seconds
Started Aug 01 05:59:02 PM PDT 24
Finished Aug 01 05:59:24 PM PDT 24
Peak memory 245908 kb
Host smart-3885dcc4-68a3-4a4f-a615-ac47f33ab064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388302122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.3388302122
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.1897638046
Short name T458
Test name
Test status
Simulation time 1408921381 ps
CPU time 16.1 seconds
Started Aug 01 05:58:57 PM PDT 24
Finished Aug 01 05:59:13 PM PDT 24
Peak memory 242116 kb
Host smart-174289a8-54e9-4950-bcab-5bbe2e2e6598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897638046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.1897638046
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.3248836842
Short name T765
Test name
Test status
Simulation time 278074357 ps
CPU time 7.4 seconds
Started Aug 01 05:58:59 PM PDT 24
Finished Aug 01 05:59:07 PM PDT 24
Peak memory 241772 kb
Host smart-1e95dd14-d320-456b-a60e-7bfd300cac39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248836842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.3248836842
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.2148153300
Short name T852
Test name
Test status
Simulation time 544533787 ps
CPU time 9.9 seconds
Started Aug 01 05:58:59 PM PDT 24
Finished Aug 01 05:59:09 PM PDT 24
Peak memory 242312 kb
Host smart-fe1d7ba6-daf7-497c-887b-402145eb0fbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2148153300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.2148153300
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.3196383694
Short name T372
Test name
Test status
Simulation time 143705124 ps
CPU time 6.23 seconds
Started Aug 01 05:59:06 PM PDT 24
Finished Aug 01 05:59:12 PM PDT 24
Peak memory 241884 kb
Host smart-a0ea1a92-6888-4a0f-9b0c-03e55e6a1273
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3196383694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.3196383694
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.1870527500
Short name T1021
Test name
Test status
Simulation time 824913536 ps
CPU time 11.88 seconds
Started Aug 01 05:59:08 PM PDT 24
Finished Aug 01 05:59:20 PM PDT 24
Peak memory 241844 kb
Host smart-c4d66917-211d-4b06-90a1-8a35ec9ece88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870527500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1870527500
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.3750871767
Short name T757
Test name
Test status
Simulation time 2524285985518 ps
CPU time 5297.06 seconds
Started Aug 01 05:58:59 PM PDT 24
Finished Aug 01 07:27:16 PM PDT 24
Peak memory 554012 kb
Host smart-aec8f19c-af5b-4c94-8e6f-f09fa751f3a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750871767 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.3750871767
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.3674884719
Short name T1082
Test name
Test status
Simulation time 3326069379 ps
CPU time 30.98 seconds
Started Aug 01 05:58:59 PM PDT 24
Finished Aug 01 05:59:30 PM PDT 24
Peak memory 242780 kb
Host smart-337cf60a-d83e-4532-b3f1-2b8f54915a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674884719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.3674884719
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.239766609
Short name T552
Test name
Test status
Simulation time 263059669 ps
CPU time 4.49 seconds
Started Aug 01 06:02:56 PM PDT 24
Finished Aug 01 06:03:01 PM PDT 24
Peak memory 241960 kb
Host smart-5f1c602a-ea5e-46d7-bfde-9fcd3e708139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239766609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.239766609
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.1668511313
Short name T963
Test name
Test status
Simulation time 257974482 ps
CPU time 4.21 seconds
Started Aug 01 06:02:56 PM PDT 24
Finished Aug 01 06:03:00 PM PDT 24
Peak memory 242336 kb
Host smart-b717480c-d911-46b7-ab58-214cc2e2661e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668511313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.1668511313
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.2418850613
Short name T797
Test name
Test status
Simulation time 485803117 ps
CPU time 3.99 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:02:59 PM PDT 24
Peak memory 241932 kb
Host smart-fab71395-1775-4a74-ad38-2bfddeb4c846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418850613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.2418850613
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.726967200
Short name T1074
Test name
Test status
Simulation time 126416633 ps
CPU time 4.01 seconds
Started Aug 01 06:02:54 PM PDT 24
Finished Aug 01 06:02:58 PM PDT 24
Peak memory 242220 kb
Host smart-c7267eae-1a84-4a6e-bf35-ed8daa8b1461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726967200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.726967200
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.1688811220
Short name T162
Test name
Test status
Simulation time 2155761453 ps
CPU time 4.79 seconds
Started Aug 01 06:03:00 PM PDT 24
Finished Aug 01 06:03:05 PM PDT 24
Peak memory 241984 kb
Host smart-f8aa1553-b2a2-4157-9105-7c043622e711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688811220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.1688811220
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.2206827287
Short name T579
Test name
Test status
Simulation time 145703207 ps
CPU time 3.7 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:02:59 PM PDT 24
Peak memory 241912 kb
Host smart-1be9f5e6-256c-4ccf-8932-bad0090d5e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206827287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.2206827287
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.1055493483
Short name T1056
Test name
Test status
Simulation time 266625509 ps
CPU time 3.91 seconds
Started Aug 01 06:02:57 PM PDT 24
Finished Aug 01 06:03:01 PM PDT 24
Peak memory 242120 kb
Host smart-1ea4bafc-3e0f-4f5b-8801-0cb199fd7f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055493483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.1055493483
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.3947808834
Short name T545
Test name
Test status
Simulation time 440367174 ps
CPU time 4.34 seconds
Started Aug 01 06:02:57 PM PDT 24
Finished Aug 01 06:03:02 PM PDT 24
Peak memory 241964 kb
Host smart-05defc38-fae1-40d6-a3ce-ff92a6798d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947808834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.3947808834
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.2463771841
Short name T424
Test name
Test status
Simulation time 177232618 ps
CPU time 4.2 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:03:00 PM PDT 24
Peak memory 242164 kb
Host smart-ecf62b2d-72c2-44d0-962d-c975adca30df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463771841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.2463771841
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.1478492607
Short name T914
Test name
Test status
Simulation time 672589559 ps
CPU time 4.78 seconds
Started Aug 01 06:02:57 PM PDT 24
Finished Aug 01 06:03:02 PM PDT 24
Peak memory 242000 kb
Host smart-f1ac6aa5-5a03-400a-b8b9-3e706d382f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478492607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.1478492607
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.4117836647
Short name T192
Test name
Test status
Simulation time 808615515 ps
CPU time 2.08 seconds
Started Aug 01 05:59:08 PM PDT 24
Finished Aug 01 05:59:11 PM PDT 24
Peak memory 240356 kb
Host smart-03f3fe4a-5171-463f-8e62-e0b1e610b807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117836647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.4117836647
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.3798275945
Short name T808
Test name
Test status
Simulation time 2045475524 ps
CPU time 20.24 seconds
Started Aug 01 05:59:10 PM PDT 24
Finished Aug 01 05:59:31 PM PDT 24
Peak memory 248492 kb
Host smart-64912fcd-169d-41ca-bf04-e52b99d6f345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798275945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.3798275945
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.4241411331
Short name T1127
Test name
Test status
Simulation time 1018975415 ps
CPU time 14.16 seconds
Started Aug 01 05:59:13 PM PDT 24
Finished Aug 01 05:59:27 PM PDT 24
Peak memory 242032 kb
Host smart-ae3cd917-d237-4878-9da0-7be0b5d247ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241411331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.4241411331
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.1332339524
Short name T98
Test name
Test status
Simulation time 865380517 ps
CPU time 19.43 seconds
Started Aug 01 05:59:12 PM PDT 24
Finished Aug 01 05:59:32 PM PDT 24
Peak memory 242452 kb
Host smart-24bd1e82-8d66-47c8-9a20-4b8e352a2ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332339524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.1332339524
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.2008199585
Short name T215
Test name
Test status
Simulation time 105403928 ps
CPU time 4 seconds
Started Aug 01 05:59:08 PM PDT 24
Finished Aug 01 05:59:12 PM PDT 24
Peak memory 242116 kb
Host smart-79e0de7b-b1f0-4844-a418-c22dfc1902d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008199585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.2008199585
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.3268711954
Short name T128
Test name
Test status
Simulation time 2210989363 ps
CPU time 14.45 seconds
Started Aug 01 05:59:09 PM PDT 24
Finished Aug 01 05:59:24 PM PDT 24
Peak memory 242452 kb
Host smart-5fc90b87-4e3f-40d0-955c-0f6034b5b032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268711954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.3268711954
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.1205935324
Short name T376
Test name
Test status
Simulation time 246523272 ps
CPU time 12.26 seconds
Started Aug 01 05:59:10 PM PDT 24
Finished Aug 01 05:59:22 PM PDT 24
Peak memory 242384 kb
Host smart-af69bc00-550c-4d2a-a9c2-b22693cc17e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205935324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.1205935324
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.2376542628
Short name T235
Test name
Test status
Simulation time 631185523 ps
CPU time 10.12 seconds
Started Aug 01 05:59:13 PM PDT 24
Finished Aug 01 05:59:23 PM PDT 24
Peak memory 242380 kb
Host smart-e3286695-c017-470f-97d4-cd68b57a3e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376542628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.2376542628
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.49008049
Short name T645
Test name
Test status
Simulation time 8624940416 ps
CPU time 20.29 seconds
Started Aug 01 05:59:00 PM PDT 24
Finished Aug 01 05:59:20 PM PDT 24
Peak memory 248688 kb
Host smart-657948c3-8aeb-461f-9267-a1e5b3aa292c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49008049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.49008049
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.3608390761
Short name T1106
Test name
Test status
Simulation time 2512467424 ps
CPU time 10.94 seconds
Started Aug 01 05:59:11 PM PDT 24
Finished Aug 01 05:59:22 PM PDT 24
Peak memory 242260 kb
Host smart-90aeb3a7-90db-478f-a72d-f053c89a3043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608390761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.3608390761
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.54378435
Short name T1145
Test name
Test status
Simulation time 217143820 ps
CPU time 5.12 seconds
Started Aug 01 05:59:08 PM PDT 24
Finished Aug 01 05:59:14 PM PDT 24
Peak memory 242228 kb
Host smart-6e623c38-e8f8-49c1-8cfc-e7ac959ce687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54378435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.54378435
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.985795945
Short name T1039
Test name
Test status
Simulation time 44692080144 ps
CPU time 224.69 seconds
Started Aug 01 05:59:13 PM PDT 24
Finished Aug 01 06:02:57 PM PDT 24
Peak memory 256840 kb
Host smart-057e4234-0d46-48cb-a167-ba3a46887b8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985795945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.
985795945
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.2457167004
Short name T271
Test name
Test status
Simulation time 203516798829 ps
CPU time 708.16 seconds
Started Aug 01 05:59:11 PM PDT 24
Finished Aug 01 06:10:59 PM PDT 24
Peak memory 277932 kb
Host smart-67d77e8c-42d6-41a4-be8c-d6161ecc6979
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457167004 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.2457167004
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.3675860852
Short name T464
Test name
Test status
Simulation time 7421920231 ps
CPU time 13.1 seconds
Started Aug 01 05:59:11 PM PDT 24
Finished Aug 01 05:59:24 PM PDT 24
Peak memory 248600 kb
Host smart-805a9051-be3b-4c49-be2e-63669c8ec259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675860852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.3675860852
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.3491355429
Short name T392
Test name
Test status
Simulation time 187012878 ps
CPU time 4.76 seconds
Started Aug 01 06:02:53 PM PDT 24
Finished Aug 01 06:02:58 PM PDT 24
Peak memory 241900 kb
Host smart-11bdabab-7523-4b09-a0ac-0aff7427b476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491355429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.3491355429
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.1015689305
Short name T1007
Test name
Test status
Simulation time 427317503 ps
CPU time 5.45 seconds
Started Aug 01 06:02:54 PM PDT 24
Finished Aug 01 06:03:00 PM PDT 24
Peak memory 241964 kb
Host smart-334b79c3-b868-4958-b9de-42738056c020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015689305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.1015689305
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.2985302130
Short name T539
Test name
Test status
Simulation time 295667946 ps
CPU time 4.39 seconds
Started Aug 01 06:02:58 PM PDT 24
Finished Aug 01 06:03:02 PM PDT 24
Peak memory 242088 kb
Host smart-c2cb7bb0-d180-4d58-aa29-8366e0c995ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985302130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.2985302130
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.2145967744
Short name T681
Test name
Test status
Simulation time 94753113 ps
CPU time 3.87 seconds
Started Aug 01 06:03:00 PM PDT 24
Finished Aug 01 06:03:04 PM PDT 24
Peak memory 242332 kb
Host smart-46b01ea5-212a-4115-9d55-a76cfe38feb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145967744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.2145967744
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.3916620575
Short name T244
Test name
Test status
Simulation time 267068102 ps
CPU time 4.59 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:03:00 PM PDT 24
Peak memory 241956 kb
Host smart-c3dcdb31-b232-4f39-9142-434a28fb0ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916620575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.3916620575
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.3942766633
Short name T702
Test name
Test status
Simulation time 165259523 ps
CPU time 4.24 seconds
Started Aug 01 06:02:57 PM PDT 24
Finished Aug 01 06:03:01 PM PDT 24
Peak memory 241908 kb
Host smart-30738b03-851b-4ad6-98e7-0bfb5d005cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942766633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.3942766633
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.2934435928
Short name T76
Test name
Test status
Simulation time 414069188 ps
CPU time 3.11 seconds
Started Aug 01 06:03:01 PM PDT 24
Finished Aug 01 06:03:04 PM PDT 24
Peak memory 242204 kb
Host smart-b58a1b66-eaff-4d82-8e44-c02d9d6fdeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934435928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.2934435928
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.202380491
Short name T886
Test name
Test status
Simulation time 108159077 ps
CPU time 2.29 seconds
Started Aug 01 05:59:12 PM PDT 24
Finished Aug 01 05:59:14 PM PDT 24
Peak memory 240648 kb
Host smart-56c98516-4702-40a7-b535-2448104b1124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202380491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.202380491
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.2851005136
Short name T329
Test name
Test status
Simulation time 985653440 ps
CPU time 11.53 seconds
Started Aug 01 05:59:12 PM PDT 24
Finished Aug 01 05:59:24 PM PDT 24
Peak memory 242116 kb
Host smart-cbf7eacf-1443-49c7-8df8-5d859577040a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851005136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.2851005136
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.1019128535
Short name T159
Test name
Test status
Simulation time 1412986223 ps
CPU time 26.03 seconds
Started Aug 01 05:59:12 PM PDT 24
Finished Aug 01 05:59:38 PM PDT 24
Peak memory 242308 kb
Host smart-afd005c5-e159-40a0-91a1-a755afbd16c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019128535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1019128535
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.2235843817
Short name T862
Test name
Test status
Simulation time 337092953 ps
CPU time 4.94 seconds
Started Aug 01 05:59:14 PM PDT 24
Finished Aug 01 05:59:19 PM PDT 24
Peak memory 242000 kb
Host smart-2a0ec5ec-7beb-4836-b14f-d91324c34db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235843817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.2235843817
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.1623519342
Short name T741
Test name
Test status
Simulation time 109530963 ps
CPU time 3.48 seconds
Started Aug 01 05:59:13 PM PDT 24
Finished Aug 01 05:59:16 PM PDT 24
Peak memory 242160 kb
Host smart-5e500446-5115-466d-a1fc-08a8a93ce21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623519342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.1623519342
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.3234608351
Short name T846
Test name
Test status
Simulation time 718136862 ps
CPU time 17.9 seconds
Started Aug 01 05:59:10 PM PDT 24
Finished Aug 01 05:59:28 PM PDT 24
Peak memory 242768 kb
Host smart-f1ba3208-63da-4471-8260-ed8d2568e5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234608351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3234608351
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.610789320
Short name T501
Test name
Test status
Simulation time 1085010614 ps
CPU time 14.63 seconds
Started Aug 01 05:59:10 PM PDT 24
Finished Aug 01 05:59:25 PM PDT 24
Peak memory 242028 kb
Host smart-7b63c13a-cce4-43c0-944b-2f251108e151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610789320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.610789320
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.800472254
Short name T987
Test name
Test status
Simulation time 684014619 ps
CPU time 6.26 seconds
Started Aug 01 05:59:10 PM PDT 24
Finished Aug 01 05:59:16 PM PDT 24
Peak memory 242244 kb
Host smart-73141215-10b9-49c1-95aa-729b06277a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800472254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.800472254
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.163265725
Short name T766
Test name
Test status
Simulation time 1683995715 ps
CPU time 23.93 seconds
Started Aug 01 05:59:10 PM PDT 24
Finished Aug 01 05:59:34 PM PDT 24
Peak memory 248540 kb
Host smart-f630a954-38fb-4656-a0ca-8d20a1fbd3ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163265725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.163265725
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.3327953279
Short name T752
Test name
Test status
Simulation time 210205949 ps
CPU time 5.6 seconds
Started Aug 01 05:59:10 PM PDT 24
Finished Aug 01 05:59:16 PM PDT 24
Peak memory 241792 kb
Host smart-6943039c-4e49-46d2-a4b2-419296b4887a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3327953279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.3327953279
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.1135464647
Short name T390
Test name
Test status
Simulation time 424648214 ps
CPU time 4.7 seconds
Started Aug 01 05:59:12 PM PDT 24
Finished Aug 01 05:59:17 PM PDT 24
Peak memory 248252 kb
Host smart-e4a53458-4718-40ea-95cf-141c61087341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135464647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.1135464647
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.3754428975
Short name T242
Test name
Test status
Simulation time 803678293 ps
CPU time 34.52 seconds
Started Aug 01 05:59:11 PM PDT 24
Finished Aug 01 05:59:45 PM PDT 24
Peak memory 248488 kb
Host smart-9db70588-81a6-4451-9976-ffcd1212e39a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754428975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.3754428975
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.2201087358
Short name T1091
Test name
Test status
Simulation time 10754887763 ps
CPU time 29.58 seconds
Started Aug 01 05:59:11 PM PDT 24
Finished Aug 01 05:59:41 PM PDT 24
Peak memory 242216 kb
Host smart-2180b70d-02ad-409a-9f84-7aaa0125cc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201087358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.2201087358
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.4227410510
Short name T492
Test name
Test status
Simulation time 146876193 ps
CPU time 4.18 seconds
Started Aug 01 06:02:56 PM PDT 24
Finished Aug 01 06:03:00 PM PDT 24
Peak memory 242128 kb
Host smart-7ad86998-90a0-44a6-a2ca-52d83203bbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227410510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.4227410510
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.621728821
Short name T932
Test name
Test status
Simulation time 2543358235 ps
CPU time 4.68 seconds
Started Aug 01 06:03:00 PM PDT 24
Finished Aug 01 06:03:05 PM PDT 24
Peak memory 242300 kb
Host smart-7de6d733-5c1f-4313-b727-2588440b88f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621728821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.621728821
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.2350912114
Short name T801
Test name
Test status
Simulation time 307572918 ps
CPU time 5.31 seconds
Started Aug 01 06:02:57 PM PDT 24
Finished Aug 01 06:03:02 PM PDT 24
Peak memory 242000 kb
Host smart-01ab66bc-f57b-4afd-960c-fbb69fb2b0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350912114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2350912114
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.2327705181
Short name T1173
Test name
Test status
Simulation time 244630755 ps
CPU time 4.98 seconds
Started Aug 01 06:02:58 PM PDT 24
Finished Aug 01 06:03:03 PM PDT 24
Peak memory 242332 kb
Host smart-8601fd26-d1c6-4b8a-8b75-01cc01ab9c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327705181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.2327705181
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.1180811843
Short name T1006
Test name
Test status
Simulation time 509297355 ps
CPU time 4.85 seconds
Started Aug 01 06:02:55 PM PDT 24
Finished Aug 01 06:03:00 PM PDT 24
Peak memory 242108 kb
Host smart-9f4288f0-d929-4200-af01-8fb9e6bb520a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180811843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.1180811843
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.1462961556
Short name T1033
Test name
Test status
Simulation time 274460209 ps
CPU time 3.76 seconds
Started Aug 01 06:03:06 PM PDT 24
Finished Aug 01 06:03:10 PM PDT 24
Peak memory 242160 kb
Host smart-9228420b-9323-4a0d-9068-6c7d04bcd821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462961556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.1462961556
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.842201217
Short name T212
Test name
Test status
Simulation time 191635079 ps
CPU time 3.88 seconds
Started Aug 01 06:03:09 PM PDT 24
Finished Aug 01 06:03:13 PM PDT 24
Peak memory 241788 kb
Host smart-52d2d0a8-a5d8-4be3-bde9-d407aff87732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842201217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.842201217
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.2612778762
Short name T1080
Test name
Test status
Simulation time 192791199 ps
CPU time 4.16 seconds
Started Aug 01 06:03:06 PM PDT 24
Finished Aug 01 06:03:10 PM PDT 24
Peak memory 241908 kb
Host smart-b3cedebe-8fe2-47d5-9cf6-e112324a8627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612778762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.2612778762
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.2763842514
Short name T478
Test name
Test status
Simulation time 149808101 ps
CPU time 4.1 seconds
Started Aug 01 06:03:07 PM PDT 24
Finished Aug 01 06:03:11 PM PDT 24
Peak memory 242100 kb
Host smart-62d505b9-b98e-4d18-a8dc-3afabd6e5a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763842514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.2763842514
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.667871818
Short name T905
Test name
Test status
Simulation time 47231920 ps
CPU time 1.59 seconds
Started Aug 01 05:59:26 PM PDT 24
Finished Aug 01 05:59:28 PM PDT 24
Peak memory 240500 kb
Host smart-d2b13841-9b22-4ae5-be39-d7910d7888c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667871818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.667871818
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.1128708820
Short name T837
Test name
Test status
Simulation time 1454723496 ps
CPU time 21.48 seconds
Started Aug 01 05:59:10 PM PDT 24
Finished Aug 01 05:59:32 PM PDT 24
Peak memory 242552 kb
Host smart-a6166233-29d2-47d8-a844-5bd0e2329f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128708820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1128708820
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.3687222816
Short name T676
Test name
Test status
Simulation time 211324162 ps
CPU time 8.68 seconds
Started Aug 01 05:59:10 PM PDT 24
Finished Aug 01 05:59:19 PM PDT 24
Peak memory 242280 kb
Host smart-0c9a9da4-6c35-46eb-9cae-9100373e8a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687222816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.3687222816
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.3454153391
Short name T910
Test name
Test status
Simulation time 7377177294 ps
CPU time 15.48 seconds
Started Aug 01 05:59:13 PM PDT 24
Finished Aug 01 05:59:28 PM PDT 24
Peak memory 243140 kb
Host smart-b617499a-919a-46ea-9655-f2a683239e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454153391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.3454153391
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.1655890388
Short name T113
Test name
Test status
Simulation time 135255063 ps
CPU time 3.85 seconds
Started Aug 01 05:59:09 PM PDT 24
Finished Aug 01 05:59:13 PM PDT 24
Peak memory 241868 kb
Host smart-55024ceb-7a95-408d-877a-db6e8f837a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655890388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.1655890388
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.3733924201
Short name T649
Test name
Test status
Simulation time 368385217 ps
CPU time 9.25 seconds
Started Aug 01 05:59:12 PM PDT 24
Finished Aug 01 05:59:22 PM PDT 24
Peak memory 242228 kb
Host smart-43a3b785-94e2-4dcb-9c4d-b5de7ec184ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733924201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.3733924201
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.1371780757
Short name T640
Test name
Test status
Simulation time 1683033500 ps
CPU time 21.87 seconds
Started Aug 01 05:59:20 PM PDT 24
Finished Aug 01 05:59:42 PM PDT 24
Peak memory 242116 kb
Host smart-72d4327e-3929-4e4c-9a20-b22c192b4b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371780757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.1371780757
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.1710380268
Short name T473
Test name
Test status
Simulation time 124907366 ps
CPU time 4.1 seconds
Started Aug 01 05:59:10 PM PDT 24
Finished Aug 01 05:59:14 PM PDT 24
Peak memory 241816 kb
Host smart-f1969bdc-3230-4842-9a9a-d65fbfc2bad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710380268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1710380268
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.917658341
Short name T535
Test name
Test status
Simulation time 12773341574 ps
CPU time 41.23 seconds
Started Aug 01 05:59:10 PM PDT 24
Finished Aug 01 05:59:51 PM PDT 24
Peak memory 242264 kb
Host smart-61cc27e1-4c8b-479e-92f6-bc951fc99e15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917658341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.917658341
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.1542460885
Short name T1130
Test name
Test status
Simulation time 607439432 ps
CPU time 7.06 seconds
Started Aug 01 05:59:20 PM PDT 24
Finished Aug 01 05:59:27 PM PDT 24
Peak memory 241940 kb
Host smart-3a593e3e-dbaa-4c84-9b94-f8a977f96ba7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1542460885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.1542460885
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.3794060040
Short name T642
Test name
Test status
Simulation time 1021290434 ps
CPU time 11.19 seconds
Started Aug 01 05:59:11 PM PDT 24
Finished Aug 01 05:59:22 PM PDT 24
Peak memory 242072 kb
Host smart-7b8ee70c-af03-41c9-b68f-28b888db4a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794060040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.3794060040
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.1864449374
Short name T196
Test name
Test status
Simulation time 27201736542 ps
CPU time 173.02 seconds
Started Aug 01 05:59:22 PM PDT 24
Finished Aug 01 06:02:15 PM PDT 24
Peak memory 248724 kb
Host smart-d8f80955-9e19-4cf7-8a5b-31a013825dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864449374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.1864449374
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.3412324454
Short name T1004
Test name
Test status
Simulation time 2744905119 ps
CPU time 29.36 seconds
Started Aug 01 05:59:28 PM PDT 24
Finished Aug 01 05:59:57 PM PDT 24
Peak memory 242100 kb
Host smart-65fe74a3-e439-450d-9bdc-20a7ca83dfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412324454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.3412324454
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.2607124218
Short name T739
Test name
Test status
Simulation time 165199510 ps
CPU time 3.79 seconds
Started Aug 01 06:03:04 PM PDT 24
Finished Aug 01 06:03:08 PM PDT 24
Peak memory 241840 kb
Host smart-a787591f-f77c-4479-a987-1d8f05d10480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607124218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.2607124218
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.92385332
Short name T487
Test name
Test status
Simulation time 443562040 ps
CPU time 4.8 seconds
Started Aug 01 06:03:07 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 242140 kb
Host smart-8eaf1c63-34e8-42cc-ab75-01165af8c724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92385332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.92385332
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.761277711
Short name T1079
Test name
Test status
Simulation time 188948127 ps
CPU time 4.23 seconds
Started Aug 01 06:03:09 PM PDT 24
Finished Aug 01 06:03:13 PM PDT 24
Peak memory 242020 kb
Host smart-be1a8072-4c24-4d5f-a63c-cd1b4805c115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761277711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.761277711
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.1053920766
Short name T30
Test name
Test status
Simulation time 2087247532 ps
CPU time 4.73 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:13 PM PDT 24
Peak memory 242116 kb
Host smart-a94aa126-f96e-44c3-953d-2d1fdfdbefb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053920766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1053920766
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.785635882
Short name T50
Test name
Test status
Simulation time 713008403 ps
CPU time 5.47 seconds
Started Aug 01 06:03:06 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 241896 kb
Host smart-df16aa2c-2040-4a86-bfea-b46be7eb529b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785635882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.785635882
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.2396564057
Short name T638
Test name
Test status
Simulation time 603091479 ps
CPU time 4.21 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 242404 kb
Host smart-dd21a828-f645-465f-ad44-199eec30e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396564057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.2396564057
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.3756327100
Short name T574
Test name
Test status
Simulation time 150072238 ps
CPU time 4.12 seconds
Started Aug 01 06:03:07 PM PDT 24
Finished Aug 01 06:03:11 PM PDT 24
Peak memory 241956 kb
Host smart-5ef421d9-b538-4e18-b86c-c19899887428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756327100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.3756327100
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.3262938833
Short name T604
Test name
Test status
Simulation time 509828904 ps
CPU time 3.72 seconds
Started Aug 01 06:03:10 PM PDT 24
Finished Aug 01 06:03:14 PM PDT 24
Peak memory 241972 kb
Host smart-cfce3c58-61e2-46fe-8127-446158f1ac0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262938833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3262938833
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.1406017283
Short name T659
Test name
Test status
Simulation time 100358506 ps
CPU time 1.74 seconds
Started Aug 01 05:59:25 PM PDT 24
Finished Aug 01 05:59:27 PM PDT 24
Peak memory 240352 kb
Host smart-02448d1a-0aa4-4093-a7b7-335cb2f7f1d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406017283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1406017283
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.411977834
Short name T787
Test name
Test status
Simulation time 2340936740 ps
CPU time 26.74 seconds
Started Aug 01 05:59:22 PM PDT 24
Finished Aug 01 05:59:49 PM PDT 24
Peak memory 242408 kb
Host smart-ea017acc-580c-4991-bd57-abd7912a60a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411977834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.411977834
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.905800014
Short name T782
Test name
Test status
Simulation time 2326135600 ps
CPU time 26.45 seconds
Started Aug 01 05:59:22 PM PDT 24
Finished Aug 01 05:59:49 PM PDT 24
Peak memory 242332 kb
Host smart-f85fc332-da71-4e0c-812a-45d438f60ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905800014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.905800014
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.1191472552
Short name T569
Test name
Test status
Simulation time 8402985046 ps
CPU time 70.26 seconds
Started Aug 01 05:59:19 PM PDT 24
Finished Aug 01 06:00:30 PM PDT 24
Peak memory 242964 kb
Host smart-02ead8db-6319-4520-a45a-fb3a16769d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191472552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.1191472552
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.3734005766
Short name T459
Test name
Test status
Simulation time 556366030 ps
CPU time 3.52 seconds
Started Aug 01 05:59:27 PM PDT 24
Finished Aug 01 05:59:31 PM PDT 24
Peak memory 242192 kb
Host smart-88d59ae4-cc3e-4abd-95a0-87277e6dd5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734005766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.3734005766
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.4154366966
Short name T999
Test name
Test status
Simulation time 652374195 ps
CPU time 20.59 seconds
Started Aug 01 05:59:28 PM PDT 24
Finished Aug 01 05:59:49 PM PDT 24
Peak memory 243460 kb
Host smart-ca64b04d-b522-4017-a54d-643eef51215a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154366966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.4154366966
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.849767951
Short name T386
Test name
Test status
Simulation time 508176356 ps
CPU time 12.14 seconds
Started Aug 01 05:59:24 PM PDT 24
Finished Aug 01 05:59:36 PM PDT 24
Peak memory 241980 kb
Host smart-01c22bf7-8a2d-408b-b90d-14e739aac9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849767951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.849767951
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.2156362190
Short name T1109
Test name
Test status
Simulation time 311848850 ps
CPU time 2.91 seconds
Started Aug 01 05:59:26 PM PDT 24
Finished Aug 01 05:59:29 PM PDT 24
Peak memory 242332 kb
Host smart-e92ad7ba-23b7-4285-95b9-a682d3d402ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156362190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2156362190
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.3727418523
Short name T687
Test name
Test status
Simulation time 1308888106 ps
CPU time 10.67 seconds
Started Aug 01 05:59:18 PM PDT 24
Finished Aug 01 05:59:29 PM PDT 24
Peak memory 248444 kb
Host smart-2285e2a1-f7bf-4a86-901e-ce11aeaedac2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3727418523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.3727418523
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.438095205
Short name T1110
Test name
Test status
Simulation time 2161980026 ps
CPU time 5.22 seconds
Started Aug 01 05:59:19 PM PDT 24
Finished Aug 01 05:59:24 PM PDT 24
Peak memory 242316 kb
Host smart-f7abb144-7806-4711-9bc7-0c741d2b8cff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438095205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.438095205
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.2016380330
Short name T537
Test name
Test status
Simulation time 322624900 ps
CPU time 8.14 seconds
Started Aug 01 05:59:29 PM PDT 24
Finished Aug 01 05:59:37 PM PDT 24
Peak memory 241900 kb
Host smart-34a33e5d-fcfb-4ded-83cf-7c754ce4655a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016380330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.2016380330
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.2975377367
Short name T678
Test name
Test status
Simulation time 589708339598 ps
CPU time 1148.21 seconds
Started Aug 01 05:59:20 PM PDT 24
Finished Aug 01 06:18:28 PM PDT 24
Peak memory 399888 kb
Host smart-ba11bff7-aa57-44fb-9565-578cd2afe91f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975377367 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.2975377367
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.3035655429
Short name T571
Test name
Test status
Simulation time 423058942 ps
CPU time 9.39 seconds
Started Aug 01 05:59:20 PM PDT 24
Finished Aug 01 05:59:30 PM PDT 24
Peak memory 241912 kb
Host smart-18690b74-eee3-421f-8530-9b0e5a4bd56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035655429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.3035655429
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.3008800546
Short name T942
Test name
Test status
Simulation time 274987611 ps
CPU time 3.78 seconds
Started Aug 01 06:03:06 PM PDT 24
Finished Aug 01 06:03:10 PM PDT 24
Peak memory 242312 kb
Host smart-2e68240c-7142-4ffd-b4e2-41d852014dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008800546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.3008800546
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.1766494394
Short name T1188
Test name
Test status
Simulation time 172373006 ps
CPU time 5.15 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:13 PM PDT 24
Peak memory 241956 kb
Host smart-72982263-cc6a-4394-872b-ee4d4d39b086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766494394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1766494394
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.3060542702
Short name T38
Test name
Test status
Simulation time 149540998 ps
CPU time 3.76 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:13 PM PDT 24
Peak memory 241776 kb
Host smart-d753ef5e-fe15-4b66-8723-9bab9a5fb86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060542702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.3060542702
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.782799485
Short name T216
Test name
Test status
Simulation time 120600399 ps
CPU time 4.77 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:13 PM PDT 24
Peak memory 242188 kb
Host smart-b81306de-d620-42ae-8abb-f0880abffcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782799485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.782799485
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.1913197422
Short name T767
Test name
Test status
Simulation time 408232243 ps
CPU time 4.28 seconds
Started Aug 01 06:03:07 PM PDT 24
Finished Aug 01 06:03:11 PM PDT 24
Peak memory 241976 kb
Host smart-2e9ee349-ad83-4a17-bd74-4697602183b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913197422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.1913197422
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.242412810
Short name T163
Test name
Test status
Simulation time 130014144 ps
CPU time 4.1 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 241904 kb
Host smart-2cacb9be-ddf6-4622-a7cf-325f89f4c241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242412810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.242412810
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.2780902530
Short name T7
Test name
Test status
Simulation time 281364006 ps
CPU time 3.56 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 242008 kb
Host smart-97da2a8e-cd21-4a64-a7ab-71b56d53a5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780902530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.2780902530
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.2219511234
Short name T524
Test name
Test status
Simulation time 308514162 ps
CPU time 4.32 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:13 PM PDT 24
Peak memory 241940 kb
Host smart-6aa38b0f-94a3-46fc-be38-b7f2debf4cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219511234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2219511234
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.1881904134
Short name T164
Test name
Test status
Simulation time 271548909 ps
CPU time 4.4 seconds
Started Aug 01 06:03:07 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 241916 kb
Host smart-bf281477-e7f9-476b-a8e1-9a52b53f2a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881904134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.1881904134
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.3038960142
Short name T868
Test name
Test status
Simulation time 383274215 ps
CPU time 4.32 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:13 PM PDT 24
Peak memory 242008 kb
Host smart-1dd2e998-7878-46c3-a03a-5c78fe9b27bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038960142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.3038960142
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.2978002577
Short name T776
Test name
Test status
Simulation time 66833696 ps
CPU time 1.86 seconds
Started Aug 01 05:59:21 PM PDT 24
Finished Aug 01 05:59:23 PM PDT 24
Peak memory 240500 kb
Host smart-821b7039-f4bc-4702-910a-0aae834fbb39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978002577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2978002577
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.2896894156
Short name T746
Test name
Test status
Simulation time 695248580 ps
CPU time 13.88 seconds
Started Aug 01 05:59:19 PM PDT 24
Finished Aug 01 05:59:33 PM PDT 24
Peak memory 242076 kb
Host smart-76af4d42-eee6-4654-ad09-64f3853e1e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896894156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.2896894156
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.1207570730
Short name T882
Test name
Test status
Simulation time 15245948863 ps
CPU time 31.07 seconds
Started Aug 01 05:59:26 PM PDT 24
Finished Aug 01 05:59:57 PM PDT 24
Peak memory 248572 kb
Host smart-221dce84-dcc1-46e2-978c-d9082a76019b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207570730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.1207570730
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.562332540
Short name T654
Test name
Test status
Simulation time 5651258093 ps
CPU time 34.84 seconds
Started Aug 01 05:59:24 PM PDT 24
Finished Aug 01 05:59:59 PM PDT 24
Peak memory 248644 kb
Host smart-5424ee6f-6f96-4433-bbcb-3c4a2c3ae21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562332540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.562332540
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.1276066233
Short name T696
Test name
Test status
Simulation time 306085219 ps
CPU time 4.07 seconds
Started Aug 01 05:59:21 PM PDT 24
Finished Aug 01 05:59:25 PM PDT 24
Peak memory 242120 kb
Host smart-96172523-3ae2-45ab-9da5-4d65d85e60f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276066233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.1276066233
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.2567593880
Short name T165
Test name
Test status
Simulation time 538830775 ps
CPU time 15.34 seconds
Started Aug 01 05:59:27 PM PDT 24
Finished Aug 01 05:59:42 PM PDT 24
Peak memory 242396 kb
Host smart-d2460525-9329-4163-8f3c-0098b8f9e0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567593880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.2567593880
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.1354181571
Short name T664
Test name
Test status
Simulation time 1292088735 ps
CPU time 28.46 seconds
Started Aug 01 05:59:21 PM PDT 24
Finished Aug 01 05:59:49 PM PDT 24
Peak memory 242308 kb
Host smart-3cbcc7a8-f715-4c46-947b-d5ed6a05fb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354181571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.1354181571
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.775076718
Short name T416
Test name
Test status
Simulation time 786743832 ps
CPU time 22.99 seconds
Started Aug 01 05:59:21 PM PDT 24
Finished Aug 01 05:59:44 PM PDT 24
Peak memory 241832 kb
Host smart-c05925b4-c42a-4f93-be93-8137f4fa4bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775076718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.775076718
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.3526513552
Short name T1030
Test name
Test status
Simulation time 1207497857 ps
CPU time 8.45 seconds
Started Aug 01 05:59:21 PM PDT 24
Finished Aug 01 05:59:30 PM PDT 24
Peak memory 242068 kb
Host smart-42c9c512-7661-4488-bec4-fb598ea5bccb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3526513552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3526513552
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.2830090307
Short name T908
Test name
Test status
Simulation time 234807229 ps
CPU time 6.6 seconds
Started Aug 01 05:59:19 PM PDT 24
Finished Aug 01 05:59:25 PM PDT 24
Peak memory 242244 kb
Host smart-3678d2db-0569-4236-95e8-ac8dc714a2ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2830090307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.2830090307
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.2658894453
Short name T444
Test name
Test status
Simulation time 663236834 ps
CPU time 5.09 seconds
Started Aug 01 05:59:29 PM PDT 24
Finished Aug 01 05:59:35 PM PDT 24
Peak memory 241908 kb
Host smart-eb67a830-b33b-4bd0-bdfb-1981d79dd0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658894453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2658894453
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.373575536
Short name T278
Test name
Test status
Simulation time 1695326636266 ps
CPU time 3155.69 seconds
Started Aug 01 05:59:19 PM PDT 24
Finished Aug 01 06:51:55 PM PDT 24
Peak memory 388168 kb
Host smart-84513f5c-d383-435e-b981-24d6311cab2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373575536 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.373575536
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.1394993901
Short name T931
Test name
Test status
Simulation time 9735036965 ps
CPU time 33.08 seconds
Started Aug 01 05:59:26 PM PDT 24
Finished Aug 01 06:00:00 PM PDT 24
Peak memory 242452 kb
Host smart-c5c2ed6b-9fd6-401d-bfec-1684af20e3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394993901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.1394993901
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.2739643602
Short name T1034
Test name
Test status
Simulation time 570924568 ps
CPU time 5.94 seconds
Started Aug 01 06:03:11 PM PDT 24
Finished Aug 01 06:03:17 PM PDT 24
Peak memory 241884 kb
Host smart-b5676522-b3d6-41b9-acb8-3a879094518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739643602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2739643602
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.2181840414
Short name T1077
Test name
Test status
Simulation time 230101379 ps
CPU time 4.29 seconds
Started Aug 01 06:03:06 PM PDT 24
Finished Aug 01 06:03:10 PM PDT 24
Peak memory 242216 kb
Host smart-037a1b36-afe2-4f49-88d8-1efdcdcbddec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181840414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.2181840414
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.1358866232
Short name T740
Test name
Test status
Simulation time 246704283 ps
CPU time 4.04 seconds
Started Aug 01 06:03:07 PM PDT 24
Finished Aug 01 06:03:11 PM PDT 24
Peak memory 242260 kb
Host smart-50b0b985-f3c0-4236-9a0d-dab5abccb6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358866232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.1358866232
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.3705587157
Short name T79
Test name
Test status
Simulation time 1802632136 ps
CPU time 4.73 seconds
Started Aug 01 06:03:09 PM PDT 24
Finished Aug 01 06:03:14 PM PDT 24
Peak memory 242348 kb
Host smart-39d65c96-d679-407d-9ee2-9e540073db19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705587157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3705587157
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.2162444568
Short name T211
Test name
Test status
Simulation time 126293876 ps
CPU time 3.35 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 241976 kb
Host smart-3c3620f2-1be0-427b-9c23-0e1085244d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162444568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2162444568
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.1079421421
Short name T855
Test name
Test status
Simulation time 144922264 ps
CPU time 4.4 seconds
Started Aug 01 06:03:10 PM PDT 24
Finished Aug 01 06:03:15 PM PDT 24
Peak memory 242104 kb
Host smart-9f931d57-695f-4551-8f48-78480fdc49b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079421421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.1079421421
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.4055716058
Short name T856
Test name
Test status
Simulation time 182373328 ps
CPU time 3.9 seconds
Started Aug 01 06:03:13 PM PDT 24
Finished Aug 01 06:03:17 PM PDT 24
Peak memory 242132 kb
Host smart-198ac5c5-4811-498c-baaf-c47abe671b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055716058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.4055716058
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.3348940297
Short name T460
Test name
Test status
Simulation time 1855964529 ps
CPU time 4.7 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:13 PM PDT 24
Peak memory 241896 kb
Host smart-1ac40939-7679-4f0d-aa20-18e970d41836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348940297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.3348940297
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.3685496968
Short name T468
Test name
Test status
Simulation time 404381761 ps
CPU time 4.6 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:13 PM PDT 24
Peak memory 242248 kb
Host smart-0aa0549c-8aef-44ec-8818-6c334016b505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685496968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.3685496968
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.2715474614
Short name T978
Test name
Test status
Simulation time 430993430 ps
CPU time 4.89 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:14 PM PDT 24
Peak memory 242156 kb
Host smart-f69e99d1-9c45-48df-aec2-d8a5ec1aefe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715474614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.2715474614
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.1373458753
Short name T1107
Test name
Test status
Simulation time 82375748 ps
CPU time 1.72 seconds
Started Aug 01 05:59:30 PM PDT 24
Finished Aug 01 05:59:32 PM PDT 24
Peak memory 240568 kb
Host smart-28f4eb9e-01e0-4f1a-a697-80f4b5098668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373458753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1373458753
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.721421656
Short name T775
Test name
Test status
Simulation time 8566035538 ps
CPU time 23.34 seconds
Started Aug 01 05:59:25 PM PDT 24
Finished Aug 01 05:59:48 PM PDT 24
Peak memory 242084 kb
Host smart-b74262d5-bafb-4298-9f75-9e266940a4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721421656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.721421656
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.111766609
Short name T397
Test name
Test status
Simulation time 1316667833 ps
CPU time 25.05 seconds
Started Aug 01 05:59:28 PM PDT 24
Finished Aug 01 05:59:53 PM PDT 24
Peak memory 242252 kb
Host smart-68c9648d-9fb2-41fa-8d03-16a0d74d137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111766609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.111766609
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.3224555251
Short name T1108
Test name
Test status
Simulation time 14944283628 ps
CPU time 31.17 seconds
Started Aug 01 05:59:22 PM PDT 24
Finished Aug 01 05:59:54 PM PDT 24
Peak memory 242748 kb
Host smart-e9eae998-67d6-4b61-947e-ec121a127f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224555251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.3224555251
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.2604388115
Short name T65
Test name
Test status
Simulation time 158943492 ps
CPU time 3.23 seconds
Started Aug 01 05:59:27 PM PDT 24
Finished Aug 01 05:59:31 PM PDT 24
Peak memory 241948 kb
Host smart-59544b79-1c4e-4925-8167-bf001988947e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604388115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.2604388115
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.2981599291
Short name T813
Test name
Test status
Simulation time 5289570923 ps
CPU time 11.7 seconds
Started Aug 01 05:59:29 PM PDT 24
Finished Aug 01 05:59:41 PM PDT 24
Peak memory 248588 kb
Host smart-e6a6b280-379a-4756-be13-dc7b59c5c58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981599291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2981599291
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.1253534992
Short name T881
Test name
Test status
Simulation time 185025336 ps
CPU time 4.07 seconds
Started Aug 01 05:59:22 PM PDT 24
Finished Aug 01 05:59:26 PM PDT 24
Peak memory 241808 kb
Host smart-297cc8b2-6124-47e2-988d-9eb20ea64ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253534992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.1253534992
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.3359558407
Short name T116
Test name
Test status
Simulation time 5082973668 ps
CPU time 8.73 seconds
Started Aug 01 05:59:20 PM PDT 24
Finished Aug 01 05:59:29 PM PDT 24
Peak memory 241896 kb
Host smart-46fc8729-4d13-4822-9c53-a7d29e745273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359558407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3359558407
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.2361479470
Short name T1176
Test name
Test status
Simulation time 2663134554 ps
CPU time 5.3 seconds
Started Aug 01 05:59:19 PM PDT 24
Finished Aug 01 05:59:24 PM PDT 24
Peak memory 241848 kb
Host smart-33416f3f-0c45-4b27-97fe-d9171616ac11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2361479470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2361479470
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.2542298572
Short name T1062
Test name
Test status
Simulation time 225026307 ps
CPU time 3.85 seconds
Started Aug 01 05:59:28 PM PDT 24
Finished Aug 01 05:59:32 PM PDT 24
Peak memory 242164 kb
Host smart-ec616d30-2cc5-478d-bf70-1ef8487aed16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2542298572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.2542298572
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.1041791194
Short name T528
Test name
Test status
Simulation time 990711412 ps
CPU time 9.99 seconds
Started Aug 01 05:59:26 PM PDT 24
Finished Aug 01 05:59:36 PM PDT 24
Peak memory 242228 kb
Host smart-b1559af8-71f7-4bc1-a5c4-c2b08105fc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041791194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.1041791194
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.2216088959
Short name T83
Test name
Test status
Simulation time 17387905238 ps
CPU time 121.29 seconds
Started Aug 01 05:59:22 PM PDT 24
Finished Aug 01 06:01:23 PM PDT 24
Peak memory 256660 kb
Host smart-e252b313-343c-4fe1-9c04-b21ec8060e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216088959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.2216088959
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.859711126
Short name T839
Test name
Test status
Simulation time 555210768236 ps
CPU time 1207.85 seconds
Started Aug 01 05:59:23 PM PDT 24
Finished Aug 01 06:19:31 PM PDT 24
Peak memory 382548 kb
Host smart-6f8bd9e4-b370-4085-961e-c9fd45a64421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859711126 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.859711126
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.1044457453
Short name T1139
Test name
Test status
Simulation time 1531898464 ps
CPU time 11.75 seconds
Started Aug 01 05:59:27 PM PDT 24
Finished Aug 01 05:59:39 PM PDT 24
Peak memory 241984 kb
Host smart-74ca4078-da2f-469a-896e-864d087efcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044457453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.1044457453
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.795824306
Short name T1162
Test name
Test status
Simulation time 1794686245 ps
CPU time 5.07 seconds
Started Aug 01 06:03:07 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 241944 kb
Host smart-37d42aac-3e81-4f1f-88cc-be5394e6fbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795824306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.795824306
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.1760248066
Short name T456
Test name
Test status
Simulation time 124419010 ps
CPU time 3.82 seconds
Started Aug 01 06:03:09 PM PDT 24
Finished Aug 01 06:03:13 PM PDT 24
Peak memory 242016 kb
Host smart-99613fb1-5188-4011-b62c-d1cc84fee002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760248066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.1760248066
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.757817919
Short name T125
Test name
Test status
Simulation time 200014273 ps
CPU time 3.45 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 241976 kb
Host smart-0595f1f8-24cf-4b48-be3f-1068f1498a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757817919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.757817919
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.2854180418
Short name T177
Test name
Test status
Simulation time 264037879 ps
CPU time 4.2 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:13 PM PDT 24
Peak memory 242132 kb
Host smart-090a6aa7-b48c-41f7-8bc8-9257784ee6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854180418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.2854180418
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.3081181372
Short name T951
Test name
Test status
Simulation time 406988415 ps
CPU time 4.69 seconds
Started Aug 01 06:03:09 PM PDT 24
Finished Aug 01 06:03:14 PM PDT 24
Peak memory 242128 kb
Host smart-dffca74c-0985-4a10-a9ae-3318048968ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081181372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.3081181372
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.1432764389
Short name T811
Test name
Test status
Simulation time 182666711 ps
CPU time 3.35 seconds
Started Aug 01 06:03:08 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 241944 kb
Host smart-5f97d039-61c6-427a-a191-f48a259a2617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432764389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.1432764389
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.1969626618
Short name T445
Test name
Test status
Simulation time 308704487 ps
CPU time 4.16 seconds
Started Aug 01 06:03:05 PM PDT 24
Finished Aug 01 06:03:09 PM PDT 24
Peak memory 242108 kb
Host smart-c604c548-bb16-480a-8c9e-46e9f19ad359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969626618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.1969626618
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.4279440958
Short name T88
Test name
Test status
Simulation time 589251336 ps
CPU time 4.56 seconds
Started Aug 01 06:03:07 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 242168 kb
Host smart-cee0a7d3-825b-4279-a055-80d4a0400e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279440958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.4279440958
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.2427228647
Short name T167
Test name
Test status
Simulation time 312672204 ps
CPU time 4.55 seconds
Started Aug 01 06:03:07 PM PDT 24
Finished Aug 01 06:03:12 PM PDT 24
Peak memory 242072 kb
Host smart-0f0ddd7b-62f3-433a-bd16-458d1beba864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427228647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.2427228647
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.2421993276
Short name T1095
Test name
Test status
Simulation time 172198423 ps
CPU time 4.32 seconds
Started Aug 01 06:03:18 PM PDT 24
Finished Aug 01 06:03:23 PM PDT 24
Peak memory 241788 kb
Host smart-ebf49ab1-664d-4724-aed2-2927399de6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421993276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.2421993276
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.3495955181
Short name T405
Test name
Test status
Simulation time 716389081 ps
CPU time 2.25 seconds
Started Aug 01 05:59:36 PM PDT 24
Finished Aug 01 05:59:39 PM PDT 24
Peak memory 240388 kb
Host smart-86266eae-740d-491a-8ec5-e94dc4d1ac2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495955181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.3495955181
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.754747445
Short name T281
Test name
Test status
Simulation time 3028682818 ps
CPU time 44.54 seconds
Started Aug 01 05:59:29 PM PDT 24
Finished Aug 01 06:00:14 PM PDT 24
Peak memory 248592 kb
Host smart-e44759b1-2ce4-479e-9e40-4698aa1d2af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754747445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.754747445
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.1887195322
Short name T503
Test name
Test status
Simulation time 196559783 ps
CPU time 11.44 seconds
Started Aug 01 05:59:36 PM PDT 24
Finished Aug 01 05:59:48 PM PDT 24
Peak memory 241812 kb
Host smart-56f0290c-2a2a-43a8-9efc-ef7e6a1cc3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887195322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.1887195322
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.388101392
Short name T584
Test name
Test status
Simulation time 10902215858 ps
CPU time 39.51 seconds
Started Aug 01 05:59:30 PM PDT 24
Finished Aug 01 06:00:10 PM PDT 24
Peak memory 242196 kb
Host smart-1f056262-afef-4321-9619-28376ae9ed57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388101392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.388101392
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.3565363271
Short name T653
Test name
Test status
Simulation time 287641987 ps
CPU time 4.65 seconds
Started Aug 01 05:59:36 PM PDT 24
Finished Aug 01 05:59:41 PM PDT 24
Peak memory 242204 kb
Host smart-1ffbf324-c7e6-4817-a040-09b52e4d2dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565363271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.3565363271
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.3812191838
Short name T916
Test name
Test status
Simulation time 758135700 ps
CPU time 19.06 seconds
Started Aug 01 05:59:30 PM PDT 24
Finished Aug 01 05:59:50 PM PDT 24
Peak memory 242624 kb
Host smart-4a10659c-9e77-4271-9a3e-470eee3f09f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812191838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.3812191838
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.1323138323
Short name T522
Test name
Test status
Simulation time 1907399184 ps
CPU time 22.53 seconds
Started Aug 01 05:59:30 PM PDT 24
Finished Aug 01 05:59:53 PM PDT 24
Peak memory 242396 kb
Host smart-8cc16c72-3a29-46fe-9881-2d563760e4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323138323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.1323138323
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.2501745098
Short name T153
Test name
Test status
Simulation time 1667551068 ps
CPU time 4.95 seconds
Started Aug 01 05:59:36 PM PDT 24
Finished Aug 01 05:59:41 PM PDT 24
Peak memory 241788 kb
Host smart-df1f6cd8-9252-4aa3-a342-70de651ff7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501745098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.2501745098
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.1334246860
Short name T1076
Test name
Test status
Simulation time 456117648 ps
CPU time 8.41 seconds
Started Aug 01 05:59:28 PM PDT 24
Finished Aug 01 05:59:37 PM PDT 24
Peak memory 242320 kb
Host smart-fcb4c834-abf0-43fa-a588-b3807a4b8a9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334246860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.1334246860
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.1481533565
Short name T876
Test name
Test status
Simulation time 1068183161 ps
CPU time 9.86 seconds
Started Aug 01 05:59:30 PM PDT 24
Finished Aug 01 05:59:40 PM PDT 24
Peak memory 241880 kb
Host smart-32406a72-68a6-4002-9406-e1a8bae3d8b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1481533565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.1481533565
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.1304206013
Short name T404
Test name
Test status
Simulation time 265471999 ps
CPU time 5.25 seconds
Started Aug 01 05:59:31 PM PDT 24
Finished Aug 01 05:59:38 PM PDT 24
Peak memory 241816 kb
Host smart-553eebf9-79eb-4640-b8e9-c9ad8caa3878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304206013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1304206013
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.3917206058
Short name T93
Test name
Test status
Simulation time 42868721287 ps
CPU time 206.45 seconds
Started Aug 01 05:59:32 PM PDT 24
Finished Aug 01 06:02:59 PM PDT 24
Peak memory 263744 kb
Host smart-ccbfdafb-7c71-48cb-b9ec-5914fb88dc15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917206058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.3917206058
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.2328222434
Short name T1051
Test name
Test status
Simulation time 397129769581 ps
CPU time 2429.49 seconds
Started Aug 01 05:59:33 PM PDT 24
Finished Aug 01 06:40:02 PM PDT 24
Peak memory 310636 kb
Host smart-6c5cd122-0dc1-4d29-9e6b-d556644972c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328222434 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.2328222434
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.3722554759
Short name T867
Test name
Test status
Simulation time 358610566 ps
CPU time 6.42 seconds
Started Aug 01 05:59:36 PM PDT 24
Finished Aug 01 05:59:43 PM PDT 24
Peak memory 248612 kb
Host smart-77091e61-e5e4-4a10-bf65-3df789b5b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722554759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.3722554759
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.2767607663
Short name T658
Test name
Test status
Simulation time 114979497 ps
CPU time 4.74 seconds
Started Aug 01 06:03:20 PM PDT 24
Finished Aug 01 06:03:25 PM PDT 24
Peak memory 242320 kb
Host smart-0e29ef38-03c3-432c-80e2-86ad9cc0196e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767607663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.2767607663
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.59807209
Short name T109
Test name
Test status
Simulation time 158470885 ps
CPU time 3.88 seconds
Started Aug 01 06:03:19 PM PDT 24
Finished Aug 01 06:03:23 PM PDT 24
Peak memory 242120 kb
Host smart-acc22b43-cc72-4d06-ba30-fd2b9b67c876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59807209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.59807209
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.2179868249
Short name T221
Test name
Test status
Simulation time 177032755 ps
CPU time 4.9 seconds
Started Aug 01 06:03:18 PM PDT 24
Finished Aug 01 06:03:23 PM PDT 24
Peak memory 241984 kb
Host smart-864c026b-75ca-4d6e-ab0c-d2b208b72726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179868249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2179868249
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.2294948125
Short name T176
Test name
Test status
Simulation time 1465643902 ps
CPU time 4.17 seconds
Started Aug 01 06:03:18 PM PDT 24
Finished Aug 01 06:03:22 PM PDT 24
Peak memory 241940 kb
Host smart-f89b3395-4dcd-4c2d-8d4f-5788300386ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294948125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.2294948125
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.3714740858
Short name T927
Test name
Test status
Simulation time 171335528 ps
CPU time 4.13 seconds
Started Aug 01 06:03:17 PM PDT 24
Finished Aug 01 06:03:21 PM PDT 24
Peak memory 242364 kb
Host smart-5ce4cbcc-3e09-491e-b8e2-6dfcab725f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714740858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.3714740858
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.3419419651
Short name T618
Test name
Test status
Simulation time 2408802415 ps
CPU time 5.72 seconds
Started Aug 01 06:03:19 PM PDT 24
Finished Aug 01 06:03:25 PM PDT 24
Peak memory 241928 kb
Host smart-6057c305-ec07-4048-ac35-34366d2a4ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419419651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.3419419651
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.227953521
Short name T39
Test name
Test status
Simulation time 2137334827 ps
CPU time 5.95 seconds
Started Aug 01 06:03:22 PM PDT 24
Finished Aug 01 06:03:28 PM PDT 24
Peak memory 242332 kb
Host smart-de732ef6-a064-4229-aa2f-15b7509ce847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227953521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.227953521
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.3950857241
Short name T715
Test name
Test status
Simulation time 311151122 ps
CPU time 4.44 seconds
Started Aug 01 06:03:20 PM PDT 24
Finished Aug 01 06:03:25 PM PDT 24
Peak memory 242136 kb
Host smart-57e5e938-857f-4aab-8c84-0d96c2672050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950857241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.3950857241
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.931099786
Short name T601
Test name
Test status
Simulation time 605179237 ps
CPU time 4.6 seconds
Started Aug 01 06:03:21 PM PDT 24
Finished Aug 01 06:03:26 PM PDT 24
Peak memory 242132 kb
Host smart-3a36156f-2627-4e60-be78-a622259c1e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931099786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.931099786
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.3495997029
Short name T995
Test name
Test status
Simulation time 106046785 ps
CPU time 1.89 seconds
Started Aug 01 05:59:32 PM PDT 24
Finished Aug 01 05:59:34 PM PDT 24
Peak memory 240460 kb
Host smart-805c565f-a831-4fa1-8538-a244986a68ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495997029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3495997029
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.1520600740
Short name T612
Test name
Test status
Simulation time 1306295526 ps
CPU time 25.75 seconds
Started Aug 01 05:59:26 PM PDT 24
Finished Aug 01 05:59:52 PM PDT 24
Peak memory 242432 kb
Host smart-c06e99d1-76b5-4a5f-aa19-bab890aad805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520600740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.1520600740
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.439263822
Short name T499
Test name
Test status
Simulation time 739513754 ps
CPU time 11.77 seconds
Started Aug 01 05:59:31 PM PDT 24
Finished Aug 01 05:59:43 PM PDT 24
Peak memory 241984 kb
Host smart-9f21d961-236e-4bb3-b866-748341437c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439263822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.439263822
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.278977525
Short name T457
Test name
Test status
Simulation time 1487382137 ps
CPU time 17.5 seconds
Started Aug 01 05:59:28 PM PDT 24
Finished Aug 01 05:59:46 PM PDT 24
Peak memory 242268 kb
Host smart-9274561e-798f-4be7-b06b-b2df3783dbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278977525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.278977525
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.518800688
Short name T557
Test name
Test status
Simulation time 100284967 ps
CPU time 3.65 seconds
Started Aug 01 05:59:28 PM PDT 24
Finished Aug 01 05:59:32 PM PDT 24
Peak memory 242100 kb
Host smart-b02b1b09-c66d-4bbe-8345-2342c67dec10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518800688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.518800688
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.2309379885
Short name T527
Test name
Test status
Simulation time 3321722554 ps
CPU time 43.61 seconds
Started Aug 01 05:59:37 PM PDT 24
Finished Aug 01 06:00:21 PM PDT 24
Peak memory 265032 kb
Host smart-9e341da1-00cc-48d1-b601-f95b5d35118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309379885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.2309379885
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.2398226983
Short name T480
Test name
Test status
Simulation time 3186394936 ps
CPU time 36.2 seconds
Started Aug 01 05:59:33 PM PDT 24
Finished Aug 01 06:00:09 PM PDT 24
Peak memory 242564 kb
Host smart-806230f9-4a35-48d4-b6f6-2788d5a25477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398226983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.2398226983
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.226350258
Short name T255
Test name
Test status
Simulation time 222793028 ps
CPU time 8.93 seconds
Started Aug 01 05:59:34 PM PDT 24
Finished Aug 01 05:59:43 PM PDT 24
Peak memory 242472 kb
Host smart-dfa80fd6-01d8-423d-a70e-56a5804093df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226350258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.226350258
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.3681427257
Short name T806
Test name
Test status
Simulation time 1481363455 ps
CPU time 24.52 seconds
Started Aug 01 05:59:30 PM PDT 24
Finished Aug 01 05:59:54 PM PDT 24
Peak memory 242132 kb
Host smart-05935b7e-7e3c-44d9-8d59-81189d643f6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3681427257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.3681427257
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.1978169827
Short name T1184
Test name
Test status
Simulation time 1016401047 ps
CPU time 12.25 seconds
Started Aug 01 05:59:29 PM PDT 24
Finished Aug 01 05:59:42 PM PDT 24
Peak memory 241952 kb
Host smart-8d1fd467-2aad-4d9e-81ef-09cba563c5ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1978169827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.1978169827
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.2382053496
Short name T1138
Test name
Test status
Simulation time 185439814 ps
CPU time 4.54 seconds
Started Aug 01 05:59:29 PM PDT 24
Finished Aug 01 05:59:34 PM PDT 24
Peak memory 248284 kb
Host smart-940853de-7f43-44ea-b407-becd5164a1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382053496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.2382053496
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.1049217120
Short name T335
Test name
Test status
Simulation time 3165559159 ps
CPU time 8.75 seconds
Started Aug 01 05:59:30 PM PDT 24
Finished Aug 01 05:59:39 PM PDT 24
Peak memory 241912 kb
Host smart-61e4a643-cbd6-451b-9ddf-6219963cc3c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049217120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.1049217120
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.1411004229
Short name T132
Test name
Test status
Simulation time 203448455796 ps
CPU time 2007.63 seconds
Started Aug 01 05:59:36 PM PDT 24
Finished Aug 01 06:33:04 PM PDT 24
Peak memory 270612 kb
Host smart-587b9d5d-5d2b-4892-8489-740bf60e9e92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411004229 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.1411004229
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.3657831889
Short name T288
Test name
Test status
Simulation time 1846948122 ps
CPU time 22.24 seconds
Started Aug 01 05:59:30 PM PDT 24
Finished Aug 01 05:59:53 PM PDT 24
Peak memory 242292 kb
Host smart-169a5a85-c82f-4be8-b002-4c9ce37a375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657831889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.3657831889
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.1719112349
Short name T547
Test name
Test status
Simulation time 165865179 ps
CPU time 4.14 seconds
Started Aug 01 06:03:18 PM PDT 24
Finished Aug 01 06:03:23 PM PDT 24
Peak memory 242200 kb
Host smart-264b87bb-6927-4de4-8be6-796136c76cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719112349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.1719112349
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.2874306433
Short name T512
Test name
Test status
Simulation time 2284967551 ps
CPU time 6.03 seconds
Started Aug 01 06:03:17 PM PDT 24
Finished Aug 01 06:03:23 PM PDT 24
Peak memory 242188 kb
Host smart-4a961a5d-1661-474c-b3ee-42ba0d69407d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874306433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.2874306433
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.1302268206
Short name T504
Test name
Test status
Simulation time 116612429 ps
CPU time 3.13 seconds
Started Aug 01 06:03:19 PM PDT 24
Finished Aug 01 06:03:22 PM PDT 24
Peak memory 242196 kb
Host smart-1840fb32-201a-428c-8bc6-b4d61cc28363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302268206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.1302268206
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.2777902427
Short name T53
Test name
Test status
Simulation time 133544710 ps
CPU time 4.05 seconds
Started Aug 01 06:03:19 PM PDT 24
Finished Aug 01 06:03:23 PM PDT 24
Peak memory 242172 kb
Host smart-9c8a9499-047b-4699-8e73-a2637e8a2127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777902427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.2777902427
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.1026140555
Short name T106
Test name
Test status
Simulation time 431178335 ps
CPU time 4.58 seconds
Started Aug 01 06:03:18 PM PDT 24
Finished Aug 01 06:03:23 PM PDT 24
Peak memory 242096 kb
Host smart-4cfc4a30-9233-4663-a455-76cca36449b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026140555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.1026140555
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.4043873828
Short name T168
Test name
Test status
Simulation time 214719224 ps
CPU time 3.15 seconds
Started Aug 01 06:03:16 PM PDT 24
Finished Aug 01 06:03:19 PM PDT 24
Peak memory 242260 kb
Host smart-598a7ddd-1e29-4905-b0df-8fdd8390c75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043873828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.4043873828
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.3677513234
Short name T937
Test name
Test status
Simulation time 138177686 ps
CPU time 4.03 seconds
Started Aug 01 06:03:25 PM PDT 24
Finished Aug 01 06:03:29 PM PDT 24
Peak memory 242048 kb
Host smart-01f4ce2b-1ebf-4202-aa6c-c6644a5d7574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677513234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.3677513234
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.3604917547
Short name T44
Test name
Test status
Simulation time 288357466 ps
CPU time 3.77 seconds
Started Aug 01 06:03:19 PM PDT 24
Finished Aug 01 06:03:23 PM PDT 24
Peak memory 241984 kb
Host smart-41af8b6f-6f95-414a-a3f6-3da276737743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604917547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.3604917547
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.3203070770
Short name T47
Test name
Test status
Simulation time 216789959 ps
CPU time 3.73 seconds
Started Aug 01 06:03:20 PM PDT 24
Finished Aug 01 06:03:24 PM PDT 24
Peak memory 241936 kb
Host smart-f23d2d5e-20bb-4e3d-a739-133ec9ea071a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203070770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.3203070770
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.2017858571
Short name T477
Test name
Test status
Simulation time 211892300 ps
CPU time 4.86 seconds
Started Aug 01 06:03:19 PM PDT 24
Finished Aug 01 06:03:24 PM PDT 24
Peak memory 242176 kb
Host smart-3a18da0f-5f14-472f-aefd-0742835a7f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017858571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.2017858571
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.161378774
Short name T661
Test name
Test status
Simulation time 157178182 ps
CPU time 2.71 seconds
Started Aug 01 05:57:51 PM PDT 24
Finished Aug 01 05:57:54 PM PDT 24
Peak memory 240380 kb
Host smart-93d16b52-c822-4477-8052-8f006a2941a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161378774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.161378774
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.641321585
Short name T980
Test name
Test status
Simulation time 3762204447 ps
CPU time 19.23 seconds
Started Aug 01 05:58:00 PM PDT 24
Finished Aug 01 05:58:19 PM PDT 24
Peak memory 248672 kb
Host smart-7cf2dbf9-e13d-4521-8f2b-f6de84ee8864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641321585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.641321585
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.3183205731
Short name T58
Test name
Test status
Simulation time 1307918667 ps
CPU time 26.2 seconds
Started Aug 01 05:57:58 PM PDT 24
Finished Aug 01 05:58:25 PM PDT 24
Peak memory 242788 kb
Host smart-0492eeaf-5b87-4c21-9a54-f63501c1a033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183205731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.3183205731
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.3870009348
Short name T807
Test name
Test status
Simulation time 2132792181 ps
CPU time 14.94 seconds
Started Aug 01 05:57:52 PM PDT 24
Finished Aug 01 05:58:07 PM PDT 24
Peak memory 241980 kb
Host smart-7b449ef8-69cd-4cba-8bba-01be15044390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870009348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.3870009348
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.1626458901
Short name T703
Test name
Test status
Simulation time 1187599605 ps
CPU time 10.75 seconds
Started Aug 01 05:58:00 PM PDT 24
Finished Aug 01 05:58:11 PM PDT 24
Peak memory 242292 kb
Host smart-df196e02-62e1-4bef-bd0e-99b52413e004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626458901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.1626458901
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.3817956212
Short name T1178
Test name
Test status
Simulation time 611689333 ps
CPU time 5.66 seconds
Started Aug 01 05:57:52 PM PDT 24
Finished Aug 01 05:57:58 PM PDT 24
Peak memory 241796 kb
Host smart-138849bb-b90b-4bbd-b591-865fbb0ec219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817956212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.3817956212
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.3066839653
Short name T548
Test name
Test status
Simulation time 667663202 ps
CPU time 19.6 seconds
Started Aug 01 05:57:59 PM PDT 24
Finished Aug 01 05:58:19 PM PDT 24
Peak memory 242496 kb
Host smart-addc1fdc-e202-42ed-8a37-4d6ba0cc0fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066839653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.3066839653
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.293072601
Short name T714
Test name
Test status
Simulation time 327453078 ps
CPU time 20.25 seconds
Started Aug 01 05:57:54 PM PDT 24
Finished Aug 01 05:58:15 PM PDT 24
Peak memory 241836 kb
Host smart-b4995987-01b4-49ec-8673-96a9558cad62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293072601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.293072601
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.3806134237
Short name T851
Test name
Test status
Simulation time 511154104 ps
CPU time 16.24 seconds
Started Aug 01 05:57:52 PM PDT 24
Finished Aug 01 05:58:09 PM PDT 24
Peak memory 241828 kb
Host smart-2faf68e0-1aed-4b3b-8a75-296cef4030e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3806134237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.3806134237
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.3614504436
Short name T367
Test name
Test status
Simulation time 199419109 ps
CPU time 7.9 seconds
Started Aug 01 05:57:58 PM PDT 24
Finished Aug 01 05:58:06 PM PDT 24
Peak memory 242200 kb
Host smart-4e22d931-a4e2-4944-90c2-0acd565791b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3614504436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3614504436
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.1171396724
Short name T224
Test name
Test status
Simulation time 11410320421 ps
CPU time 192.42 seconds
Started Aug 01 05:57:59 PM PDT 24
Finished Aug 01 06:01:11 PM PDT 24
Peak memory 268916 kb
Host smart-cfb36733-b0a4-4863-8d34-17205ad8fc1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171396724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1171396724
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.1315761122
Short name T849
Test name
Test status
Simulation time 450353775 ps
CPU time 10.76 seconds
Started Aug 01 05:57:51 PM PDT 24
Finished Aug 01 05:58:02 PM PDT 24
Peak memory 242256 kb
Host smart-cbb1f168-166b-49ea-a4c3-8abd0371c3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315761122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.1315761122
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.452989842
Short name T293
Test name
Test status
Simulation time 12191251403 ps
CPU time 133.62 seconds
Started Aug 01 05:57:52 PM PDT 24
Finished Aug 01 06:00:06 PM PDT 24
Peak memory 255240 kb
Host smart-a1baf49a-e981-4200-b077-73d46e4e05ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452989842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.452989842
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.4109350129
Short name T1070
Test name
Test status
Simulation time 60699308144 ps
CPU time 1045.72 seconds
Started Aug 01 05:57:53 PM PDT 24
Finished Aug 01 06:15:18 PM PDT 24
Peak memory 249624 kb
Host smart-b8aacb88-e118-4485-a822-500639fbb98f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109350129 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.4109350129
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.3013224179
Short name T421
Test name
Test status
Simulation time 10720458710 ps
CPU time 16.82 seconds
Started Aug 01 05:57:57 PM PDT 24
Finished Aug 01 05:58:14 PM PDT 24
Peak memory 242116 kb
Host smart-0cce97ac-7140-431e-920a-2965a51f790f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013224179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.3013224179
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.3054648788
Short name T930
Test name
Test status
Simulation time 252057314 ps
CPU time 2.32 seconds
Started Aug 01 05:59:38 PM PDT 24
Finished Aug 01 05:59:40 PM PDT 24
Peak memory 240496 kb
Host smart-e7152bfd-a77b-44cd-9ce8-6fea894fe817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054648788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.3054648788
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.953175100
Short name T25
Test name
Test status
Simulation time 3687768959 ps
CPU time 11.4 seconds
Started Aug 01 05:59:39 PM PDT 24
Finished Aug 01 05:59:50 PM PDT 24
Peak memory 242852 kb
Host smart-67c8c594-1839-4a6f-8f8d-9126d7da03e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953175100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.953175100
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.420562432
Short name T1185
Test name
Test status
Simulation time 4349445693 ps
CPU time 39.16 seconds
Started Aug 01 05:59:36 PM PDT 24
Finished Aug 01 06:00:16 PM PDT 24
Peak memory 242688 kb
Host smart-5762ecb9-8ccc-4fb9-9021-2545616a5dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420562432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.420562432
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.2204113256
Short name T1155
Test name
Test status
Simulation time 918103925 ps
CPU time 11.49 seconds
Started Aug 01 05:59:32 PM PDT 24
Finished Aug 01 05:59:44 PM PDT 24
Peak memory 242060 kb
Host smart-ab0eddec-0f51-4b19-ac1d-6e17d605df7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204113256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2204113256
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.905134248
Short name T967
Test name
Test status
Simulation time 263040916 ps
CPU time 5.1 seconds
Started Aug 01 05:59:29 PM PDT 24
Finished Aug 01 05:59:34 PM PDT 24
Peak memory 241864 kb
Host smart-d62723ff-21c6-4e52-a22d-efa31bdc51bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905134248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.905134248
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.2619145847
Short name T429
Test name
Test status
Simulation time 4093010201 ps
CPU time 24.1 seconds
Started Aug 01 05:59:39 PM PDT 24
Finished Aug 01 06:00:03 PM PDT 24
Peak memory 248564 kb
Host smart-e579627d-bb32-4549-86ed-9eae6b4d29b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619145847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.2619145847
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.1969356233
Short name T636
Test name
Test status
Simulation time 3605396794 ps
CPU time 41.15 seconds
Started Aug 01 05:59:37 PM PDT 24
Finished Aug 01 06:00:18 PM PDT 24
Peak memory 242364 kb
Host smart-605029a3-0d88-4f0f-aa5e-7d37b105326c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969356233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.1969356233
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.3884764730
Short name T646
Test name
Test status
Simulation time 1784111123 ps
CPU time 13.76 seconds
Started Aug 01 05:59:31 PM PDT 24
Finished Aug 01 05:59:45 PM PDT 24
Peak memory 241940 kb
Host smart-bf751ad1-516d-4968-a875-74aa814155ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884764730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.3884764730
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.3032389757
Short name T414
Test name
Test status
Simulation time 548714569 ps
CPU time 16.83 seconds
Started Aug 01 05:59:28 PM PDT 24
Finished Aug 01 05:59:45 PM PDT 24
Peak memory 248632 kb
Host smart-4fbedc8e-e600-4e2e-8ded-a1bedcf289d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3032389757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3032389757
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.1649235974
Short name T1000
Test name
Test status
Simulation time 2307247554 ps
CPU time 9.58 seconds
Started Aug 01 05:59:37 PM PDT 24
Finished Aug 01 05:59:47 PM PDT 24
Peak memory 242296 kb
Host smart-e3ea3c7f-ec88-4ec7-94a6-295e43352da6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649235974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.1649235974
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.4247261170
Short name T637
Test name
Test status
Simulation time 340090777 ps
CPU time 6.24 seconds
Started Aug 01 05:59:27 PM PDT 24
Finished Aug 01 05:59:34 PM PDT 24
Peak memory 241908 kb
Host smart-8bc24992-7e6f-48db-b369-318f3d524da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247261170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.4247261170
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.3844234310
Short name T1019
Test name
Test status
Simulation time 1849379160 ps
CPU time 14.26 seconds
Started Aug 01 05:59:40 PM PDT 24
Finished Aug 01 05:59:55 PM PDT 24
Peak memory 241916 kb
Host smart-e682737b-9aae-43ed-ac47-65f516fadde4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844234310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.3844234310
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.4182524723
Short name T921
Test name
Test status
Simulation time 122401053585 ps
CPU time 1208.89 seconds
Started Aug 01 05:59:40 PM PDT 24
Finished Aug 01 06:19:49 PM PDT 24
Peak memory 268316 kb
Host smart-e224dbde-f601-48c1-afd5-c3c354dd16b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182524723 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.4182524723
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.3866313562
Short name T286
Test name
Test status
Simulation time 1047213149 ps
CPU time 28.16 seconds
Started Aug 01 05:59:40 PM PDT 24
Finished Aug 01 06:00:08 PM PDT 24
Peak memory 242296 kb
Host smart-300b50b3-3955-4a75-b65d-d2786b9db967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866313562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.3866313562
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.3829571953
Short name T793
Test name
Test status
Simulation time 89723725 ps
CPU time 1.69 seconds
Started Aug 01 05:59:39 PM PDT 24
Finished Aug 01 05:59:41 PM PDT 24
Peak memory 240316 kb
Host smart-7c61663b-d901-49db-acb5-f896ff7b1683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829571953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.3829571953
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.843743176
Short name T37
Test name
Test status
Simulation time 3793783188 ps
CPU time 9.13 seconds
Started Aug 01 05:59:40 PM PDT 24
Finished Aug 01 05:59:49 PM PDT 24
Peak memory 242812 kb
Host smart-9e9b2247-faa9-4587-9a09-5777c2998130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843743176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.843743176
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.3401707707
Short name T789
Test name
Test status
Simulation time 13690347034 ps
CPU time 34.96 seconds
Started Aug 01 05:59:43 PM PDT 24
Finished Aug 01 06:00:18 PM PDT 24
Peak memory 242760 kb
Host smart-fc1fb226-eee2-492f-bee7-e8186423fce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401707707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.3401707707
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.2978362199
Short name T432
Test name
Test status
Simulation time 145357767 ps
CPU time 4.71 seconds
Started Aug 01 05:59:39 PM PDT 24
Finished Aug 01 05:59:44 PM PDT 24
Peak memory 241944 kb
Host smart-a5fa5d80-b15b-46c8-95e4-86d49e729886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978362199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.2978362199
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.124527500
Short name T582
Test name
Test status
Simulation time 2133539901 ps
CPU time 4.78 seconds
Started Aug 01 05:59:41 PM PDT 24
Finished Aug 01 05:59:46 PM PDT 24
Peak memory 242004 kb
Host smart-75352bd7-d8e4-486f-b1cc-64be0f2d84b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124527500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.124527500
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.3592019288
Short name T708
Test name
Test status
Simulation time 1796233450 ps
CPU time 31.14 seconds
Started Aug 01 05:59:38 PM PDT 24
Finished Aug 01 06:00:10 PM PDT 24
Peak memory 244896 kb
Host smart-a6b6fd15-e060-4ef0-b1f2-0de4b6c7c75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592019288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.3592019288
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.3787392882
Short name T529
Test name
Test status
Simulation time 3979325247 ps
CPU time 15.23 seconds
Started Aug 01 05:59:38 PM PDT 24
Finished Aug 01 05:59:54 PM PDT 24
Peak memory 242720 kb
Host smart-ef911140-cee6-4467-9e0e-cbf6dff1e573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787392882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.3787392882
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.4069121181
Short name T941
Test name
Test status
Simulation time 482422359 ps
CPU time 6.62 seconds
Started Aug 01 05:59:37 PM PDT 24
Finished Aug 01 05:59:44 PM PDT 24
Peak memory 241892 kb
Host smart-3b7e43db-2f4b-4d2b-846b-1fbfc4eaa00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069121181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.4069121181
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.1260498677
Short name T848
Test name
Test status
Simulation time 719834170 ps
CPU time 8.08 seconds
Started Aug 01 05:59:39 PM PDT 24
Finished Aug 01 05:59:47 PM PDT 24
Peak memory 248628 kb
Host smart-ec29fb3d-a152-4eec-851e-ab9ce8363934
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260498677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.1260498677
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.800757309
Short name T417
Test name
Test status
Simulation time 2226845703 ps
CPU time 5.92 seconds
Started Aug 01 05:59:38 PM PDT 24
Finished Aug 01 05:59:44 PM PDT 24
Peak memory 242392 kb
Host smart-252c1091-1b27-4ff1-975e-d8d81b8ee705
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=800757309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.800757309
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.3203872834
Short name T486
Test name
Test status
Simulation time 800494037 ps
CPU time 10.59 seconds
Started Aug 01 05:59:41 PM PDT 24
Finished Aug 01 05:59:51 PM PDT 24
Peak memory 241836 kb
Host smart-73625ad8-99ec-4ffa-a989-df9544d97ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203872834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3203872834
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.1935691766
Short name T847
Test name
Test status
Simulation time 31355274191 ps
CPU time 441.64 seconds
Started Aug 01 05:59:40 PM PDT 24
Finished Aug 01 06:07:01 PM PDT 24
Peak memory 295956 kb
Host smart-c416d137-d70a-48fe-a40f-a64390a98724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935691766 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.1935691766
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.937152078
Short name T842
Test name
Test status
Simulation time 11586554597 ps
CPU time 39.89 seconds
Started Aug 01 05:59:40 PM PDT 24
Finished Aug 01 06:00:20 PM PDT 24
Peak memory 242228 kb
Host smart-2efed2f4-b8f9-4f0f-8a72-cf785374ec5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937152078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.937152078
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.2052595980
Short name T709
Test name
Test status
Simulation time 203063948 ps
CPU time 2.06 seconds
Started Aug 01 05:59:39 PM PDT 24
Finished Aug 01 05:59:41 PM PDT 24
Peak memory 240308 kb
Host smart-5412d233-c1c1-461c-a1f4-9dedf68fa310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052595980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.2052595980
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.2231544854
Short name T920
Test name
Test status
Simulation time 1513084694 ps
CPU time 32.71 seconds
Started Aug 01 05:59:41 PM PDT 24
Finished Aug 01 06:00:14 PM PDT 24
Peak memory 242488 kb
Host smart-cae29924-46c3-42d1-9fba-f311d7555965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231544854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.2231544854
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.2095029156
Short name T769
Test name
Test status
Simulation time 530513339 ps
CPU time 11.27 seconds
Started Aug 01 05:59:39 PM PDT 24
Finished Aug 01 05:59:50 PM PDT 24
Peak memory 242052 kb
Host smart-c5f5bbba-1299-4f68-a57d-e05d0fbdd2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095029156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.2095029156
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.3973878720
Short name T269
Test name
Test status
Simulation time 400272209 ps
CPU time 8.54 seconds
Started Aug 01 05:59:39 PM PDT 24
Finished Aug 01 05:59:47 PM PDT 24
Peak memory 241948 kb
Host smart-f81fb483-b18a-423e-af7e-ee293bfe3ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973878720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.3973878720
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.4269961762
Short name T814
Test name
Test status
Simulation time 1701956932 ps
CPU time 4.19 seconds
Started Aug 01 05:59:39 PM PDT 24
Finished Aug 01 05:59:43 PM PDT 24
Peak memory 242068 kb
Host smart-3053c62a-7b65-42c2-b407-5de87f0c5dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269961762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.4269961762
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.359842184
Short name T945
Test name
Test status
Simulation time 1081979356 ps
CPU time 7.78 seconds
Started Aug 01 05:59:42 PM PDT 24
Finished Aug 01 05:59:51 PM PDT 24
Peak memory 242260 kb
Host smart-3a0ccea4-b016-4647-a4a9-3aa3701967a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359842184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.359842184
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.4188204290
Short name T870
Test name
Test status
Simulation time 6240290627 ps
CPU time 46.48 seconds
Started Aug 01 05:59:38 PM PDT 24
Finished Aug 01 06:00:25 PM PDT 24
Peak memory 242492 kb
Host smart-818a2cf8-c302-4e3c-8418-62b1dd2f2537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188204290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.4188204290
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.2218953966
Short name T969
Test name
Test status
Simulation time 1708853952 ps
CPU time 11.51 seconds
Started Aug 01 05:59:38 PM PDT 24
Finished Aug 01 05:59:50 PM PDT 24
Peak memory 241804 kb
Host smart-79db0d63-25d9-4452-b554-5d00a558252f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218953966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.2218953966
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.2272902641
Short name T1157
Test name
Test status
Simulation time 703066805 ps
CPU time 18.99 seconds
Started Aug 01 05:59:39 PM PDT 24
Finished Aug 01 05:59:58 PM PDT 24
Peak memory 241964 kb
Host smart-b9491635-7ff3-46af-bc2f-0e87e038cbe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272902641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.2272902641
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.3219568298
Short name T698
Test name
Test status
Simulation time 272160446 ps
CPU time 5.35 seconds
Started Aug 01 05:59:41 PM PDT 24
Finished Aug 01 05:59:46 PM PDT 24
Peak memory 241916 kb
Host smart-871b8821-2b1f-4cd6-8ab1-826584ec46af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3219568298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.3219568298
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.2915659665
Short name T718
Test name
Test status
Simulation time 686314708 ps
CPU time 5.96 seconds
Started Aug 01 05:59:39 PM PDT 24
Finished Aug 01 05:59:45 PM PDT 24
Peak memory 241852 kb
Host smart-9dc743ff-e10c-454b-bc09-894d81515866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915659665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.2915659665
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.1457659874
Short name T55
Test name
Test status
Simulation time 5420415855 ps
CPU time 45.7 seconds
Started Aug 01 05:59:40 PM PDT 24
Finished Aug 01 06:00:26 PM PDT 24
Peak memory 244692 kb
Host smart-e39ef83a-1c3d-4c9c-a232-5a7789be5e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457659874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.1457659874
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.1086421176
Short name T826
Test name
Test status
Simulation time 20983109154 ps
CPU time 39.01 seconds
Started Aug 01 05:59:39 PM PDT 24
Finished Aug 01 06:00:18 PM PDT 24
Peak memory 241916 kb
Host smart-ab92fb95-f5fa-47d8-be3e-47e530feb69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086421176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.1086421176
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.708324250
Short name T603
Test name
Test status
Simulation time 167622324 ps
CPU time 2.03 seconds
Started Aug 01 05:59:50 PM PDT 24
Finished Aug 01 05:59:52 PM PDT 24
Peak memory 240608 kb
Host smart-48ddaf52-667f-4c72-a037-8ed60053829d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708324250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.708324250
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.3325174329
Short name T1128
Test name
Test status
Simulation time 2967703029 ps
CPU time 25.56 seconds
Started Aug 01 05:59:49 PM PDT 24
Finished Aug 01 06:00:15 PM PDT 24
Peak memory 245016 kb
Host smart-f6dee83c-bf73-454d-8c7d-185f9bd4ff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325174329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.3325174329
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.3993472461
Short name T1177
Test name
Test status
Simulation time 1901035534 ps
CPU time 25.34 seconds
Started Aug 01 05:59:51 PM PDT 24
Finished Aug 01 06:00:17 PM PDT 24
Peak memory 242976 kb
Host smart-6c015592-2532-4918-a6bc-e3da31fb2358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993472461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.3993472461
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.3968402271
Short name T731
Test name
Test status
Simulation time 2757420918 ps
CPU time 9.4 seconds
Started Aug 01 05:59:48 PM PDT 24
Finished Aug 01 05:59:57 PM PDT 24
Peak memory 242040 kb
Host smart-cdc850e1-7ca8-4c73-8707-08f76b92564b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968402271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3968402271
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.1967398483
Short name T925
Test name
Test status
Simulation time 155106044 ps
CPU time 4.29 seconds
Started Aug 01 05:59:51 PM PDT 24
Finished Aug 01 05:59:55 PM PDT 24
Peak memory 242372 kb
Host smart-496cfc46-e4ae-4b2c-bba9-416d9c2586b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967398483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.1967398483
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.2666297778
Short name T755
Test name
Test status
Simulation time 491098925 ps
CPU time 13.38 seconds
Started Aug 01 05:59:51 PM PDT 24
Finished Aug 01 06:00:04 PM PDT 24
Peak memory 248648 kb
Host smart-bc04e4f4-34c5-40db-94a2-288df51f9947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666297778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.2666297778
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.2427311789
Short name T710
Test name
Test status
Simulation time 1771023987 ps
CPU time 38.39 seconds
Started Aug 01 05:59:50 PM PDT 24
Finished Aug 01 06:00:29 PM PDT 24
Peak memory 248448 kb
Host smart-5de88b7c-b965-4f75-90ba-02f109187c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427311789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2427311789
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.488765206
Short name T340
Test name
Test status
Simulation time 165205402 ps
CPU time 8.32 seconds
Started Aug 01 05:59:51 PM PDT 24
Finished Aug 01 06:00:00 PM PDT 24
Peak memory 242220 kb
Host smart-45c517e9-5c70-41fb-8d51-72846cf481a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488765206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.488765206
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.1574212655
Short name T897
Test name
Test status
Simulation time 10297214392 ps
CPU time 31.55 seconds
Started Aug 01 05:59:50 PM PDT 24
Finished Aug 01 06:00:22 PM PDT 24
Peak memory 241980 kb
Host smart-e897231d-e6bf-4f05-8053-8a4004212ed3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574212655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1574212655
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.1511243421
Short name T365
Test name
Test status
Simulation time 424588274 ps
CPU time 3.68 seconds
Started Aug 01 05:59:52 PM PDT 24
Finished Aug 01 05:59:55 PM PDT 24
Peak memory 242032 kb
Host smart-5bba46b5-8c7c-4763-9301-786410b930bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1511243421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.1511243421
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.3678883297
Short name T251
Test name
Test status
Simulation time 872415911 ps
CPU time 10.62 seconds
Started Aug 01 05:59:39 PM PDT 24
Finished Aug 01 05:59:50 PM PDT 24
Peak memory 242080 kb
Host smart-9111f075-7eb5-47a4-86f0-9ab0f0d260cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678883297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.3678883297
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.1071676613
Short name T419
Test name
Test status
Simulation time 9691922187 ps
CPU time 26.35 seconds
Started Aug 01 05:59:49 PM PDT 24
Finished Aug 01 06:00:16 PM PDT 24
Peak memory 242168 kb
Host smart-7150f917-f4e2-4b7b-be07-2d5dbfc0accf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071676613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.1071676613
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.783604309
Short name T619
Test name
Test status
Simulation time 1293480530 ps
CPU time 2.18 seconds
Started Aug 01 05:59:51 PM PDT 24
Finished Aug 01 05:59:53 PM PDT 24
Peak memory 240820 kb
Host smart-6413226a-2534-4d1b-941b-7b890bf7441c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783604309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.783604309
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.1567012857
Short name T784
Test name
Test status
Simulation time 397956389 ps
CPU time 6.88 seconds
Started Aug 01 05:59:49 PM PDT 24
Finished Aug 01 05:59:57 PM PDT 24
Peak memory 242328 kb
Host smart-678f004e-5a29-4862-bcad-b2ccf3d11355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567012857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1567012857
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.1558740237
Short name T883
Test name
Test status
Simulation time 922144988 ps
CPU time 22.78 seconds
Started Aug 01 05:59:50 PM PDT 24
Finished Aug 01 06:00:13 PM PDT 24
Peak memory 241908 kb
Host smart-d3012f34-b725-4f25-82a3-a9a784a8dfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558740237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.1558740237
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.1757599175
Short name T455
Test name
Test status
Simulation time 281300330 ps
CPU time 6.22 seconds
Started Aug 01 05:59:52 PM PDT 24
Finished Aug 01 05:59:58 PM PDT 24
Peak memory 242296 kb
Host smart-37657d64-0731-4f98-b3e8-c5fbd4389c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757599175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.1757599175
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.1521220410
Short name T1061
Test name
Test status
Simulation time 144393547 ps
CPU time 4.17 seconds
Started Aug 01 05:59:50 PM PDT 24
Finished Aug 01 05:59:55 PM PDT 24
Peak memory 242136 kb
Host smart-0e8453c0-1ac7-477f-82cb-a28db21852a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521220410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.1521220410
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.3525872694
Short name T518
Test name
Test status
Simulation time 5046379007 ps
CPU time 32.86 seconds
Started Aug 01 05:59:50 PM PDT 24
Finished Aug 01 06:00:23 PM PDT 24
Peak memory 248624 kb
Host smart-3aea8cae-1bd4-411e-8eb5-7896ae0d1237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525872694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.3525872694
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.3571781237
Short name T1057
Test name
Test status
Simulation time 276630688 ps
CPU time 5.52 seconds
Started Aug 01 05:59:50 PM PDT 24
Finished Aug 01 05:59:56 PM PDT 24
Peak memory 242448 kb
Host smart-7e3f25bf-c98b-4b64-b080-632582d8f954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571781237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3571781237
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.4016439961
Short name T1154
Test name
Test status
Simulation time 314591477 ps
CPU time 3.1 seconds
Started Aug 01 05:59:49 PM PDT 24
Finished Aug 01 05:59:52 PM PDT 24
Peak memory 241880 kb
Host smart-ceaf0b07-c955-44d3-b85d-edcc83f37c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016439961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.4016439961
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.1318798358
Short name T507
Test name
Test status
Simulation time 877341519 ps
CPU time 23.99 seconds
Started Aug 01 05:59:48 PM PDT 24
Finished Aug 01 06:00:12 PM PDT 24
Peak memory 242024 kb
Host smart-5546b607-7955-4f86-b3fa-29b6c516a1dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1318798358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.1318798358
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.1250975754
Short name T694
Test name
Test status
Simulation time 5570135371 ps
CPU time 22.33 seconds
Started Aug 01 05:59:49 PM PDT 24
Finished Aug 01 06:00:12 PM PDT 24
Peak memory 241996 kb
Host smart-fca58132-1630-496b-9905-180b888f371d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250975754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1250975754
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.1878543692
Short name T895
Test name
Test status
Simulation time 6902854019 ps
CPU time 71.47 seconds
Started Aug 01 05:59:51 PM PDT 24
Finished Aug 01 06:01:03 PM PDT 24
Peak memory 248524 kb
Host smart-d5592dd2-9577-485a-b33a-0ccfb7ed0d15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878543692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.1878543692
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.2094570652
Short name T509
Test name
Test status
Simulation time 136161230342 ps
CPU time 643.55 seconds
Started Aug 01 05:59:48 PM PDT 24
Finished Aug 01 06:10:32 PM PDT 24
Peak memory 280300 kb
Host smart-bdc95455-94f6-4830-b734-549529627cac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094570652 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.2094570652
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.258816303
Short name T850
Test name
Test status
Simulation time 8298025448 ps
CPU time 15.26 seconds
Started Aug 01 05:59:51 PM PDT 24
Finished Aug 01 06:00:06 PM PDT 24
Peak memory 242324 kb
Host smart-eb38890d-78ae-41b8-91eb-33932c9aa897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258816303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.258816303
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.1091300659
Short name T581
Test name
Test status
Simulation time 47215061 ps
CPU time 1.7 seconds
Started Aug 01 06:00:01 PM PDT 24
Finished Aug 01 06:00:02 PM PDT 24
Peak memory 240776 kb
Host smart-6a0ccb37-8875-447c-b38b-d4058805af27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091300659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.1091300659
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.3422443382
Short name T121
Test name
Test status
Simulation time 2550838632 ps
CPU time 30.24 seconds
Started Aug 01 06:00:05 PM PDT 24
Finished Aug 01 06:01:25 PM PDT 24
Peak memory 248568 kb
Host smart-3c6505f1-95d9-47ee-bbcb-7c74f59542db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422443382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.3422443382
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.1162180069
Short name T1022
Test name
Test status
Simulation time 2079655087 ps
CPU time 22.34 seconds
Started Aug 01 06:00:05 PM PDT 24
Finished Aug 01 06:01:18 PM PDT 24
Peak memory 241844 kb
Host smart-88146058-f4bd-487d-adfd-b4c986bb6955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162180069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.1162180069
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.3251840986
Short name T1049
Test name
Test status
Simulation time 881116011 ps
CPU time 5.64 seconds
Started Aug 01 06:00:06 PM PDT 24
Finished Aug 01 06:01:01 PM PDT 24
Peak memory 241628 kb
Host smart-b52db2bc-06c3-441d-b754-fc91eaa72a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251840986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.3251840986
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.1114514980
Short name T632
Test name
Test status
Simulation time 202851026 ps
CPU time 4.44 seconds
Started Aug 01 05:59:51 PM PDT 24
Finished Aug 01 05:59:55 PM PDT 24
Peak memory 241956 kb
Host smart-4499061a-d24b-4a40-94fe-9176e7d52cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114514980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.1114514980
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.3465277430
Short name T984
Test name
Test status
Simulation time 14384604506 ps
CPU time 31.73 seconds
Started Aug 01 06:00:06 PM PDT 24
Finished Aug 01 06:01:27 PM PDT 24
Peak memory 244924 kb
Host smart-32ff8bfd-1d90-4c8d-8a73-c963051c8d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465277430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3465277430
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.4134033361
Short name T482
Test name
Test status
Simulation time 1753573957 ps
CPU time 30.61 seconds
Started Aug 01 06:00:04 PM PDT 24
Finished Aug 01 06:01:26 PM PDT 24
Peak memory 242064 kb
Host smart-5955bd47-82dc-456e-ba97-bd2c1b34fc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134033361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.4134033361
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.1541634102
Short name T201
Test name
Test status
Simulation time 427611211 ps
CPU time 6.79 seconds
Started Aug 01 05:59:51 PM PDT 24
Finished Aug 01 05:59:58 PM PDT 24
Peak memory 242008 kb
Host smart-14c4fae8-6fb3-4da0-9d29-1ebf998f7c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541634102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.1541634102
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.3325306425
Short name T588
Test name
Test status
Simulation time 1447869976 ps
CPU time 11.36 seconds
Started Aug 01 05:59:51 PM PDT 24
Finished Aug 01 06:00:02 PM PDT 24
Peak memory 241836 kb
Host smart-cf221cd7-1e10-4441-b8aa-3191aff3a6e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3325306425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.3325306425
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.2440923162
Short name T809
Test name
Test status
Simulation time 2222370561 ps
CPU time 10.31 seconds
Started Aug 01 06:00:05 PM PDT 24
Finished Aug 01 06:01:06 PM PDT 24
Peak memory 242028 kb
Host smart-17ab99e1-e14d-4ebc-a242-29e1b2d73982
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2440923162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.2440923162
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.3247987578
Short name T1102
Test name
Test status
Simulation time 382549902 ps
CPU time 4.05 seconds
Started Aug 01 05:59:50 PM PDT 24
Finished Aug 01 05:59:55 PM PDT 24
Peak memory 241936 kb
Host smart-3856b59d-12a5-4a18-aa5d-2146eb603a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247987578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.3247987578
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.266581720
Short name T576
Test name
Test status
Simulation time 2150631936 ps
CPU time 20.98 seconds
Started Aug 01 06:00:05 PM PDT 24
Finished Aug 01 06:01:16 PM PDT 24
Peak memory 241964 kb
Host smart-c1e550e2-a899-4157-a0c0-a312e8d1a8fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266581720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.
266581720
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.207875375
Short name T284
Test name
Test status
Simulation time 37768453637 ps
CPU time 419.72 seconds
Started Aug 01 06:00:04 PM PDT 24
Finished Aug 01 06:07:55 PM PDT 24
Peak memory 256936 kb
Host smart-81f33ce7-b084-4872-a828-96905b9bf2fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207875375 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.207875375
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.3022167135
Short name T633
Test name
Test status
Simulation time 465607287 ps
CPU time 15.36 seconds
Started Aug 01 06:00:04 PM PDT 24
Finished Aug 01 06:01:11 PM PDT 24
Peak memory 242660 kb
Host smart-2cfb6a38-00da-41fd-9b48-4239292ac28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022167135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.3022167135
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.3449801169
Short name T725
Test name
Test status
Simulation time 749089386 ps
CPU time 1.81 seconds
Started Aug 01 06:00:03 PM PDT 24
Finished Aug 01 06:00:57 PM PDT 24
Peak memory 240524 kb
Host smart-012351b3-b95e-4194-8643-d7f8d4f91f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449801169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.3449801169
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.1710335027
Short name T42
Test name
Test status
Simulation time 14881257468 ps
CPU time 36.88 seconds
Started Aug 01 06:00:06 PM PDT 24
Finished Aug 01 06:01:32 PM PDT 24
Peak memory 248588 kb
Host smart-25d96ed2-2819-40aa-aa2a-b6430893a00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710335027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.1710335027
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.940600608
Short name T854
Test name
Test status
Simulation time 2759933216 ps
CPU time 36.96 seconds
Started Aug 01 06:00:03 PM PDT 24
Finished Aug 01 06:01:32 PM PDT 24
Peak memory 253672 kb
Host smart-80c42191-41bd-4cd4-90ed-ac2d4352983d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940600608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.940600608
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.1413163185
Short name T475
Test name
Test status
Simulation time 1452980796 ps
CPU time 18.83 seconds
Started Aug 01 06:00:03 PM PDT 24
Finished Aug 01 06:01:14 PM PDT 24
Peak memory 241968 kb
Host smart-a0b1fce8-0bf8-4a88-9ef0-c1ba0b826f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413163185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.1413163185
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.1070052615
Short name T695
Test name
Test status
Simulation time 522114029 ps
CPU time 4.51 seconds
Started Aug 01 06:00:01 PM PDT 24
Finished Aug 01 06:00:06 PM PDT 24
Peak memory 242120 kb
Host smart-8822f3c4-ff1a-4697-b6c8-44c1a555e8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070052615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.1070052615
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.2695111486
Short name T795
Test name
Test status
Simulation time 2224236927 ps
CPU time 21.85 seconds
Started Aug 01 06:00:04 PM PDT 24
Finished Aug 01 06:01:17 PM PDT 24
Peak memory 242352 kb
Host smart-c3213d92-9a22-4330-987b-9ba1145bbaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695111486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.2695111486
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.1250365481
Short name T544
Test name
Test status
Simulation time 12177560652 ps
CPU time 34.93 seconds
Started Aug 01 06:00:05 PM PDT 24
Finished Aug 01 06:01:30 PM PDT 24
Peak memory 242196 kb
Host smart-8b794ef2-349c-426d-b9e1-df179dfa9a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250365481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1250365481
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.955375453
Short name T1089
Test name
Test status
Simulation time 159594850 ps
CPU time 2.88 seconds
Started Aug 01 06:00:06 PM PDT 24
Finished Aug 01 06:00:58 PM PDT 24
Peak memory 241876 kb
Host smart-fc67dbce-101c-46bc-bf87-e3db6fcae72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955375453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.955375453
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.563724850
Short name T1119
Test name
Test status
Simulation time 244332402 ps
CPU time 8.93 seconds
Started Aug 01 06:00:05 PM PDT 24
Finished Aug 01 06:01:04 PM PDT 24
Peak memory 241980 kb
Host smart-e4fec60e-bff0-4b74-b886-c05515ad822f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563724850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.563724850
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.2182667278
Short name T733
Test name
Test status
Simulation time 949535314 ps
CPU time 9.37 seconds
Started Aug 01 06:00:05 PM PDT 24
Finished Aug 01 06:01:05 PM PDT 24
Peak memory 242024 kb
Host smart-7690694c-6375-4a6b-826f-47df63da08ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182667278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.2182667278
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.767154992
Short name T1121
Test name
Test status
Simulation time 13735141364 ps
CPU time 34.13 seconds
Started Aug 01 06:00:06 PM PDT 24
Finished Aug 01 06:01:29 PM PDT 24
Peak memory 241776 kb
Host smart-d2e0099e-7fc7-4f10-b243-5b12b8c3354b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767154992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.
767154992
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.4030804693
Short name T1048
Test name
Test status
Simulation time 5490558799 ps
CPU time 177.77 seconds
Started Aug 01 06:00:04 PM PDT 24
Finished Aug 01 06:03:53 PM PDT 24
Peak memory 261828 kb
Host smart-519cc1ce-9491-48ea-8a2e-17e4d283b81f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030804693 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.4030804693
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.3944422686
Short name T1085
Test name
Test status
Simulation time 539323721 ps
CPU time 11.6 seconds
Started Aug 01 06:00:04 PM PDT 24
Finished Aug 01 06:01:07 PM PDT 24
Peak memory 242060 kb
Host smart-332378f3-21cc-4b59-bb29-57c940ff9cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944422686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.3944422686
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.1984573825
Short name T647
Test name
Test status
Simulation time 95961892 ps
CPU time 1.65 seconds
Started Aug 01 06:00:02 PM PDT 24
Finished Aug 01 06:00:57 PM PDT 24
Peak memory 240316 kb
Host smart-b58f3d94-c0ee-48c6-ba03-e1112a34df45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984573825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.1984573825
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.4287375405
Short name T127
Test name
Test status
Simulation time 18227628726 ps
CPU time 56.91 seconds
Started Aug 01 06:00:04 PM PDT 24
Finished Aug 01 06:01:52 PM PDT 24
Peak memory 248616 kb
Host smart-eeec16df-b88d-4367-b703-2aafc5e868f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287375405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.4287375405
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.1731734623
Short name T716
Test name
Test status
Simulation time 1795502146 ps
CPU time 17.74 seconds
Started Aug 01 06:00:03 PM PDT 24
Finished Aug 01 06:01:13 PM PDT 24
Peak memory 242476 kb
Host smart-f1d102ce-97ca-401f-ad23-a7b78a9c99cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731734623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.1731734623
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.3373182273
Short name T292
Test name
Test status
Simulation time 8476254499 ps
CPU time 20.11 seconds
Started Aug 01 06:00:04 PM PDT 24
Finished Aug 01 06:01:15 PM PDT 24
Peak memory 248480 kb
Host smart-d94f4a41-3104-439b-b8d0-d7afad05bd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373182273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.3373182273
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.3324075248
Short name T123
Test name
Test status
Simulation time 237482030 ps
CPU time 3.23 seconds
Started Aug 01 06:00:05 PM PDT 24
Finished Aug 01 06:00:58 PM PDT 24
Peak memory 241764 kb
Host smart-83c1ac76-cc44-4a2a-8460-8d4f9ee7482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324075248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3324075248
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.3895165092
Short name T792
Test name
Test status
Simulation time 2084162624 ps
CPU time 37.69 seconds
Started Aug 01 06:00:03 PM PDT 24
Finished Aug 01 06:01:33 PM PDT 24
Peak memory 256764 kb
Host smart-4e0271bf-8db5-48b5-8d33-f34c22bfec23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895165092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.3895165092
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.932303584
Short name T1105
Test name
Test status
Simulation time 1594845841 ps
CPU time 38.25 seconds
Started Aug 01 06:00:04 PM PDT 24
Finished Aug 01 06:01:34 PM PDT 24
Peak memory 248460 kb
Host smart-a5e10b2a-f676-466a-b8b4-b023be92d23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932303584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.932303584
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.1164699784
Short name T841
Test name
Test status
Simulation time 961556684 ps
CPU time 10.09 seconds
Started Aug 01 06:00:04 PM PDT 24
Finished Aug 01 06:01:05 PM PDT 24
Peak memory 241808 kb
Host smart-4b30e749-7dcf-4803-840d-519d2663a15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164699784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.1164699784
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.655753249
Short name T954
Test name
Test status
Simulation time 953286843 ps
CPU time 21.03 seconds
Started Aug 01 06:00:04 PM PDT 24
Finished Aug 01 06:01:16 PM PDT 24
Peak memory 242080 kb
Host smart-4c5cf640-98e3-44e7-8490-7b1f5b0ad44a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=655753249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.655753249
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.3441821537
Short name T357
Test name
Test status
Simulation time 985459206 ps
CPU time 8.66 seconds
Started Aug 01 06:00:05 PM PDT 24
Finished Aug 01 06:01:04 PM PDT 24
Peak memory 242196 kb
Host smart-6ca7a18e-04a1-4d20-90a1-70c5f2e422be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3441821537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3441821537
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.2591081403
Short name T1169
Test name
Test status
Simulation time 1229100171 ps
CPU time 8.07 seconds
Started Aug 01 06:00:03 PM PDT 24
Finished Aug 01 06:01:03 PM PDT 24
Peak memory 241924 kb
Host smart-ca0e2e27-defd-4f86-b5f1-a60cf345a703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591081403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.2591081403
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.2774768572
Short name T948
Test name
Test status
Simulation time 1707045380 ps
CPU time 11.8 seconds
Started Aug 01 06:00:05 PM PDT 24
Finished Aug 01 06:01:07 PM PDT 24
Peak memory 241924 kb
Host smart-6dff2b0a-947f-469c-bd77-a68d208c9d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774768572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.2774768572
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.1192333287
Short name T1038
Test name
Test status
Simulation time 778110954 ps
CPU time 1.87 seconds
Started Aug 01 06:00:22 PM PDT 24
Finished Aug 01 06:00:57 PM PDT 24
Peak memory 240496 kb
Host smart-3d25e1fb-3a97-49c6-b770-df8d92225ff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192333287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.1192333287
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.2876738688
Short name T650
Test name
Test status
Simulation time 5209109258 ps
CPU time 17.08 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:01:12 PM PDT 24
Peak memory 243084 kb
Host smart-c06d68ed-ed9a-421d-9cdc-b64649d0fc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876738688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.2876738688
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.446792724
Short name T968
Test name
Test status
Simulation time 3014475985 ps
CPU time 35.56 seconds
Started Aug 01 06:00:22 PM PDT 24
Finished Aug 01 06:01:31 PM PDT 24
Peak memory 243984 kb
Host smart-beca8ce8-3e67-4ee1-ab5f-544e2cc8786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446792724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.446792724
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.2259487934
Short name T692
Test name
Test status
Simulation time 6928961477 ps
CPU time 20.58 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:01:16 PM PDT 24
Peak memory 242832 kb
Host smart-1d2ba999-407c-4a75-bddd-9f4f8627b5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259487934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.2259487934
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.1629942952
Short name T1017
Test name
Test status
Simulation time 2430013298 ps
CPU time 8.51 seconds
Started Aug 01 06:00:06 PM PDT 24
Finished Aug 01 06:01:04 PM PDT 24
Peak memory 242344 kb
Host smart-a23b3b4f-5826-4114-b48a-e5dbc9bebcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629942952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.1629942952
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.267509793
Short name T600
Test name
Test status
Simulation time 6770394873 ps
CPU time 67.7 seconds
Started Aug 01 06:00:18 PM PDT 24
Finished Aug 01 06:02:03 PM PDT 24
Peak memory 264800 kb
Host smart-adcdbf4c-f0e0-4747-93b4-317931ab13b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267509793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.267509793
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.2696681866
Short name T1137
Test name
Test status
Simulation time 349492373 ps
CPU time 16.15 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:01:11 PM PDT 24
Peak memory 242108 kb
Host smart-d4cc91e0-c087-4878-abe0-1e086d67d3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696681866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.2696681866
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.579773635
Short name T428
Test name
Test status
Simulation time 173032228 ps
CPU time 4.89 seconds
Started Aug 01 06:00:21 PM PDT 24
Finished Aug 01 06:01:00 PM PDT 24
Peak memory 242160 kb
Host smart-ec1237d0-0056-45ae-9d91-674864d8b18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579773635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.579773635
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.3259043994
Short name T377
Test name
Test status
Simulation time 1559623033 ps
CPU time 22.3 seconds
Started Aug 01 06:00:22 PM PDT 24
Finished Aug 01 06:01:18 PM PDT 24
Peak memory 242076 kb
Host smart-8172977c-fbf5-418f-acef-3346d4e09958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259043994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.3259043994
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.3143523520
Short name T621
Test name
Test status
Simulation time 580162761 ps
CPU time 7.6 seconds
Started Aug 01 06:00:04 PM PDT 24
Finished Aug 01 06:01:03 PM PDT 24
Peak memory 242184 kb
Host smart-5f4a7530-d58e-4d0e-ac35-57eb58d20ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143523520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.3143523520
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.3655263193
Short name T1125
Test name
Test status
Simulation time 97280137734 ps
CPU time 266.58 seconds
Started Aug 01 06:00:24 PM PDT 24
Finished Aug 01 06:05:22 PM PDT 24
Peak memory 264964 kb
Host smart-fd5613b6-19a5-4dea-a5cc-a09cadd30b4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655263193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.3655263193
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.3829747031
Short name T903
Test name
Test status
Simulation time 1871682192 ps
CPU time 25.05 seconds
Started Aug 01 06:00:20 PM PDT 24
Finished Aug 01 06:01:20 PM PDT 24
Peak memory 242188 kb
Host smart-3a3bc7ff-d5bb-4b8f-b308-77c209ce2a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829747031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3829747031
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.1977191996
Short name T439
Test name
Test status
Simulation time 193316283 ps
CPU time 1.86 seconds
Started Aug 01 06:00:18 PM PDT 24
Finished Aug 01 06:00:57 PM PDT 24
Peak memory 240240 kb
Host smart-d1a96fbe-c34c-4be7-bae8-a321c2c40c39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977191996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.1977191996
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.2958373462
Short name T443
Test name
Test status
Simulation time 399813277 ps
CPU time 11.87 seconds
Started Aug 01 06:00:17 PM PDT 24
Finished Aug 01 06:01:07 PM PDT 24
Peak memory 241904 kb
Host smart-25c6bb70-2621-4a01-88fa-9dcf0f96e4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958373462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.2958373462
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.4245736080
Short name T594
Test name
Test status
Simulation time 5272892660 ps
CPU time 34.76 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:01:30 PM PDT 24
Peak memory 242080 kb
Host smart-7815fbb3-02e9-4c2c-be6b-5e329d7d56b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245736080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.4245736080
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.921625595
Short name T476
Test name
Test status
Simulation time 464998251 ps
CPU time 4.19 seconds
Started Aug 01 06:00:22 PM PDT 24
Finished Aug 01 06:00:59 PM PDT 24
Peak memory 242068 kb
Host smart-90b53845-be5f-4522-b3ec-cf2af8754046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921625595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.921625595
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.3989093394
Short name T558
Test name
Test status
Simulation time 345101373 ps
CPU time 11.13 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:01:06 PM PDT 24
Peak memory 242016 kb
Host smart-5066a1f1-aa21-4219-a342-11c32ddd03ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989093394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.3989093394
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.1211801825
Short name T384
Test name
Test status
Simulation time 2338193889 ps
CPU time 24.41 seconds
Started Aug 01 06:00:23 PM PDT 24
Finished Aug 01 06:01:20 PM PDT 24
Peak memory 241912 kb
Host smart-aebd4058-f3d3-4804-a0ba-7f23a07b965d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211801825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.1211801825
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.2537335159
Short name T743
Test name
Test status
Simulation time 330377330 ps
CPU time 2.83 seconds
Started Aug 01 06:00:20 PM PDT 24
Finished Aug 01 06:00:58 PM PDT 24
Peak memory 247212 kb
Host smart-61b5659b-49bb-4a87-a9f0-a8c4dfc6645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537335159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.2537335159
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.1940105338
Short name T668
Test name
Test status
Simulation time 878235806 ps
CPU time 15.45 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:01:11 PM PDT 24
Peak memory 241884 kb
Host smart-32c9f820-d8e3-480d-a06f-844c156933b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1940105338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1940105338
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.1660364425
Short name T363
Test name
Test status
Simulation time 2461276911 ps
CPU time 7.73 seconds
Started Aug 01 06:00:20 PM PDT 24
Finished Aug 01 06:01:03 PM PDT 24
Peak memory 241908 kb
Host smart-c886281d-df6d-449d-a44c-c6ee96373e7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1660364425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.1660364425
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.802805616
Short name T950
Test name
Test status
Simulation time 814140143 ps
CPU time 9.36 seconds
Started Aug 01 06:00:20 PM PDT 24
Finished Aug 01 06:01:05 PM PDT 24
Peak memory 242220 kb
Host smart-83e34ac6-633c-420c-8d8e-44f9ceb0caf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802805616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.802805616
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.2187119945
Short name T129
Test name
Test status
Simulation time 6098511880 ps
CPU time 96.23 seconds
Started Aug 01 06:00:21 PM PDT 24
Finished Aug 01 06:02:32 PM PDT 24
Peak memory 258740 kb
Host smart-40c6e1f3-8da5-48e5-b712-365d98ddeef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187119945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.2187119945
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.3359044392
Short name T700
Test name
Test status
Simulation time 63415979808 ps
CPU time 392.16 seconds
Started Aug 01 06:00:21 PM PDT 24
Finished Aug 01 06:07:27 PM PDT 24
Peak memory 267200 kb
Host smart-db535b55-30f6-44b0-8892-5eff8b573212
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359044392 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.3359044392
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.3750232283
Short name T674
Test name
Test status
Simulation time 605064056 ps
CPU time 15.29 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:01:11 PM PDT 24
Peak memory 241964 kb
Host smart-da093af1-53c5-4eda-a639-4ea4072649b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750232283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.3750232283
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.1313131571
Short name T742
Test name
Test status
Simulation time 710067620 ps
CPU time 2.28 seconds
Started Aug 01 05:57:58 PM PDT 24
Finished Aug 01 05:58:00 PM PDT 24
Peak memory 240800 kb
Host smart-11c809a5-ae37-4146-a649-ec381f65cc06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313131571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.1313131571
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.3718304106
Short name T554
Test name
Test status
Simulation time 4923522077 ps
CPU time 30.96 seconds
Started Aug 01 05:57:51 PM PDT 24
Finished Aug 01 05:58:22 PM PDT 24
Peak memory 242108 kb
Host smart-d5348d7c-e67b-4e3d-a21c-97b13d4606e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718304106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.3718304106
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.710435415
Short name T104
Test name
Test status
Simulation time 865157397 ps
CPU time 11.21 seconds
Started Aug 01 05:57:53 PM PDT 24
Finished Aug 01 05:58:05 PM PDT 24
Peak memory 248524 kb
Host smart-f04eff15-bc74-4115-be61-e7025c9d8788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710435415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.710435415
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.3025676320
Short name T345
Test name
Test status
Simulation time 851227305 ps
CPU time 13.72 seconds
Started Aug 01 05:57:53 PM PDT 24
Finished Aug 01 05:58:07 PM PDT 24
Peak memory 242104 kb
Host smart-c6f9a310-97e6-42e2-a70e-9776fe50e801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025676320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.3025676320
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.2633560981
Short name T330
Test name
Test status
Simulation time 1546916565 ps
CPU time 16.63 seconds
Started Aug 01 05:57:54 PM PDT 24
Finished Aug 01 05:58:11 PM PDT 24
Peak memory 242032 kb
Host smart-489d3cf8-45ee-4416-b6c3-777d32d9ea59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633560981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.2633560981
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.734746795
Short name T1151
Test name
Test status
Simulation time 200667955 ps
CPU time 3.85 seconds
Started Aug 01 05:57:58 PM PDT 24
Finished Aug 01 05:58:02 PM PDT 24
Peak memory 242036 kb
Host smart-620a42a5-551d-485c-8bbe-2afa6c4a0919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734746795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.734746795
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.650950214
Short name T1037
Test name
Test status
Simulation time 401812293 ps
CPU time 12.66 seconds
Started Aug 01 05:57:58 PM PDT 24
Finished Aug 01 05:58:11 PM PDT 24
Peak memory 242480 kb
Host smart-11a6443f-58dc-4c9f-be18-a7dc06a0f39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650950214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.650950214
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.823767472
Short name T750
Test name
Test status
Simulation time 1263058255 ps
CPU time 21.68 seconds
Started Aug 01 05:57:59 PM PDT 24
Finished Aug 01 05:58:21 PM PDT 24
Peak memory 242484 kb
Host smart-a21e4760-791f-4e2f-b078-6d3c1404a0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823767472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.823767472
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.2809215805
Short name T208
Test name
Test status
Simulation time 1137621985 ps
CPU time 8.29 seconds
Started Aug 01 05:57:52 PM PDT 24
Finished Aug 01 05:58:00 PM PDT 24
Peak memory 241800 kb
Host smart-7c555de0-1e56-42a7-b828-bbfed9202d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809215805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.2809215805
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.2357036248
Short name T523
Test name
Test status
Simulation time 614927603 ps
CPU time 18.96 seconds
Started Aug 01 05:57:52 PM PDT 24
Finished Aug 01 05:58:12 PM PDT 24
Peak memory 241920 kb
Host smart-dd1a4cb5-1722-4f96-a125-846a317665b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2357036248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2357036248
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.1600959352
Short name T371
Test name
Test status
Simulation time 220739779 ps
CPU time 7.03 seconds
Started Aug 01 05:57:58 PM PDT 24
Finished Aug 01 05:58:05 PM PDT 24
Peak memory 241868 kb
Host smart-db6448bf-3a0f-4701-ae91-cb54ffb52bfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600959352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1600959352
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.3385176941
Short name T555
Test name
Test status
Simulation time 2254398522 ps
CPU time 4.64 seconds
Started Aug 01 05:57:59 PM PDT 24
Finished Aug 01 05:58:03 PM PDT 24
Peak memory 242240 kb
Host smart-14e6bb08-52ce-40ad-b206-7bbca5eec915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385176941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.3385176941
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.492083788
Short name T549
Test name
Test status
Simulation time 5739422477 ps
CPU time 101.59 seconds
Started Aug 01 05:57:56 PM PDT 24
Finished Aug 01 05:59:38 PM PDT 24
Peak memory 245516 kb
Host smart-180717e3-34c2-4c32-bcf8-e3daac209e7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492083788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.492083788
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.515117469
Short name T1186
Test name
Test status
Simulation time 105796117083 ps
CPU time 2636.27 seconds
Started Aug 01 05:57:58 PM PDT 24
Finished Aug 01 06:41:55 PM PDT 24
Peak memory 360072 kb
Host smart-203a5154-9783-4d05-ab2d-0ab4fd13f935
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515117469 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.515117469
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.2591638358
Short name T463
Test name
Test status
Simulation time 1408616146 ps
CPU time 15.78 seconds
Started Aug 01 05:57:59 PM PDT 24
Finished Aug 01 05:58:15 PM PDT 24
Peak memory 242060 kb
Host smart-c083e744-2c46-4f47-82ee-46353d0986ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591638358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.2591638358
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.2474250324
Short name T402
Test name
Test status
Simulation time 51275855 ps
CPU time 1.68 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:00:57 PM PDT 24
Peak memory 240556 kb
Host smart-ada76534-c527-4299-bcf6-a1a687fa7b6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474250324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.2474250324
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.1264167635
Short name T825
Test name
Test status
Simulation time 6333031093 ps
CPU time 13.13 seconds
Started Aug 01 06:00:21 PM PDT 24
Finished Aug 01 06:01:09 PM PDT 24
Peak memory 243444 kb
Host smart-0f2c1a27-fe1d-4a1d-9e2f-385346bea08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264167635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1264167635
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.2681501746
Short name T751
Test name
Test status
Simulation time 638285890 ps
CPU time 21.07 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:01:16 PM PDT 24
Peak memory 241884 kb
Host smart-b6969e62-b8ab-49a2-9065-505be2c2eb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681501746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.2681501746
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.4205182178
Short name T294
Test name
Test status
Simulation time 3417619501 ps
CPU time 36.92 seconds
Started Aug 01 06:00:20 PM PDT 24
Finished Aug 01 06:01:32 PM PDT 24
Peak memory 248520 kb
Host smart-87199de1-88a8-4faa-aa58-34c44736d59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205182178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.4205182178
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.581987251
Short name T1172
Test name
Test status
Simulation time 492893716 ps
CPU time 4.53 seconds
Started Aug 01 06:00:21 PM PDT 24
Finished Aug 01 06:01:00 PM PDT 24
Peak memory 242104 kb
Host smart-412a39c1-ce5f-47a8-912a-71c72ac43626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581987251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.581987251
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.3587715212
Short name T1159
Test name
Test status
Simulation time 1454920941 ps
CPU time 21.46 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:01:17 PM PDT 24
Peak memory 243912 kb
Host smart-b68a34a1-2c2a-4762-8ac2-5418b2afbc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587715212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3587715212
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.1455638824
Short name T332
Test name
Test status
Simulation time 565372075 ps
CPU time 14.49 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:01:10 PM PDT 24
Peak memory 242464 kb
Host smart-44145239-b82c-44ef-95e9-78df55d5a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455638824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.1455638824
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.1886437582
Short name T562
Test name
Test status
Simulation time 7753907716 ps
CPU time 18.68 seconds
Started Aug 01 06:00:20 PM PDT 24
Finished Aug 01 06:01:14 PM PDT 24
Peak memory 242264 kb
Host smart-f292874d-5045-4fc6-ae45-e62103e6aa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886437582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.1886437582
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.1478993781
Short name T623
Test name
Test status
Simulation time 530356771 ps
CPU time 13.35 seconds
Started Aug 01 06:00:21 PM PDT 24
Finished Aug 01 06:01:09 PM PDT 24
Peak memory 241944 kb
Host smart-5bdda327-a42e-44be-82a7-43aa09744e1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478993781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.1478993781
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.2812735235
Short name T823
Test name
Test status
Simulation time 137206432 ps
CPU time 6.08 seconds
Started Aug 01 06:00:18 PM PDT 24
Finished Aug 01 06:01:01 PM PDT 24
Peak memory 241780 kb
Host smart-0357d0aa-8c4e-4ea8-8865-ccfda107a657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2812735235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.2812735235
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.4008604096
Short name T628
Test name
Test status
Simulation time 282999652 ps
CPU time 7.58 seconds
Started Aug 01 06:00:20 PM PDT 24
Finished Aug 01 06:01:03 PM PDT 24
Peak memory 241948 kb
Host smart-35c0b3d5-87ee-4e9a-98af-313c932c9307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008604096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.4008604096
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.196740568
Short name T878
Test name
Test status
Simulation time 116635918263 ps
CPU time 384.24 seconds
Started Aug 01 06:00:18 PM PDT 24
Finished Aug 01 06:07:20 PM PDT 24
Peak memory 262460 kb
Host smart-bb5be338-6c83-479e-a442-3041b7c951ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196740568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.
196740568
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.1445319036
Short name T1114
Test name
Test status
Simulation time 140322670483 ps
CPU time 1010.67 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:17:46 PM PDT 24
Peak memory 252952 kb
Host smart-4a3c7c6c-ffb7-4d1a-aafe-4c67b8f00d65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445319036 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.1445319036
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.4180730943
Short name T408
Test name
Test status
Simulation time 625717326 ps
CPU time 13.36 seconds
Started Aug 01 06:00:20 PM PDT 24
Finished Aug 01 06:01:09 PM PDT 24
Peak memory 241848 kb
Host smart-e43849e2-f073-43a3-89f0-cf86069f747b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180730943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.4180730943
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.955281055
Short name T1002
Test name
Test status
Simulation time 362184231 ps
CPU time 2.12 seconds
Started Aug 01 06:00:18 PM PDT 24
Finished Aug 01 06:00:58 PM PDT 24
Peak memory 240728 kb
Host smart-bd7ca429-8e3d-4aa8-8cf3-102ec93dc524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955281055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.955281055
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.3245884192
Short name T467
Test name
Test status
Simulation time 456139393 ps
CPU time 13.8 seconds
Started Aug 01 06:00:20 PM PDT 24
Finished Aug 01 06:01:09 PM PDT 24
Peak memory 241900 kb
Host smart-771a7946-4c49-4212-9767-76892d60fb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245884192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.3245884192
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.1526624543
Short name T89
Test name
Test status
Simulation time 18914076999 ps
CPU time 27.13 seconds
Started Aug 01 06:00:23 PM PDT 24
Finished Aug 01 06:01:22 PM PDT 24
Peak memory 243400 kb
Host smart-b776bc3b-c6d7-461b-99e2-9be2a8e73970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526624543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.1526624543
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.25294309
Short name T824
Test name
Test status
Simulation time 522922081 ps
CPU time 4.4 seconds
Started Aug 01 06:00:25 PM PDT 24
Finished Aug 01 06:01:00 PM PDT 24
Peak memory 242076 kb
Host smart-bf395c3a-72ab-4358-a4d8-cf175fdaa7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25294309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.25294309
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.2605178201
Short name T158
Test name
Test status
Simulation time 3571369928 ps
CPU time 30.01 seconds
Started Aug 01 06:00:20 PM PDT 24
Finished Aug 01 06:01:26 PM PDT 24
Peak memory 244388 kb
Host smart-3e1215f1-8472-4d00-af28-3d442d4b0f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605178201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2605178201
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.1430819552
Short name T171
Test name
Test status
Simulation time 363635789 ps
CPU time 12.51 seconds
Started Aug 01 06:00:20 PM PDT 24
Finished Aug 01 06:01:08 PM PDT 24
Peak memory 241928 kb
Host smart-7bee5694-95b4-4449-91fb-c53f6ac3fe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430819552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1430819552
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.3040486049
Short name T803
Test name
Test status
Simulation time 126277564 ps
CPU time 5.34 seconds
Started Aug 01 06:00:19 PM PDT 24
Finished Aug 01 06:01:01 PM PDT 24
Peak memory 241896 kb
Host smart-dd50d014-96b6-4b86-8ded-99c95084b34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040486049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.3040486049
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.907704658
Short name T617
Test name
Test status
Simulation time 2747488315 ps
CPU time 6.22 seconds
Started Aug 01 06:00:21 PM PDT 24
Finished Aug 01 06:01:01 PM PDT 24
Peak memory 241964 kb
Host smart-9222774e-d756-4d2b-8646-bfec92b166b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=907704658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.907704658
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.3580763829
Short name T1171
Test name
Test status
Simulation time 194501110 ps
CPU time 4.71 seconds
Started Aug 01 06:00:21 PM PDT 24
Finished Aug 01 06:01:00 PM PDT 24
Peak memory 241772 kb
Host smart-d185d854-5449-4625-8e34-8d81113e7f15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580763829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.3580763829
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.415980549
Short name T665
Test name
Test status
Simulation time 327370142 ps
CPU time 10.63 seconds
Started Aug 01 06:00:23 PM PDT 24
Finished Aug 01 06:01:06 PM PDT 24
Peak memory 241952 kb
Host smart-4c2b5f8b-e317-4c45-8110-df69bd5d3136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415980549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.415980549
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.2726393397
Short name T791
Test name
Test status
Simulation time 21617825872 ps
CPU time 213.84 seconds
Started Aug 01 06:00:22 PM PDT 24
Finished Aug 01 06:04:29 PM PDT 24
Peak memory 283644 kb
Host smart-67ba511c-991c-40a5-bc96-9dd638d67a00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726393397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.2726393397
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.934097704
Short name T223
Test name
Test status
Simulation time 403735226171 ps
CPU time 563.8 seconds
Started Aug 01 06:00:21 PM PDT 24
Finished Aug 01 06:10:19 PM PDT 24
Peak memory 261832 kb
Host smart-d5e6464e-ad9a-424e-b847-68b83a308873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934097704 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.934097704
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.2545108479
Short name T732
Test name
Test status
Simulation time 9335078765 ps
CPU time 46.19 seconds
Started Aug 01 06:00:16 PM PDT 24
Finished Aug 01 06:01:41 PM PDT 24
Peak memory 241992 kb
Host smart-e17d0495-1ae1-42a3-8d38-984a9f1d573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545108479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.2545108479
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.313231547
Short name T290
Test name
Test status
Simulation time 61211677 ps
CPU time 1.73 seconds
Started Aug 01 06:00:38 PM PDT 24
Finished Aug 01 06:00:57 PM PDT 24
Peak memory 240392 kb
Host smart-d3bf0b22-c7d5-4dad-9ad1-e9c0306853bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313231547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.313231547
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.272123006
Short name T108
Test name
Test status
Simulation time 4153091799 ps
CPU time 7.61 seconds
Started Aug 01 06:00:41 PM PDT 24
Finished Aug 01 06:01:03 PM PDT 24
Peak memory 241908 kb
Host smart-d76f2243-019a-4b0c-abf4-ce6cfdd4542f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272123006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.272123006
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.3340239444
Short name T673
Test name
Test status
Simulation time 1116287275 ps
CPU time 32.01 seconds
Started Aug 01 06:00:41 PM PDT 24
Finished Aug 01 06:01:28 PM PDT 24
Peak memory 244108 kb
Host smart-2947f387-026c-4f32-bd9a-c1dd2eafbed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340239444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.3340239444
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.1960139575
Short name T1035
Test name
Test status
Simulation time 1098109623 ps
CPU time 28.03 seconds
Started Aug 01 06:00:38 PM PDT 24
Finished Aug 01 06:01:23 PM PDT 24
Peak memory 248592 kb
Host smart-e93fa874-ae0d-4c2e-973f-51ef6c98306c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960139575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.1960139575
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.120827924
Short name T971
Test name
Test status
Simulation time 508271612 ps
CPU time 5.41 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:01:01 PM PDT 24
Peak memory 241920 kb
Host smart-e67abec2-4948-4035-ab53-ebbeb59f8f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120827924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.120827924
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.4181050100
Short name T536
Test name
Test status
Simulation time 926710626 ps
CPU time 25.92 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:01:21 PM PDT 24
Peak memory 243940 kb
Host smart-408f55ff-a28c-45d4-87d3-e728d263849c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181050100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.4181050100
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.443931877
Short name T1126
Test name
Test status
Simulation time 7202096616 ps
CPU time 19.84 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:01:15 PM PDT 24
Peak memory 248672 kb
Host smart-6671f80f-4199-4b11-aeb3-59901bc773c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443931877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.443931877
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.959358140
Short name T730
Test name
Test status
Simulation time 397085216 ps
CPU time 5.44 seconds
Started Aug 01 06:00:27 PM PDT 24
Finished Aug 01 06:01:01 PM PDT 24
Peak memory 241912 kb
Host smart-a478d212-b980-4bee-b443-46945b55bec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959358140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.959358140
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.3280828938
Short name T933
Test name
Test status
Simulation time 144655058 ps
CPU time 5.74 seconds
Started Aug 01 06:00:39 PM PDT 24
Finished Aug 01 06:01:01 PM PDT 24
Peak memory 248276 kb
Host smart-3f98481e-1f00-4d66-9e01-9e4ef4667d3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3280828938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.3280828938
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.3115213957
Short name T173
Test name
Test status
Simulation time 470984387 ps
CPU time 8 seconds
Started Aug 01 06:00:28 PM PDT 24
Finished Aug 01 06:01:04 PM PDT 24
Peak memory 241920 kb
Host smart-e82fc329-6b9d-44ba-86cd-037adb381eeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3115213957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3115213957
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.2479653229
Short name T517
Test name
Test status
Simulation time 301677292 ps
CPU time 4.91 seconds
Started Aug 01 06:00:43 PM PDT 24
Finished Aug 01 06:01:00 PM PDT 24
Peak memory 241924 kb
Host smart-96dbd8eb-f4e2-43a0-b715-dd98d91425bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479653229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.2479653229
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.3720633708
Short name T570
Test name
Test status
Simulation time 8430786145 ps
CPU time 114.53 seconds
Started Aug 01 06:00:27 PM PDT 24
Finished Aug 01 06:02:50 PM PDT 24
Peak memory 257912 kb
Host smart-79a1a1ff-9588-40cc-9de7-693220f35856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720633708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.3720633708
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.3733079842
Short name T11
Test name
Test status
Simulation time 532607346766 ps
CPU time 2580.64 seconds
Started Aug 01 06:01:00 PM PDT 24
Finished Aug 01 06:44:01 PM PDT 24
Peak memory 409136 kb
Host smart-a1c6ac7e-0d8f-4c19-82c4-6eb483e43287
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733079842 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.3733079842
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.3954158853
Short name T1014
Test name
Test status
Simulation time 5769356060 ps
CPU time 28.93 seconds
Started Aug 01 06:00:42 PM PDT 24
Finished Aug 01 06:01:25 PM PDT 24
Peak memory 242128 kb
Host smart-13d7fedb-7fc0-4c92-b734-29d4ba838456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954158853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.3954158853
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.2160533658
Short name T794
Test name
Test status
Simulation time 81985444 ps
CPU time 1.61 seconds
Started Aug 01 06:00:30 PM PDT 24
Finished Aug 01 06:00:57 PM PDT 24
Peak memory 240320 kb
Host smart-2a86b9ee-b976-45d2-93bc-5ffd6e3fece3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160533658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.2160533658
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.3495796553
Short name T1055
Test name
Test status
Simulation time 1177307417 ps
CPU time 18.05 seconds
Started Aug 01 06:00:42 PM PDT 24
Finished Aug 01 06:01:14 PM PDT 24
Peak memory 248528 kb
Host smart-03f90e7c-42f8-4436-9599-d0aca94be04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495796553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.3495796553
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.2908332800
Short name T99
Test name
Test status
Simulation time 369542389 ps
CPU time 24.7 seconds
Started Aug 01 06:00:28 PM PDT 24
Finished Aug 01 06:01:20 PM PDT 24
Peak memory 242252 kb
Host smart-7651d475-fe63-4ef6-83dd-8791976690ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908332800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.2908332800
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.964683661
Short name T996
Test name
Test status
Simulation time 916737754 ps
CPU time 17.73 seconds
Started Aug 01 06:00:39 PM PDT 24
Finished Aug 01 06:01:13 PM PDT 24
Peak memory 242036 kb
Host smart-5f56f990-cd45-4447-837b-6685087cf2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964683661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.964683661
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.633283640
Short name T722
Test name
Test status
Simulation time 497189000 ps
CPU time 4.2 seconds
Started Aug 01 06:00:41 PM PDT 24
Finished Aug 01 06:01:00 PM PDT 24
Peak memory 242416 kb
Host smart-a7af6c4e-539c-493c-8bf3-891160d0ad2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633283640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.633283640
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.2988649514
Short name T462
Test name
Test status
Simulation time 4692366461 ps
CPU time 29.39 seconds
Started Aug 01 06:00:29 PM PDT 24
Finished Aug 01 06:01:25 PM PDT 24
Peak memory 248564 kb
Host smart-4a81074c-193b-4198-a5f9-03dc7538f25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988649514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.2988649514
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.2064326981
Short name T832
Test name
Test status
Simulation time 324573468 ps
CPU time 12.34 seconds
Started Aug 01 06:00:42 PM PDT 24
Finished Aug 01 06:01:08 PM PDT 24
Peak memory 248612 kb
Host smart-184dd28a-65f6-4f2d-bf03-ba0feaaf8c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064326981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.2064326981
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.3060860495
Short name T461
Test name
Test status
Simulation time 3926168176 ps
CPU time 9.73 seconds
Started Aug 01 06:00:30 PM PDT 24
Finished Aug 01 06:01:05 PM PDT 24
Peak memory 241852 kb
Host smart-0ee4870a-be38-4e6e-8af7-ba81607834b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060860495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.3060860495
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.423952403
Short name T723
Test name
Test status
Simulation time 3827645882 ps
CPU time 10.52 seconds
Started Aug 01 06:01:00 PM PDT 24
Finished Aug 01 06:01:10 PM PDT 24
Peak memory 242200 kb
Host smart-81fc838d-40d9-4623-b0d8-6df2b5ec6cc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=423952403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.423952403
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.2149766811
Short name T737
Test name
Test status
Simulation time 336822149 ps
CPU time 6.17 seconds
Started Aug 01 06:01:01 PM PDT 24
Finished Aug 01 06:01:07 PM PDT 24
Peak memory 242044 kb
Host smart-8c3c00ae-30f7-4813-be40-bd60a8670364
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149766811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.2149766811
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.2029291861
Short name T1042
Test name
Test status
Simulation time 1160890489 ps
CPU time 12.1 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:01:07 PM PDT 24
Peak memory 241784 kb
Host smart-8c39944e-742c-4734-a2fa-952e984aebcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029291861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.2029291861
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.2901193001
Short name T573
Test name
Test status
Simulation time 46918553085 ps
CPU time 132.71 seconds
Started Aug 01 06:00:41 PM PDT 24
Finished Aug 01 06:03:08 PM PDT 24
Peak memory 249180 kb
Host smart-7211e5d3-c83a-4618-985e-ae0913853903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901193001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.2901193001
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.823388964
Short name T1104
Test name
Test status
Simulation time 200982532850 ps
CPU time 1272.54 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:22:08 PM PDT 24
Peak memory 277948 kb
Host smart-325b2821-a44a-4544-8142-63b6921503e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823388964 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.823388964
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.1174865965
Short name T491
Test name
Test status
Simulation time 4356057521 ps
CPU time 8.38 seconds
Started Aug 01 06:00:42 PM PDT 24
Finished Aug 01 06:01:04 PM PDT 24
Peak memory 243092 kb
Host smart-55c0dffb-9623-4cf2-9832-6dc0619f6c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174865965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.1174865965
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.2488691222
Short name T400
Test name
Test status
Simulation time 60675009 ps
CPU time 1.85 seconds
Started Aug 01 06:00:42 PM PDT 24
Finished Aug 01 06:00:57 PM PDT 24
Peak memory 240488 kb
Host smart-80ef6d32-7315-4f30-a16a-c1bd00c379b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488691222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.2488691222
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.3625460078
Short name T52
Test name
Test status
Simulation time 9479136921 ps
CPU time 24.09 seconds
Started Aug 01 06:01:06 PM PDT 24
Finished Aug 01 06:01:30 PM PDT 24
Peak memory 242824 kb
Host smart-7f7c2280-b665-4f14-9b21-d945415201d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625460078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.3625460078
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.4076919616
Short name T1071
Test name
Test status
Simulation time 15171789491 ps
CPU time 30.37 seconds
Started Aug 01 06:01:01 PM PDT 24
Finished Aug 01 06:01:32 PM PDT 24
Peak memory 247116 kb
Host smart-aeb23791-c186-444a-9c87-87c5e56013ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076919616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.4076919616
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.2439122329
Short name T1170
Test name
Test status
Simulation time 991699009 ps
CPU time 17.32 seconds
Started Aug 01 06:01:00 PM PDT 24
Finished Aug 01 06:01:18 PM PDT 24
Peak memory 241892 kb
Host smart-a9c066ca-274d-4a46-8040-3fd7aec2401e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439122329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2439122329
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.3709092510
Short name T1094
Test name
Test status
Simulation time 587100981 ps
CPU time 4.97 seconds
Started Aug 01 06:00:28 PM PDT 24
Finished Aug 01 06:01:00 PM PDT 24
Peak memory 242260 kb
Host smart-baa0b97a-2e98-420e-936a-b57a090f3adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709092510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.3709092510
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.2735895012
Short name T704
Test name
Test status
Simulation time 3029470586 ps
CPU time 25.7 seconds
Started Aug 01 06:00:29 PM PDT 24
Finished Aug 01 06:01:21 PM PDT 24
Peak memory 244556 kb
Host smart-52084126-f87b-4763-a4c3-7972693e5358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735895012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2735895012
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.4163223902
Short name T10
Test name
Test status
Simulation time 837398631 ps
CPU time 7.46 seconds
Started Aug 01 06:01:00 PM PDT 24
Finished Aug 01 06:01:08 PM PDT 24
Peak memory 248504 kb
Host smart-727d23ac-eba4-48c3-9e3a-9b9d827fbaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163223902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.4163223902
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.1970575851
Short name T206
Test name
Test status
Simulation time 247507273 ps
CPU time 6.26 seconds
Started Aug 01 06:00:29 PM PDT 24
Finished Aug 01 06:01:02 PM PDT 24
Peak memory 242364 kb
Host smart-6cd0442b-2c05-4fa8-a5b5-fb24b2283128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970575851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.1970575851
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.1081193055
Short name T802
Test name
Test status
Simulation time 240882431 ps
CPU time 8.66 seconds
Started Aug 01 06:00:41 PM PDT 24
Finished Aug 01 06:01:04 PM PDT 24
Peak memory 248636 kb
Host smart-92ba4ed9-1021-4802-acc5-a9d19ac79687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1081193055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.1081193055
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.3979204164
Short name T1148
Test name
Test status
Simulation time 652641535 ps
CPU time 10.91 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:01:06 PM PDT 24
Peak memory 242216 kb
Host smart-08eace1c-9f50-4e62-949e-c705d8a30a2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979204164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3979204164
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.4095439227
Short name T393
Test name
Test status
Simulation time 356818981 ps
CPU time 5.28 seconds
Started Aug 01 06:00:42 PM PDT 24
Finished Aug 01 06:01:01 PM PDT 24
Peak memory 241928 kb
Host smart-930ad835-358b-4979-a60f-b8ad8c067d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095439227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.4095439227
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.1277290406
Short name T506
Test name
Test status
Simulation time 75060064319 ps
CPU time 138.53 seconds
Started Aug 01 06:00:42 PM PDT 24
Finished Aug 01 06:03:14 PM PDT 24
Peak memory 262620 kb
Host smart-e03ecdcf-b148-4ae6-ba55-75964c050acf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277290406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.1277290406
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.3742208172
Short name T899
Test name
Test status
Simulation time 3433159719 ps
CPU time 21.7 seconds
Started Aug 01 06:00:41 PM PDT 24
Finished Aug 01 06:01:17 PM PDT 24
Peak memory 242400 kb
Host smart-3e76640f-b83f-4370-a6a3-66608a805ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742208172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.3742208172
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.1007038865
Short name T949
Test name
Test status
Simulation time 109189769 ps
CPU time 1.83 seconds
Started Aug 01 06:00:38 PM PDT 24
Finished Aug 01 06:00:57 PM PDT 24
Peak memory 240756 kb
Host smart-2d0dcb7c-7f4f-4975-9350-725da6c0c9de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007038865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.1007038865
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.2331102758
Short name T675
Test name
Test status
Simulation time 743887889 ps
CPU time 25.25 seconds
Started Aug 01 06:00:42 PM PDT 24
Finished Aug 01 06:01:21 PM PDT 24
Peak memory 241900 kb
Host smart-885f27fe-f0ea-4b88-a3aa-7ab75eec53f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331102758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.2331102758
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.3513456968
Short name T845
Test name
Test status
Simulation time 601300823 ps
CPU time 6.65 seconds
Started Aug 01 06:01:00 PM PDT 24
Finished Aug 01 06:01:07 PM PDT 24
Peak memory 242260 kb
Host smart-05ca4094-1f19-48bb-bcd8-ab1e44a27105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513456968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.3513456968
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.402995597
Short name T1043
Test name
Test status
Simulation time 398671259 ps
CPU time 4.73 seconds
Started Aug 01 06:00:29 PM PDT 24
Finished Aug 01 06:01:00 PM PDT 24
Peak memory 242204 kb
Host smart-8e7f3a5a-fdc4-4796-8911-348536565165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402995597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.402995597
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.4102698939
Short name T979
Test name
Test status
Simulation time 3251512604 ps
CPU time 16.75 seconds
Started Aug 01 06:01:00 PM PDT 24
Finished Aug 01 06:01:17 PM PDT 24
Peak memory 246180 kb
Host smart-ce48762c-6d22-4d4f-8f87-ed504ef3f3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102698939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.4102698939
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.3368262752
Short name T926
Test name
Test status
Simulation time 525240093 ps
CPU time 16.79 seconds
Started Aug 01 06:00:39 PM PDT 24
Finished Aug 01 06:01:12 PM PDT 24
Peak memory 242124 kb
Host smart-3a5fb4c6-6095-4da4-9cac-e0028330766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368262752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.3368262752
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.1306601183
Short name T1096
Test name
Test status
Simulation time 204377388 ps
CPU time 4.19 seconds
Started Aug 01 06:00:28 PM PDT 24
Finished Aug 01 06:01:00 PM PDT 24
Peak memory 241928 kb
Host smart-3ee6a9bf-1242-4073-98ee-08f136f5bf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306601183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.1306601183
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.3082060774
Short name T749
Test name
Test status
Simulation time 863735490 ps
CPU time 6.25 seconds
Started Aug 01 06:00:27 PM PDT 24
Finished Aug 01 06:01:02 PM PDT 24
Peak memory 241900 kb
Host smart-0b2616dc-2751-480d-85ca-148919ee506a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3082060774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.3082060774
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.1172526781
Short name T229
Test name
Test status
Simulation time 350527910 ps
CPU time 7.8 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:01:03 PM PDT 24
Peak memory 241976 kb
Host smart-62f2c490-9983-4c7a-acf7-d89f171d6827
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172526781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.1172526781
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.1505451581
Short name T689
Test name
Test status
Simulation time 758643700 ps
CPU time 10.68 seconds
Started Aug 01 06:00:30 PM PDT 24
Finished Aug 01 06:01:06 PM PDT 24
Peak memory 242084 kb
Host smart-89ade406-377a-4379-a857-460d69a05fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505451581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.1505451581
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.374583563
Short name T1086
Test name
Test status
Simulation time 171596770 ps
CPU time 3.53 seconds
Started Aug 01 06:00:29 PM PDT 24
Finished Aug 01 06:00:59 PM PDT 24
Peak memory 242056 kb
Host smart-75784acb-46a4-492d-979b-296e6199e73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374583563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.374583563
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.91167555
Short name T440
Test name
Test status
Simulation time 309588687 ps
CPU time 2.05 seconds
Started Aug 01 06:00:39 PM PDT 24
Finished Aug 01 06:00:57 PM PDT 24
Peak memory 240668 kb
Host smart-1fc1314e-250e-4b53-acc7-22abc26058fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91167555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.91167555
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.3860769156
Short name T1044
Test name
Test status
Simulation time 249228057 ps
CPU time 5.47 seconds
Started Aug 01 06:00:43 PM PDT 24
Finished Aug 01 06:01:01 PM PDT 24
Peak memory 248496 kb
Host smart-fe18bc78-276b-4f48-8325-4af6a778b5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860769156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.3860769156
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.2278499901
Short name T1011
Test name
Test status
Simulation time 1113186815 ps
CPU time 26.23 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:01:22 PM PDT 24
Peak memory 242280 kb
Host smart-15363044-a742-4e06-90f1-253e6ec12fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278499901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2278499901
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.1856118928
Short name T511
Test name
Test status
Simulation time 23892951925 ps
CPU time 58.84 seconds
Started Aug 01 06:00:39 PM PDT 24
Finished Aug 01 06:01:54 PM PDT 24
Peak memory 243248 kb
Host smart-e493ddf8-7b83-40c7-b442-377d06a4756f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856118928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.1856118928
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.2726484861
Short name T952
Test name
Test status
Simulation time 541662881 ps
CPU time 4 seconds
Started Aug 01 06:00:39 PM PDT 24
Finished Aug 01 06:00:59 PM PDT 24
Peak memory 242200 kb
Host smart-2ae3220a-565b-4591-9670-a177c7d81ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726484861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2726484861
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.107883679
Short name T672
Test name
Test status
Simulation time 5476453660 ps
CPU time 41.24 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:01:37 PM PDT 24
Peak memory 256808 kb
Host smart-4aaf3db9-4f37-49d1-89eb-cabd89c43b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107883679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.107883679
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.1399531924
Short name T1053
Test name
Test status
Simulation time 1304564389 ps
CPU time 28.63 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:01:24 PM PDT 24
Peak memory 242376 kb
Host smart-1dd350cf-772e-4cf6-8abc-62d32647af70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399531924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1399531924
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.1668898228
Short name T935
Test name
Test status
Simulation time 126544555 ps
CPU time 4.53 seconds
Started Aug 01 06:00:39 PM PDT 24
Finished Aug 01 06:01:00 PM PDT 24
Peak memory 241728 kb
Host smart-f3eb16ea-64b2-4876-8052-cd83b9e62840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668898228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1668898228
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.1425388372
Short name T449
Test name
Test status
Simulation time 499481422 ps
CPU time 9.39 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:01:05 PM PDT 24
Peak memory 242140 kb
Host smart-d1b67a82-7b4c-49c2-840c-e1924cbfa2de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425388372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.1425388372
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.478001563
Short name T1083
Test name
Test status
Simulation time 671527308 ps
CPU time 13.48 seconds
Started Aug 01 06:00:38 PM PDT 24
Finished Aug 01 06:01:09 PM PDT 24
Peak memory 242196 kb
Host smart-37a89de5-4a07-4a8f-b17c-1676d5787a6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=478001563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.478001563
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.553433869
Short name T890
Test name
Test status
Simulation time 378530149 ps
CPU time 6.82 seconds
Started Aug 01 06:00:39 PM PDT 24
Finished Aug 01 06:01:02 PM PDT 24
Peak memory 248580 kb
Host smart-ddfa1fa3-cb28-4c4d-acef-6064b3c58b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553433869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.553433869
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.3266623266
Short name T871
Test name
Test status
Simulation time 4695950357 ps
CPU time 105.94 seconds
Started Aug 01 06:00:39 PM PDT 24
Finished Aug 01 06:02:41 PM PDT 24
Peak memory 245752 kb
Host smart-bb3a8ca3-a50f-483c-8199-7a423b1a46cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266623266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.3266623266
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.3697107886
Short name T326
Test name
Test status
Simulation time 65011814594 ps
CPU time 1446.24 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:25:02 PM PDT 24
Peak memory 286304 kb
Host smart-34c826f4-acfd-416b-9532-f282c653a06a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697107886 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.3697107886
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.1916055315
Short name T913
Test name
Test status
Simulation time 721362988 ps
CPU time 13.38 seconds
Started Aug 01 06:01:05 PM PDT 24
Finished Aug 01 06:01:18 PM PDT 24
Peak memory 241888 kb
Host smart-ca6fc1bd-856a-48be-bbc4-8565ed1c0df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916055315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.1916055315
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.958769369
Short name T199
Test name
Test status
Simulation time 98437207 ps
CPU time 1.94 seconds
Started Aug 01 06:00:41 PM PDT 24
Finished Aug 01 06:00:57 PM PDT 24
Peak memory 240376 kb
Host smart-b54248b2-d936-40bd-a0ad-631e5d51fa3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958769369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.958769369
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.4219203757
Short name T924
Test name
Test status
Simulation time 1610357250 ps
CPU time 19.23 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:01:15 PM PDT 24
Peak memory 248396 kb
Host smart-1be32599-47db-4c21-8b41-b087ca1034ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219203757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.4219203757
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.2915606801
Short name T438
Test name
Test status
Simulation time 1559046493 ps
CPU time 34.18 seconds
Started Aug 01 06:00:38 PM PDT 24
Finished Aug 01 06:01:30 PM PDT 24
Peak memory 241904 kb
Host smart-c5d9e64d-7bb7-445c-bf8f-d0eeda4e9a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915606801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.2915606801
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.9901231
Short name T1050
Test name
Test status
Simulation time 12895091418 ps
CPU time 34.13 seconds
Started Aug 01 06:00:37 PM PDT 24
Finished Aug 01 06:01:29 PM PDT 24
Peak memory 242252 kb
Host smart-f9be7f18-debf-4a7d-9e5d-c0bf71d2f43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9901231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.9901231
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.2147332196
Short name T629
Test name
Test status
Simulation time 201637513 ps
CPU time 4.2 seconds
Started Aug 01 06:00:39 PM PDT 24
Finished Aug 01 06:00:59 PM PDT 24
Peak memory 242416 kb
Host smart-9126c369-e5b8-43d2-b10b-cc9b7fe65cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147332196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.2147332196
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.3065461151
Short name T1189
Test name
Test status
Simulation time 5799315964 ps
CPU time 14.86 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:01:10 PM PDT 24
Peak memory 242784 kb
Host smart-5de8b9d0-3a8c-416f-b0a0-81dfa0aa114f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065461151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.3065461151
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.528183596
Short name T378
Test name
Test status
Simulation time 11783685078 ps
CPU time 35.54 seconds
Started Aug 01 06:01:05 PM PDT 24
Finished Aug 01 06:01:41 PM PDT 24
Peak memory 243452 kb
Host smart-513059b0-2181-40b9-aa09-46b7e3479705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528183596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.528183596
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.1188748870
Short name T719
Test name
Test status
Simulation time 1548734382 ps
CPU time 18.53 seconds
Started Aug 01 06:00:38 PM PDT 24
Finished Aug 01 06:01:14 PM PDT 24
Peak memory 248532 kb
Host smart-e9729fa4-26fa-4644-8c0c-c3d80177cdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188748870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.1188748870
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.746945606
Short name T810
Test name
Test status
Simulation time 280046613 ps
CPU time 5.09 seconds
Started Aug 01 06:01:04 PM PDT 24
Finished Aug 01 06:01:09 PM PDT 24
Peak memory 248480 kb
Host smart-5e42da11-6a3c-4c84-a330-c63c55dad9d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=746945606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.746945606
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.854866314
Short name T362
Test name
Test status
Simulation time 179229176 ps
CPU time 5.93 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:01:01 PM PDT 24
Peak memory 241996 kb
Host smart-7f3289d7-fb69-4406-920f-4317f3267977
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854866314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.854866314
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.54735028
Short name T994
Test name
Test status
Simulation time 848646179 ps
CPU time 7.71 seconds
Started Aug 01 06:00:39 PM PDT 24
Finished Aug 01 06:01:03 PM PDT 24
Peak memory 242032 kb
Host smart-da5474c0-6c62-4ecc-aab4-31f3f6c1c58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54735028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.54735028
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.19132613
Short name T1040
Test name
Test status
Simulation time 211318756149 ps
CPU time 471.79 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:08:47 PM PDT 24
Peak memory 275612 kb
Host smart-ef3eda49-bd78-4cc6-ab29-ca0e5dd86abe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19132613 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.19132613
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.2179628086
Short name T441
Test name
Test status
Simulation time 445700333 ps
CPU time 8.39 seconds
Started Aug 01 06:01:05 PM PDT 24
Finished Aug 01 06:01:14 PM PDT 24
Peak memory 242024 kb
Host smart-d3b4ead4-e31a-4882-be7f-e71637582530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179628086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.2179628086
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.1765070566
Short name T566
Test name
Test status
Simulation time 120087682 ps
CPU time 1.88 seconds
Started Aug 01 06:01:02 PM PDT 24
Finished Aug 01 06:01:04 PM PDT 24
Peak memory 240712 kb
Host smart-aeb9fea5-b9a8-434d-8768-7a1431ff8014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765070566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.1765070566
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.3998822031
Short name T735
Test name
Test status
Simulation time 1356923204 ps
CPU time 22.74 seconds
Started Aug 01 06:00:39 PM PDT 24
Finished Aug 01 06:01:18 PM PDT 24
Peak memory 241892 kb
Host smart-6bb55570-6caf-48a8-a5f9-d1abb2798c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998822031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.3998822031
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.2965316402
Short name T1129
Test name
Test status
Simulation time 3891146023 ps
CPU time 8.74 seconds
Started Aug 01 06:00:41 PM PDT 24
Finished Aug 01 06:01:04 PM PDT 24
Peak memory 242292 kb
Host smart-d913dbdf-50f9-433d-b163-51cd0047749b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965316402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.2965316402
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.2312142966
Short name T67
Test name
Test status
Simulation time 309436110 ps
CPU time 4.17 seconds
Started Aug 01 06:00:40 PM PDT 24
Finished Aug 01 06:00:59 PM PDT 24
Peak memory 242144 kb
Host smart-ddd7fa71-0682-405e-9057-48e2036d2dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312142966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2312142966
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.3043948430
Short name T185
Test name
Test status
Simulation time 623691205 ps
CPU time 21.85 seconds
Started Aug 01 06:00:38 PM PDT 24
Finished Aug 01 06:01:17 PM PDT 24
Peak memory 243560 kb
Host smart-86c4f059-34f7-4821-b507-45dcb0a412dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043948430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.3043948430
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.2737135123
Short name T774
Test name
Test status
Simulation time 3314544545 ps
CPU time 34.81 seconds
Started Aug 01 06:00:39 PM PDT 24
Finished Aug 01 06:01:30 PM PDT 24
Peak memory 242252 kb
Host smart-284abe91-3a01-4a88-bd4c-a266bc6e3b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737135123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.2737135123
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.4179799439
Short name T983
Test name
Test status
Simulation time 686606750 ps
CPU time 22.27 seconds
Started Aug 01 06:00:44 PM PDT 24
Finished Aug 01 06:01:18 PM PDT 24
Peak memory 242256 kb
Host smart-caaef0f7-4d63-46b2-8219-e88cc3af1b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179799439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.4179799439
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.1524884803
Short name T1064
Test name
Test status
Simulation time 1649663260 ps
CPU time 24.19 seconds
Started Aug 01 06:00:44 PM PDT 24
Finished Aug 01 06:01:20 PM PDT 24
Peak memory 241900 kb
Host smart-f408c4d2-ad0f-459c-b3e9-61c610ffbd4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1524884803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.1524884803
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.4154228186
Short name T96
Test name
Test status
Simulation time 240151290 ps
CPU time 6.74 seconds
Started Aug 01 06:00:44 PM PDT 24
Finished Aug 01 06:01:02 PM PDT 24
Peak memory 241880 kb
Host smart-5da067d7-28e0-4531-a38a-58950aeff8ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4154228186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.4154228186
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.1760956023
Short name T956
Test name
Test status
Simulation time 2518448450 ps
CPU time 8.31 seconds
Started Aug 01 06:01:04 PM PDT 24
Finished Aug 01 06:01:12 PM PDT 24
Peak memory 241972 kb
Host smart-ce7c4b23-632d-4c52-aa57-a17066c9ecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760956023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.1760956023
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.1501033165
Short name T447
Test name
Test status
Simulation time 1472835448 ps
CPU time 22.45 seconds
Started Aug 01 06:00:44 PM PDT 24
Finished Aug 01 06:01:18 PM PDT 24
Peak memory 241884 kb
Host smart-71a130da-d9a7-45a0-9236-0773acabb185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501033165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1501033165
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.913263330
Short name T1027
Test name
Test status
Simulation time 56977658 ps
CPU time 1.75 seconds
Started Aug 01 06:01:24 PM PDT 24
Finished Aug 01 06:01:25 PM PDT 24
Peak memory 240432 kb
Host smart-9fe5f582-382f-4dc6-b220-fc04b54b6c6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913263330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.913263330
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.1288785759
Short name T74
Test name
Test status
Simulation time 961787754 ps
CPU time 20.68 seconds
Started Aug 01 06:01:10 PM PDT 24
Finished Aug 01 06:01:31 PM PDT 24
Peak memory 242264 kb
Host smart-ce97b66c-cc82-4383-9226-5bc0018cf6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288785759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.1288785759
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.4027175225
Short name T904
Test name
Test status
Simulation time 1297962213 ps
CPU time 12.01 seconds
Started Aug 01 06:01:11 PM PDT 24
Finished Aug 01 06:01:23 PM PDT 24
Peak memory 241916 kb
Host smart-c1cc901b-f9b9-430b-9a85-b60f0ab99ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027175225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.4027175225
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.2084137894
Short name T1029
Test name
Test status
Simulation time 811292460 ps
CPU time 23.45 seconds
Started Aug 01 06:01:13 PM PDT 24
Finished Aug 01 06:01:36 PM PDT 24
Peak memory 242496 kb
Host smart-96e18479-1cde-4331-87ea-196ffdcb126b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084137894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.2084137894
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.3386691739
Short name T836
Test name
Test status
Simulation time 202384417 ps
CPU time 4.54 seconds
Started Aug 01 06:00:58 PM PDT 24
Finished Aug 01 06:01:02 PM PDT 24
Peak memory 241952 kb
Host smart-aa0de992-14ef-4448-87b7-80ffc4dc71c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386691739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.3386691739
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.3951129020
Short name T724
Test name
Test status
Simulation time 5248766692 ps
CPU time 48.41 seconds
Started Aug 01 06:01:11 PM PDT 24
Finished Aug 01 06:01:59 PM PDT 24
Peak memory 256752 kb
Host smart-444d4bc7-5001-47be-b7c8-207d3b44e074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951129020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.3951129020
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.3976049457
Short name T514
Test name
Test status
Simulation time 1241473058 ps
CPU time 32.74 seconds
Started Aug 01 06:01:10 PM PDT 24
Finished Aug 01 06:01:43 PM PDT 24
Peak memory 242268 kb
Host smart-991c25c7-ab13-4489-8056-5fbac4f444b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976049457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.3976049457
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.3321381786
Short name T238
Test name
Test status
Simulation time 524429501 ps
CPU time 7.61 seconds
Started Aug 01 06:01:08 PM PDT 24
Finished Aug 01 06:01:15 PM PDT 24
Peak memory 241948 kb
Host smart-72b86ed0-2efd-41ac-9876-fbc958faa33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321381786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3321381786
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.3482306625
Short name T965
Test name
Test status
Simulation time 1218232405 ps
CPU time 27.92 seconds
Started Aug 01 06:00:58 PM PDT 24
Finished Aug 01 06:01:26 PM PDT 24
Peak memory 242496 kb
Host smart-09ae1639-26f2-4fda-9fa6-372473b54bc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3482306625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.3482306625
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.346398745
Short name T516
Test name
Test status
Simulation time 213602103 ps
CPU time 3.24 seconds
Started Aug 01 06:01:10 PM PDT 24
Finished Aug 01 06:01:14 PM PDT 24
Peak memory 248352 kb
Host smart-6a4ba480-c793-4ebc-8311-eb67f1bbd7b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=346398745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.346398745
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.170905456
Short name T607
Test name
Test status
Simulation time 1375499064 ps
CPU time 16.23 seconds
Started Aug 01 06:00:59 PM PDT 24
Finished Aug 01 06:01:15 PM PDT 24
Peak memory 241960 kb
Host smart-79ef2ec6-b8f8-4f49-9e99-bcf937b714f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170905456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.170905456
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.623342267
Short name T103
Test name
Test status
Simulation time 550137622 ps
CPU time 5.9 seconds
Started Aug 01 06:01:10 PM PDT 24
Finished Aug 01 06:01:16 PM PDT 24
Peak memory 241984 kb
Host smart-85550631-71a3-4548-87ac-29d06f8f6f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623342267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.623342267
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.3010189193
Short name T268
Test name
Test status
Simulation time 126770252 ps
CPU time 1.9 seconds
Started Aug 01 05:58:05 PM PDT 24
Finished Aug 01 05:58:07 PM PDT 24
Peak memory 240480 kb
Host smart-ec39a6f1-2111-4d62-97d1-d149d4ab7f48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010189193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.3010189193
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.3454717665
Short name T804
Test name
Test status
Simulation time 5624693858 ps
CPU time 24.5 seconds
Started Aug 01 05:57:56 PM PDT 24
Finished Aug 01 05:58:21 PM PDT 24
Peak memory 242056 kb
Host smart-b06155d1-c957-45b6-b6d7-871c95940c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454717665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.3454717665
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.3428687535
Short name T69
Test name
Test status
Simulation time 509115512 ps
CPU time 19.9 seconds
Started Aug 01 05:57:59 PM PDT 24
Finished Aug 01 05:58:19 PM PDT 24
Peak memory 244124 kb
Host smart-4fc94ad7-4a32-40a4-90a0-0ffa7c132b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428687535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.3428687535
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.736066790
Short name T418
Test name
Test status
Simulation time 5892709373 ps
CPU time 29 seconds
Started Aug 01 05:57:53 PM PDT 24
Finished Aug 01 05:58:23 PM PDT 24
Peak memory 241836 kb
Host smart-e674af5b-076a-41d8-93f8-5c704a505447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736066790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.736066790
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.3799503066
Short name T92
Test name
Test status
Simulation time 2531050269 ps
CPU time 14.98 seconds
Started Aug 01 05:57:58 PM PDT 24
Finished Aug 01 05:58:13 PM PDT 24
Peak memory 242440 kb
Host smart-862054ef-fc79-4e9a-b6f4-4276957aeed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799503066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.3799503066
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.2334216911
Short name T427
Test name
Test status
Simulation time 402327114 ps
CPU time 4.39 seconds
Started Aug 01 05:57:55 PM PDT 24
Finished Aug 01 05:58:00 PM PDT 24
Peak memory 241996 kb
Host smart-4fa663e5-2056-48b2-a183-7be64c1dff1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334216911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.2334216911
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.3570677142
Short name T1156
Test name
Test status
Simulation time 1881224964 ps
CPU time 13.51 seconds
Started Aug 01 05:57:56 PM PDT 24
Finished Aug 01 05:58:10 PM PDT 24
Peak memory 248608 kb
Host smart-0bbb0e56-390f-427a-abda-b311e710b63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570677142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.3570677142
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.2526917705
Short name T122
Test name
Test status
Simulation time 5718694853 ps
CPU time 15.43 seconds
Started Aug 01 05:57:53 PM PDT 24
Finished Aug 01 05:58:08 PM PDT 24
Peak memory 248600 kb
Host smart-3c95b062-01c4-4be0-8bc0-a6bb32d6eb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526917705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.2526917705
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.1315925454
Short name T247
Test name
Test status
Simulation time 254361073 ps
CPU time 3.44 seconds
Started Aug 01 05:57:59 PM PDT 24
Finished Aug 01 05:58:02 PM PDT 24
Peak memory 241744 kb
Host smart-6b402a65-e972-4f26-a47c-6eed3c26f58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315925454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.1315925454
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.2726813719
Short name T997
Test name
Test status
Simulation time 676990442 ps
CPU time 11.8 seconds
Started Aug 01 05:57:52 PM PDT 24
Finished Aug 01 05:58:04 PM PDT 24
Peak memory 248644 kb
Host smart-d96247bf-4bcb-4329-8cca-83c29153c2a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726813719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.2726813719
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.1870287169
Short name T361
Test name
Test status
Simulation time 1573706669 ps
CPU time 6.03 seconds
Started Aug 01 05:58:03 PM PDT 24
Finished Aug 01 05:58:09 PM PDT 24
Peak memory 242228 kb
Host smart-a8e98ffe-5bf8-4842-8f3f-cc794663bfcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1870287169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.1870287169
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.2308812973
Short name T1015
Test name
Test status
Simulation time 1131388354 ps
CPU time 6.61 seconds
Started Aug 01 05:57:57 PM PDT 24
Finished Aug 01 05:58:04 PM PDT 24
Peak memory 242180 kb
Host smart-c2cbec1b-5740-429f-b84e-7a551cfc824f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308812973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.2308812973
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.2875677239
Short name T1143
Test name
Test status
Simulation time 46389012105 ps
CPU time 158.4 seconds
Started Aug 01 05:58:02 PM PDT 24
Finished Aug 01 06:00:41 PM PDT 24
Peak memory 256824 kb
Host smart-59bcacb8-3dc7-4ffd-a6b1-49da97c45175
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875677239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
2875677239
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.3754659737
Short name T788
Test name
Test status
Simulation time 97085969020 ps
CPU time 1480.68 seconds
Started Aug 01 05:58:03 PM PDT 24
Finished Aug 01 06:22:44 PM PDT 24
Peak memory 379744 kb
Host smart-89e70f99-0868-4193-aa70-80a974134866
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754659737 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.3754659737
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.813033688
Short name T80
Test name
Test status
Simulation time 446420449 ps
CPU time 13.45 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:17 PM PDT 24
Peak memory 242088 kb
Host smart-71fa42c4-2b68-4273-903d-fa44cfe7ff00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813033688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.813033688
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.130924136
Short name T680
Test name
Test status
Simulation time 540735306 ps
CPU time 4.45 seconds
Started Aug 01 06:01:22 PM PDT 24
Finished Aug 01 06:01:26 PM PDT 24
Peak memory 242140 kb
Host smart-3a920b7d-b906-4875-9b08-ac9ff538d882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130924136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.130924136
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.2535223140
Short name T761
Test name
Test status
Simulation time 537669755 ps
CPU time 10.61 seconds
Started Aug 01 06:01:21 PM PDT 24
Finished Aug 01 06:01:31 PM PDT 24
Peak memory 241900 kb
Host smart-545581c0-12b6-4c44-bbaf-eb9cbce70092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535223140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.2535223140
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.2343313281
Short name T502
Test name
Test status
Simulation time 164926084 ps
CPU time 3.72 seconds
Started Aug 01 06:01:23 PM PDT 24
Finished Aug 01 06:01:26 PM PDT 24
Peak memory 241260 kb
Host smart-5706bcd1-18ff-4849-9e79-977eb3426535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343313281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.2343313281
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.151771673
Short name T620
Test name
Test status
Simulation time 712336696 ps
CPU time 22.81 seconds
Started Aug 01 06:01:23 PM PDT 24
Finished Aug 01 06:01:46 PM PDT 24
Peak memory 241868 kb
Host smart-9cda6d80-ab15-4905-bad7-054130f4e577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151771673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.151771673
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.604898205
Short name T915
Test name
Test status
Simulation time 18596053765 ps
CPU time 580 seconds
Started Aug 01 06:01:21 PM PDT 24
Finished Aug 01 06:11:01 PM PDT 24
Peak memory 338792 kb
Host smart-5fbc2e37-8097-4e10-8318-bcad181f4197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604898205 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.604898205
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.2918821811
Short name T1175
Test name
Test status
Simulation time 1768371221 ps
CPU time 4.2 seconds
Started Aug 01 06:01:23 PM PDT 24
Finished Aug 01 06:01:27 PM PDT 24
Peak memory 240936 kb
Host smart-633c6901-aa0e-4470-a3c1-fefc83a45250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918821811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.2918821811
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.277549215
Short name T771
Test name
Test status
Simulation time 3804891080 ps
CPU time 26.1 seconds
Started Aug 01 06:01:21 PM PDT 24
Finished Aug 01 06:01:47 PM PDT 24
Peak memory 242268 kb
Host smart-7bfb97e7-fb8d-4f27-88ba-73203e0ea920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277549215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.277549215
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.3051064843
Short name T202
Test name
Test status
Simulation time 1813482551 ps
CPU time 3.67 seconds
Started Aug 01 06:01:20 PM PDT 24
Finished Aug 01 06:01:24 PM PDT 24
Peak memory 242400 kb
Host smart-9982235a-5125-491f-b870-a122fe284283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051064843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.3051064843
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.3392681068
Short name T909
Test name
Test status
Simulation time 1744100942 ps
CPU time 8.09 seconds
Started Aug 01 06:01:23 PM PDT 24
Finished Aug 01 06:01:31 PM PDT 24
Peak memory 242016 kb
Host smart-431195b4-c61e-4335-b6ef-41f3607c10e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392681068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.3392681068
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.1704615911
Short name T383
Test name
Test status
Simulation time 87181874794 ps
CPU time 1012.49 seconds
Started Aug 01 06:01:23 PM PDT 24
Finished Aug 01 06:18:16 PM PDT 24
Peak memory 261108 kb
Host smart-756c3ee4-00fb-4e72-b2c5-ef25e1a8b3b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704615911 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.1704615911
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.433219203
Short name T991
Test name
Test status
Simulation time 157417753 ps
CPU time 4.02 seconds
Started Aug 01 06:01:23 PM PDT 24
Finished Aug 01 06:01:28 PM PDT 24
Peak memory 241996 kb
Host smart-05b62bd9-5d2a-4c95-9333-7903a6cc375a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433219203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.433219203
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.139024954
Short name T147
Test name
Test status
Simulation time 154182640 ps
CPU time 3.75 seconds
Started Aug 01 06:01:20 PM PDT 24
Finished Aug 01 06:01:24 PM PDT 24
Peak memory 242208 kb
Host smart-4999c455-43d9-401e-b3b1-5fbc5ca1774e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139024954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.139024954
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.4063622942
Short name T1167
Test name
Test status
Simulation time 14816156340 ps
CPU time 443.52 seconds
Started Aug 01 06:01:24 PM PDT 24
Finished Aug 01 06:08:47 PM PDT 24
Peak memory 297904 kb
Host smart-3de8d09b-7f32-4628-a3b8-d8be1ba9f8d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063622942 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.4063622942
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.241757033
Short name T70
Test name
Test status
Simulation time 202111665 ps
CPU time 4.32 seconds
Started Aug 01 06:01:22 PM PDT 24
Finished Aug 01 06:01:27 PM PDT 24
Peak memory 242284 kb
Host smart-d3a4bd88-fa41-4620-a82e-eaaa7f889518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241757033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.241757033
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.985092991
Short name T420
Test name
Test status
Simulation time 200623623 ps
CPU time 4.97 seconds
Started Aug 01 06:01:22 PM PDT 24
Finished Aug 01 06:01:28 PM PDT 24
Peak memory 241860 kb
Host smart-fa06f63e-ae2c-4db2-9a85-6531f705359e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985092991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.985092991
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.1986300213
Short name T31
Test name
Test status
Simulation time 862125374151 ps
CPU time 1809.06 seconds
Started Aug 01 06:01:20 PM PDT 24
Finished Aug 01 06:31:29 PM PDT 24
Peak memory 458364 kb
Host smart-e107e5eb-0690-46c1-a866-3deebf7ee6fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986300213 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.1986300213
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.2831751391
Short name T561
Test name
Test status
Simulation time 1962643336 ps
CPU time 4.02 seconds
Started Aug 01 06:01:23 PM PDT 24
Finished Aug 01 06:01:27 PM PDT 24
Peak memory 242132 kb
Host smart-6cbec475-a52e-420f-9fba-ac5ee847c8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831751391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.2831751391
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.1479060313
Short name T254
Test name
Test status
Simulation time 266032848 ps
CPU time 5.25 seconds
Started Aug 01 06:01:21 PM PDT 24
Finished Aug 01 06:01:27 PM PDT 24
Peak memory 241908 kb
Host smart-6b9f0d17-5c01-46a0-be26-0487eded7344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479060313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1479060313
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.121925500
Short name T85
Test name
Test status
Simulation time 505189979152 ps
CPU time 774.08 seconds
Started Aug 01 06:01:24 PM PDT 24
Finished Aug 01 06:14:18 PM PDT 24
Peak memory 265136 kb
Host smart-1a18a5c8-f730-44c1-98d2-a5b0d1926d39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121925500 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.121925500
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.324526143
Short name T1073
Test name
Test status
Simulation time 585497522 ps
CPU time 3.92 seconds
Started Aug 01 06:01:24 PM PDT 24
Finished Aug 01 06:01:28 PM PDT 24
Peak memory 241956 kb
Host smart-8fdffb8b-eef0-4cad-a439-75feba568fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324526143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.324526143
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.882556608
Short name T385
Test name
Test status
Simulation time 505675244 ps
CPU time 17.78 seconds
Started Aug 01 06:01:22 PM PDT 24
Finished Aug 01 06:01:39 PM PDT 24
Peak memory 241692 kb
Host smart-0cd72b86-17f6-485f-a681-c877f373eb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882556608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.882556608
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.3808896982
Short name T54
Test name
Test status
Simulation time 261349539 ps
CPU time 5.52 seconds
Started Aug 01 06:01:22 PM PDT 24
Finished Aug 01 06:01:27 PM PDT 24
Peak memory 242240 kb
Host smart-e6880585-6dc5-4e76-8968-82a1a4549b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808896982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.3808896982
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.1595137365
Short name T222
Test name
Test status
Simulation time 1715665182 ps
CPU time 7.31 seconds
Started Aug 01 06:01:20 PM PDT 24
Finished Aug 01 06:01:27 PM PDT 24
Peak memory 241824 kb
Host smart-9dc28eaf-836d-49b8-a655-69fb652caa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595137365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.1595137365
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.3114630654
Short name T320
Test name
Test status
Simulation time 176913840510 ps
CPU time 1679.03 seconds
Started Aug 01 06:01:21 PM PDT 24
Finished Aug 01 06:29:20 PM PDT 24
Peak memory 313796 kb
Host smart-7ae2eb42-3971-4d20-b7d6-5c9f9220dc1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114630654 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.3114630654
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.2465204853
Short name T1092
Test name
Test status
Simulation time 250209988 ps
CPU time 4.01 seconds
Started Aug 01 06:01:35 PM PDT 24
Finished Aug 01 06:01:39 PM PDT 24
Peak memory 242192 kb
Host smart-9b0301a4-8660-40cd-b2ef-4317315faad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465204853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.2465204853
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.2812441886
Short name T1088
Test name
Test status
Simulation time 1128887874 ps
CPU time 16.68 seconds
Started Aug 01 06:01:32 PM PDT 24
Finished Aug 01 06:01:49 PM PDT 24
Peak memory 241772 kb
Host smart-a4141ec7-6441-4e3d-8151-acc1c9011c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812441886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.2812441886
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.4142990177
Short name T241
Test name
Test status
Simulation time 354820320672 ps
CPU time 865.24 seconds
Started Aug 01 06:01:35 PM PDT 24
Finished Aug 01 06:16:00 PM PDT 24
Peak memory 265040 kb
Host smart-8e5f304b-f35b-442c-bcec-5f38c43f738a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142990177 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.4142990177
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.1667939332
Short name T1045
Test name
Test status
Simulation time 94753444 ps
CPU time 2.25 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:06 PM PDT 24
Peak memory 240524 kb
Host smart-aea47533-e500-49c4-ad80-250b0843a1d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667939332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.1667939332
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.1180360698
Short name T1009
Test name
Test status
Simulation time 14351805531 ps
CPU time 26.36 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:31 PM PDT 24
Peak memory 243124 kb
Host smart-9e9c38db-7ab3-47dc-af40-51d43eb94c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180360698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.1180360698
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.1216115417
Short name T48
Test name
Test status
Simulation time 1218173557 ps
CPU time 8.55 seconds
Started Aug 01 05:58:03 PM PDT 24
Finished Aug 01 05:58:12 PM PDT 24
Peak memory 247512 kb
Host smart-c05be42c-e80f-4956-afff-e93f76c0027f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216115417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.1216115417
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.3467077208
Short name T82
Test name
Test status
Simulation time 4973225876 ps
CPU time 32.52 seconds
Started Aug 01 05:58:02 PM PDT 24
Finished Aug 01 05:58:34 PM PDT 24
Peak memory 243488 kb
Host smart-64712aac-3c84-4993-aa1f-caec06bd4518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467077208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.3467077208
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.316313887
Short name T534
Test name
Test status
Simulation time 131704860 ps
CPU time 4.3 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:08 PM PDT 24
Peak memory 248572 kb
Host smart-5ba08df5-9126-4286-baa3-112667ad3ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316313887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.316313887
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.1728840953
Short name T214
Test name
Test status
Simulation time 136662069 ps
CPU time 4.1 seconds
Started Aug 01 05:58:03 PM PDT 24
Finished Aug 01 05:58:07 PM PDT 24
Peak memory 240936 kb
Host smart-4afec14e-a0f4-4d95-9771-35bfe240454e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728840953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1728840953
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.2585091623
Short name T1115
Test name
Test status
Simulation time 809871678 ps
CPU time 27.14 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:31 PM PDT 24
Peak memory 244092 kb
Host smart-98035c6b-f072-44d9-b63f-b4d5a19d9684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585091623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.2585091623
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.1455940894
Short name T900
Test name
Test status
Simulation time 435245223 ps
CPU time 16.65 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:20 PM PDT 24
Peak memory 241876 kb
Host smart-d0d901d8-adcd-4f7b-8fd9-5435edbf3572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455940894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.1455940894
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.296798528
Short name T399
Test name
Test status
Simulation time 224485645 ps
CPU time 5.56 seconds
Started Aug 01 05:58:02 PM PDT 24
Finished Aug 01 05:58:08 PM PDT 24
Peak memory 241884 kb
Host smart-d6eabefb-cf98-497a-84b9-2fbf5c0e4586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296798528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.296798528
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.966242739
Short name T1111
Test name
Test status
Simulation time 5576781127 ps
CPU time 16.91 seconds
Started Aug 01 05:58:03 PM PDT 24
Finished Aug 01 05:58:20 PM PDT 24
Peak memory 242160 kb
Host smart-ca89a1f2-e1ba-457d-926c-d9af9c1f3f9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=966242739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.966242739
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.6772769
Short name T101
Test name
Test status
Simulation time 243544925 ps
CPU time 3.31 seconds
Started Aug 01 05:58:02 PM PDT 24
Finished Aug 01 05:58:05 PM PDT 24
Peak memory 241888 kb
Host smart-7aa40fd8-90c4-4932-b392-f26d35f38f19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6772769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.6772769
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.398283786
Short name T892
Test name
Test status
Simulation time 323444334 ps
CPU time 5.8 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:10 PM PDT 24
Peak memory 242308 kb
Host smart-978e64ab-9d3d-44de-84c4-731e3004e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398283786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.398283786
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.2000316568
Short name T857
Test name
Test status
Simulation time 9773756472 ps
CPU time 121.85 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 06:00:06 PM PDT 24
Peak memory 248556 kb
Host smart-87026ecc-16d4-407c-bd44-4a750a0bb018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000316568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
2000316568
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.2174290337
Short name T273
Test name
Test status
Simulation time 2307579256 ps
CPU time 23.78 seconds
Started Aug 01 05:58:01 PM PDT 24
Finished Aug 01 05:58:24 PM PDT 24
Peak memory 242956 kb
Host smart-6d549a4a-daa9-4c9a-b396-bcf2eb8c318b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174290337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2174290337
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.132352851
Short name T872
Test name
Test status
Simulation time 437121227 ps
CPU time 5.15 seconds
Started Aug 01 06:01:33 PM PDT 24
Finished Aug 01 06:01:38 PM PDT 24
Peak memory 242176 kb
Host smart-b4f11574-4356-4956-bded-cf861affa53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132352851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.132352851
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.878184594
Short name T960
Test name
Test status
Simulation time 123046729 ps
CPU time 3.49 seconds
Started Aug 01 06:01:34 PM PDT 24
Finished Aug 01 06:01:37 PM PDT 24
Peak memory 241892 kb
Host smart-4bf6dfd0-7088-4dd7-ba4c-eeb58f3654b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878184594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.878184594
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.3095937221
Short name T590
Test name
Test status
Simulation time 2382218288 ps
CPU time 5.88 seconds
Started Aug 01 06:01:35 PM PDT 24
Finished Aug 01 06:01:40 PM PDT 24
Peak memory 242004 kb
Host smart-66b691af-782a-41f1-a261-bdb4c9f98d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095937221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.3095937221
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.2364747641
Short name T690
Test name
Test status
Simulation time 1603415462 ps
CPU time 5.17 seconds
Started Aug 01 06:01:34 PM PDT 24
Finished Aug 01 06:01:39 PM PDT 24
Peak memory 241860 kb
Host smart-7aafe728-4ce9-44a5-945d-bb8bb3444c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364747641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.2364747641
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.2638750727
Short name T768
Test name
Test status
Simulation time 233381178052 ps
CPU time 1412.56 seconds
Started Aug 01 06:01:33 PM PDT 24
Finished Aug 01 06:25:06 PM PDT 24
Peak memory 353620 kb
Host smart-b81f2eb5-0dc0-40f6-8bc4-245939948721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638750727 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.2638750727
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.2112754160
Short name T1081
Test name
Test status
Simulation time 545080907 ps
CPU time 3.97 seconds
Started Aug 01 06:01:35 PM PDT 24
Finished Aug 01 06:01:39 PM PDT 24
Peak memory 241980 kb
Host smart-7859921b-eaa8-4c2f-8ece-682e507fdd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112754160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.2112754160
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.1964698548
Short name T86
Test name
Test status
Simulation time 675283485 ps
CPU time 5.44 seconds
Started Aug 01 06:01:34 PM PDT 24
Finished Aug 01 06:01:40 PM PDT 24
Peak memory 241904 kb
Host smart-2b378738-7d46-4dd0-b044-c94505d0f430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964698548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.1964698548
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.4130423888
Short name T738
Test name
Test status
Simulation time 88998226602 ps
CPU time 1253.63 seconds
Started Aug 01 06:01:37 PM PDT 24
Finished Aug 01 06:22:30 PM PDT 24
Peak memory 265056 kb
Host smart-b6710774-98cc-4b0d-94ff-673c4d177cf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130423888 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.4130423888
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.367968650
Short name T1008
Test name
Test status
Simulation time 2219401735 ps
CPU time 7.76 seconds
Started Aug 01 06:01:33 PM PDT 24
Finished Aug 01 06:01:41 PM PDT 24
Peak memory 242212 kb
Host smart-7bc5604c-06a2-409e-a1bc-df84c10a918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367968650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.367968650
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.2807352341
Short name T834
Test name
Test status
Simulation time 842951271 ps
CPU time 7.61 seconds
Started Aug 01 06:01:33 PM PDT 24
Finished Aug 01 06:01:41 PM PDT 24
Peak memory 242144 kb
Host smart-ac6f01b3-3a5f-4886-b000-21b72f627c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807352341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.2807352341
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.4198294455
Short name T1054
Test name
Test status
Simulation time 53076287212 ps
CPU time 327.07 seconds
Started Aug 01 06:01:34 PM PDT 24
Finished Aug 01 06:07:01 PM PDT 24
Peak memory 289600 kb
Host smart-934e4426-4b08-4355-82a5-2c5bc2e44ed4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198294455 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.4198294455
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.2931528739
Short name T756
Test name
Test status
Simulation time 300538426 ps
CPU time 4.81 seconds
Started Aug 01 06:01:33 PM PDT 24
Finished Aug 01 06:01:38 PM PDT 24
Peak memory 242116 kb
Host smart-90fa6029-2077-4aea-b9fd-2a9870579a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931528739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.2931528739
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.3909532499
Short name T1103
Test name
Test status
Simulation time 698648265 ps
CPU time 10.73 seconds
Started Aug 01 06:01:35 PM PDT 24
Finished Aug 01 06:01:45 PM PDT 24
Peak memory 242056 kb
Host smart-22060a6c-5f78-4f52-b205-cc6661043d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909532499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.3909532499
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.3685574585
Short name T671
Test name
Test status
Simulation time 252264987 ps
CPU time 4.05 seconds
Started Aug 01 06:01:43 PM PDT 24
Finished Aug 01 06:01:48 PM PDT 24
Peak memory 241988 kb
Host smart-503dbc23-176d-47a2-83ed-bcf6467750a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685574585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3685574585
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.3376337502
Short name T426
Test name
Test status
Simulation time 194431938 ps
CPU time 4.73 seconds
Started Aug 01 06:01:43 PM PDT 24
Finished Aug 01 06:01:48 PM PDT 24
Peak memory 241956 kb
Host smart-36006f2b-c827-4d50-9211-4a7cbdd3bbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376337502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3376337502
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.2825736310
Short name T934
Test name
Test status
Simulation time 43769572478 ps
CPU time 874.66 seconds
Started Aug 01 06:01:46 PM PDT 24
Finished Aug 01 06:16:21 PM PDT 24
Peak memory 265808 kb
Host smart-5f79cfa7-0ccb-45f5-a1e5-345f26a70f2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825736310 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.2825736310
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.444633208
Short name T595
Test name
Test status
Simulation time 2269964622 ps
CPU time 4.59 seconds
Started Aug 01 06:01:44 PM PDT 24
Finished Aug 01 06:01:49 PM PDT 24
Peak memory 242392 kb
Host smart-e40dac8e-2914-4c83-8949-160866ab60b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444633208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.444633208
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.2525129530
Short name T1075
Test name
Test status
Simulation time 487450938 ps
CPU time 6.42 seconds
Started Aug 01 06:01:42 PM PDT 24
Finished Aug 01 06:01:48 PM PDT 24
Peak memory 242224 kb
Host smart-9432234d-6a4a-4624-b910-ab4b17f276e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525129530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.2525129530
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.3868268461
Short name T276
Test name
Test status
Simulation time 379599176043 ps
CPU time 2704.81 seconds
Started Aug 01 06:01:46 PM PDT 24
Finished Aug 01 06:46:52 PM PDT 24
Peak memory 330596 kb
Host smart-977de55c-02e3-4d0a-86e7-181d0cde9fa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868268461 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.3868268461
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.2815806169
Short name T112
Test name
Test status
Simulation time 482998508 ps
CPU time 5.4 seconds
Started Aug 01 06:01:44 PM PDT 24
Finished Aug 01 06:01:50 PM PDT 24
Peak memory 241824 kb
Host smart-e89b2e7d-07ed-4f25-9f8f-a037d261ef31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815806169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.2815806169
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.2527688723
Short name T232
Test name
Test status
Simulation time 642296568 ps
CPU time 4.66 seconds
Started Aug 01 06:01:46 PM PDT 24
Finished Aug 01 06:01:51 PM PDT 24
Peak memory 242308 kb
Host smart-614863f8-0517-40e8-a0f8-8b3fd4a730b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527688723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2527688723
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.3929685020
Short name T175
Test name
Test status
Simulation time 30113891710 ps
CPU time 789.06 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:14:55 PM PDT 24
Peak memory 258372 kb
Host smart-7e5cbe40-69f2-4bbe-bac3-d56c0d305caa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929685020 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.3929685020
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.3417945236
Short name T219
Test name
Test status
Simulation time 259785867 ps
CPU time 4.46 seconds
Started Aug 01 06:01:44 PM PDT 24
Finished Aug 01 06:01:49 PM PDT 24
Peak memory 242136 kb
Host smart-5c0e6ad3-7c48-4f2f-b3e0-dbe67cc29814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417945236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.3417945236
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.2672489409
Short name T928
Test name
Test status
Simulation time 3171601682 ps
CPU time 28.04 seconds
Started Aug 01 06:01:44 PM PDT 24
Finished Aug 01 06:02:13 PM PDT 24
Peak memory 241980 kb
Host smart-ed702020-8245-407e-b760-a9eed22df5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672489409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.2672489409
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.1125587668
Short name T947
Test name
Test status
Simulation time 309057394 ps
CPU time 4.61 seconds
Started Aug 01 06:01:43 PM PDT 24
Finished Aug 01 06:01:47 PM PDT 24
Peak memory 242248 kb
Host smart-71fb15fb-43db-4679-aad6-59a45bd3c5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125587668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.1125587668
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.4215218532
Short name T138
Test name
Test status
Simulation time 160908025 ps
CPU time 2.71 seconds
Started Aug 01 06:01:43 PM PDT 24
Finished Aug 01 06:01:46 PM PDT 24
Peak memory 242360 kb
Host smart-36f9e2d6-55a0-4679-8863-15bba6a4b507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215218532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.4215218532
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.3919593362
Short name T250
Test name
Test status
Simulation time 273526378033 ps
CPU time 553.64 seconds
Started Aug 01 06:01:43 PM PDT 24
Finished Aug 01 06:10:57 PM PDT 24
Peak memory 250268 kb
Host smart-cb600667-d0f7-4513-bc05-4fcb8e0d7f4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919593362 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.3919593362
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.449131043
Short name T403
Test name
Test status
Simulation time 383486886 ps
CPU time 2.57 seconds
Started Aug 01 05:58:05 PM PDT 24
Finished Aug 01 05:58:07 PM PDT 24
Peak memory 240280 kb
Host smart-1f454f70-d39e-4278-a54e-f0e6cbb6ed6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449131043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.449131043
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.4259890539
Short name T380
Test name
Test status
Simulation time 2158954111 ps
CPU time 28.89 seconds
Started Aug 01 05:58:01 PM PDT 24
Finished Aug 01 05:58:30 PM PDT 24
Peak memory 242152 kb
Host smart-ef4d7fb2-38f3-4793-b94c-7ac14d7e4e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259890539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.4259890539
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.3272972952
Short name T43
Test name
Test status
Simulation time 1242840300 ps
CPU time 17.35 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:21 PM PDT 24
Peak memory 242376 kb
Host smart-93e2a8f2-a39e-49c0-908d-22e393f63a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272972952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.3272972952
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.841942529
Short name T720
Test name
Test status
Simulation time 1426078804 ps
CPU time 26.58 seconds
Started Aug 01 05:58:03 PM PDT 24
Finished Aug 01 05:58:30 PM PDT 24
Peak memory 241996 kb
Host smart-9bdf78e0-94cc-4507-970e-f604321eaf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841942529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.841942529
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.792932618
Short name T430
Test name
Test status
Simulation time 1332314812 ps
CPU time 22.37 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:26 PM PDT 24
Peak memory 243096 kb
Host smart-34d42924-98b8-4edb-b0ee-a734a5e2e841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792932618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.792932618
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.2170487808
Short name T51
Test name
Test status
Simulation time 297999056 ps
CPU time 4.22 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:08 PM PDT 24
Peak memory 242000 kb
Host smart-035ed44a-c31b-4267-bbdd-b98280cd093e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170487808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.2170487808
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.213022561
Short name T745
Test name
Test status
Simulation time 7046519341 ps
CPU time 16.23 seconds
Started Aug 01 05:58:02 PM PDT 24
Finished Aug 01 05:58:19 PM PDT 24
Peak memory 242328 kb
Host smart-0a453123-174f-4937-9788-f6585a113e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213022561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.213022561
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.1261091059
Short name T685
Test name
Test status
Simulation time 416111994 ps
CPU time 10.85 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:15 PM PDT 24
Peak memory 241928 kb
Host smart-25f9f919-5351-4c33-8a19-4eb6ccfaa2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261091059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.1261091059
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.618098228
Short name T415
Test name
Test status
Simulation time 308546726 ps
CPU time 6.17 seconds
Started Aug 01 05:58:05 PM PDT 24
Finished Aug 01 05:58:11 PM PDT 24
Peak memory 242104 kb
Host smart-0aca8ee8-ad06-4164-b27d-6a8f6d79f431
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618098228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.618098228
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.287119250
Short name T1181
Test name
Test status
Simulation time 156749436 ps
CPU time 4.87 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:09 PM PDT 24
Peak memory 241816 kb
Host smart-1cd5fcb0-ee52-4175-9eec-3ba1f294664f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=287119250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.287119250
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.908843659
Short name T625
Test name
Test status
Simulation time 537273368 ps
CPU time 8.39 seconds
Started Aug 01 05:58:02 PM PDT 24
Finished Aug 01 05:58:11 PM PDT 24
Peak memory 242240 kb
Host smart-875b286d-eb2f-4ed1-8659-b8e899a86a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908843659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.908843659
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.3782845038
Short name T245
Test name
Test status
Simulation time 10857304781 ps
CPU time 244.65 seconds
Started Aug 01 05:58:05 PM PDT 24
Finished Aug 01 06:02:10 PM PDT 24
Peak memory 248716 kb
Host smart-50b8ef81-a597-4dc6-8645-1f9f39c1b1ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782845038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
3782845038
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.2408352162
Short name T451
Test name
Test status
Simulation time 3782629555 ps
CPU time 32.93 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:37 PM PDT 24
Peak memory 242516 kb
Host smart-3a529b41-6598-4183-b146-1a91dece4982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408352162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2408352162
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.1071244976
Short name T779
Test name
Test status
Simulation time 115557531 ps
CPU time 3.03 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:01:48 PM PDT 24
Peak memory 242344 kb
Host smart-77fd1b85-93d0-4dcc-85d0-9874178bab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071244976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.1071244976
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.1973425346
Short name T144
Test name
Test status
Simulation time 220773650 ps
CPU time 4.79 seconds
Started Aug 01 06:01:43 PM PDT 24
Finished Aug 01 06:01:47 PM PDT 24
Peak memory 241816 kb
Host smart-39bc25d5-d72f-497d-b4ec-97d7d3cd7827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973425346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.1973425346
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.222378086
Short name T634
Test name
Test status
Simulation time 174215900 ps
CPU time 3.34 seconds
Started Aug 01 06:01:44 PM PDT 24
Finished Aug 01 06:01:48 PM PDT 24
Peak memory 241920 kb
Host smart-99c9e751-fefd-40bb-9df6-e8925c564459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222378086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.222378086
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.3963287341
Short name T611
Test name
Test status
Simulation time 5708378964 ps
CPU time 12.05 seconds
Started Aug 01 06:01:43 PM PDT 24
Finished Aug 01 06:01:56 PM PDT 24
Peak memory 242264 kb
Host smart-a27457b2-ba86-48a7-a297-784b00660164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963287341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.3963287341
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2168397074
Short name T328
Test name
Test status
Simulation time 69919555961 ps
CPU time 621.41 seconds
Started Aug 01 06:01:47 PM PDT 24
Finished Aug 01 06:12:08 PM PDT 24
Peak memory 265168 kb
Host smart-c34f1d8e-6be9-454c-ae7c-e158e0276256
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168397074 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.2168397074
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.3030718686
Short name T711
Test name
Test status
Simulation time 270566668 ps
CPU time 3.77 seconds
Started Aug 01 06:01:46 PM PDT 24
Finished Aug 01 06:01:50 PM PDT 24
Peak memory 241920 kb
Host smart-e4f608c5-3283-4168-819d-3fe46217c457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030718686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3030718686
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.113424206
Short name T790
Test name
Test status
Simulation time 437462140 ps
CPU time 9.36 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:01:54 PM PDT 24
Peak memory 241716 kb
Host smart-9cd66c05-17d0-4ecb-abef-9fad1acdea40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113424206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.113424206
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.1404793940
Short name T974
Test name
Test status
Simulation time 44297993607 ps
CPU time 956.01 seconds
Started Aug 01 06:01:47 PM PDT 24
Finished Aug 01 06:17:43 PM PDT 24
Peak memory 256340 kb
Host smart-7f355dba-06fb-4a25-bac5-dc76b6133940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404793940 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.1404793940
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.1117140780
Short name T118
Test name
Test status
Simulation time 569209301 ps
CPU time 4.84 seconds
Started Aug 01 06:01:42 PM PDT 24
Finished Aug 01 06:01:47 PM PDT 24
Peak memory 241832 kb
Host smart-309222bc-2ca9-4839-ac40-cfc78cc98426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117140780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.1117140780
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.186503973
Short name T228
Test name
Test status
Simulation time 6806684525 ps
CPU time 16.07 seconds
Started Aug 01 06:01:43 PM PDT 24
Finished Aug 01 06:01:59 PM PDT 24
Peak memory 242328 kb
Host smart-61d4316e-cb98-4575-adae-3260fee540d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186503973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.186503973
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.15620750
Short name T283
Test name
Test status
Simulation time 515284193 ps
CPU time 4.19 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:01:50 PM PDT 24
Peak memory 242080 kb
Host smart-01e008ac-8e25-436a-bb0b-9c7c3173e934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15620750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.15620750
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.1121918182
Short name T1018
Test name
Test status
Simulation time 1681233212 ps
CPU time 7.75 seconds
Started Aug 01 06:01:44 PM PDT 24
Finished Aug 01 06:01:52 PM PDT 24
Peak memory 242340 kb
Host smart-968cdc37-4b08-46db-946d-31dd0ca6bb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121918182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1121918182
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.965635565
Short name T772
Test name
Test status
Simulation time 147158444567 ps
CPU time 222.77 seconds
Started Aug 01 06:01:43 PM PDT 24
Finished Aug 01 06:05:26 PM PDT 24
Peak memory 256904 kb
Host smart-992af4ab-478e-43b4-9ca3-ac9685326b65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965635565 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.965635565
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.2717562229
Short name T936
Test name
Test status
Simulation time 153262832 ps
CPU time 3.86 seconds
Started Aug 01 06:01:44 PM PDT 24
Finished Aug 01 06:01:48 PM PDT 24
Peak memory 242296 kb
Host smart-5388625e-db6f-4e68-b851-c8f0c4a33b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717562229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.2717562229
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.1560003186
Short name T1101
Test name
Test status
Simulation time 206532328 ps
CPU time 10.53 seconds
Started Aug 01 06:01:44 PM PDT 24
Finished Aug 01 06:01:55 PM PDT 24
Peak memory 242224 kb
Host smart-a3061584-b889-46bd-881b-7f4c36bcefea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560003186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.1560003186
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.3553641834
Short name T470
Test name
Test status
Simulation time 219829104 ps
CPU time 4.1 seconds
Started Aug 01 06:01:49 PM PDT 24
Finished Aug 01 06:01:54 PM PDT 24
Peak memory 242236 kb
Host smart-20a5439f-a489-4260-bb9f-c5f1388c0fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553641834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.3553641834
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.1206778254
Short name T193
Test name
Test status
Simulation time 159697954 ps
CPU time 4.42 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:01:50 PM PDT 24
Peak memory 242192 kb
Host smart-11a2f43b-5e02-4675-ab56-6a914d2f7a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206778254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.1206778254
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.1570449426
Short name T614
Test name
Test status
Simulation time 33929150955 ps
CPU time 898.76 seconds
Started Aug 01 06:01:43 PM PDT 24
Finished Aug 01 06:16:42 PM PDT 24
Peak memory 331356 kb
Host smart-7306fc3d-c394-4b32-8c65-7aa09855541e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570449426 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.1570449426
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.1247371236
Short name T220
Test name
Test status
Simulation time 125226939 ps
CPU time 4.73 seconds
Started Aug 01 06:01:44 PM PDT 24
Finished Aug 01 06:01:49 PM PDT 24
Peak memory 241984 kb
Host smart-dfc9b487-0712-4da6-9596-0c1a07755fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247371236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.1247371236
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.487485628
Short name T884
Test name
Test status
Simulation time 1917928161 ps
CPU time 23.91 seconds
Started Aug 01 06:01:42 PM PDT 24
Finished Aug 01 06:02:06 PM PDT 24
Peak memory 242184 kb
Host smart-76ce730c-1012-4aa5-b8e9-6af1d5eb53c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487485628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.487485628
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.4077193393
Short name T494
Test name
Test status
Simulation time 88999129876 ps
CPU time 451.16 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:09:16 PM PDT 24
Peak memory 313272 kb
Host smart-4c7fcaae-6b30-451f-b02a-526696e44916
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077193393 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.4077193393
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.1244563515
Short name T859
Test name
Test status
Simulation time 264119951 ps
CPU time 4.52 seconds
Started Aug 01 06:01:43 PM PDT 24
Finished Aug 01 06:01:48 PM PDT 24
Peak memory 242056 kb
Host smart-78d022a9-134f-4de3-9360-4ff06cdacb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244563515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.1244563515
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.3077090870
Short name T239
Test name
Test status
Simulation time 1995040618 ps
CPU time 26.2 seconds
Started Aug 01 06:01:47 PM PDT 24
Finished Aug 01 06:02:14 PM PDT 24
Peak memory 241736 kb
Host smart-37cc3018-df49-4f88-8363-cd355a79ca19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077090870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.3077090870
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.509823539
Short name T864
Test name
Test status
Simulation time 54254586814 ps
CPU time 458.67 seconds
Started Aug 01 06:02:21 PM PDT 24
Finished Aug 01 06:10:00 PM PDT 24
Peak memory 248628 kb
Host smart-191dce11-e010-410d-bf5c-b6e61cf01376
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509823539 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.509823539
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.3596487074
Short name T964
Test name
Test status
Simulation time 296535897 ps
CPU time 4.43 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:01:50 PM PDT 24
Peak memory 242136 kb
Host smart-ec89ecb0-817b-45ed-8755-01f10a29a086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596487074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.3596487074
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.1816131911
Short name T275
Test name
Test status
Simulation time 77439635810 ps
CPU time 657.09 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:12:42 PM PDT 24
Peak memory 256948 kb
Host smart-27778dab-fccd-4e00-874c-608667b97680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816131911 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.1816131911
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.3177609349
Short name T610
Test name
Test status
Simulation time 842130142 ps
CPU time 2.59 seconds
Started Aug 01 05:58:16 PM PDT 24
Finished Aug 01 05:58:19 PM PDT 24
Peak memory 240384 kb
Host smart-d63f63b4-eda5-4209-bb62-7af8a8db2480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177609349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.3177609349
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.3535339618
Short name T893
Test name
Test status
Simulation time 3814774494 ps
CPU time 23.4 seconds
Started Aug 01 05:58:16 PM PDT 24
Finished Aug 01 05:58:40 PM PDT 24
Peak memory 248580 kb
Host smart-f58995c1-891c-4ec1-9cab-7fc29c214ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535339618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.3535339618
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.1825112593
Short name T483
Test name
Test status
Simulation time 230621736 ps
CPU time 6.17 seconds
Started Aug 01 05:58:17 PM PDT 24
Finished Aug 01 05:58:23 PM PDT 24
Peak memory 242180 kb
Host smart-c1c69927-d086-46d1-b82f-b59b6a073a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825112593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.1825112593
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.1427007698
Short name T568
Test name
Test status
Simulation time 325358932 ps
CPU time 18.91 seconds
Started Aug 01 05:58:18 PM PDT 24
Finished Aug 01 05:58:37 PM PDT 24
Peak memory 242336 kb
Host smart-5ca27550-3f30-4df4-b02b-260a90135388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427007698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.1427007698
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.2244574084
Short name T1012
Test name
Test status
Simulation time 1576217554 ps
CPU time 18.66 seconds
Started Aug 01 05:58:20 PM PDT 24
Finished Aug 01 05:58:39 PM PDT 24
Peak memory 242100 kb
Host smart-354c1670-d7f6-4e70-a5ec-10c4594218bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244574084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.2244574084
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.2887604211
Short name T598
Test name
Test status
Simulation time 143930060 ps
CPU time 4.43 seconds
Started Aug 01 05:58:19 PM PDT 24
Finished Aug 01 05:58:24 PM PDT 24
Peak memory 242168 kb
Host smart-9a192d61-cc0c-4f08-943c-39ccc962cdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887604211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.2887604211
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.907564972
Short name T156
Test name
Test status
Simulation time 7680948533 ps
CPU time 21.56 seconds
Started Aug 01 05:58:16 PM PDT 24
Finished Aug 01 05:58:38 PM PDT 24
Peak memory 245400 kb
Host smart-284fb22d-9cbb-44a0-b2a5-fab5cbf98230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907564972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.907564972
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.4232023880
Short name T1160
Test name
Test status
Simulation time 1811248300 ps
CPU time 17.94 seconds
Started Aug 01 05:58:17 PM PDT 24
Finished Aug 01 05:58:36 PM PDT 24
Peak memory 242416 kb
Host smart-91294476-e9ea-4b6a-bc4d-b05b445c1d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232023880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.4232023880
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.400618480
Short name T976
Test name
Test status
Simulation time 1243531644 ps
CPU time 15.09 seconds
Started Aug 01 05:58:16 PM PDT 24
Finished Aug 01 05:58:31 PM PDT 24
Peak memory 242380 kb
Host smart-3974aa99-fffe-43a7-a2d8-b46de63273b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400618480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.400618480
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.177536912
Short name T472
Test name
Test status
Simulation time 1914169639 ps
CPU time 23.94 seconds
Started Aug 01 05:58:19 PM PDT 24
Finished Aug 01 05:58:43 PM PDT 24
Peak memory 242132 kb
Host smart-aef0b5bb-d103-4521-a984-2d922ed6e5a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=177536912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.177536912
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.1225322643
Short name T496
Test name
Test status
Simulation time 5046792470 ps
CPU time 10.38 seconds
Started Aug 01 05:58:17 PM PDT 24
Finished Aug 01 05:58:28 PM PDT 24
Peak memory 242736 kb
Host smart-b0edecf7-6120-48c6-a0f2-9dc441d95f67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225322643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.1225322643
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.3330975990
Short name T748
Test name
Test status
Simulation time 398446893 ps
CPU time 5.05 seconds
Started Aug 01 05:58:04 PM PDT 24
Finished Aug 01 05:58:09 PM PDT 24
Peak memory 248348 kb
Host smart-5f4c44f0-f9a1-4eaf-a8b5-a8636f28094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330975990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.3330975990
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.728270252
Short name T270
Test name
Test status
Simulation time 1646946227 ps
CPU time 25.38 seconds
Started Aug 01 05:58:19 PM PDT 24
Finished Aug 01 05:58:45 PM PDT 24
Peak memory 241716 kb
Host smart-f79dd61e-6144-4e1f-9a72-a8187e6917ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728270252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.728270252
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.3830213586
Short name T1182
Test name
Test status
Simulation time 83404418191 ps
CPU time 1539.71 seconds
Started Aug 01 05:58:19 PM PDT 24
Finished Aug 01 06:24:00 PM PDT 24
Peak memory 400508 kb
Host smart-0558d669-127b-4a5d-8733-143a5cf06c8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830213586 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.3830213586
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.1763304136
Short name T762
Test name
Test status
Simulation time 964269807 ps
CPU time 11.65 seconds
Started Aug 01 05:58:17 PM PDT 24
Finished Aug 01 05:58:29 PM PDT 24
Peak memory 242028 kb
Host smart-9b03b0cf-8e1f-44e3-8f4f-28c0c7df8488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763304136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.1763304136
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.4037701704
Short name T713
Test name
Test status
Simulation time 263957632 ps
CPU time 4.64 seconds
Started Aug 01 06:01:46 PM PDT 24
Finished Aug 01 06:01:51 PM PDT 24
Peak memory 241908 kb
Host smart-c97c7ea9-6bb5-42cc-8191-bdf9ac1afa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037701704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.4037701704
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.3082183517
Short name T469
Test name
Test status
Simulation time 1275713688 ps
CPU time 18.29 seconds
Started Aug 01 06:01:47 PM PDT 24
Finished Aug 01 06:02:05 PM PDT 24
Peak memory 241920 kb
Host smart-1417d391-0d81-4f4a-9b53-5b7e8c73b011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082183517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.3082183517
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.1715260811
Short name T433
Test name
Test status
Simulation time 134174608 ps
CPU time 3.61 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:01:49 PM PDT 24
Peak memory 242408 kb
Host smart-174ea46f-afeb-481f-bf5e-a6176a6f2cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715260811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.1715260811
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.1157991173
Short name T146
Test name
Test status
Simulation time 604829785 ps
CPU time 9.04 seconds
Started Aug 01 06:01:47 PM PDT 24
Finished Aug 01 06:01:56 PM PDT 24
Peak memory 242188 kb
Host smart-153cb2eb-1636-4e93-814c-564b8df2a74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157991173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.1157991173
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1054316883
Short name T1005
Test name
Test status
Simulation time 147173138057 ps
CPU time 1817.14 seconds
Started Aug 01 06:01:44 PM PDT 24
Finished Aug 01 06:32:02 PM PDT 24
Peak memory 297916 kb
Host smart-de550073-b7cf-495e-8311-c2f945e02573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054316883 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.1054316883
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.2370387668
Short name T182
Test name
Test status
Simulation time 99766653 ps
CPU time 3.81 seconds
Started Aug 01 06:01:42 PM PDT 24
Finished Aug 01 06:01:46 PM PDT 24
Peak memory 242260 kb
Host smart-84d4c760-11f7-463e-b2ab-233fcaf1c737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370387668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.2370387668
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.3661916047
Short name T578
Test name
Test status
Simulation time 215163612 ps
CPU time 6.1 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:01:52 PM PDT 24
Peak memory 241876 kb
Host smart-84340efa-6b8f-450a-9a2d-02add9bdbec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661916047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.3661916047
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.1613511744
Short name T1063
Test name
Test status
Simulation time 1059466542713 ps
CPU time 3256.7 seconds
Started Aug 01 06:01:47 PM PDT 24
Finished Aug 01 06:56:04 PM PDT 24
Peak memory 338768 kb
Host smart-845d1dd3-6cb2-47d2-bea9-8a1db2f4cca8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613511744 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.1613511744
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.4012631975
Short name T407
Test name
Test status
Simulation time 256414364 ps
CPU time 4.15 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:01:50 PM PDT 24
Peak memory 242340 kb
Host smart-11c4e7a3-39b2-47cd-ab67-4c54115e79b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012631975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.4012631975
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.211705152
Short name T860
Test name
Test status
Simulation time 168264435 ps
CPU time 4.38 seconds
Started Aug 01 06:01:50 PM PDT 24
Finished Aug 01 06:01:55 PM PDT 24
Peak memory 242112 kb
Host smart-c852d691-c7ac-4b51-8796-dfb7ecf18fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211705152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.211705152
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.2896981919
Short name T869
Test name
Test status
Simulation time 2091384077 ps
CPU time 7.68 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:01:53 PM PDT 24
Peak memory 241980 kb
Host smart-51b75347-782d-4701-8abc-6ae2d252b557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896981919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2896981919
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.3519811465
Short name T1187
Test name
Test status
Simulation time 200594930 ps
CPU time 5.72 seconds
Started Aug 01 06:01:45 PM PDT 24
Finished Aug 01 06:01:51 PM PDT 24
Peak memory 242388 kb
Host smart-b65c214a-b798-4df7-80a1-692ad1d06dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519811465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3519811465
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.3220409051
Short name T760
Test name
Test status
Simulation time 175738014160 ps
CPU time 1703.65 seconds
Started Aug 01 06:01:50 PM PDT 24
Finished Aug 01 06:30:14 PM PDT 24
Peak memory 300696 kb
Host smart-47476698-f51f-452d-a790-dc23cb1ecc6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220409051 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.3220409051
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.1034393125
Short name T498
Test name
Test status
Simulation time 152189590 ps
CPU time 5.84 seconds
Started Aug 01 06:01:55 PM PDT 24
Finished Aug 01 06:02:01 PM PDT 24
Peak memory 241844 kb
Host smart-10a7a873-970e-4a13-ba1f-f98524d8e9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034393125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.1034393125
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.4287261146
Short name T277
Test name
Test status
Simulation time 48593968362 ps
CPU time 1094.79 seconds
Started Aug 01 06:02:00 PM PDT 24
Finished Aug 01 06:20:15 PM PDT 24
Peak memory 271384 kb
Host smart-627ba715-76f7-4fb9-8286-c204c7b35e15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287261146 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.4287261146
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.4038972968
Short name T213
Test name
Test status
Simulation time 142041169 ps
CPU time 3.11 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:00 PM PDT 24
Peak memory 241908 kb
Host smart-2b30e409-6bad-49b7-bfb9-112548e5e5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038972968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.4038972968
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.2490717665
Short name T1135
Test name
Test status
Simulation time 571011067 ps
CPU time 16.38 seconds
Started Aug 01 06:01:56 PM PDT 24
Finished Aug 01 06:02:13 PM PDT 24
Peak memory 241956 kb
Host smart-f13682b5-2d93-47ee-a4f7-f9d011b397d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490717665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.2490717665
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.731289003
Short name T4
Test name
Test status
Simulation time 20810382689 ps
CPU time 603.17 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:12:00 PM PDT 24
Peak memory 281156 kb
Host smart-81b81728-73ad-4621-9693-d6838631f901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731289003 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.731289003
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.2918528611
Short name T919
Test name
Test status
Simulation time 565539484 ps
CPU time 5.19 seconds
Started Aug 01 06:01:56 PM PDT 24
Finished Aug 01 06:02:02 PM PDT 24
Peak memory 241944 kb
Host smart-4c1768b0-344b-42ac-8c9b-0922eaa773a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918528611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.2918528611
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.3488977344
Short name T1133
Test name
Test status
Simulation time 260574876 ps
CPU time 4.9 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:02 PM PDT 24
Peak memory 241760 kb
Host smart-05c79422-e8a9-4feb-94b5-7b4dc5b23014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488977344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.3488977344
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.867472197
Short name T248
Test name
Test status
Simulation time 428933714040 ps
CPU time 603.42 seconds
Started Aug 01 06:01:54 PM PDT 24
Finished Aug 01 06:11:57 PM PDT 24
Peak memory 280192 kb
Host smart-d0d5da3f-8c35-4d65-bf5b-8c4abbc59c9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867472197 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.867472197
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.4231456690
Short name T189
Test name
Test status
Simulation time 122738798 ps
CPU time 3.12 seconds
Started Aug 01 06:01:58 PM PDT 24
Finished Aug 01 06:02:01 PM PDT 24
Peak memory 241976 kb
Host smart-ea92f7f8-85ad-4c35-bed2-bc2bc978bb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231456690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.4231456690
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.2796019818
Short name T726
Test name
Test status
Simulation time 7076186069 ps
CPU time 16.54 seconds
Started Aug 01 06:01:56 PM PDT 24
Finished Aug 01 06:02:13 PM PDT 24
Peak memory 241792 kb
Host smart-022fb5c4-33e7-4509-98c3-ee681a19cba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796019818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.2796019818
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.1933994143
Short name T688
Test name
Test status
Simulation time 143639671127 ps
CPU time 1485.78 seconds
Started Aug 01 06:01:59 PM PDT 24
Finished Aug 01 06:26:45 PM PDT 24
Peak memory 267320 kb
Host smart-a0f85131-d7f9-4106-9ea9-9a3bb17326b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933994143 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.1933994143
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.3524043255
Short name T973
Test name
Test status
Simulation time 493490124 ps
CPU time 3.7 seconds
Started Aug 01 06:01:53 PM PDT 24
Finished Aug 01 06:01:56 PM PDT 24
Peak memory 242228 kb
Host smart-7a937949-0547-46a3-9ea6-07bfa1e9db0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524043255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.3524043255
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.4028538251
Short name T252
Test name
Test status
Simulation time 448831580 ps
CPU time 11.98 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:10 PM PDT 24
Peak memory 241980 kb
Host smart-a0683396-87df-44bd-8c5f-564aefade492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028538251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.4028538251
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.281007135
Short name T266
Test name
Test status
Simulation time 112920216 ps
CPU time 1.79 seconds
Started Aug 01 05:58:16 PM PDT 24
Finished Aug 01 05:58:18 PM PDT 24
Peak memory 240316 kb
Host smart-d2fe8198-3034-44dc-841e-2ab2e9ff983e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281007135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.281007135
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.4290238686
Short name T1058
Test name
Test status
Simulation time 207007350 ps
CPU time 6.58 seconds
Started Aug 01 05:58:20 PM PDT 24
Finished Aug 01 05:58:27 PM PDT 24
Peak memory 248556 kb
Host smart-55707319-cf3e-410b-bab2-d698831808ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290238686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.4290238686
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.1893172605
Short name T988
Test name
Test status
Simulation time 1572458999 ps
CPU time 30.27 seconds
Started Aug 01 05:58:16 PM PDT 24
Finished Aug 01 05:58:47 PM PDT 24
Peak memory 244024 kb
Host smart-c2fcca3f-bca6-481d-9a14-cc86a33e4a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893172605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.1893172605
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.4184807454
Short name T684
Test name
Test status
Simulation time 1975434928 ps
CPU time 34.25 seconds
Started Aug 01 05:58:15 PM PDT 24
Finished Aug 01 05:58:50 PM PDT 24
Peak memory 245536 kb
Host smart-67d69265-dbc5-49aa-a4a0-6e27b48fcb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184807454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.4184807454
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.2096849460
Short name T597
Test name
Test status
Simulation time 919948850 ps
CPU time 10.4 seconds
Started Aug 01 05:58:17 PM PDT 24
Finished Aug 01 05:58:27 PM PDT 24
Peak memory 242224 kb
Host smart-07f54602-c3e0-4739-8ab7-6dbcb1b86b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096849460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.2096849460
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.1769397538
Short name T331
Test name
Test status
Simulation time 721620258 ps
CPU time 4.46 seconds
Started Aug 01 05:58:16 PM PDT 24
Finished Aug 01 05:58:20 PM PDT 24
Peak memory 241952 kb
Host smart-631d6183-9596-4c3c-b2dc-f6afb05e1810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769397538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.1769397538
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.1254050840
Short name T154
Test name
Test status
Simulation time 1331199861 ps
CPU time 21.3 seconds
Started Aug 01 05:58:17 PM PDT 24
Finished Aug 01 05:58:39 PM PDT 24
Peak memory 242240 kb
Host smart-bb168350-0bb7-4bec-8418-406fbfe28f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254050840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.1254050840
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.1845317023
Short name T667
Test name
Test status
Simulation time 4895645628 ps
CPU time 16.48 seconds
Started Aug 01 05:58:17 PM PDT 24
Finished Aug 01 05:58:34 PM PDT 24
Peak memory 248660 kb
Host smart-144b8594-bb7e-4a95-8749-ce5678e9c152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845317023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.1845317023
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.821503014
Short name T744
Test name
Test status
Simulation time 13245752736 ps
CPU time 36.04 seconds
Started Aug 01 05:58:18 PM PDT 24
Finished Aug 01 05:58:54 PM PDT 24
Peak memory 241880 kb
Host smart-809e3436-a27e-45df-a6fd-2e5bf600af33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821503014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.821503014
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.2511180082
Short name T986
Test name
Test status
Simulation time 1976581226 ps
CPU time 19.17 seconds
Started Aug 01 05:58:16 PM PDT 24
Finished Aug 01 05:58:35 PM PDT 24
Peak memory 248632 kb
Host smart-50cd79f2-15eb-4891-bcfc-7d1dd987e6cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511180082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.2511180082
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.18600966
Short name T359
Test name
Test status
Simulation time 852043841 ps
CPU time 9.62 seconds
Started Aug 01 05:58:20 PM PDT 24
Finished Aug 01 05:58:30 PM PDT 24
Peak memory 242252 kb
Host smart-1e9f71e3-c40a-4012-847d-9dac41eb4a04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18600966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.18600966
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.3168139265
Short name T592
Test name
Test status
Simulation time 543655780 ps
CPU time 7.3 seconds
Started Aug 01 05:58:16 PM PDT 24
Finished Aug 01 05:58:23 PM PDT 24
Peak memory 242120 kb
Host smart-6582d7e3-06eb-4a60-9fc5-3c70964771c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168139265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.3168139265
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.1158546833
Short name T953
Test name
Test status
Simulation time 95352229917 ps
CPU time 243.87 seconds
Started Aug 01 05:58:18 PM PDT 24
Finished Aug 01 06:02:22 PM PDT 24
Peak memory 281364 kb
Host smart-3166662b-6914-46f2-9768-5e78c22fcc26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158546833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
1158546833
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.1517740958
Short name T705
Test name
Test status
Simulation time 269855337 ps
CPU time 4.85 seconds
Started Aug 01 05:58:21 PM PDT 24
Finished Aug 01 05:58:26 PM PDT 24
Peak memory 242316 kb
Host smart-b5e5284d-06f3-4fb9-b334-2d8cc8a6a16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517740958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.1517740958
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.495678342
Short name T889
Test name
Test status
Simulation time 348983981 ps
CPU time 4.6 seconds
Started Aug 01 06:01:56 PM PDT 24
Finished Aug 01 06:02:01 PM PDT 24
Peak memory 242336 kb
Host smart-49a4e271-5d56-4d68-b912-f7b8e8821983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495678342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.495678342
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.667645291
Short name T200
Test name
Test status
Simulation time 1175012541 ps
CPU time 20.33 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:18 PM PDT 24
Peak memory 241984 kb
Host smart-06f72984-3cea-4a5a-bb7d-5db171ce6283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667645291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.667645291
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.1221783150
Short name T1100
Test name
Test status
Simulation time 67070512657 ps
CPU time 1000.63 seconds
Started Aug 01 06:01:56 PM PDT 24
Finished Aug 01 06:18:37 PM PDT 24
Peak memory 373304 kb
Host smart-344f32be-ea60-47ec-a64f-361b5577aaa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221783150 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.1221783150
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.2293483827
Short name T1166
Test name
Test status
Simulation time 236131633 ps
CPU time 4.18 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:01 PM PDT 24
Peak memory 242216 kb
Host smart-b9ba7212-a0bc-4bbb-8594-950850e8c879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293483827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2293483827
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.150416667
Short name T84
Test name
Test status
Simulation time 123067022 ps
CPU time 3.23 seconds
Started Aug 01 06:01:55 PM PDT 24
Finished Aug 01 06:01:58 PM PDT 24
Peak memory 241736 kb
Host smart-787b63ff-ccec-4d20-8c1f-91aaf3f31f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150416667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.150416667
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.3739744170
Short name T572
Test name
Test status
Simulation time 75414097123 ps
CPU time 1074.31 seconds
Started Aug 01 06:01:56 PM PDT 24
Finished Aug 01 06:19:50 PM PDT 24
Peak memory 411072 kb
Host smart-40512668-6f1b-4c6f-931b-dd73273b862b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739744170 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.3739744170
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.1661727202
Short name T630
Test name
Test status
Simulation time 274678259 ps
CPU time 3.25 seconds
Started Aug 01 06:02:00 PM PDT 24
Finished Aug 01 06:02:03 PM PDT 24
Peak memory 241848 kb
Host smart-c1c61f88-d274-464c-bc04-615427005a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661727202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.1661727202
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.3429793079
Short name T1183
Test name
Test status
Simulation time 209407009 ps
CPU time 4.29 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:02 PM PDT 24
Peak memory 242052 kb
Host smart-9e8a9e26-de3a-4887-a95f-ce6eeb6514af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429793079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3429793079
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.4272290413
Short name T660
Test name
Test status
Simulation time 186475128113 ps
CPU time 1317.28 seconds
Started Aug 01 06:01:55 PM PDT 24
Finished Aug 01 06:23:52 PM PDT 24
Peak memory 363288 kb
Host smart-d56b334c-2676-4803-b7e8-b83fb8dba9a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272290413 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.4272290413
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.3675467929
Short name T1153
Test name
Test status
Simulation time 118488560 ps
CPU time 4.13 seconds
Started Aug 01 06:01:59 PM PDT 24
Finished Aug 01 06:02:03 PM PDT 24
Peak memory 242356 kb
Host smart-56256dc0-e1dc-4d8b-a612-07fe48c4d5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675467929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.3675467929
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.1159420033
Short name T102
Test name
Test status
Simulation time 369117253 ps
CPU time 9.97 seconds
Started Aug 01 06:01:58 PM PDT 24
Finished Aug 01 06:02:08 PM PDT 24
Peak memory 242396 kb
Host smart-e8a42ac6-2393-4232-8643-02ae3a35a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159420033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.1159420033
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.2881597681
Short name T655
Test name
Test status
Simulation time 34351302385 ps
CPU time 489.59 seconds
Started Aug 01 06:01:55 PM PDT 24
Finished Aug 01 06:10:05 PM PDT 24
Peak memory 265528 kb
Host smart-a5876650-8b34-47fe-855d-b4ea1116f86a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881597681 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.2881597681
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.461396566
Short name T778
Test name
Test status
Simulation time 513405054 ps
CPU time 4.57 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:02 PM PDT 24
Peak memory 242136 kb
Host smart-0ee8c1d0-3c23-4402-ad84-b8eae8bbd721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461396566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.461396566
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.3856520892
Short name T780
Test name
Test status
Simulation time 182030343 ps
CPU time 4.36 seconds
Started Aug 01 06:01:55 PM PDT 24
Finished Aug 01 06:02:00 PM PDT 24
Peak memory 242060 kb
Host smart-81dfce76-8962-4a1f-b5de-1c003d14da9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856520892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.3856520892
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.1173958668
Short name T1041
Test name
Test status
Simulation time 184628551 ps
CPU time 3.82 seconds
Started Aug 01 06:01:56 PM PDT 24
Finished Aug 01 06:02:00 PM PDT 24
Peak memory 242196 kb
Host smart-f2b31754-9cc8-4e23-b803-0bb556f4bd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173958668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.1173958668
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.3581028307
Short name T993
Test name
Test status
Simulation time 212673613 ps
CPU time 3.47 seconds
Started Aug 01 06:01:59 PM PDT 24
Finished Aug 01 06:02:03 PM PDT 24
Peak memory 242220 kb
Host smart-8e8d079e-03d7-4cdb-84a9-f10c85881d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581028307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.3581028307
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.432347597
Short name T246
Test name
Test status
Simulation time 120517441623 ps
CPU time 1687.51 seconds
Started Aug 01 06:01:54 PM PDT 24
Finished Aug 01 06:30:01 PM PDT 24
Peak memory 555236 kb
Host smart-3a6329c6-5cb0-4904-b55a-3c778e1bd572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432347597 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.432347597
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.2837807927
Short name T865
Test name
Test status
Simulation time 267322387 ps
CPU time 4.12 seconds
Started Aug 01 06:01:55 PM PDT 24
Finished Aug 01 06:01:59 PM PDT 24
Peak memory 242128 kb
Host smart-d1144a9c-8ddc-414a-8931-5d3db652ee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837807927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2837807927
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.670141019
Short name T959
Test name
Test status
Simulation time 978289609 ps
CPU time 15.61 seconds
Started Aug 01 06:01:58 PM PDT 24
Finished Aug 01 06:02:13 PM PDT 24
Peak memory 241752 kb
Host smart-743ac109-bbe6-4ec5-9e4b-8a8bcf1904c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670141019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.670141019
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.2454708508
Short name T321
Test name
Test status
Simulation time 264635422269 ps
CPU time 1588.03 seconds
Started Aug 01 06:01:56 PM PDT 24
Finished Aug 01 06:28:24 PM PDT 24
Peak memory 402256 kb
Host smart-a3d71ee4-5147-4694-9452-91041eafeece
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454708508 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.2454708508
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.2539961342
Short name T243
Test name
Test status
Simulation time 179022382 ps
CPU time 4.05 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:01 PM PDT 24
Peak memory 241992 kb
Host smart-80b65688-fac2-4a74-b947-9733f6b10188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539961342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2539961342
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.4158456460
Short name T139
Test name
Test status
Simulation time 1835845189 ps
CPU time 6.51 seconds
Started Aug 01 06:01:59 PM PDT 24
Finished Aug 01 06:02:06 PM PDT 24
Peak memory 241872 kb
Host smart-e5e95b98-5872-4972-a793-3c06d8638842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158456460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.4158456460
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.4008462663
Short name T946
Test name
Test status
Simulation time 553606518835 ps
CPU time 1057.35 seconds
Started Aug 01 06:02:02 PM PDT 24
Finished Aug 01 06:19:40 PM PDT 24
Peak memory 297864 kb
Host smart-3f2aa904-19f8-48bd-993b-6f9295cf215c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008462663 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.4008462663
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.2432317612
Short name T830
Test name
Test status
Simulation time 201513213 ps
CPU time 3.85 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:01 PM PDT 24
Peak memory 241948 kb
Host smart-2bde577e-1c13-4e34-a338-166562d7a5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432317612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.2432317612
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.3937056907
Short name T639
Test name
Test status
Simulation time 432177828 ps
CPU time 7.09 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:04 PM PDT 24
Peak memory 241940 kb
Host smart-4cc1b415-0a88-4bac-984e-81a1d5e02624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937056907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.3937056907
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.2687352438
Short name T575
Test name
Test status
Simulation time 290599254 ps
CPU time 3.97 seconds
Started Aug 01 06:01:57 PM PDT 24
Finished Aug 01 06:02:01 PM PDT 24
Peak memory 242344 kb
Host smart-0e8dafd2-7c2b-487b-97e4-29b3849494e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687352438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2687352438
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.2566833021
Short name T712
Test name
Test status
Simulation time 142799183 ps
CPU time 6.66 seconds
Started Aug 01 06:02:02 PM PDT 24
Finished Aug 01 06:02:09 PM PDT 24
Peak memory 241908 kb
Host smart-8a147c71-43c6-4ebd-9aec-b5f1c2776a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566833021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.2566833021
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest
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