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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.86 93.79 96.25 95.51 91.89 97.05 96.34 93.21


Total test records in report: 1324
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T1263 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.216081133 Aug 06 05:40:50 PM PDT 24 Aug 06 05:40:53 PM PDT 24 1676805087 ps
T1264 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2407402176 Aug 06 05:40:50 PM PDT 24 Aug 06 05:40:53 PM PDT 24 279449998 ps
T1265 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.103175432 Aug 06 05:40:25 PM PDT 24 Aug 06 05:40:27 PM PDT 24 595606396 ps
T1266 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.170751159 Aug 06 05:40:05 PM PDT 24 Aug 06 05:40:07 PM PDT 24 559566060 ps
T1267 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2708160994 Aug 06 05:41:14 PM PDT 24 Aug 06 05:41:15 PM PDT 24 40786940 ps
T336 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1286336117 Aug 06 05:40:49 PM PDT 24 Aug 06 05:41:09 PM PDT 24 1325069735 ps
T339 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2611710711 Aug 06 05:40:10 PM PDT 24 Aug 06 05:40:21 PM PDT 24 2469565368 ps
T1268 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2219591104 Aug 06 05:40:51 PM PDT 24 Aug 06 05:40:55 PM PDT 24 385752646 ps
T340 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3642016090 Aug 06 05:40:30 PM PDT 24 Aug 06 05:40:40 PM PDT 24 1213427201 ps
T1269 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2855741700 Aug 06 05:40:48 PM PDT 24 Aug 06 05:40:59 PM PDT 24 2513342824 ps
T1270 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1425323897 Aug 06 05:40:06 PM PDT 24 Aug 06 05:40:08 PM PDT 24 86180184 ps
T344 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3653271350 Aug 06 05:40:25 PM PDT 24 Aug 06 05:40:41 PM PDT 24 10340161546 ps
T300 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.341444163 Aug 06 05:40:07 PM PDT 24 Aug 06 05:40:12 PM PDT 24 77970323 ps
T1271 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1343541348 Aug 06 05:40:10 PM PDT 24 Aug 06 05:40:11 PM PDT 24 130435199 ps
T1272 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3458847068 Aug 06 05:40:27 PM PDT 24 Aug 06 05:40:31 PM PDT 24 214883027 ps
T1273 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3017117433 Aug 06 05:40:06 PM PDT 24 Aug 06 05:40:09 PM PDT 24 1035169461 ps
T1274 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.705522856 Aug 06 05:41:11 PM PDT 24 Aug 06 05:41:12 PM PDT 24 146580628 ps
T1275 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3932601278 Aug 06 05:40:50 PM PDT 24 Aug 06 05:40:52 PM PDT 24 108803731 ps
T1276 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3595989513 Aug 06 05:40:27 PM PDT 24 Aug 06 05:40:34 PM PDT 24 181230880 ps
T343 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.494483047 Aug 06 05:40:08 PM PDT 24 Aug 06 05:40:18 PM PDT 24 2452688986 ps
T341 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1182995593 Aug 06 05:40:27 PM PDT 24 Aug 06 05:40:37 PM PDT 24 1239610819 ps
T1277 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1212788165 Aug 06 05:40:08 PM PDT 24 Aug 06 05:40:10 PM PDT 24 97364730 ps
T1278 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1899001367 Aug 06 05:40:04 PM PDT 24 Aug 06 05:40:23 PM PDT 24 1531057193 ps
T1279 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.159295566 Aug 06 05:40:51 PM PDT 24 Aug 06 05:40:54 PM PDT 24 1279576022 ps
T1280 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.1289392438 Aug 06 05:40:52 PM PDT 24 Aug 06 05:40:53 PM PDT 24 52413936 ps
T1281 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.302076462 Aug 06 05:40:48 PM PDT 24 Aug 06 05:40:55 PM PDT 24 316471025 ps
T1282 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2874029581 Aug 06 05:41:13 PM PDT 24 Aug 06 05:41:15 PM PDT 24 75008930 ps
T1283 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.831424729 Aug 06 05:40:24 PM PDT 24 Aug 06 05:40:25 PM PDT 24 46002908 ps
T1284 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3982702668 Aug 06 05:40:48 PM PDT 24 Aug 06 05:40:49 PM PDT 24 70427960 ps
T1285 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.422754964 Aug 06 05:40:26 PM PDT 24 Aug 06 05:40:45 PM PDT 24 2482772134 ps
T1286 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3424697671 Aug 06 05:40:06 PM PDT 24 Aug 06 05:40:07 PM PDT 24 72524477 ps
T1287 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1039764184 Aug 06 05:40:25 PM PDT 24 Aug 06 05:40:28 PM PDT 24 112190661 ps
T1288 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.2492814958 Aug 06 05:40:08 PM PDT 24 Aug 06 05:40:09 PM PDT 24 43343504 ps
T1289 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1145767511 Aug 06 05:40:04 PM PDT 24 Aug 06 05:40:06 PM PDT 24 94861173 ps
T1290 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1840351816 Aug 06 05:40:25 PM PDT 24 Aug 06 05:40:26 PM PDT 24 43347920 ps
T1291 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.581779418 Aug 06 05:40:10 PM PDT 24 Aug 06 05:40:12 PM PDT 24 83373036 ps
T1292 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3392564642 Aug 06 05:40:26 PM PDT 24 Aug 06 05:40:29 PM PDT 24 1507745245 ps
T337 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2146929452 Aug 06 05:40:12 PM PDT 24 Aug 06 05:40:32 PM PDT 24 2793032088 ps
T342 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1354820976 Aug 06 05:40:51 PM PDT 24 Aug 06 05:41:02 PM PDT 24 732457084 ps
T1293 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.1097708424 Aug 06 05:41:14 PM PDT 24 Aug 06 05:41:16 PM PDT 24 576926468 ps
T1294 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3787096726 Aug 06 05:40:06 PM PDT 24 Aug 06 05:40:18 PM PDT 24 1507478570 ps
T1295 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3357282353 Aug 06 05:41:13 PM PDT 24 Aug 06 05:41:15 PM PDT 24 558229303 ps
T1296 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.4214375135 Aug 06 05:40:49 PM PDT 24 Aug 06 05:40:52 PM PDT 24 156250633 ps
T1297 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.595530984 Aug 06 05:40:09 PM PDT 24 Aug 06 05:40:13 PM PDT 24 98465310 ps
T1298 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1315180628 Aug 06 05:40:48 PM PDT 24 Aug 06 05:40:59 PM PDT 24 10202693807 ps
T1299 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.4257192184 Aug 06 05:40:10 PM PDT 24 Aug 06 05:40:11 PM PDT 24 68525196 ps
T1300 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1547237462 Aug 06 05:40:49 PM PDT 24 Aug 06 05:40:50 PM PDT 24 72598700 ps
T1301 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3005242216 Aug 06 05:40:04 PM PDT 24 Aug 06 05:40:06 PM PDT 24 68444373 ps
T1302 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2991808543 Aug 06 05:40:07 PM PDT 24 Aug 06 05:40:13 PM PDT 24 249401209 ps
T1303 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1584726527 Aug 06 05:40:04 PM PDT 24 Aug 06 05:40:07 PM PDT 24 210261959 ps
T1304 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3694534162 Aug 06 05:40:49 PM PDT 24 Aug 06 05:40:52 PM PDT 24 371804652 ps
T1305 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2640755791 Aug 06 05:40:26 PM PDT 24 Aug 06 05:40:30 PM PDT 24 196581452 ps
T1306 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1766496978 Aug 06 05:40:28 PM PDT 24 Aug 06 05:40:31 PM PDT 24 189992016 ps
T1307 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.62698755 Aug 06 05:40:49 PM PDT 24 Aug 06 05:40:50 PM PDT 24 38137413 ps
T1308 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.4255743261 Aug 06 05:40:08 PM PDT 24 Aug 06 05:40:10 PM PDT 24 134666102 ps
T301 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2130656226 Aug 06 05:40:06 PM PDT 24 Aug 06 05:40:08 PM PDT 24 70594253 ps
T1309 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2681624450 Aug 06 05:41:11 PM PDT 24 Aug 06 05:41:12 PM PDT 24 69864737 ps
T1310 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3537260530 Aug 06 05:40:49 PM PDT 24 Aug 06 05:40:50 PM PDT 24 57711662 ps
T1311 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.490000771 Aug 06 05:40:10 PM PDT 24 Aug 06 05:40:14 PM PDT 24 105968145 ps
T1312 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.276290533 Aug 06 05:40:48 PM PDT 24 Aug 06 05:40:55 PM PDT 24 583467591 ps
T1313 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.4272122610 Aug 06 05:40:11 PM PDT 24 Aug 06 05:40:15 PM PDT 24 278528091 ps
T1314 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.2121053676 Aug 06 05:40:52 PM PDT 24 Aug 06 05:40:53 PM PDT 24 582753207 ps
T303 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3276305172 Aug 06 05:40:50 PM PDT 24 Aug 06 05:40:52 PM PDT 24 166522593 ps
T1315 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.3884677978 Aug 06 05:40:52 PM PDT 24 Aug 06 05:40:54 PM PDT 24 41390230 ps
T1316 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3724596289 Aug 06 05:40:25 PM PDT 24 Aug 06 05:40:28 PM PDT 24 357742136 ps
T302 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1654115837 Aug 06 05:40:07 PM PDT 24 Aug 06 05:40:14 PM PDT 24 1996834845 ps
T1317 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.481272501 Aug 06 05:40:47 PM PDT 24 Aug 06 05:40:48 PM PDT 24 128301875 ps
T1318 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.972469774 Aug 06 05:41:12 PM PDT 24 Aug 06 05:41:13 PM PDT 24 70591596 ps
T1319 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1751059087 Aug 06 05:40:10 PM PDT 24 Aug 06 05:40:12 PM PDT 24 67885916 ps
T1320 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1111488447 Aug 06 05:40:50 PM PDT 24 Aug 06 05:40:53 PM PDT 24 126985472 ps
T1321 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.74252007 Aug 06 05:40:26 PM PDT 24 Aug 06 05:40:28 PM PDT 24 52564983 ps
T1322 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3910257189 Aug 06 05:40:29 PM PDT 24 Aug 06 05:40:35 PM PDT 24 154311646 ps
T1323 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3766420226 Aug 06 05:40:07 PM PDT 24 Aug 06 05:40:13 PM PDT 24 269871512 ps
T1324 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1147130012 Aug 06 05:40:04 PM PDT 24 Aug 06 05:40:06 PM PDT 24 74976626 ps

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.3453165342
Short name T4
Test name
Test status
Simulation time 151123501256 ps
CPU time 1037.46 seconds
Started Aug 06 05:35:00 PM PDT 24
Finished Aug 06 05:52:18 PM PDT 24
Peak memory 268788 kb
Host smart-3c0f59fd-311f-49ad-acab-2b8199e5e197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453165342 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.3453165342
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.3563514996
Short name T5
Test name
Test status
Simulation time 13556020026 ps
CPU time 208.99 seconds
Started Aug 06 05:36:29 PM PDT 24
Finished Aug 06 05:39:59 PM PDT 24
Peak memory 250056 kb
Host smart-ea98902f-eb00-4e53-9922-ceb8552822b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563514996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.3563514996
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.1668437144
Short name T203
Test name
Test status
Simulation time 150704609052 ps
CPU time 200.48 seconds
Started Aug 06 05:32:42 PM PDT 24
Finished Aug 06 05:36:03 PM PDT 24
Peak memory 273104 kb
Host smart-a15fffc7-2f6b-49c7-9b6b-d9475a4bd57b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668437144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.1668437144
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.4201723004
Short name T73
Test name
Test status
Simulation time 134237720 ps
CPU time 3.77 seconds
Started Aug 06 05:38:40 PM PDT 24
Finished Aug 06 05:38:44 PM PDT 24
Peak memory 242304 kb
Host smart-b3bd2847-515f-4156-a155-621ee1352285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201723004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.4201723004
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.1303817403
Short name T236
Test name
Test status
Simulation time 41573430191 ps
CPU time 218.81 seconds
Started Aug 06 05:31:32 PM PDT 24
Finished Aug 06 05:35:11 PM PDT 24
Peak memory 268240 kb
Host smart-d7ecc535-5037-444f-a24a-6bb7ba198242
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303817403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1303817403
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.3490542153
Short name T94
Test name
Test status
Simulation time 7379963005 ps
CPU time 207.38 seconds
Started Aug 06 05:33:48 PM PDT 24
Finished Aug 06 05:37:16 PM PDT 24
Peak memory 248536 kb
Host smart-78b758f0-6667-4366-a8ea-43b7ac2b96e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490542153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.3490542153
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.254321016
Short name T19
Test name
Test status
Simulation time 172741582041 ps
CPU time 1943.54 seconds
Started Aug 06 05:36:59 PM PDT 24
Finished Aug 06 06:09:23 PM PDT 24
Peak memory 386856 kb
Host smart-e97c81ec-f9c4-444f-9a31-6f83dbf96b8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254321016 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.254321016
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.2791247042
Short name T11
Test name
Test status
Simulation time 399315934 ps
CPU time 5.06 seconds
Started Aug 06 05:36:46 PM PDT 24
Finished Aug 06 05:36:51 PM PDT 24
Peak memory 242128 kb
Host smart-604220d6-b8f1-423a-80c7-52f477cdc29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791247042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.2791247042
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.3345577450
Short name T38
Test name
Test status
Simulation time 6976083609 ps
CPU time 40.5 seconds
Started Aug 06 05:34:25 PM PDT 24
Finished Aug 06 05:35:06 PM PDT 24
Peak memory 245396 kb
Host smart-2a45c0f9-93b9-456e-8818-ffb6f28d1771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345577450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.3345577450
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.1714082185
Short name T6
Test name
Test status
Simulation time 184822552091 ps
CPU time 1777.86 seconds
Started Aug 06 05:32:42 PM PDT 24
Finished Aug 06 06:02:20 PM PDT 24
Peak memory 318672 kb
Host smart-2a2f89bb-13db-4fcf-887b-04b2d4989e7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714082185 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.1714082185
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3814421068
Short name T271
Test name
Test status
Simulation time 1503358854 ps
CPU time 19.99 seconds
Started Aug 06 05:40:50 PM PDT 24
Finished Aug 06 05:41:10 PM PDT 24
Peak memory 243960 kb
Host smart-e08da4e6-3239-402a-82a3-03ff1b48f909
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814421068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.3814421068
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.3417045728
Short name T87
Test name
Test status
Simulation time 712641496 ps
CPU time 28.39 seconds
Started Aug 06 05:34:23 PM PDT 24
Finished Aug 06 05:34:52 PM PDT 24
Peak memory 245812 kb
Host smart-a09613b6-4b8a-4435-b59f-993db9d86983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417045728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.3417045728
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.1815939277
Short name T263
Test name
Test status
Simulation time 22812177501 ps
CPU time 88.44 seconds
Started Aug 06 05:34:47 PM PDT 24
Finished Aug 06 05:36:15 PM PDT 24
Peak memory 246816 kb
Host smart-03f66569-0e70-471e-8ae4-05be62b922b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815939277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.1815939277
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.2961517679
Short name T51
Test name
Test status
Simulation time 369858563 ps
CPU time 5.11 seconds
Started Aug 06 05:33:04 PM PDT 24
Finished Aug 06 05:33:09 PM PDT 24
Peak memory 241992 kb
Host smart-2a5e7623-5359-4432-afba-8d21ea14383d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961517679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.2961517679
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.185059942
Short name T46
Test name
Test status
Simulation time 255626181 ps
CPU time 3.51 seconds
Started Aug 06 05:39:02 PM PDT 24
Finished Aug 06 05:39:05 PM PDT 24
Peak memory 242028 kb
Host smart-38a72c5e-81ac-462f-a77d-7df716877aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185059942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.185059942
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.3464874275
Short name T33
Test name
Test status
Simulation time 200827232 ps
CPU time 4.75 seconds
Started Aug 06 05:36:59 PM PDT 24
Finished Aug 06 05:37:04 PM PDT 24
Peak memory 242024 kb
Host smart-9e9ba8f2-75f6-4cb7-8401-5ebddf183a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464874275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.3464874275
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.107382251
Short name T123
Test name
Test status
Simulation time 1725311496 ps
CPU time 5.12 seconds
Started Aug 06 05:39:07 PM PDT 24
Finished Aug 06 05:39:12 PM PDT 24
Peak memory 241968 kb
Host smart-d4c1f1ee-f283-416a-a76d-1c87e21c29f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107382251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.107382251
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.1219489908
Short name T76
Test name
Test status
Simulation time 7300924956 ps
CPU time 71.16 seconds
Started Aug 06 05:33:04 PM PDT 24
Finished Aug 06 05:34:16 PM PDT 24
Peak memory 248616 kb
Host smart-433c3f56-be35-4c63-8471-81205cd99c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219489908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1219489908
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.3289148217
Short name T376
Test name
Test status
Simulation time 889499160 ps
CPU time 2.15 seconds
Started Aug 06 05:33:09 PM PDT 24
Finished Aug 06 05:33:11 PM PDT 24
Peak memory 240608 kb
Host smart-92b1c8e3-6c91-491f-8d28-416e3a269abd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289148217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.3289148217
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.2589717596
Short name T186
Test name
Test status
Simulation time 1744940921 ps
CPU time 7.94 seconds
Started Aug 06 05:38:28 PM PDT 24
Finished Aug 06 05:38:36 PM PDT 24
Peak memory 241992 kb
Host smart-125bd1c7-54c3-441c-be7f-c4edbaa41a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589717596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.2589717596
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.3885873985
Short name T53
Test name
Test status
Simulation time 355295647 ps
CPU time 5.07 seconds
Started Aug 06 05:38:29 PM PDT 24
Finished Aug 06 05:38:34 PM PDT 24
Peak memory 241904 kb
Host smart-89f73384-ce65-401d-9288-3dc61ce38d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885873985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.3885873985
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.668206269
Short name T88
Test name
Test status
Simulation time 21727553548 ps
CPU time 130.32 seconds
Started Aug 06 05:34:23 PM PDT 24
Finished Aug 06 05:36:33 PM PDT 24
Peak memory 277876 kb
Host smart-45a46498-e73d-437e-9a3d-04b58c91bcc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668206269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.
668206269
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.1304510612
Short name T62
Test name
Test status
Simulation time 213241750 ps
CPU time 5 seconds
Started Aug 06 05:38:00 PM PDT 24
Finished Aug 06 05:38:05 PM PDT 24
Peak memory 241880 kb
Host smart-a43114bc-ed41-47e5-894e-cec8bca7a9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304510612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.1304510612
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.1410616134
Short name T58
Test name
Test status
Simulation time 134375106 ps
CPU time 4.21 seconds
Started Aug 06 05:36:30 PM PDT 24
Finished Aug 06 05:36:35 PM PDT 24
Peak memory 242232 kb
Host smart-71c47837-05a8-4b37-a2ce-6bcb1406d52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410616134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.1410616134
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.893323721
Short name T166
Test name
Test status
Simulation time 297333909 ps
CPU time 4.02 seconds
Started Aug 06 05:33:02 PM PDT 24
Finished Aug 06 05:33:06 PM PDT 24
Peak memory 242056 kb
Host smart-ed911b4b-a17e-45a2-9dbf-2c1f3c490bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893323721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.893323721
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.2527823980
Short name T172
Test name
Test status
Simulation time 551701719 ps
CPU time 4.14 seconds
Started Aug 06 05:34:05 PM PDT 24
Finished Aug 06 05:34:09 PM PDT 24
Peak memory 242352 kb
Host smart-ef4e445e-11ea-4112-a60c-0060b25fc6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527823980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.2527823980
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.3008916254
Short name T235
Test name
Test status
Simulation time 11295049727 ps
CPU time 158.85 seconds
Started Aug 06 05:33:23 PM PDT 24
Finished Aug 06 05:36:02 PM PDT 24
Peak memory 248636 kb
Host smart-7fe0173a-7b67-4ea6-b09f-2ee97f761207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008916254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.3008916254
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.3597857970
Short name T9
Test name
Test status
Simulation time 240548328 ps
CPU time 4.32 seconds
Started Aug 06 05:32:02 PM PDT 24
Finished Aug 06 05:32:06 PM PDT 24
Peak memory 242232 kb
Host smart-91e010a5-c14c-4464-aef9-f364260dc7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597857970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.3597857970
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.2852830144
Short name T439
Test name
Test status
Simulation time 150382710 ps
CPU time 3.79 seconds
Started Aug 06 05:33:03 PM PDT 24
Finished Aug 06 05:33:07 PM PDT 24
Peak memory 242384 kb
Host smart-e35af094-d2cf-4fdc-869c-3dc6216d1fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852830144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.2852830144
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.3065837726
Short name T40
Test name
Test status
Simulation time 194852373 ps
CPU time 4.91 seconds
Started Aug 06 05:38:12 PM PDT 24
Finished Aug 06 05:38:17 PM PDT 24
Peak memory 242076 kb
Host smart-10502169-7b0e-42fa-80bf-b3b4cac340b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065837726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.3065837726
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.1756365359
Short name T77
Test name
Test status
Simulation time 4136196958 ps
CPU time 28.9 seconds
Started Aug 06 05:31:00 PM PDT 24
Finished Aug 06 05:31:29 PM PDT 24
Peak memory 248616 kb
Host smart-2676796d-4705-4738-9d11-2157d8f9767c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756365359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.1756365359
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.3585275210
Short name T161
Test name
Test status
Simulation time 4270902751 ps
CPU time 43.05 seconds
Started Aug 06 05:31:47 PM PDT 24
Finished Aug 06 05:32:30 PM PDT 24
Peak memory 248704 kb
Host smart-518f8cc9-000f-47da-b110-e34ce3d6177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585275210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.3585275210
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.480595519
Short name T370
Test name
Test status
Simulation time 20117515235 ps
CPU time 220.09 seconds
Started Aug 06 05:33:04 PM PDT 24
Finished Aug 06 05:36:45 PM PDT 24
Peak memory 297860 kb
Host smart-fb084bae-ed40-4ac2-852a-77d0a4fb120d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480595519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.
480595519
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.1227703245
Short name T74
Test name
Test status
Simulation time 1107213904 ps
CPU time 11.61 seconds
Started Aug 06 05:38:12 PM PDT 24
Finished Aug 06 05:38:23 PM PDT 24
Peak memory 248572 kb
Host smart-65b02b32-0c99-4f41-9ac2-2fabfbaaa24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227703245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.1227703245
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.1345397462
Short name T124
Test name
Test status
Simulation time 255067005954 ps
CPU time 609.51 seconds
Started Aug 06 05:35:20 PM PDT 24
Finished Aug 06 05:45:30 PM PDT 24
Peak memory 282540 kb
Host smart-3d6d4a1f-c310-460e-a0f0-e913d87e5053
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345397462 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.1345397462
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.2241004637
Short name T149
Test name
Test status
Simulation time 1657423920 ps
CPU time 3.67 seconds
Started Aug 06 05:35:21 PM PDT 24
Finished Aug 06 05:35:25 PM PDT 24
Peak memory 241936 kb
Host smart-78af8596-6fae-4f7c-ba32-584d6c631b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241004637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2241004637
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.4194707343
Short name T204
Test name
Test status
Simulation time 50427172119 ps
CPU time 224.8 seconds
Started Aug 06 05:33:31 PM PDT 24
Finished Aug 06 05:37:17 PM PDT 24
Peak memory 259568 kb
Host smart-0a1c4e2e-0857-4342-906b-da9b7ec2e69c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194707343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.4194707343
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.1211654436
Short name T234
Test name
Test status
Simulation time 305297925 ps
CPU time 10.22 seconds
Started Aug 06 05:33:22 PM PDT 24
Finished Aug 06 05:33:33 PM PDT 24
Peak memory 241920 kb
Host smart-f889c802-5062-444f-8c69-a57fc3673448
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211654436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.1211654436
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.2127825018
Short name T43
Test name
Test status
Simulation time 123318800 ps
CPU time 3.54 seconds
Started Aug 06 05:36:32 PM PDT 24
Finished Aug 06 05:36:36 PM PDT 24
Peak memory 242128 kb
Host smart-a13704fa-cd99-40b6-83fb-920d368ed5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127825018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.2127825018
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.3744088161
Short name T252
Test name
Test status
Simulation time 1867979718 ps
CPU time 5.06 seconds
Started Aug 06 05:38:25 PM PDT 24
Finished Aug 06 05:38:30 PM PDT 24
Peak memory 241852 kb
Host smart-633d1d91-ea0d-4d04-a1b1-2cfd5eb7c2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744088161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.3744088161
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1286336117
Short name T336
Test name
Test status
Simulation time 1325069735 ps
CPU time 20.01 seconds
Started Aug 06 05:40:49 PM PDT 24
Finished Aug 06 05:41:09 PM PDT 24
Peak memory 238824 kb
Host smart-daf4cc75-8ef9-4276-97fe-5ed0d567f00e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286336117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.1286336117
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.586863323
Short name T113
Test name
Test status
Simulation time 2106649393 ps
CPU time 28.41 seconds
Started Aug 06 05:34:07 PM PDT 24
Finished Aug 06 05:34:35 PM PDT 24
Peak memory 245196 kb
Host smart-adc3e5d6-c000-4da5-99d0-b0c6dcbc5a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586863323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.586863323
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.2683940707
Short name T27
Test name
Test status
Simulation time 8290799908 ps
CPU time 15.74 seconds
Started Aug 06 05:36:12 PM PDT 24
Finished Aug 06 05:36:28 PM PDT 24
Peak memory 248588 kb
Host smart-e0ff232a-ad62-4db5-9822-6a9a431d9745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683940707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.2683940707
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.508998780
Short name T69
Test name
Test status
Simulation time 377796761 ps
CPU time 4.26 seconds
Started Aug 06 05:36:43 PM PDT 24
Finished Aug 06 05:36:48 PM PDT 24
Peak memory 242196 kb
Host smart-da70e295-1bde-478c-b5ac-af9d274a5040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508998780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.508998780
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.957688748
Short name T808
Test name
Test status
Simulation time 38060888280 ps
CPU time 839.43 seconds
Started Aug 06 05:33:01 PM PDT 24
Finished Aug 06 05:47:01 PM PDT 24
Peak memory 278844 kb
Host smart-be3feff6-05f9-47ec-80f1-5fdeb2a2d64e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957688748 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.957688748
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.1330052323
Short name T281
Test name
Test status
Simulation time 657472947594 ps
CPU time 1571.77 seconds
Started Aug 06 05:37:08 PM PDT 24
Finished Aug 06 06:03:20 PM PDT 24
Peak memory 364332 kb
Host smart-e523b024-fb0d-4e12-9af7-3ac7e36da2de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330052323 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.1330052323
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.2340340991
Short name T68
Test name
Test status
Simulation time 212329407 ps
CPU time 9.94 seconds
Started Aug 06 05:36:46 PM PDT 24
Finished Aug 06 05:36:56 PM PDT 24
Peak memory 242000 kb
Host smart-63aba11a-af3b-4bba-9aeb-569b97accf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340340991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2340340991
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.3535909307
Short name T127
Test name
Test status
Simulation time 1033704488 ps
CPU time 13.14 seconds
Started Aug 06 05:31:30 PM PDT 24
Finished Aug 06 05:31:44 PM PDT 24
Peak memory 242444 kb
Host smart-606dcb0b-162b-4c81-8ea0-fe49af87fd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535909307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.3535909307
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.3866846360
Short name T142
Test name
Test status
Simulation time 295051763 ps
CPU time 17.55 seconds
Started Aug 06 05:37:09 PM PDT 24
Finished Aug 06 05:37:27 PM PDT 24
Peak memory 241752 kb
Host smart-0884577a-8758-405a-af2f-5ad480a21530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866846360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.3866846360
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.3054184135
Short name T52
Test name
Test status
Simulation time 2920086888 ps
CPU time 20.14 seconds
Started Aug 06 05:33:04 PM PDT 24
Finished Aug 06 05:33:24 PM PDT 24
Peak memory 247228 kb
Host smart-3a7d58c5-4813-4204-96a2-db2cd921eaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054184135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.3054184135
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.3830358978
Short name T1121
Test name
Test status
Simulation time 36215595606 ps
CPU time 151.69 seconds
Started Aug 06 05:30:53 PM PDT 24
Finished Aug 06 05:33:25 PM PDT 24
Peak memory 258112 kb
Host smart-d08f971e-ef20-4742-b314-b2c0eecdd110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830358978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
3830358978
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.3254299877
Short name T81
Test name
Test status
Simulation time 279213894 ps
CPU time 10.19 seconds
Started Aug 06 05:32:42 PM PDT 24
Finished Aug 06 05:32:52 PM PDT 24
Peak memory 242596 kb
Host smart-6ee96c62-d68a-4499-a988-8c9d608fd879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254299877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.3254299877
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.2645614214
Short name T251
Test name
Test status
Simulation time 1177570034 ps
CPU time 9.61 seconds
Started Aug 06 05:37:35 PM PDT 24
Finished Aug 06 05:37:44 PM PDT 24
Peak memory 241952 kb
Host smart-13a3ee54-22a9-4c89-9e0b-89aded1a2e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645614214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.2645614214
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.2784222472
Short name T265
Test name
Test status
Simulation time 204770385 ps
CPU time 10.07 seconds
Started Aug 06 05:38:13 PM PDT 24
Finished Aug 06 05:38:23 PM PDT 24
Peak memory 241820 kb
Host smart-f015053e-9f39-4bae-96ac-d17dbc97202d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784222472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.2784222472
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.3260651010
Short name T207
Test name
Test status
Simulation time 1214776143 ps
CPU time 18.54 seconds
Started Aug 06 05:38:17 PM PDT 24
Finished Aug 06 05:38:35 PM PDT 24
Peak memory 241968 kb
Host smart-42bd674a-e26f-476c-91cd-6027f913c500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260651010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.3260651010
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.154073371
Short name T141
Test name
Test status
Simulation time 540182994 ps
CPU time 15.44 seconds
Started Aug 06 05:36:05 PM PDT 24
Finished Aug 06 05:36:21 PM PDT 24
Peak memory 241964 kb
Host smart-2fb053aa-4557-41d4-9ed2-34fc58b3ede8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154073371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.154073371
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.902519415
Short name T226
Test name
Test status
Simulation time 2373179194 ps
CPU time 5.02 seconds
Started Aug 06 05:38:42 PM PDT 24
Finished Aug 06 05:38:47 PM PDT 24
Peak memory 242296 kb
Host smart-1734da5f-0f16-452f-b248-a733efde7831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902519415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.902519415
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.3296080387
Short name T596
Test name
Test status
Simulation time 4085369108 ps
CPU time 10.65 seconds
Started Aug 06 05:31:05 PM PDT 24
Finished Aug 06 05:31:16 PM PDT 24
Peak memory 242112 kb
Host smart-82cbe2c4-b822-4c41-87dd-01e6f0d714f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296080387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3296080387
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3961670450
Short name T293
Test name
Test status
Simulation time 50847683 ps
CPU time 1.65 seconds
Started Aug 06 05:40:27 PM PDT 24
Finished Aug 06 05:40:28 PM PDT 24
Peak memory 238716 kb
Host smart-73ca76d2-7812-4c2d-8dcb-16f62be05b84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961670450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3961670450
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.1992516990
Short name T128
Test name
Test status
Simulation time 20545865163 ps
CPU time 43.15 seconds
Started Aug 06 05:32:02 PM PDT 24
Finished Aug 06 05:32:46 PM PDT 24
Peak memory 243636 kb
Host smart-e259e2da-d7e3-4a19-8709-7d53faf78b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992516990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1992516990
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.2447125444
Short name T194
Test name
Test status
Simulation time 2085315077 ps
CPU time 27.98 seconds
Started Aug 06 05:31:59 PM PDT 24
Finished Aug 06 05:32:27 PM PDT 24
Peak memory 242204 kb
Host smart-89aec7c4-6c99-4d59-a5ef-4f8447314c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447125444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2447125444
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.1263184873
Short name T606
Test name
Test status
Simulation time 643041293 ps
CPU time 9.56 seconds
Started Aug 06 05:33:48 PM PDT 24
Finished Aug 06 05:33:58 PM PDT 24
Peak memory 242004 kb
Host smart-1c3b20d5-c196-443f-af70-bd1ed38e375d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1263184873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.1263184873
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.2621413101
Short name T249
Test name
Test status
Simulation time 232670554564 ps
CPU time 734.49 seconds
Started Aug 06 05:37:10 PM PDT 24
Finished Aug 06 05:49:24 PM PDT 24
Peak memory 279532 kb
Host smart-0b3efb53-6473-48bc-865c-9c17753605cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621413101 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.2621413101
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.3433322525
Short name T14
Test name
Test status
Simulation time 6067880870 ps
CPU time 92.72 seconds
Started Aug 06 05:35:59 PM PDT 24
Finished Aug 06 05:37:32 PM PDT 24
Peak memory 248592 kb
Host smart-8d5ac4f6-0036-4fa1-86df-585aa5705aca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433322525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.3433322525
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.2520967288
Short name T243
Test name
Test status
Simulation time 399136329 ps
CPU time 10.09 seconds
Started Aug 06 05:36:00 PM PDT 24
Finished Aug 06 05:36:10 PM PDT 24
Peak memory 242092 kb
Host smart-574e76e6-9641-4597-8d16-305fccb908f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520967288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.2520967288
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.203826605
Short name T83
Test name
Test status
Simulation time 5131864000 ps
CPU time 10.66 seconds
Started Aug 06 05:32:19 PM PDT 24
Finished Aug 06 05:32:29 PM PDT 24
Peak memory 243028 kb
Host smart-0e463f2d-0cbf-4b45-98f7-7a04e6357f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203826605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.203826605
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.3489385033
Short name T59
Test name
Test status
Simulation time 1326614312 ps
CPU time 25.19 seconds
Started Aug 06 05:36:14 PM PDT 24
Finished Aug 06 05:36:40 PM PDT 24
Peak memory 248564 kb
Host smart-f3de9f62-ce63-44c1-9d5c-752e49fd5328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489385033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.3489385033
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1435775613
Short name T290
Test name
Test status
Simulation time 51356481 ps
CPU time 1.75 seconds
Started Aug 06 05:40:09 PM PDT 24
Finished Aug 06 05:40:11 PM PDT 24
Peak memory 241012 kb
Host smart-12ba916e-4a26-4ee8-94a0-b11958c66367
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435775613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1435775613
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.2130682520
Short name T1057
Test name
Test status
Simulation time 116122010 ps
CPU time 3.97 seconds
Started Aug 06 05:37:47 PM PDT 24
Finished Aug 06 05:37:51 PM PDT 24
Peak memory 241972 kb
Host smart-18058ef8-bbe9-4337-88ef-4f605219ca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130682520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2130682520
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.2472191367
Short name T195
Test name
Test status
Simulation time 134857612 ps
CPU time 4.17 seconds
Started Aug 06 05:37:56 PM PDT 24
Finished Aug 06 05:38:00 PM PDT 24
Peak memory 241992 kb
Host smart-1b8abf11-9b9b-42ae-80df-5d31dad1a712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472191367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.2472191367
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.12482224
Short name T278
Test name
Test status
Simulation time 37088880455 ps
CPU time 681.64 seconds
Started Aug 06 05:31:59 PM PDT 24
Finished Aug 06 05:43:21 PM PDT 24
Peak memory 266944 kb
Host smart-08c9127e-4e10-4cc8-8dea-d92e06003f4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12482224 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.12482224
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3653271350
Short name T344
Test name
Test status
Simulation time 10340161546 ps
CPU time 15.83 seconds
Started Aug 06 05:40:25 PM PDT 24
Finished Aug 06 05:40:41 PM PDT 24
Peak memory 244240 kb
Host smart-31622374-b311-4668-a3aa-70d56721c45b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653271350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.3653271350
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3642016090
Short name T340
Test name
Test status
Simulation time 1213427201 ps
CPU time 9.17 seconds
Started Aug 06 05:40:30 PM PDT 24
Finished Aug 06 05:40:40 PM PDT 24
Peak memory 238784 kb
Host smart-b1766c18-3339-4eeb-bc86-1faccc9924b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642016090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.3642016090
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2611710711
Short name T339
Test name
Test status
Simulation time 2469565368 ps
CPU time 10.91 seconds
Started Aug 06 05:40:10 PM PDT 24
Finished Aug 06 05:40:21 PM PDT 24
Peak memory 243844 kb
Host smart-a23269d4-c08d-4ff7-9777-ca010e195ccd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611710711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.2611710711
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.1168991478
Short name T541
Test name
Test status
Simulation time 156260624 ps
CPU time 6.72 seconds
Started Aug 06 05:37:45 PM PDT 24
Finished Aug 06 05:37:52 PM PDT 24
Peak memory 242204 kb
Host smart-fbdeb786-11a0-46d8-a1f1-cdefe5638d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168991478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.1168991478
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.3892098287
Short name T64
Test name
Test status
Simulation time 245318914 ps
CPU time 3.52 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:38 PM PDT 24
Peak memory 242332 kb
Host smart-12138b16-0084-4cb0-b890-338390f6d472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892098287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.3892098287
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.3402501319
Short name T162
Test name
Test status
Simulation time 738005141 ps
CPU time 2 seconds
Started Aug 06 05:30:54 PM PDT 24
Finished Aug 06 05:30:56 PM PDT 24
Peak memory 240428 kb
Host smart-7431c8ee-aab9-4e24-a1f0-d328c7ac2b6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3402501319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.3402501319
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.4113176673
Short name T82
Test name
Test status
Simulation time 264929562 ps
CPU time 3.34 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:10 PM PDT 24
Peak memory 242108 kb
Host smart-653f45b6-e48c-48d7-aba8-0f4d1c63057a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113176673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.4113176673
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3160305680
Short name T270
Test name
Test status
Simulation time 1263745019 ps
CPU time 11.43 seconds
Started Aug 06 05:40:28 PM PDT 24
Finished Aug 06 05:40:40 PM PDT 24
Peak memory 243612 kb
Host smart-801b90a1-fa82-4415-b83d-1fc6273089a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160305680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.3160305680
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3880486750
Short name T277
Test name
Test status
Simulation time 714607959 ps
CPU time 10.61 seconds
Started Aug 06 05:40:22 PM PDT 24
Finished Aug 06 05:40:33 PM PDT 24
Peak memory 243496 kb
Host smart-eb76e9a8-9093-41d2-94c9-2c88c6184fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880486750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.3880486750
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.4054803270
Short name T131
Test name
Test status
Simulation time 400781866 ps
CPU time 4.04 seconds
Started Aug 06 05:38:59 PM PDT 24
Finished Aug 06 05:39:04 PM PDT 24
Peak memory 242220 kb
Host smart-6a56c97c-1567-4587-8f8f-093fff4b35cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054803270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.4054803270
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.2182566221
Short name T139
Test name
Test status
Simulation time 32506813027 ps
CPU time 877.83 seconds
Started Aug 06 05:35:20 PM PDT 24
Finished Aug 06 05:49:58 PM PDT 24
Peak memory 257012 kb
Host smart-3c818b3c-8385-4e27-9053-8b619c479dbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182566221 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.2182566221
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.2491965872
Short name T98
Test name
Test status
Simulation time 2274630172 ps
CPU time 19.36 seconds
Started Aug 06 05:35:03 PM PDT 24
Finished Aug 06 05:35:23 PM PDT 24
Peak memory 241896 kb
Host smart-0176fe3b-a3e1-4605-98bf-69f21ae40ec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2491965872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.2491965872
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.1322775697
Short name T86
Test name
Test status
Simulation time 630043417 ps
CPU time 4.23 seconds
Started Aug 06 05:38:54 PM PDT 24
Finished Aug 06 05:38:58 PM PDT 24
Peak memory 241940 kb
Host smart-a576ca0f-4489-4a17-abbd-e7682bc9c623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322775697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.1322775697
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.595530984
Short name T1297
Test name
Test status
Simulation time 98465310 ps
CPU time 3.72 seconds
Started Aug 06 05:40:09 PM PDT 24
Finished Aug 06 05:40:13 PM PDT 24
Peak memory 238732 kb
Host smart-1bcc20a3-f49c-43ef-a62b-ab1f6259a4c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595530984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alias
ing.595530984
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1654115837
Short name T302
Test name
Test status
Simulation time 1996834845 ps
CPU time 6.94 seconds
Started Aug 06 05:40:07 PM PDT 24
Finished Aug 06 05:40:14 PM PDT 24
Peak memory 238844 kb
Host smart-02ac675d-0e81-4248-99a3-69c9df89cae5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654115837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.1654115837
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2130656226
Short name T301
Test name
Test status
Simulation time 70594253 ps
CPU time 1.92 seconds
Started Aug 06 05:40:06 PM PDT 24
Finished Aug 06 05:40:08 PM PDT 24
Peak memory 240184 kb
Host smart-386f8ed7-e957-4948-8aa2-3543260b7132
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130656226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.2130656226
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.4255743261
Short name T1308
Test name
Test status
Simulation time 134666102 ps
CPU time 2.05 seconds
Started Aug 06 05:40:08 PM PDT 24
Finished Aug 06 05:40:10 PM PDT 24
Peak memory 244120 kb
Host smart-412cd0dd-3987-42ca-8e78-3b4f70e0654e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255743261 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.4255743261
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1425323897
Short name T1270
Test name
Test status
Simulation time 86180184 ps
CPU time 1.46 seconds
Started Aug 06 05:40:06 PM PDT 24
Finished Aug 06 05:40:08 PM PDT 24
Peak memory 240784 kb
Host smart-9f450c16-d4fb-4ec6-96b6-637f77bccfbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425323897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1425323897
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2050786246
Short name T1233
Test name
Test status
Simulation time 155241415 ps
CPU time 1.48 seconds
Started Aug 06 05:40:06 PM PDT 24
Finished Aug 06 05:40:07 PM PDT 24
Peak memory 229928 kb
Host smart-7c18b41e-f4a9-4b60-b5ed-88a1d3dc45a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050786246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2050786246
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3424697671
Short name T1286
Test name
Test status
Simulation time 72524477 ps
CPU time 1.4 seconds
Started Aug 06 05:40:06 PM PDT 24
Finished Aug 06 05:40:07 PM PDT 24
Peak memory 229564 kb
Host smart-c67719f4-011d-4ab9-8b45-5c27a674da58
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424697671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.3424697671
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.170751159
Short name T1266
Test name
Test status
Simulation time 559566060 ps
CPU time 1.8 seconds
Started Aug 06 05:40:05 PM PDT 24
Finished Aug 06 05:40:07 PM PDT 24
Peak memory 229652 kb
Host smart-1a2b1d18-f189-49b6-8c2e-6a46dc929cae
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170751159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.
170751159
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1584726527
Short name T1303
Test name
Test status
Simulation time 210261959 ps
CPU time 2.83 seconds
Started Aug 06 05:40:04 PM PDT 24
Finished Aug 06 05:40:07 PM PDT 24
Peak memory 242020 kb
Host smart-2ca60629-66dc-4407-ba4e-cb5bd34a467d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584726527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.1584726527
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.227831154
Short name T1194
Test name
Test status
Simulation time 346200229 ps
CPU time 6.22 seconds
Started Aug 06 05:40:05 PM PDT 24
Finished Aug 06 05:40:11 PM PDT 24
Peak memory 245964 kb
Host smart-63dc6211-547f-4e24-9117-bb9cc5a00bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227831154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.227831154
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3787096726
Short name T1294
Test name
Test status
Simulation time 1507478570 ps
CPU time 11.23 seconds
Started Aug 06 05:40:06 PM PDT 24
Finished Aug 06 05:40:18 PM PDT 24
Peak memory 238800 kb
Host smart-cb3847d9-3370-4643-98e2-44e02e82a6c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787096726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.3787096726
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.341444163
Short name T300
Test name
Test status
Simulation time 77970323 ps
CPU time 4.95 seconds
Started Aug 06 05:40:07 PM PDT 24
Finished Aug 06 05:40:12 PM PDT 24
Peak memory 238832 kb
Host smart-07fe204c-b4cb-4566-a379-0f5f79196f4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341444163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alias
ing.341444163
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.4272122610
Short name T1313
Test name
Test status
Simulation time 278528091 ps
CPU time 3.99 seconds
Started Aug 06 05:40:11 PM PDT 24
Finished Aug 06 05:40:15 PM PDT 24
Peak memory 238692 kb
Host smart-de715673-6d82-4635-9662-febb8505e810
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272122610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.4272122610
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1212788165
Short name T1277
Test name
Test status
Simulation time 97364730 ps
CPU time 2.58 seconds
Started Aug 06 05:40:08 PM PDT 24
Finished Aug 06 05:40:10 PM PDT 24
Peak memory 238764 kb
Host smart-14e6b93c-5e20-4128-9d17-a49517b982c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212788165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.1212788165
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2293603498
Short name T1224
Test name
Test status
Simulation time 439780875 ps
CPU time 2.78 seconds
Started Aug 06 05:40:11 PM PDT 24
Finished Aug 06 05:40:13 PM PDT 24
Peak memory 246332 kb
Host smart-20e382a8-c4e2-4b60-990a-f7ea30c144b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293603498 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.2293603498
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2922063840
Short name T1208
Test name
Test status
Simulation time 151624770 ps
CPU time 1.42 seconds
Started Aug 06 05:40:10 PM PDT 24
Finished Aug 06 05:40:11 PM PDT 24
Peak memory 230148 kb
Host smart-f3598493-8714-41b5-92b3-2a3f11c03577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922063840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.2922063840
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.4257192184
Short name T1299
Test name
Test status
Simulation time 68525196 ps
CPU time 1.35 seconds
Started Aug 06 05:40:10 PM PDT 24
Finished Aug 06 05:40:11 PM PDT 24
Peak memory 229540 kb
Host smart-eda2d365-c9f5-4a1f-9747-521b9d0129e3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257192184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.4257192184
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2759487898
Short name T1213
Test name
Test status
Simulation time 39355776 ps
CPU time 1.29 seconds
Started Aug 06 05:40:08 PM PDT 24
Finished Aug 06 05:40:09 PM PDT 24
Peak memory 230636 kb
Host smart-bbfc90fd-8ccd-4f9e-9c03-eb69fe9466a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759487898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.2759487898
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.490000771
Short name T1311
Test name
Test status
Simulation time 105968145 ps
CPU time 3.45 seconds
Started Aug 06 05:40:10 PM PDT 24
Finished Aug 06 05:40:14 PM PDT 24
Peak memory 238720 kb
Host smart-51963a8b-f0c7-42dd-a521-7b1f1897bf3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490000771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ct
rl_same_csr_outstanding.490000771
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3766420226
Short name T1323
Test name
Test status
Simulation time 269871512 ps
CPU time 5.38 seconds
Started Aug 06 05:40:07 PM PDT 24
Finished Aug 06 05:40:13 PM PDT 24
Peak memory 245988 kb
Host smart-62ddde15-6a26-45f5-b617-1adf39c42fd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766420226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.3766420226
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.494483047
Short name T343
Test name
Test status
Simulation time 2452688986 ps
CPU time 10.54 seconds
Started Aug 06 05:40:08 PM PDT 24
Finished Aug 06 05:40:18 PM PDT 24
Peak memory 243956 kb
Host smart-97ad967d-f757-48d7-8527-e9891fd123a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494483047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_int
g_err.494483047
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2996212662
Short name T1203
Test name
Test status
Simulation time 1067080309 ps
CPU time 2.88 seconds
Started Aug 06 05:40:25 PM PDT 24
Finished Aug 06 05:40:28 PM PDT 24
Peak memory 244384 kb
Host smart-ba5a5301-cbb3-4ee9-977b-93785d2c6694
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996212662 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.2996212662
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1324183321
Short name T1199
Test name
Test status
Simulation time 39597785 ps
CPU time 1.44 seconds
Started Aug 06 05:40:27 PM PDT 24
Finished Aug 06 05:40:28 PM PDT 24
Peak memory 230104 kb
Host smart-f8ebb734-2a68-47fa-ac6a-2da14181beaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324183321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.1324183321
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1816759199
Short name T275
Test name
Test status
Simulation time 118323674 ps
CPU time 3.82 seconds
Started Aug 06 05:40:27 PM PDT 24
Finished Aug 06 05:40:31 PM PDT 24
Peak memory 238628 kb
Host smart-fc5b5552-fbb2-479d-aa2c-06b54245c7ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816759199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.1816759199
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.595073353
Short name T1191
Test name
Test status
Simulation time 379278296 ps
CPU time 4.26 seconds
Started Aug 06 05:40:27 PM PDT 24
Finished Aug 06 05:40:31 PM PDT 24
Peak memory 246180 kb
Host smart-37f1e7bf-1fac-4eb7-b517-c4fe4c95cc76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595073353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.595073353
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1866346674
Short name T1244
Test name
Test status
Simulation time 95137245 ps
CPU time 2.84 seconds
Started Aug 06 05:40:24 PM PDT 24
Finished Aug 06 05:40:27 PM PDT 24
Peak memory 247124 kb
Host smart-5ee5b93f-1460-4574-8cce-27b14c50c8c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866346674 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.1866346674
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1194877111
Short name T299
Test name
Test status
Simulation time 41030499 ps
CPU time 1.66 seconds
Started Aug 06 05:40:25 PM PDT 24
Finished Aug 06 05:40:27 PM PDT 24
Peak memory 240624 kb
Host smart-7c460aab-ee50-4e16-b25b-9b739e2d5944
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194877111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.1194877111
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1353455160
Short name T1210
Test name
Test status
Simulation time 73478913 ps
CPU time 1.42 seconds
Started Aug 06 05:40:26 PM PDT 24
Finished Aug 06 05:40:28 PM PDT 24
Peak memory 230552 kb
Host smart-3e5c3125-6059-4d20-b31a-5dbd582ad1e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353455160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.1353455160
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.484877377
Short name T1245
Test name
Test status
Simulation time 135928810 ps
CPU time 2.26 seconds
Started Aug 06 05:40:29 PM PDT 24
Finished Aug 06 05:40:31 PM PDT 24
Peak memory 241684 kb
Host smart-e574f615-c645-4b07-b013-d36fa6a1ddb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484877377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_c
trl_same_csr_outstanding.484877377
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3910257189
Short name T1322
Test name
Test status
Simulation time 154311646 ps
CPU time 5.44 seconds
Started Aug 06 05:40:29 PM PDT 24
Finished Aug 06 05:40:35 PM PDT 24
Peak memory 246824 kb
Host smart-dd75f3c6-70c2-4bf0-9370-7de1028493db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910257189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.3910257189
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1102781206
Short name T1240
Test name
Test status
Simulation time 1138778590 ps
CPU time 3.35 seconds
Started Aug 06 05:40:27 PM PDT 24
Finished Aug 06 05:40:30 PM PDT 24
Peak memory 238808 kb
Host smart-ff5baded-a321-4c96-ab6b-a3d035463c9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102781206 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.1102781206
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2665296026
Short name T1221
Test name
Test status
Simulation time 94055499 ps
CPU time 1.86 seconds
Started Aug 06 05:40:24 PM PDT 24
Finished Aug 06 05:40:26 PM PDT 24
Peak memory 240896 kb
Host smart-a257fcfa-c101-4123-9578-c6678f0751af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665296026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.2665296026
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2992898730
Short name T1242
Test name
Test status
Simulation time 39376517 ps
CPU time 1.4 seconds
Started Aug 06 05:40:27 PM PDT 24
Finished Aug 06 05:40:29 PM PDT 24
Peak memory 229856 kb
Host smart-552017b8-238c-4f1c-bb00-3ee9e97a90f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992898730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2992898730
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2682723569
Short name T306
Test name
Test status
Simulation time 178940362 ps
CPU time 2.83 seconds
Started Aug 06 05:40:25 PM PDT 24
Finished Aug 06 05:40:28 PM PDT 24
Peak memory 238780 kb
Host smart-9b30a252-187a-4f93-a558-87f9875a9f80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682723569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.2682723569
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.4100603703
Short name T1236
Test name
Test status
Simulation time 100037797 ps
CPU time 4.7 seconds
Started Aug 06 05:40:24 PM PDT 24
Finished Aug 06 05:40:29 PM PDT 24
Peak memory 245968 kb
Host smart-6f4938c8-bd77-43cd-8924-c9135b0ebaa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100603703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.4100603703
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3932601278
Short name T1275
Test name
Test status
Simulation time 108803731 ps
CPU time 2.64 seconds
Started Aug 06 05:40:50 PM PDT 24
Finished Aug 06 05:40:52 PM PDT 24
Peak memory 244716 kb
Host smart-d980b8eb-bcec-48b9-88f1-94822472f8b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932601278 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.3932601278
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.103175432
Short name T1265
Test name
Test status
Simulation time 595606396 ps
CPU time 1.95 seconds
Started Aug 06 05:40:25 PM PDT 24
Finished Aug 06 05:40:27 PM PDT 24
Peak memory 240720 kb
Host smart-0bc2902d-b5ca-4aac-bfde-fc7d16b539be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103175432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.103175432
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2144614795
Short name T1197
Test name
Test status
Simulation time 36204279 ps
CPU time 1.38 seconds
Started Aug 06 05:40:39 PM PDT 24
Finished Aug 06 05:40:41 PM PDT 24
Peak memory 230584 kb
Host smart-16459bda-fa25-4263-9c6f-a90d9b6e01ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144614795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.2144614795
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.159295566
Short name T1279
Test name
Test status
Simulation time 1279576022 ps
CPU time 3.35 seconds
Started Aug 06 05:40:51 PM PDT 24
Finished Aug 06 05:40:54 PM PDT 24
Peak memory 238820 kb
Host smart-ad2c8d9f-7de8-4960-b073-e29435d1345d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159295566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_c
trl_same_csr_outstanding.159295566
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.120700605
Short name T1230
Test name
Test status
Simulation time 271587079 ps
CPU time 4.58 seconds
Started Aug 06 05:40:26 PM PDT 24
Finished Aug 06 05:40:31 PM PDT 24
Peak memory 238848 kb
Host smart-0e4880e4-2a25-4939-9a65-b1ca3bd258d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120700605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.120700605
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2219591104
Short name T1268
Test name
Test status
Simulation time 385752646 ps
CPU time 3.86 seconds
Started Aug 06 05:40:51 PM PDT 24
Finished Aug 06 05:40:55 PM PDT 24
Peak memory 246968 kb
Host smart-ba022552-2bdf-4ca8-b8ae-bd5148b8ff85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219591104 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.2219591104
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2291554989
Short name T1225
Test name
Test status
Simulation time 43191049 ps
CPU time 1.66 seconds
Started Aug 06 05:40:49 PM PDT 24
Finished Aug 06 05:40:51 PM PDT 24
Peak memory 240840 kb
Host smart-9e4c3b5e-884b-46b9-ac26-40a118155461
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291554989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.2291554989
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1547237462
Short name T1300
Test name
Test status
Simulation time 72598700 ps
CPU time 1.56 seconds
Started Aug 06 05:40:49 PM PDT 24
Finished Aug 06 05:40:50 PM PDT 24
Peak memory 229768 kb
Host smart-050140b7-5347-430f-8e33-2f38a0d309aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547237462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.1547237462
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1441109714
Short name T1231
Test name
Test status
Simulation time 172678955 ps
CPU time 1.93 seconds
Started Aug 06 05:40:49 PM PDT 24
Finished Aug 06 05:40:51 PM PDT 24
Peak memory 238752 kb
Host smart-42655f05-bb68-486f-bed4-e416f80ad1dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441109714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.1441109714
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3862695378
Short name T1200
Test name
Test status
Simulation time 372759086 ps
CPU time 6.88 seconds
Started Aug 06 05:40:49 PM PDT 24
Finished Aug 06 05:40:56 PM PDT 24
Peak memory 245984 kb
Host smart-e4bb07d1-2f3d-4fe5-b832-3d5cf39cef11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862695378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3862695378
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.4220902056
Short name T338
Test name
Test status
Simulation time 1263142323 ps
CPU time 19.64 seconds
Started Aug 06 05:40:53 PM PDT 24
Finished Aug 06 05:41:13 PM PDT 24
Peak memory 238840 kb
Host smart-14781ab1-bc0f-48a2-9a1c-1c64b146d8a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220902056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.4220902056
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2539384889
Short name T1250
Test name
Test status
Simulation time 421792855 ps
CPU time 3.1 seconds
Started Aug 06 05:40:49 PM PDT 24
Finished Aug 06 05:40:52 PM PDT 24
Peak memory 245800 kb
Host smart-c730922a-e0b5-46a6-8ee7-5a359d324bc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539384889 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.2539384889
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3276305172
Short name T303
Test name
Test status
Simulation time 166522593 ps
CPU time 1.79 seconds
Started Aug 06 05:40:50 PM PDT 24
Finished Aug 06 05:40:52 PM PDT 24
Peak memory 241188 kb
Host smart-332713c9-6eb0-4662-af4a-0a0d0fce7892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276305172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3276305172
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.2391474541
Short name T1201
Test name
Test status
Simulation time 128863773 ps
CPU time 1.47 seconds
Started Aug 06 05:40:49 PM PDT 24
Finished Aug 06 05:40:51 PM PDT 24
Peak memory 229852 kb
Host smart-87fe35dd-280c-4181-9db9-84117b801834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391474541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.2391474541
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3694534162
Short name T1304
Test name
Test status
Simulation time 371804652 ps
CPU time 3.5 seconds
Started Aug 06 05:40:49 PM PDT 24
Finished Aug 06 05:40:52 PM PDT 24
Peak memory 238716 kb
Host smart-75440fe5-905c-4b50-9cc5-1636f686b318
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694534162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.3694534162
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.276290533
Short name T1312
Test name
Test status
Simulation time 583467591 ps
CPU time 6.94 seconds
Started Aug 06 05:40:48 PM PDT 24
Finished Aug 06 05:40:55 PM PDT 24
Peak memory 246760 kb
Host smart-2bad3e38-fdf1-4b7a-aeb8-265aff3979c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276290533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.276290533
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1354820976
Short name T342
Test name
Test status
Simulation time 732457084 ps
CPU time 10.71 seconds
Started Aug 06 05:40:51 PM PDT 24
Finished Aug 06 05:41:02 PM PDT 24
Peak memory 243668 kb
Host smart-836d7e1e-98c5-49d9-8433-9e4a600c47d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354820976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.1354820976
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.216081133
Short name T1263
Test name
Test status
Simulation time 1676805087 ps
CPU time 2.77 seconds
Started Aug 06 05:40:50 PM PDT 24
Finished Aug 06 05:40:53 PM PDT 24
Peak memory 238976 kb
Host smart-543be68c-5113-4261-831d-fc081c153a4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216081133 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.216081133
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.414495152
Short name T297
Test name
Test status
Simulation time 39692573 ps
CPU time 1.6 seconds
Started Aug 06 05:40:50 PM PDT 24
Finished Aug 06 05:40:52 PM PDT 24
Peak memory 240784 kb
Host smart-ae597ad2-35fb-4ea6-96ec-c6a99a301453
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414495152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.414495152
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.481272501
Short name T1317
Test name
Test status
Simulation time 128301875 ps
CPU time 1.33 seconds
Started Aug 06 05:40:47 PM PDT 24
Finished Aug 06 05:40:48 PM PDT 24
Peak memory 230100 kb
Host smart-7dd07411-d3ee-4e6e-8d26-43c126a90e8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481272501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.481272501
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2407402176
Short name T1264
Test name
Test status
Simulation time 279449998 ps
CPU time 3.28 seconds
Started Aug 06 05:40:50 PM PDT 24
Finished Aug 06 05:40:53 PM PDT 24
Peak memory 238728 kb
Host smart-9f0a9403-f2d5-46c9-a9b7-b4778d4f0188
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407402176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.2407402176
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.685774113
Short name T1204
Test name
Test status
Simulation time 327638979 ps
CPU time 4.52 seconds
Started Aug 06 05:40:50 PM PDT 24
Finished Aug 06 05:40:55 PM PDT 24
Peak memory 246988 kb
Host smart-a941e3c7-1d57-4508-8237-4086534872ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685774113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.685774113
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2855741700
Short name T1269
Test name
Test status
Simulation time 2513342824 ps
CPU time 11.17 seconds
Started Aug 06 05:40:48 PM PDT 24
Finished Aug 06 05:40:59 PM PDT 24
Peak memory 244044 kb
Host smart-4c1c399f-7408-4fff-b9f7-681ca17dcd47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855741700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.2855741700
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.4214375135
Short name T1296
Test name
Test status
Simulation time 156250633 ps
CPU time 3.48 seconds
Started Aug 06 05:40:49 PM PDT 24
Finished Aug 06 05:40:52 PM PDT 24
Peak memory 247112 kb
Host smart-5369ab31-801d-47dd-9328-100f1136a71a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214375135 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.4214375135
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1789028629
Short name T1258
Test name
Test status
Simulation time 72885383 ps
CPU time 1.64 seconds
Started Aug 06 05:40:50 PM PDT 24
Finished Aug 06 05:40:52 PM PDT 24
Peak memory 240936 kb
Host smart-b922e517-8272-43b1-af14-c236b8639650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789028629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.1789028629
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.3710671398
Short name T1207
Test name
Test status
Simulation time 37733227 ps
CPU time 1.43 seconds
Started Aug 06 05:40:52 PM PDT 24
Finished Aug 06 05:40:54 PM PDT 24
Peak memory 229872 kb
Host smart-2d9a3f71-58ff-4e36-a8c9-0cdcc567fd8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710671398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.3710671398
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.141155595
Short name T1216
Test name
Test status
Simulation time 214299277 ps
CPU time 2.5 seconds
Started Aug 06 05:40:49 PM PDT 24
Finished Aug 06 05:40:52 PM PDT 24
Peak memory 238860 kb
Host smart-6a5a28d3-8751-49fa-8eaf-84d020de1ba7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141155595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_c
trl_same_csr_outstanding.141155595
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.302076462
Short name T1281
Test name
Test status
Simulation time 316471025 ps
CPU time 6.36 seconds
Started Aug 06 05:40:48 PM PDT 24
Finished Aug 06 05:40:55 PM PDT 24
Peak memory 238788 kb
Host smart-0c995806-ca57-4457-8a8d-772b1f0038e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302076462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.302076462
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2380326117
Short name T276
Test name
Test status
Simulation time 101316326 ps
CPU time 3.72 seconds
Started Aug 06 05:40:53 PM PDT 24
Finished Aug 06 05:40:56 PM PDT 24
Peak memory 247024 kb
Host smart-5f0198ce-0d8b-4dae-a458-dcf8477633ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380326117 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.2380326117
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.4002915040
Short name T298
Test name
Test status
Simulation time 50253836 ps
CPU time 1.75 seconds
Started Aug 06 05:40:48 PM PDT 24
Finished Aug 06 05:40:50 PM PDT 24
Peak memory 241064 kb
Host smart-fa24fdfb-faab-4dbb-887d-dffc1be48897
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002915040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.4002915040
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.3884677978
Short name T1315
Test name
Test status
Simulation time 41390230 ps
CPU time 1.43 seconds
Started Aug 06 05:40:52 PM PDT 24
Finished Aug 06 05:40:54 PM PDT 24
Peak memory 230132 kb
Host smart-4adac3f5-4bf9-4868-a063-056e8220b3db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884677978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.3884677978
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.2487821053
Short name T1228
Test name
Test status
Simulation time 129655415 ps
CPU time 3.4 seconds
Started Aug 06 05:40:49 PM PDT 24
Finished Aug 06 05:40:53 PM PDT 24
Peak memory 238844 kb
Host smart-ab90ba58-20e1-49ba-a047-234f71efb668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487821053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.2487821053
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3435051381
Short name T1215
Test name
Test status
Simulation time 157850997 ps
CPU time 4.06 seconds
Started Aug 06 05:40:50 PM PDT 24
Finished Aug 06 05:40:54 PM PDT 24
Peak memory 245888 kb
Host smart-0d10082b-5f37-44ef-8816-a714be630299
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435051381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.3435051381
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1315180628
Short name T1298
Test name
Test status
Simulation time 10202693807 ps
CPU time 10.61 seconds
Started Aug 06 05:40:48 PM PDT 24
Finished Aug 06 05:40:59 PM PDT 24
Peak memory 244044 kb
Host smart-99327c24-8efc-489c-b8f8-3bd4210f737b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315180628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.1315180628
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1111488447
Short name T1320
Test name
Test status
Simulation time 126985472 ps
CPU time 2.1 seconds
Started Aug 06 05:40:50 PM PDT 24
Finished Aug 06 05:40:53 PM PDT 24
Peak memory 244768 kb
Host smart-57349445-a1fe-405c-ae46-82b94c313d71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111488447 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.1111488447
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1349566164
Short name T294
Test name
Test status
Simulation time 686469873 ps
CPU time 1.88 seconds
Started Aug 06 05:40:50 PM PDT 24
Finished Aug 06 05:40:52 PM PDT 24
Peak memory 240788 kb
Host smart-6ff0f2f9-5363-4228-a82b-e9cbc560596d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349566164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1349566164
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3982702668
Short name T1284
Test name
Test status
Simulation time 70427960 ps
CPU time 1.49 seconds
Started Aug 06 05:40:48 PM PDT 24
Finished Aug 06 05:40:49 PM PDT 24
Peak memory 229940 kb
Host smart-1cab713d-c278-4955-a3d7-d3ae549753ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982702668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.3982702668
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2956527787
Short name T1253
Test name
Test status
Simulation time 1011793572 ps
CPU time 2.91 seconds
Started Aug 06 05:40:45 PM PDT 24
Finished Aug 06 05:40:48 PM PDT 24
Peak memory 238708 kb
Host smart-30651a69-04c6-40f2-b87e-035811c48428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956527787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.2956527787
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.526493767
Short name T1202
Test name
Test status
Simulation time 51586633 ps
CPU time 2.85 seconds
Started Aug 06 05:40:50 PM PDT 24
Finished Aug 06 05:40:53 PM PDT 24
Peak memory 238904 kb
Host smart-cfc0c0be-a9ea-401b-abeb-067182a011a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526493767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.526493767
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3738519069
Short name T289
Test name
Test status
Simulation time 76128959 ps
CPU time 4.65 seconds
Started Aug 06 05:40:10 PM PDT 24
Finished Aug 06 05:40:15 PM PDT 24
Peak memory 238728 kb
Host smart-ee934834-d158-46de-8fa0-a33cdcd92fe8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738519069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.3738519069
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1567150226
Short name T1227
Test name
Test status
Simulation time 379543473 ps
CPU time 5.43 seconds
Started Aug 06 05:40:05 PM PDT 24
Finished Aug 06 05:40:11 PM PDT 24
Peak memory 238884 kb
Host smart-cbe1182c-3d2a-4978-9acf-7080cd6e04ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567150226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.1567150226
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1751059087
Short name T1319
Test name
Test status
Simulation time 67885916 ps
CPU time 1.81 seconds
Started Aug 06 05:40:10 PM PDT 24
Finished Aug 06 05:40:12 PM PDT 24
Peak memory 238880 kb
Host smart-d4effa4d-b295-40d8-82b1-9f9d2060cbce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751059087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.1751059087
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.330022825
Short name T1209
Test name
Test status
Simulation time 151121268 ps
CPU time 2.19 seconds
Started Aug 06 05:40:12 PM PDT 24
Finished Aug 06 05:40:15 PM PDT 24
Peak memory 245640 kb
Host smart-b1d7a757-f080-4db2-8fb5-4b818f543a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330022825 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.330022825
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3054646776
Short name T296
Test name
Test status
Simulation time 42896344 ps
CPU time 1.59 seconds
Started Aug 06 05:40:12 PM PDT 24
Finished Aug 06 05:40:14 PM PDT 24
Peak memory 238720 kb
Host smart-fb1c2894-487d-44ab-bba9-c1ec2aff98cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054646776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.3054646776
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.3615006764
Short name T1232
Test name
Test status
Simulation time 135917428 ps
CPU time 1.41 seconds
Started Aug 06 05:40:10 PM PDT 24
Finished Aug 06 05:40:12 PM PDT 24
Peak memory 230652 kb
Host smart-e2fb52db-4d31-41a3-8bf6-71965d04be6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615006764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.3615006764
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1343541348
Short name T1271
Test name
Test status
Simulation time 130435199 ps
CPU time 1.34 seconds
Started Aug 06 05:40:10 PM PDT 24
Finished Aug 06 05:40:11 PM PDT 24
Peak memory 229600 kb
Host smart-2c26bce4-f6df-4810-8446-a5085578cee2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343541348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.1343541348
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.581779418
Short name T1291
Test name
Test status
Simulation time 83373036 ps
CPU time 1.34 seconds
Started Aug 06 05:40:10 PM PDT 24
Finished Aug 06 05:40:12 PM PDT 24
Peak memory 229776 kb
Host smart-53edab3b-382f-47d7-9b86-312df27bf2ec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581779418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.
581779418
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3017117433
Short name T1273
Test name
Test status
Simulation time 1035169461 ps
CPU time 3.54 seconds
Started Aug 06 05:40:06 PM PDT 24
Finished Aug 06 05:40:09 PM PDT 24
Peak memory 241804 kb
Host smart-ef912c5b-32ea-439f-9c3d-f54b948ccd70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017117433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.3017117433
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3092940547
Short name T1211
Test name
Test status
Simulation time 145526036 ps
CPU time 5.7 seconds
Started Aug 06 05:40:10 PM PDT 24
Finished Aug 06 05:40:16 PM PDT 24
Peak memory 245888 kb
Host smart-54b2dd71-284e-4758-908c-c8724a899602
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092940547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3092940547
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3160897137
Short name T1187
Test name
Test status
Simulation time 63869980 ps
CPU time 1.32 seconds
Started Aug 06 05:40:51 PM PDT 24
Finished Aug 06 05:40:53 PM PDT 24
Peak memory 230056 kb
Host smart-25d72000-8ee2-4cae-b01e-2de5270666ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160897137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.3160897137
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3537260530
Short name T1310
Test name
Test status
Simulation time 57711662 ps
CPU time 1.39 seconds
Started Aug 06 05:40:49 PM PDT 24
Finished Aug 06 05:40:50 PM PDT 24
Peak memory 230640 kb
Host smart-982de042-4c4c-4231-8055-d060f1b9b04e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537260530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.3537260530
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2516694319
Short name T1262
Test name
Test status
Simulation time 146524325 ps
CPU time 1.6 seconds
Started Aug 06 05:40:51 PM PDT 24
Finished Aug 06 05:40:53 PM PDT 24
Peak memory 229816 kb
Host smart-938a0274-3e55-47f9-8585-267258a58889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516694319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.2516694319
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1693442399
Short name T1220
Test name
Test status
Simulation time 80197682 ps
CPU time 1.49 seconds
Started Aug 06 05:40:52 PM PDT 24
Finished Aug 06 05:40:54 PM PDT 24
Peak memory 230604 kb
Host smart-b22523ab-296b-44d0-8fd9-38f3ab0c7119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693442399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1693442399
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.1289392438
Short name T1280
Test name
Test status
Simulation time 52413936 ps
CPU time 1.42 seconds
Started Aug 06 05:40:52 PM PDT 24
Finished Aug 06 05:40:53 PM PDT 24
Peak memory 229896 kb
Host smart-19d66dc2-d19d-49d9-a1a0-f32f45d008c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289392438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.1289392438
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.2121053676
Short name T1314
Test name
Test status
Simulation time 582753207 ps
CPU time 1.72 seconds
Started Aug 06 05:40:52 PM PDT 24
Finished Aug 06 05:40:53 PM PDT 24
Peak memory 229840 kb
Host smart-781f8abb-de11-4699-af97-c7efee134820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121053676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.2121053676
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.3493060339
Short name T1196
Test name
Test status
Simulation time 55635968 ps
CPU time 1.49 seconds
Started Aug 06 05:40:52 PM PDT 24
Finished Aug 06 05:40:54 PM PDT 24
Peak memory 229856 kb
Host smart-fcdd0006-fa22-4693-af70-c6190184876c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493060339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.3493060339
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1226386657
Short name T1256
Test name
Test status
Simulation time 586320319 ps
CPU time 1.55 seconds
Started Aug 06 05:40:52 PM PDT 24
Finished Aug 06 05:40:54 PM PDT 24
Peak memory 230608 kb
Host smart-18f5255f-3136-43b9-b44c-7ef40ba7cbc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226386657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1226386657
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.62698755
Short name T1307
Test name
Test status
Simulation time 38137413 ps
CPU time 1.37 seconds
Started Aug 06 05:40:49 PM PDT 24
Finished Aug 06 05:40:50 PM PDT 24
Peak memory 229904 kb
Host smart-c6071b3b-345b-407e-b3e8-83b8d114a690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62698755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.62698755
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1127971139
Short name T1260
Test name
Test status
Simulation time 150277111 ps
CPU time 1.5 seconds
Started Aug 06 05:40:51 PM PDT 24
Finished Aug 06 05:40:53 PM PDT 24
Peak memory 230520 kb
Host smart-98eb7552-923c-423e-bf48-15b2984229f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127971139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1127971139
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2974336088
Short name T1257
Test name
Test status
Simulation time 123856966 ps
CPU time 4.01 seconds
Started Aug 06 05:40:06 PM PDT 24
Finished Aug 06 05:40:10 PM PDT 24
Peak memory 238872 kb
Host smart-5ef97f8d-2de9-43b6-828c-1239ca77cce7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974336088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.2974336088
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.798434708
Short name T1249
Test name
Test status
Simulation time 5573229516 ps
CPU time 12.86 seconds
Started Aug 06 05:40:05 PM PDT 24
Finished Aug 06 05:40:19 PM PDT 24
Peak memory 238924 kb
Host smart-6e824440-2266-4ad3-8452-2d9387b03174
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798434708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_b
ash.798434708
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1145767511
Short name T1289
Test name
Test status
Simulation time 94861173 ps
CPU time 2.2 seconds
Started Aug 06 05:40:04 PM PDT 24
Finished Aug 06 05:40:06 PM PDT 24
Peak memory 238820 kb
Host smart-87f6fc0f-59a7-43d7-8133-ba7042430e93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145767511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.1145767511
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1147130012
Short name T1324
Test name
Test status
Simulation time 74976626 ps
CPU time 2.19 seconds
Started Aug 06 05:40:04 PM PDT 24
Finished Aug 06 05:40:06 PM PDT 24
Peak memory 245036 kb
Host smart-99b8ce6a-5840-4d0b-be8c-2c578daa3e42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147130012 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.1147130012
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.1290860809
Short name T309
Test name
Test status
Simulation time 60228309 ps
CPU time 1.78 seconds
Started Aug 06 05:40:03 PM PDT 24
Finished Aug 06 05:40:05 PM PDT 24
Peak memory 241084 kb
Host smart-51292cf6-3dc5-4a95-af53-ce0e65e00342
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290860809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.1290860809
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1883493582
Short name T1226
Test name
Test status
Simulation time 72655818 ps
CPU time 1.49 seconds
Started Aug 06 05:40:07 PM PDT 24
Finished Aug 06 05:40:08 PM PDT 24
Peak memory 230104 kb
Host smart-c0c1c8b6-9eb9-4c3e-850e-66a45a61d69c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883493582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.1883493582
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.551644872
Short name T1198
Test name
Test status
Simulation time 102462918 ps
CPU time 1.42 seconds
Started Aug 06 05:40:04 PM PDT 24
Finished Aug 06 05:40:05 PM PDT 24
Peak memory 230432 kb
Host smart-eb4f4634-5aaa-4fdc-876c-4d88b9780993
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551644872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl
_mem_partial_access.551644872
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2649736714
Short name T1195
Test name
Test status
Simulation time 68504276 ps
CPU time 1.34 seconds
Started Aug 06 05:40:05 PM PDT 24
Finished Aug 06 05:40:06 PM PDT 24
Peak memory 229780 kb
Host smart-f4f72734-a2f2-43dc-9fe4-7ad24d0271a8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649736714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.2649736714
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1984955105
Short name T305
Test name
Test status
Simulation time 67461504 ps
CPU time 2.24 seconds
Started Aug 06 05:40:03 PM PDT 24
Finished Aug 06 05:40:05 PM PDT 24
Peak memory 238856 kb
Host smart-0d8dd676-377a-4077-b19c-0f7cbf21613d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984955105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.1984955105
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1786015174
Short name T1188
Test name
Test status
Simulation time 59071711 ps
CPU time 3.44 seconds
Started Aug 06 05:40:14 PM PDT 24
Finished Aug 06 05:40:17 PM PDT 24
Peak memory 245808 kb
Host smart-e2db5a95-a3b9-4836-9fc4-16451945af95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786015174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1786015174
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2146929452
Short name T337
Test name
Test status
Simulation time 2793032088 ps
CPU time 19.78 seconds
Started Aug 06 05:40:12 PM PDT 24
Finished Aug 06 05:40:32 PM PDT 24
Peak memory 244212 kb
Host smart-bad54bb7-c505-4f6d-9ffc-c15563f7a871
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146929452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.2146929452
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1023466167
Short name T1222
Test name
Test status
Simulation time 74851885 ps
CPU time 1.51 seconds
Started Aug 06 05:40:48 PM PDT 24
Finished Aug 06 05:40:49 PM PDT 24
Peak memory 230040 kb
Host smart-9c196ef4-7828-459d-8d66-973731eb31e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023466167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1023466167
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3636759303
Short name T1206
Test name
Test status
Simulation time 42937836 ps
CPU time 1.49 seconds
Started Aug 06 05:41:13 PM PDT 24
Finished Aug 06 05:41:15 PM PDT 24
Peak memory 230548 kb
Host smart-e83af7e4-cc4c-40be-b8eb-54dbea2194b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636759303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.3636759303
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.560635108
Short name T1237
Test name
Test status
Simulation time 560480977 ps
CPU time 1.79 seconds
Started Aug 06 05:41:11 PM PDT 24
Finished Aug 06 05:41:13 PM PDT 24
Peak memory 229948 kb
Host smart-1d14e993-720f-4eca-a2d3-ae57e68aac87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560635108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.560635108
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2753007719
Short name T1223
Test name
Test status
Simulation time 603716330 ps
CPU time 2.24 seconds
Started Aug 06 05:41:14 PM PDT 24
Finished Aug 06 05:41:16 PM PDT 24
Peak memory 229892 kb
Host smart-0b7669a2-8618-47c0-b725-60d8eb97a433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753007719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.2753007719
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.705522856
Short name T1274
Test name
Test status
Simulation time 146580628 ps
CPU time 1.44 seconds
Started Aug 06 05:41:11 PM PDT 24
Finished Aug 06 05:41:12 PM PDT 24
Peak memory 230184 kb
Host smart-27af9286-8948-4052-b7f0-2006ce3c809f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705522856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.705522856
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.972469774
Short name T1318
Test name
Test status
Simulation time 70591596 ps
CPU time 1.44 seconds
Started Aug 06 05:41:12 PM PDT 24
Finished Aug 06 05:41:13 PM PDT 24
Peak memory 230496 kb
Host smart-25a48554-adc4-4bf6-8309-d6cddf8d253f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972469774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.972469774
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3357282353
Short name T1295
Test name
Test status
Simulation time 558229303 ps
CPU time 1.85 seconds
Started Aug 06 05:41:13 PM PDT 24
Finished Aug 06 05:41:15 PM PDT 24
Peak memory 230184 kb
Host smart-dcc68664-2234-4675-ac3a-e83425636eb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357282353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.3357282353
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2874029581
Short name T1282
Test name
Test status
Simulation time 75008930 ps
CPU time 1.44 seconds
Started Aug 06 05:41:13 PM PDT 24
Finished Aug 06 05:41:15 PM PDT 24
Peak memory 230516 kb
Host smart-5c72d31b-9943-4b09-ab9e-af23abfe964d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874029581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.2874029581
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2603158921
Short name T1218
Test name
Test status
Simulation time 76567450 ps
CPU time 1.44 seconds
Started Aug 06 05:41:14 PM PDT 24
Finished Aug 06 05:41:15 PM PDT 24
Peak memory 230592 kb
Host smart-bdae7d2b-f04f-418f-b766-914ae7e64af4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603158921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2603158921
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2681624450
Short name T1309
Test name
Test status
Simulation time 69864737 ps
CPU time 1.4 seconds
Started Aug 06 05:41:11 PM PDT 24
Finished Aug 06 05:41:12 PM PDT 24
Peak memory 230552 kb
Host smart-a1f5ed34-792e-4df0-9642-1eaddec7e295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681624450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2681624450
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.4059756945
Short name T292
Test name
Test status
Simulation time 101020572 ps
CPU time 3.71 seconds
Started Aug 06 05:40:04 PM PDT 24
Finished Aug 06 05:40:07 PM PDT 24
Peak memory 241372 kb
Host smart-ada3a3f8-4a08-4984-9df8-dc19ab74f084
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059756945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.4059756945
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2991808543
Short name T1302
Test name
Test status
Simulation time 249401209 ps
CPU time 6.04 seconds
Started Aug 06 05:40:07 PM PDT 24
Finished Aug 06 05:40:13 PM PDT 24
Peak memory 238848 kb
Host smart-f29825f5-b358-408e-a737-bb743562bf46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991808543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.2991808543
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.215685745
Short name T1246
Test name
Test status
Simulation time 1528167848 ps
CPU time 3.75 seconds
Started Aug 06 05:40:04 PM PDT 24
Finished Aug 06 05:40:07 PM PDT 24
Peak memory 238868 kb
Host smart-3c1efbc7-02d8-4f6e-9afd-6419167dff32
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215685745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_re
set.215685745
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.156869126
Short name T1248
Test name
Test status
Simulation time 121116819 ps
CPU time 2.88 seconds
Started Aug 06 05:40:06 PM PDT 24
Finished Aug 06 05:40:09 PM PDT 24
Peak memory 246764 kb
Host smart-bdb60d0a-cca3-4de4-ba50-5817e0603d85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156869126 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.156869126
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2387846955
Short name T1243
Test name
Test status
Simulation time 47959988 ps
CPU time 1.57 seconds
Started Aug 06 05:40:07 PM PDT 24
Finished Aug 06 05:40:09 PM PDT 24
Peak memory 240588 kb
Host smart-4a501e27-f5db-492f-bb7f-bb9bd2b2c6ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387846955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.2387846955
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1325837746
Short name T1234
Test name
Test status
Simulation time 41578672 ps
CPU time 1.45 seconds
Started Aug 06 05:40:04 PM PDT 24
Finished Aug 06 05:40:06 PM PDT 24
Peak memory 230192 kb
Host smart-8c7027c7-d0da-495c-9f4d-8f603016610b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325837746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1325837746
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3005242216
Short name T1301
Test name
Test status
Simulation time 68444373 ps
CPU time 1.41 seconds
Started Aug 06 05:40:04 PM PDT 24
Finished Aug 06 05:40:06 PM PDT 24
Peak memory 229548 kb
Host smart-22f1d799-8245-420c-8e10-3b6af5bb9665
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005242216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.3005242216
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.386282415
Short name T1251
Test name
Test status
Simulation time 142156051 ps
CPU time 1.37 seconds
Started Aug 06 05:40:05 PM PDT 24
Finished Aug 06 05:40:06 PM PDT 24
Peak memory 230548 kb
Host smart-6b88a1fa-48f5-47c1-acd0-05989a8987a9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386282415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.
386282415
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.93331795
Short name T1241
Test name
Test status
Simulation time 95722695 ps
CPU time 3.01 seconds
Started Aug 06 05:40:04 PM PDT 24
Finished Aug 06 05:40:07 PM PDT 24
Peak memory 238888 kb
Host smart-02ebebcc-8220-4a99-8c15-7634c615251d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93331795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_same_csr_outstanding.93331795
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1675030559
Short name T1189
Test name
Test status
Simulation time 347083192 ps
CPU time 6.22 seconds
Started Aug 06 05:40:06 PM PDT 24
Finished Aug 06 05:40:12 PM PDT 24
Peak memory 245980 kb
Host smart-3302e890-b64c-40ae-8943-6fdaa85df145
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675030559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.1675030559
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1162418644
Short name T335
Test name
Test status
Simulation time 1238008995 ps
CPU time 18.96 seconds
Started Aug 06 05:40:06 PM PDT 24
Finished Aug 06 05:40:25 PM PDT 24
Peak memory 243940 kb
Host smart-0f19a48a-7ce8-494a-8fb5-a7f08346f067
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162418644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.1162418644
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2941787515
Short name T1239
Test name
Test status
Simulation time 55960425 ps
CPU time 1.46 seconds
Started Aug 06 05:41:15 PM PDT 24
Finished Aug 06 05:41:16 PM PDT 24
Peak memory 229712 kb
Host smart-0c7966bc-3fa3-44ba-9220-c6794c16caa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941787515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2941787515
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.1097708424
Short name T1293
Test name
Test status
Simulation time 576926468 ps
CPU time 1.66 seconds
Started Aug 06 05:41:14 PM PDT 24
Finished Aug 06 05:41:16 PM PDT 24
Peak memory 230260 kb
Host smart-c2a40db7-3142-4650-88b9-d93a64e0ad70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097708424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.1097708424
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1261607549
Short name T1193
Test name
Test status
Simulation time 156539011 ps
CPU time 1.54 seconds
Started Aug 06 05:41:13 PM PDT 24
Finished Aug 06 05:41:15 PM PDT 24
Peak memory 229956 kb
Host smart-fcda1607-dd26-4123-92b4-b5880469ef4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261607549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.1261607549
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2708160994
Short name T1267
Test name
Test status
Simulation time 40786940 ps
CPU time 1.43 seconds
Started Aug 06 05:41:14 PM PDT 24
Finished Aug 06 05:41:15 PM PDT 24
Peak memory 229904 kb
Host smart-7eb47528-086c-4e8b-8e23-096640903602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708160994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.2708160994
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2898966314
Short name T1212
Test name
Test status
Simulation time 36645326 ps
CPU time 1.32 seconds
Started Aug 06 05:41:16 PM PDT 24
Finished Aug 06 05:41:18 PM PDT 24
Peak memory 230116 kb
Host smart-2682322c-1aa4-4ddf-8279-6856109d3d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898966314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2898966314
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.3872816572
Short name T1192
Test name
Test status
Simulation time 127271397 ps
CPU time 1.47 seconds
Started Aug 06 05:41:14 PM PDT 24
Finished Aug 06 05:41:15 PM PDT 24
Peak memory 230204 kb
Host smart-29c6880a-7c2d-4bc6-9b6d-d18c77a00867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872816572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.3872816572
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2767578887
Short name T1252
Test name
Test status
Simulation time 42021495 ps
CPU time 1.42 seconds
Started Aug 06 05:41:12 PM PDT 24
Finished Aug 06 05:41:13 PM PDT 24
Peak memory 230232 kb
Host smart-78f2b068-8b95-4e52-9e35-58bc933a2486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767578887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2767578887
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.2115025390
Short name T1247
Test name
Test status
Simulation time 565095168 ps
CPU time 1.5 seconds
Started Aug 06 05:41:12 PM PDT 24
Finished Aug 06 05:41:14 PM PDT 24
Peak memory 230556 kb
Host smart-d90c501f-801a-4859-95c0-f86222ac7ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115025390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.2115025390
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2894278921
Short name T1217
Test name
Test status
Simulation time 120997101 ps
CPU time 1.49 seconds
Started Aug 06 05:41:11 PM PDT 24
Finished Aug 06 05:41:13 PM PDT 24
Peak memory 229876 kb
Host smart-af4f26af-65ee-46de-a4c1-a88594fd4cf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894278921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2894278921
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3772807225
Short name T1255
Test name
Test status
Simulation time 76016275 ps
CPU time 1.42 seconds
Started Aug 06 05:41:12 PM PDT 24
Finished Aug 06 05:41:14 PM PDT 24
Peak memory 230140 kb
Host smart-f9bfab98-1254-4fa2-a104-b7b7eaa51f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772807225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3772807225
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.1436598020
Short name T1219
Test name
Test status
Simulation time 1599162925 ps
CPU time 5.1 seconds
Started Aug 06 05:40:28 PM PDT 24
Finished Aug 06 05:40:34 PM PDT 24
Peak memory 247060 kb
Host smart-15a2a612-649e-4a26-b710-0838ae12b418
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436598020 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.1436598020
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.758832767
Short name T274
Test name
Test status
Simulation time 46123054 ps
CPU time 1.49 seconds
Started Aug 06 05:40:25 PM PDT 24
Finished Aug 06 05:40:26 PM PDT 24
Peak memory 240452 kb
Host smart-d0a707c8-68c9-4b27-a34d-add25fe3aa68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758832767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.758832767
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.2492814958
Short name T1288
Test name
Test status
Simulation time 43343504 ps
CPU time 1.36 seconds
Started Aug 06 05:40:08 PM PDT 24
Finished Aug 06 05:40:09 PM PDT 24
Peak memory 229884 kb
Host smart-9e6b0553-8108-48f2-bb7b-7927c8feeba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492814958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.2492814958
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.820318118
Short name T1238
Test name
Test status
Simulation time 85325523 ps
CPU time 2.69 seconds
Started Aug 06 05:40:26 PM PDT 24
Finished Aug 06 05:40:29 PM PDT 24
Peak memory 238676 kb
Host smart-a7ec7b3e-a3fb-454a-b824-dc2b0a01b806
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820318118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ct
rl_same_csr_outstanding.820318118
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.988402439
Short name T1205
Test name
Test status
Simulation time 1075549229 ps
CPU time 5.06 seconds
Started Aug 06 05:40:05 PM PDT 24
Finished Aug 06 05:40:10 PM PDT 24
Peak memory 246072 kb
Host smart-a48b64dd-08dc-4447-819b-951593e39bec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988402439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.988402439
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1899001367
Short name T1278
Test name
Test status
Simulation time 1531057193 ps
CPU time 18.75 seconds
Started Aug 06 05:40:04 PM PDT 24
Finished Aug 06 05:40:23 PM PDT 24
Peak memory 238736 kb
Host smart-5e7813e9-2e61-4b6e-925e-e6ce42e5aa8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899001367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.1899001367
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1039764184
Short name T1287
Test name
Test status
Simulation time 112190661 ps
CPU time 2.74 seconds
Started Aug 06 05:40:25 PM PDT 24
Finished Aug 06 05:40:28 PM PDT 24
Peak memory 246916 kb
Host smart-4136373b-15d2-4760-814b-f488f66bde5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039764184 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.1039764184
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.82706215
Short name T291
Test name
Test status
Simulation time 76456431 ps
CPU time 1.73 seconds
Started Aug 06 05:40:24 PM PDT 24
Finished Aug 06 05:40:26 PM PDT 24
Peak memory 241028 kb
Host smart-cd65a238-06a9-4673-8045-d2c048f3a0c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82706215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.82706215
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1437499363
Short name T1214
Test name
Test status
Simulation time 576369929 ps
CPU time 1.86 seconds
Started Aug 06 05:40:24 PM PDT 24
Finished Aug 06 05:40:26 PM PDT 24
Peak memory 229948 kb
Host smart-f0d4bb4b-3a9a-4edd-9351-84390aace650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437499363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1437499363
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3674056535
Short name T1259
Test name
Test status
Simulation time 187513527 ps
CPU time 2.98 seconds
Started Aug 06 05:40:25 PM PDT 24
Finished Aug 06 05:40:28 PM PDT 24
Peak memory 238756 kb
Host smart-a7b89255-38a6-4625-af03-af45759bf760
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674056535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.3674056535
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1753276606
Short name T1261
Test name
Test status
Simulation time 66819055 ps
CPU time 3.36 seconds
Started Aug 06 05:40:25 PM PDT 24
Finished Aug 06 05:40:28 PM PDT 24
Peak memory 245708 kb
Host smart-aad13ce8-2235-4fcb-9e57-ae245c0c387e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753276606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.1753276606
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.422754964
Short name T1285
Test name
Test status
Simulation time 2482772134 ps
CPU time 19.04 seconds
Started Aug 06 05:40:26 PM PDT 24
Finished Aug 06 05:40:45 PM PDT 24
Peak memory 244252 kb
Host smart-24f88fb6-28ef-496a-a2f2-67e9ad508874
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422754964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_int
g_err.422754964
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3392564642
Short name T1292
Test name
Test status
Simulation time 1507745245 ps
CPU time 3.07 seconds
Started Aug 06 05:40:26 PM PDT 24
Finished Aug 06 05:40:29 PM PDT 24
Peak memory 247124 kb
Host smart-55ff5622-703c-453b-8c16-7ace85cfc90c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392564642 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.3392564642
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.74252007
Short name T1321
Test name
Test status
Simulation time 52564983 ps
CPU time 1.63 seconds
Started Aug 06 05:40:26 PM PDT 24
Finished Aug 06 05:40:28 PM PDT 24
Peak memory 240092 kb
Host smart-d93f24e7-2a3c-497e-b050-998d6e479ee5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74252007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.74252007
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.831424729
Short name T1283
Test name
Test status
Simulation time 46002908 ps
CPU time 1.41 seconds
Started Aug 06 05:40:24 PM PDT 24
Finished Aug 06 05:40:25 PM PDT 24
Peak memory 229828 kb
Host smart-9c51e349-3bb7-41db-bb94-7c9a448ca9e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831424729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.831424729
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1998425442
Short name T304
Test name
Test status
Simulation time 1102455849 ps
CPU time 3.84 seconds
Started Aug 06 05:40:23 PM PDT 24
Finished Aug 06 05:40:27 PM PDT 24
Peak memory 238756 kb
Host smart-8c904e12-c05e-4078-a737-36854fa14aa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998425442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.1998425442
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3458847068
Short name T1272
Test name
Test status
Simulation time 214883027 ps
CPU time 3.45 seconds
Started Aug 06 05:40:27 PM PDT 24
Finished Aug 06 05:40:31 PM PDT 24
Peak memory 246032 kb
Host smart-65a3eff7-9f22-4c43-859b-be2d55daee70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458847068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3458847068
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1518291762
Short name T1254
Test name
Test status
Simulation time 9754583915 ps
CPU time 15.08 seconds
Started Aug 06 05:40:27 PM PDT 24
Finished Aug 06 05:40:42 PM PDT 24
Peak memory 244196 kb
Host smart-e6050755-b46c-4d4d-a679-d51e663efca4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518291762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.1518291762
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3078885625
Short name T1229
Test name
Test status
Simulation time 1068571968 ps
CPU time 2.72 seconds
Started Aug 06 05:40:27 PM PDT 24
Finished Aug 06 05:40:30 PM PDT 24
Peak memory 244544 kb
Host smart-8e9d66dd-a37c-4012-b411-4dd86c660957
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078885625 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.3078885625
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2596627956
Short name T295
Test name
Test status
Simulation time 158958976 ps
CPU time 1.69 seconds
Started Aug 06 05:40:24 PM PDT 24
Finished Aug 06 05:40:26 PM PDT 24
Peak memory 240872 kb
Host smart-679b6978-222e-47b9-9834-db5ff8ee9271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596627956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.2596627956
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.4195002615
Short name T1190
Test name
Test status
Simulation time 66141174 ps
CPU time 1.36 seconds
Started Aug 06 05:40:27 PM PDT 24
Finished Aug 06 05:40:29 PM PDT 24
Peak memory 230172 kb
Host smart-a2b37eac-6409-4215-a791-f0f9985dbe38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195002615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.4195002615
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3724596289
Short name T1316
Test name
Test status
Simulation time 357742136 ps
CPU time 3.06 seconds
Started Aug 06 05:40:25 PM PDT 24
Finished Aug 06 05:40:28 PM PDT 24
Peak memory 241884 kb
Host smart-47a22e65-d6c4-47e1-9eb1-52083069a7af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724596289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.3724596289
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3595989513
Short name T1276
Test name
Test status
Simulation time 181230880 ps
CPU time 6.6 seconds
Started Aug 06 05:40:27 PM PDT 24
Finished Aug 06 05:40:34 PM PDT 24
Peak memory 246060 kb
Host smart-84bb0c8b-a619-4a3a-a20a-2b7dfdf90ba0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595989513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.3595989513
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2244717099
Short name T272
Test name
Test status
Simulation time 2449023890 ps
CPU time 11.4 seconds
Started Aug 06 05:40:30 PM PDT 24
Finished Aug 06 05:40:41 PM PDT 24
Peak memory 243828 kb
Host smart-19a87c6e-6881-4f28-8762-b5d23b5bc5a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244717099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.2244717099
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1766496978
Short name T1306
Test name
Test status
Simulation time 189992016 ps
CPU time 2.74 seconds
Started Aug 06 05:40:28 PM PDT 24
Finished Aug 06 05:40:31 PM PDT 24
Peak memory 247068 kb
Host smart-bdf14f86-d7cb-4b83-b1c0-6fe58a93b792
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766496978 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.1766496978
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1840351816
Short name T1290
Test name
Test status
Simulation time 43347920 ps
CPU time 1.56 seconds
Started Aug 06 05:40:25 PM PDT 24
Finished Aug 06 05:40:26 PM PDT 24
Peak memory 238748 kb
Host smart-0073ca72-caab-4cb3-961e-be2c85ccb757
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840351816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1840351816
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1615352428
Short name T1235
Test name
Test status
Simulation time 75379150 ps
CPU time 1.5 seconds
Started Aug 06 05:40:25 PM PDT 24
Finished Aug 06 05:40:26 PM PDT 24
Peak memory 229880 kb
Host smart-ebae1a7c-c3d1-4ddc-91c9-cee78064b00a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615352428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1615352428
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1228799277
Short name T273
Test name
Test status
Simulation time 107931543 ps
CPU time 3.11 seconds
Started Aug 06 05:40:25 PM PDT 24
Finished Aug 06 05:40:28 PM PDT 24
Peak memory 238728 kb
Host smart-d0fe323d-8512-4caf-8c00-75fc013a259e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228799277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.1228799277
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2640755791
Short name T1305
Test name
Test status
Simulation time 196581452 ps
CPU time 3.47 seconds
Started Aug 06 05:40:26 PM PDT 24
Finished Aug 06 05:40:30 PM PDT 24
Peak memory 245628 kb
Host smart-033c5e8c-d543-4992-93b6-1238a5be5db3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640755791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.2640755791
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1182995593
Short name T341
Test name
Test status
Simulation time 1239610819 ps
CPU time 9.2 seconds
Started Aug 06 05:40:27 PM PDT 24
Finished Aug 06 05:40:37 PM PDT 24
Peak memory 238800 kb
Host smart-ae0bc814-d8be-4bed-aeb7-5a0f5b085733
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182995593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.1182995593
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.4254644362
Short name T452
Test name
Test status
Simulation time 210191058 ps
CPU time 1.87 seconds
Started Aug 06 05:31:06 PM PDT 24
Finished Aug 06 05:31:08 PM PDT 24
Peak memory 240492 kb
Host smart-49a20277-5027-4a25-afa9-2b9fbc9d72a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254644362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.4254644362
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.3495301704
Short name T90
Test name
Test status
Simulation time 982978085 ps
CPU time 5.77 seconds
Started Aug 06 05:30:59 PM PDT 24
Finished Aug 06 05:31:05 PM PDT 24
Peak memory 242480 kb
Host smart-22551e03-cb36-461e-b952-c26681e23c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495301704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.3495301704
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.1628364841
Short name T924
Test name
Test status
Simulation time 1367903319 ps
CPU time 32.21 seconds
Started Aug 06 05:30:53 PM PDT 24
Finished Aug 06 05:31:26 PM PDT 24
Peak memory 245188 kb
Host smart-718dcba9-c73a-4ce4-bead-f6503f443b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628364841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.1628364841
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.2343080141
Short name T902
Test name
Test status
Simulation time 221680890 ps
CPU time 4.84 seconds
Started Aug 06 05:31:00 PM PDT 24
Finished Aug 06 05:31:05 PM PDT 24
Peak memory 248428 kb
Host smart-a0824904-8799-4704-ac13-2020d96b605d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343080141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.2343080141
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.2756105012
Short name T957
Test name
Test status
Simulation time 248213414 ps
CPU time 5.25 seconds
Started Aug 06 05:30:51 PM PDT 24
Finished Aug 06 05:30:56 PM PDT 24
Peak memory 242152 kb
Host smart-0b310fb6-3189-4ffa-9bac-c3efb110f008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756105012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.2756105012
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.1188612667
Short name T182
Test name
Test status
Simulation time 3007646266 ps
CPU time 16.35 seconds
Started Aug 06 05:30:52 PM PDT 24
Finished Aug 06 05:31:08 PM PDT 24
Peak memory 240576 kb
Host smart-72e973b0-f503-41f6-ad5e-be4af52bc930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188612667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.1188612667
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.281523674
Short name T527
Test name
Test status
Simulation time 358034515 ps
CPU time 8.02 seconds
Started Aug 06 05:31:00 PM PDT 24
Finished Aug 06 05:31:08 PM PDT 24
Peak memory 248488 kb
Host smart-aa63e14b-16a2-4bc0-925b-ff90357e1882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281523674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.281523674
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.2121123887
Short name T1085
Test name
Test status
Simulation time 3998532109 ps
CPU time 24.89 seconds
Started Aug 06 05:30:54 PM PDT 24
Finished Aug 06 05:31:19 PM PDT 24
Peak memory 242376 kb
Host smart-2b30eb37-a78d-4f13-a790-b7541eaebab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121123887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.2121123887
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.4210260742
Short name T118
Test name
Test status
Simulation time 411921415 ps
CPU time 5.2 seconds
Started Aug 06 05:31:00 PM PDT 24
Finished Aug 06 05:31:05 PM PDT 24
Peak memory 242268 kb
Host smart-08f99aca-5fa1-411b-9587-ced9d010a3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210260742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.4210260742
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.744735105
Short name T366
Test name
Test status
Simulation time 2002665447 ps
CPU time 20.55 seconds
Started Aug 06 05:30:52 PM PDT 24
Finished Aug 06 05:31:13 PM PDT 24
Peak memory 241944 kb
Host smart-c24d8324-58a4-4d35-91fe-e1425574e27b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744735105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.744735105
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.4270239662
Short name T215
Test name
Test status
Simulation time 1132726956 ps
CPU time 17.81 seconds
Started Aug 06 05:31:00 PM PDT 24
Finished Aug 06 05:31:18 PM PDT 24
Peak memory 242004 kb
Host smart-54379939-9aa6-481a-995d-8904ed7651c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270239662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.4270239662
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.1132721838
Short name T1081
Test name
Test status
Simulation time 234530845 ps
CPU time 6.42 seconds
Started Aug 06 05:30:53 PM PDT 24
Finished Aug 06 05:30:59 PM PDT 24
Peak memory 241840 kb
Host smart-7be0619f-5c00-4f6c-99cf-6b3694a7a627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132721838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1132721838
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.1164555209
Short name T23
Test name
Test status
Simulation time 23119080770 ps
CPU time 234.76 seconds
Started Aug 06 05:30:51 PM PDT 24
Finished Aug 06 05:34:46 PM PDT 24
Peak memory 278620 kb
Host smart-6683078c-4c24-4632-ae64-0249a0f3625a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164555209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.1164555209
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.4201512731
Short name T1017
Test name
Test status
Simulation time 3360954576 ps
CPU time 7.09 seconds
Started Aug 06 05:30:52 PM PDT 24
Finished Aug 06 05:31:00 PM PDT 24
Peak memory 242040 kb
Host smart-4b6f854c-246d-4050-9a2b-170f2cee46a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201512731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.4201512731
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.1473441914
Short name T282
Test name
Test status
Simulation time 59600432960 ps
CPU time 1471.3 seconds
Started Aug 06 05:30:54 PM PDT 24
Finished Aug 06 05:55:25 PM PDT 24
Peak memory 321948 kb
Host smart-a041dadd-77e5-4199-89cf-77023e752c32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473441914 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.1473441914
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.517734341
Short name T966
Test name
Test status
Simulation time 234752365 ps
CPU time 4.67 seconds
Started Aug 06 05:30:54 PM PDT 24
Finished Aug 06 05:30:58 PM PDT 24
Peak memory 241832 kb
Host smart-05c93bea-340f-40c0-b182-c507528b5e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517734341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.517734341
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.4262427868
Short name T550
Test name
Test status
Simulation time 63353393 ps
CPU time 1.84 seconds
Started Aug 06 05:31:07 PM PDT 24
Finished Aug 06 05:31:09 PM PDT 24
Peak memory 240412 kb
Host smart-3023b06c-c568-4240-8beb-ba030842b368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262427868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.4262427868
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.866332086
Short name T247
Test name
Test status
Simulation time 8364106013 ps
CPU time 44.13 seconds
Started Aug 06 05:31:06 PM PDT 24
Finished Aug 06 05:31:50 PM PDT 24
Peak memory 248684 kb
Host smart-a039b88f-5cd0-4dda-bb52-b19861cae39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866332086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.866332086
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.3741433875
Short name T638
Test name
Test status
Simulation time 2454593767 ps
CPU time 24.13 seconds
Started Aug 06 05:31:05 PM PDT 24
Finished Aug 06 05:31:29 PM PDT 24
Peak memory 242196 kb
Host smart-d716dffe-3c04-4c57-89e0-f9c62ed532a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741433875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.3741433875
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.4225343678
Short name T655
Test name
Test status
Simulation time 5424005304 ps
CPU time 26.77 seconds
Started Aug 06 05:31:05 PM PDT 24
Finished Aug 06 05:31:32 PM PDT 24
Peak memory 242236 kb
Host smart-963d713c-bdb6-4a25-8623-48beb5183d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225343678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.4225343678
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.2396090192
Short name T1143
Test name
Test status
Simulation time 981233219 ps
CPU time 19.26 seconds
Started Aug 06 05:31:06 PM PDT 24
Finished Aug 06 05:31:25 PM PDT 24
Peak memory 242408 kb
Host smart-2c40c3d1-c6b3-436f-aceb-d45ecda05606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396090192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.2396090192
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.1298601169
Short name T793
Test name
Test status
Simulation time 156895720 ps
CPU time 3.98 seconds
Started Aug 06 05:31:06 PM PDT 24
Finished Aug 06 05:31:10 PM PDT 24
Peak memory 241964 kb
Host smart-77c2212b-5488-4145-bdfe-9c9f600e4a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298601169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.1298601169
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.3734699058
Short name T191
Test name
Test status
Simulation time 8027850324 ps
CPU time 60.95 seconds
Started Aug 06 05:31:04 PM PDT 24
Finished Aug 06 05:32:05 PM PDT 24
Peak memory 261828 kb
Host smart-25439ecf-ea4e-4473-96c9-7decc7f3f9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734699058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.3734699058
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.1777079056
Short name T967
Test name
Test status
Simulation time 1848906900 ps
CPU time 16.74 seconds
Started Aug 06 05:31:06 PM PDT 24
Finished Aug 06 05:31:23 PM PDT 24
Peak memory 242492 kb
Host smart-c968a512-fab1-4653-8532-936706230f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777079056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.1777079056
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.2307986504
Short name T1133
Test name
Test status
Simulation time 165235799 ps
CPU time 5.02 seconds
Started Aug 06 05:31:07 PM PDT 24
Finished Aug 06 05:31:12 PM PDT 24
Peak memory 241860 kb
Host smart-5cf67f12-6b26-454a-97ff-56e206907273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307986504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.2307986504
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.142828623
Short name T368
Test name
Test status
Simulation time 808017070 ps
CPU time 21.53 seconds
Started Aug 06 05:31:05 PM PDT 24
Finished Aug 06 05:31:27 PM PDT 24
Peak memory 242032 kb
Host smart-a23c7c36-f9a0-4976-b2a2-8198b82a0979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=142828623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.142828623
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.3417240636
Short name T22
Test name
Test status
Simulation time 19038313548 ps
CPU time 170.63 seconds
Started Aug 06 05:31:05 PM PDT 24
Finished Aug 06 05:33:56 PM PDT 24
Peak memory 270232 kb
Host smart-4b619bb0-dc6c-4803-96d5-b0d273692e87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417240636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3417240636
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.2551589536
Short name T413
Test name
Test status
Simulation time 902839101 ps
CPU time 13.01 seconds
Started Aug 06 05:31:05 PM PDT 24
Finished Aug 06 05:31:18 PM PDT 24
Peak memory 241948 kb
Host smart-e23d868a-53c6-4328-8068-f7d33bf5bb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551589536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.2551589536
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.4049649071
Short name T588
Test name
Test status
Simulation time 1634475653 ps
CPU time 15.55 seconds
Started Aug 06 05:31:06 PM PDT 24
Finished Aug 06 05:31:22 PM PDT 24
Peak memory 241908 kb
Host smart-40f770f4-7b29-4d69-8b36-5cb03ffbd747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049649071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
4049649071
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.841467550
Short name T947
Test name
Test status
Simulation time 661745012 ps
CPU time 14.38 seconds
Started Aug 06 05:31:07 PM PDT 24
Finished Aug 06 05:31:21 PM PDT 24
Peak memory 242284 kb
Host smart-6cac5a68-da6e-4314-ada6-40d6d6c3e99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841467550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.841467550
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.2041135687
Short name T678
Test name
Test status
Simulation time 135644163 ps
CPU time 1.97 seconds
Started Aug 06 05:32:15 PM PDT 24
Finished Aug 06 05:32:17 PM PDT 24
Peak memory 240820 kb
Host smart-9b6a437e-2fc3-4fa1-a2ac-09195a1728a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041135687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.2041135687
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.3470419864
Short name T834
Test name
Test status
Simulation time 478281009 ps
CPU time 13.39 seconds
Started Aug 06 05:32:16 PM PDT 24
Finished Aug 06 05:32:30 PM PDT 24
Peak memory 241948 kb
Host smart-d21104a8-4b46-4918-974f-e27e5a5e53ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470419864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.3470419864
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.1615128601
Short name T449
Test name
Test status
Simulation time 1785833507 ps
CPU time 28.86 seconds
Started Aug 06 05:32:16 PM PDT 24
Finished Aug 06 05:32:45 PM PDT 24
Peak memory 241968 kb
Host smart-652ccdbc-eaea-4687-b97c-7a70fcc8b4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615128601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.1615128601
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.1504651665
Short name T634
Test name
Test status
Simulation time 380582128 ps
CPU time 4.83 seconds
Started Aug 06 05:32:15 PM PDT 24
Finished Aug 06 05:32:20 PM PDT 24
Peak memory 242284 kb
Host smart-5cd307c1-2995-4e98-9c5f-11511adcd629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504651665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.1504651665
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.2163478568
Short name T706
Test name
Test status
Simulation time 239173415 ps
CPU time 6.13 seconds
Started Aug 06 05:32:14 PM PDT 24
Finished Aug 06 05:32:20 PM PDT 24
Peak memory 242020 kb
Host smart-1881e064-939d-47ba-8dc7-6ada20d2a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163478568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.2163478568
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.4242521314
Short name T108
Test name
Test status
Simulation time 3036713302 ps
CPU time 7.45 seconds
Started Aug 06 05:32:19 PM PDT 24
Finished Aug 06 05:32:26 PM PDT 24
Peak memory 241988 kb
Host smart-b4063aab-3eca-4c7c-90ea-48fe3b4e2449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242521314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.4242521314
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.2371640087
Short name T310
Test name
Test status
Simulation time 226867478 ps
CPU time 5.32 seconds
Started Aug 06 05:32:16 PM PDT 24
Finished Aug 06 05:32:21 PM PDT 24
Peak memory 241956 kb
Host smart-58525e4f-9e2f-4f78-9125-c6f802831055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371640087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.2371640087
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.2504953092
Short name T710
Test name
Test status
Simulation time 502063399 ps
CPU time 5.34 seconds
Started Aug 06 05:32:14 PM PDT 24
Finished Aug 06 05:32:19 PM PDT 24
Peak memory 247704 kb
Host smart-d47a74a7-5d44-4c22-8df3-ffb9c6d0907a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2504953092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.2504953092
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.4138242214
Short name T350
Test name
Test status
Simulation time 321538568 ps
CPU time 6.24 seconds
Started Aug 06 05:32:16 PM PDT 24
Finished Aug 06 05:32:22 PM PDT 24
Peak memory 241956 kb
Host smart-c206ab4a-3bc7-4be7-a9e2-f3758f80cf85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138242214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.4138242214
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.559212183
Short name T384
Test name
Test status
Simulation time 279481115 ps
CPU time 5.68 seconds
Started Aug 06 05:32:18 PM PDT 24
Finished Aug 06 05:32:23 PM PDT 24
Peak memory 241956 kb
Host smart-7595227b-22a2-4e0f-b5df-8a0620f93c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559212183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.559212183
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.1635831709
Short name T332
Test name
Test status
Simulation time 24922970412 ps
CPU time 304.97 seconds
Started Aug 06 05:32:14 PM PDT 24
Finished Aug 06 05:37:19 PM PDT 24
Peak memory 278380 kb
Host smart-26960b67-54dc-4cc3-9cba-1d8e49813bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635831709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.1635831709
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.740147829
Short name T121
Test name
Test status
Simulation time 384313188 ps
CPU time 10.63 seconds
Started Aug 06 05:32:15 PM PDT 24
Finished Aug 06 05:32:26 PM PDT 24
Peak memory 248572 kb
Host smart-91356c10-5f7d-420a-b563-be20ccf8891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740147829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.740147829
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.3533419718
Short name T431
Test name
Test status
Simulation time 1777824857 ps
CPU time 4.92 seconds
Started Aug 06 05:37:32 PM PDT 24
Finished Aug 06 05:37:37 PM PDT 24
Peak memory 242312 kb
Host smart-f817d5e0-52a0-429d-9bd1-b3b4d4a21f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533419718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.3533419718
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.728346578
Short name T490
Test name
Test status
Simulation time 2015715740 ps
CPU time 8.26 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:43 PM PDT 24
Peak memory 242368 kb
Host smart-2fbb2896-23bc-4a85-81f7-99601ec2ba5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728346578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.728346578
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.532715535
Short name T833
Test name
Test status
Simulation time 1558829416 ps
CPU time 5.98 seconds
Started Aug 06 05:37:32 PM PDT 24
Finished Aug 06 05:37:38 PM PDT 24
Peak memory 242120 kb
Host smart-981b3881-ad91-4f70-8d49-11b86527cbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532715535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.532715535
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.692280922
Short name T209
Test name
Test status
Simulation time 3728974615 ps
CPU time 19.75 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:54 PM PDT 24
Peak memory 242132 kb
Host smart-ccf2f099-fe37-4915-8d25-2c555c509877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692280922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.692280922
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.1155658771
Short name T632
Test name
Test status
Simulation time 338498855 ps
CPU time 4.91 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:39 PM PDT 24
Peak memory 241844 kb
Host smart-18b9f6d4-60ad-45a0-90e2-6d919e9c4633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155658771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.1155658771
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.2698681612
Short name T568
Test name
Test status
Simulation time 4865727967 ps
CPU time 27.1 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:38:01 PM PDT 24
Peak memory 241936 kb
Host smart-2fc6c2bf-74f7-46a3-91e1-cae3bb51d0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698681612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2698681612
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.1207222719
Short name T656
Test name
Test status
Simulation time 102272306 ps
CPU time 4.34 seconds
Started Aug 06 05:37:32 PM PDT 24
Finished Aug 06 05:37:36 PM PDT 24
Peak memory 242044 kb
Host smart-a03f1c80-ed94-4616-a814-9e14feeec118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207222719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.1207222719
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.3084833621
Short name T433
Test name
Test status
Simulation time 255778013 ps
CPU time 4.41 seconds
Started Aug 06 05:37:32 PM PDT 24
Finished Aug 06 05:37:37 PM PDT 24
Peak memory 241920 kb
Host smart-8983cd43-dd28-4b2c-bb6d-aed14a007a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084833621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.3084833621
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.1387268355
Short name T24
Test name
Test status
Simulation time 203159141 ps
CPU time 4.56 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:38 PM PDT 24
Peak memory 242208 kb
Host smart-75015656-6183-437d-a519-ed3086c58f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387268355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.1387268355
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.662799778
Short name T206
Test name
Test status
Simulation time 968043250 ps
CPU time 18.67 seconds
Started Aug 06 05:37:36 PM PDT 24
Finished Aug 06 05:37:55 PM PDT 24
Peak memory 242228 kb
Host smart-24b9ebd7-a2a2-4d56-86ee-891be4d55497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662799778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.662799778
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.2631838711
Short name T49
Test name
Test status
Simulation time 198852645 ps
CPU time 3.09 seconds
Started Aug 06 05:37:33 PM PDT 24
Finished Aug 06 05:37:37 PM PDT 24
Peak memory 242280 kb
Host smart-5bcbbd44-be83-44e4-8b3b-21603514fe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631838711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.2631838711
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.617328523
Short name T396
Test name
Test status
Simulation time 104770492 ps
CPU time 3.09 seconds
Started Aug 06 05:37:39 PM PDT 24
Finished Aug 06 05:37:42 PM PDT 24
Peak memory 241940 kb
Host smart-338b71f1-0a24-48f9-ae4b-61f6db022d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617328523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.617328523
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.1195173513
Short name T427
Test name
Test status
Simulation time 507698076 ps
CPU time 5.1 seconds
Started Aug 06 05:37:35 PM PDT 24
Finished Aug 06 05:37:40 PM PDT 24
Peak memory 241972 kb
Host smart-10b76d2c-dac9-48c1-ac67-36e7b757c1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195173513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1195173513
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.2801076002
Short name T760
Test name
Test status
Simulation time 1830994670 ps
CPU time 3.72 seconds
Started Aug 06 05:37:35 PM PDT 24
Finished Aug 06 05:37:39 PM PDT 24
Peak memory 242220 kb
Host smart-263d0042-d121-4cff-8893-dfe0e3137b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801076002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.2801076002
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.2739191206
Short name T657
Test name
Test status
Simulation time 396325070 ps
CPU time 4.24 seconds
Started Aug 06 05:37:35 PM PDT 24
Finished Aug 06 05:37:39 PM PDT 24
Peak memory 242244 kb
Host smart-fdb83b87-7340-4ae7-a788-5bb848e90afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739191206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.2739191206
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.843171099
Short name T775
Test name
Test status
Simulation time 948122421 ps
CPU time 13.93 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:48 PM PDT 24
Peak memory 242140 kb
Host smart-8fc1f999-5605-4441-8cbe-cbe36284f833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843171099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.843171099
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.4110782136
Short name T1128
Test name
Test status
Simulation time 578191986 ps
CPU time 4.72 seconds
Started Aug 06 05:37:39 PM PDT 24
Finished Aug 06 05:37:44 PM PDT 24
Peak memory 242128 kb
Host smart-32e5c729-deef-45a6-8f6d-0aed27ce5a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110782136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.4110782136
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.3517589799
Short name T1126
Test name
Test status
Simulation time 3753637627 ps
CPU time 17.3 seconds
Started Aug 06 05:37:32 PM PDT 24
Finished Aug 06 05:37:50 PM PDT 24
Peak memory 242084 kb
Host smart-6e4ceb6f-7596-47a0-bd6e-d3309fdef26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517589799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3517589799
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.2918210526
Short name T572
Test name
Test status
Simulation time 126033428 ps
CPU time 4.76 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:39 PM PDT 24
Peak memory 242052 kb
Host smart-e7ed0ea9-aaa5-47f7-9f56-22f21b1ab076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918210526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.2918210526
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.3688673753
Short name T416
Test name
Test status
Simulation time 1662727540 ps
CPU time 5 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:39 PM PDT 24
Peak memory 242248 kb
Host smart-c9d834cd-b3c4-4fa8-95a8-fdb3a9e4c787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688673753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.3688673753
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.3865799741
Short name T388
Test name
Test status
Simulation time 573217364 ps
CPU time 1.79 seconds
Started Aug 06 05:32:41 PM PDT 24
Finished Aug 06 05:32:42 PM PDT 24
Peak memory 240420 kb
Host smart-68b71ada-5219-4fc0-af4f-5edc3e4250cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865799741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.3865799741
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.1120140710
Short name T853
Test name
Test status
Simulation time 996744379 ps
CPU time 25.35 seconds
Started Aug 06 05:32:14 PM PDT 24
Finished Aug 06 05:32:40 PM PDT 24
Peak memory 242208 kb
Host smart-7378cf9f-de5d-427f-81c6-7c72d5e4dbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120140710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1120140710
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.1728017779
Short name T361
Test name
Test status
Simulation time 1396826380 ps
CPU time 34.64 seconds
Started Aug 06 05:32:15 PM PDT 24
Finished Aug 06 05:32:49 PM PDT 24
Peak memory 242544 kb
Host smart-fbf52936-2baa-4521-90d9-661853b52b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728017779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.1728017779
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.877188335
Short name T598
Test name
Test status
Simulation time 435867375 ps
CPU time 4.09 seconds
Started Aug 06 05:32:23 PM PDT 24
Finished Aug 06 05:32:27 PM PDT 24
Peak memory 242040 kb
Host smart-600ce037-7947-4cbf-85a7-d389b22c8a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877188335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.877188335
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.3722685871
Short name T531
Test name
Test status
Simulation time 379279326 ps
CPU time 7.49 seconds
Started Aug 06 05:32:41 PM PDT 24
Finished Aug 06 05:32:48 PM PDT 24
Peak memory 242360 kb
Host smart-71a96a03-4f00-4847-aa9f-f6dd4bf3daef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722685871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.3722685871
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.2933485351
Short name T1086
Test name
Test status
Simulation time 565990938 ps
CPU time 12.04 seconds
Started Aug 06 05:32:40 PM PDT 24
Finished Aug 06 05:32:52 PM PDT 24
Peak memory 242628 kb
Host smart-f8909af5-5798-4a13-8f9d-fc4548d0b1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933485351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2933485351
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.4045295699
Short name T438
Test name
Test status
Simulation time 2240986636 ps
CPU time 7.82 seconds
Started Aug 06 05:32:14 PM PDT 24
Finished Aug 06 05:32:22 PM PDT 24
Peak memory 242276 kb
Host smart-23140f5e-6919-4b35-87df-cce5d60bec64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045295699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.4045295699
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.1803614902
Short name T718
Test name
Test status
Simulation time 4208827365 ps
CPU time 7.83 seconds
Started Aug 06 05:32:19 PM PDT 24
Finished Aug 06 05:32:27 PM PDT 24
Peak memory 248664 kb
Host smart-dd3ac5c7-9ed8-428d-b3fe-6eca5768eebf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1803614902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.1803614902
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.2072529484
Short name T879
Test name
Test status
Simulation time 2066277451 ps
CPU time 5.86 seconds
Started Aug 06 05:32:40 PM PDT 24
Finished Aug 06 05:32:46 PM PDT 24
Peak memory 241944 kb
Host smart-61bdc2e9-e1ba-4dbe-890b-80a757383298
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072529484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.2072529484
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.1941400816
Short name T607
Test name
Test status
Simulation time 2837005065 ps
CPU time 7.11 seconds
Started Aug 06 05:32:22 PM PDT 24
Finished Aug 06 05:32:29 PM PDT 24
Peak memory 241984 kb
Host smart-46dd1c1d-ee6a-4bcc-b72c-1e24ebbfe9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941400816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.1941400816
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.1502274285
Short name T1102
Test name
Test status
Simulation time 26489757804 ps
CPU time 303.09 seconds
Started Aug 06 05:32:42 PM PDT 24
Finished Aug 06 05:37:46 PM PDT 24
Peak memory 265068 kb
Host smart-cc8c3fb1-4a82-409e-8930-d2b06771f4e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502274285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.1502274285
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.1525993345
Short name T537
Test name
Test status
Simulation time 10455217865 ps
CPU time 16.74 seconds
Started Aug 06 05:32:41 PM PDT 24
Finished Aug 06 05:32:58 PM PDT 24
Peak memory 248676 kb
Host smart-28abe415-4d5e-4315-afaa-b9540e9433c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525993345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.1525993345
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.1752230872
Short name T1150
Test name
Test status
Simulation time 159688509 ps
CPU time 4.55 seconds
Started Aug 06 05:37:35 PM PDT 24
Finished Aug 06 05:37:39 PM PDT 24
Peak memory 242076 kb
Host smart-29a98194-fe28-4fa1-bcf1-84224a1cb823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752230872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.1752230872
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.3252810991
Short name T1044
Test name
Test status
Simulation time 116529301 ps
CPU time 4.92 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:39 PM PDT 24
Peak memory 241752 kb
Host smart-d88dda57-c806-449c-9dcb-df45cdd611d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252810991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.3252810991
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.3453756129
Short name T1147
Test name
Test status
Simulation time 120674690 ps
CPU time 3.82 seconds
Started Aug 06 05:37:31 PM PDT 24
Finished Aug 06 05:37:35 PM PDT 24
Peak memory 241932 kb
Host smart-9e60b346-723f-49a7-889c-dfba4f92d776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453756129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3453756129
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.1918400834
Short name T261
Test name
Test status
Simulation time 149419715 ps
CPU time 5.77 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:40 PM PDT 24
Peak memory 242396 kb
Host smart-72a2966c-7989-4bfe-9c0d-932ef290b9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918400834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.1918400834
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.4259914933
Short name T403
Test name
Test status
Simulation time 151325816 ps
CPU time 4.04 seconds
Started Aug 06 05:37:32 PM PDT 24
Finished Aug 06 05:37:37 PM PDT 24
Peak memory 241876 kb
Host smart-85accb8d-4969-4741-a051-c8528e0a47e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259914933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.4259914933
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.192159136
Short name T669
Test name
Test status
Simulation time 336426029 ps
CPU time 8.64 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:43 PM PDT 24
Peak memory 241704 kb
Host smart-9bd0a8c7-e2e5-4ab1-9965-d27847411758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192159136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.192159136
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.3807081200
Short name T819
Test name
Test status
Simulation time 342800019 ps
CPU time 3.77 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:38 PM PDT 24
Peak memory 242320 kb
Host smart-7932ab0f-487e-49b7-9a56-bda0b889f9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807081200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3807081200
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.4163473230
Short name T1103
Test name
Test status
Simulation time 248739028 ps
CPU time 12.24 seconds
Started Aug 06 05:37:33 PM PDT 24
Finished Aug 06 05:37:46 PM PDT 24
Peak memory 242072 kb
Host smart-0d7a6c35-1aae-4cf0-be2d-8545c38de60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163473230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.4163473230
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.3156190010
Short name T662
Test name
Test status
Simulation time 261800692 ps
CPU time 4.98 seconds
Started Aug 06 05:37:32 PM PDT 24
Finished Aug 06 05:37:37 PM PDT 24
Peak memory 242056 kb
Host smart-f1a4d90c-009a-408b-b3f0-b844ef7939a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156190010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.3156190010
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.3331312906
Short name T841
Test name
Test status
Simulation time 2218485537 ps
CPU time 8.49 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:42 PM PDT 24
Peak memory 242304 kb
Host smart-cf930575-84a4-4b5d-9cb0-a7e7a10ac110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331312906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.3331312906
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.901685630
Short name T1007
Test name
Test status
Simulation time 1420376542 ps
CPU time 4.64 seconds
Started Aug 06 05:37:39 PM PDT 24
Finished Aug 06 05:37:44 PM PDT 24
Peak memory 241956 kb
Host smart-7bdc9232-fd4f-40f1-a081-100904f87a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901685630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.901685630
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.1669925186
Short name T401
Test name
Test status
Simulation time 208508212 ps
CPU time 3.54 seconds
Started Aug 06 05:37:35 PM PDT 24
Finished Aug 06 05:37:39 PM PDT 24
Peak memory 241888 kb
Host smart-d71937f1-a878-402c-ade6-0f6d1c7eab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669925186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.1669925186
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.21266663
Short name T547
Test name
Test status
Simulation time 717414044 ps
CPU time 17.75 seconds
Started Aug 06 05:37:34 PM PDT 24
Finished Aug 06 05:37:52 PM PDT 24
Peak memory 241760 kb
Host smart-cf45a5f9-7cf3-4117-81e4-73596f85bd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21266663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.21266663
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.4279709974
Short name T129
Test name
Test status
Simulation time 366210082 ps
CPU time 3.45 seconds
Started Aug 06 05:37:35 PM PDT 24
Finished Aug 06 05:37:38 PM PDT 24
Peak memory 242324 kb
Host smart-dff71057-ae85-46d2-ba85-b5d49b361f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279709974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.4279709974
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.147043188
Short name T41
Test name
Test status
Simulation time 2288565238 ps
CPU time 5.04 seconds
Started Aug 06 05:37:31 PM PDT 24
Finished Aug 06 05:37:36 PM PDT 24
Peak memory 242304 kb
Host smart-b3f8f40b-a8e2-469f-8863-5566efadf518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147043188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.147043188
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.2343275730
Short name T157
Test name
Test status
Simulation time 1844692513 ps
CPU time 7.7 seconds
Started Aug 06 05:37:35 PM PDT 24
Finished Aug 06 05:37:43 PM PDT 24
Peak memory 242084 kb
Host smart-e322f354-bf76-4408-8321-fcfaeafaee42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343275730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2343275730
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.404508710
Short name T546
Test name
Test status
Simulation time 632522376 ps
CPU time 5.51 seconds
Started Aug 06 05:37:32 PM PDT 24
Finished Aug 06 05:37:37 PM PDT 24
Peak memory 242368 kb
Host smart-d1b03bcb-dc99-4065-9400-b3b466e3fc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404508710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.404508710
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.3995346461
Short name T325
Test name
Test status
Simulation time 331918938 ps
CPU time 5.19 seconds
Started Aug 06 05:37:31 PM PDT 24
Finished Aug 06 05:37:36 PM PDT 24
Peak memory 241956 kb
Host smart-a0d24155-ed64-41a1-ad49-e06c29571d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995346461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.3995346461
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.257148280
Short name T1012
Test name
Test status
Simulation time 113234345 ps
CPU time 1.84 seconds
Started Aug 06 05:32:42 PM PDT 24
Finished Aug 06 05:32:44 PM PDT 24
Peak memory 240472 kb
Host smart-d7f0dc0b-f90c-4a97-9cc8-50b96f12c797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257148280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.257148280
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.3532801193
Short name T1047
Test name
Test status
Simulation time 2250984484 ps
CPU time 11.82 seconds
Started Aug 06 05:32:42 PM PDT 24
Finished Aug 06 05:32:54 PM PDT 24
Peak memory 248632 kb
Host smart-104a4d65-a976-494f-b100-ae75f90b0f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532801193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.3532801193
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.3790044866
Short name T538
Test name
Test status
Simulation time 25208178086 ps
CPU time 92.25 seconds
Started Aug 06 05:32:45 PM PDT 24
Finished Aug 06 05:34:18 PM PDT 24
Peak memory 258488 kb
Host smart-411137c9-767a-4adf-bd69-2a43b81c1840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790044866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.3790044866
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.2354020932
Short name T822
Test name
Test status
Simulation time 3056172260 ps
CPU time 21.23 seconds
Started Aug 06 05:32:44 PM PDT 24
Finished Aug 06 05:33:06 PM PDT 24
Peak memory 242408 kb
Host smart-a28bfbe1-b339-49b0-a157-0e402360fcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354020932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.2354020932
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.1238341301
Short name T901
Test name
Test status
Simulation time 2106865900 ps
CPU time 5.85 seconds
Started Aug 06 05:32:42 PM PDT 24
Finished Aug 06 05:32:48 PM PDT 24
Peak memory 241912 kb
Host smart-d5c5b050-39b1-49f4-a4f8-c41e87856a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238341301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1238341301
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.3870085194
Short name T939
Test name
Test status
Simulation time 3263103528 ps
CPU time 29.33 seconds
Started Aug 06 05:32:43 PM PDT 24
Finished Aug 06 05:33:12 PM PDT 24
Peak memory 248624 kb
Host smart-77d8121e-4f7f-4dcc-a9f4-6edb2a2149d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870085194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.3870085194
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.553776028
Short name T959
Test name
Test status
Simulation time 719782566 ps
CPU time 6.62 seconds
Started Aug 06 05:32:42 PM PDT 24
Finished Aug 06 05:32:49 PM PDT 24
Peak memory 242072 kb
Host smart-fa7a87c8-5784-4bd5-ab82-8c1367dbeb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553776028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.553776028
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.1617703830
Short name T532
Test name
Test status
Simulation time 94045052 ps
CPU time 2.68 seconds
Started Aug 06 05:32:42 PM PDT 24
Finished Aug 06 05:32:45 PM PDT 24
Peak memory 241956 kb
Host smart-120ce849-c44e-4071-83a4-b1f78120bcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617703830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1617703830
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.3622997029
Short name T994
Test name
Test status
Simulation time 809947004 ps
CPU time 10 seconds
Started Aug 06 05:32:45 PM PDT 24
Finished Aug 06 05:32:55 PM PDT 24
Peak memory 248508 kb
Host smart-32489481-bb15-4d0b-a322-890d6e97cddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622997029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.3622997029
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.1245170049
Short name T1113
Test name
Test status
Simulation time 5142442855 ps
CPU time 15.85 seconds
Started Aug 06 05:32:43 PM PDT 24
Finished Aug 06 05:32:59 PM PDT 24
Peak memory 242888 kb
Host smart-5388847a-03ac-4359-84b8-edff4f3ec327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1245170049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1245170049
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.2627315902
Short name T519
Test name
Test status
Simulation time 332931927 ps
CPU time 6.33 seconds
Started Aug 06 05:32:41 PM PDT 24
Finished Aug 06 05:32:47 PM PDT 24
Peak memory 242232 kb
Host smart-bc73a545-3d8c-4c77-a6d4-22e9fc808062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627315902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2627315902
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.1741194680
Short name T371
Test name
Test status
Simulation time 114080971659 ps
CPU time 1386.44 seconds
Started Aug 06 05:32:44 PM PDT 24
Finished Aug 06 05:55:51 PM PDT 24
Peak memory 333088 kb
Host smart-f8b1e588-77f0-42ff-86e9-a0e55cf9631a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741194680 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.1741194680
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.1248028781
Short name T1163
Test name
Test status
Simulation time 5630668185 ps
CPU time 49.91 seconds
Started Aug 06 05:32:42 PM PDT 24
Finished Aug 06 05:33:32 PM PDT 24
Peak memory 242212 kb
Host smart-2de60cc6-c213-4af7-b1cd-563932ce07a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248028781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1248028781
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.1521889082
Short name T1061
Test name
Test status
Simulation time 1850918878 ps
CPU time 5.51 seconds
Started Aug 06 05:37:46 PM PDT 24
Finished Aug 06 05:37:52 PM PDT 24
Peak memory 242376 kb
Host smart-4de01093-be75-4ee8-944e-528f93234ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521889082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.1521889082
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.537716212
Short name T258
Test name
Test status
Simulation time 402774302 ps
CPU time 5.36 seconds
Started Aug 06 05:37:47 PM PDT 24
Finished Aug 06 05:37:52 PM PDT 24
Peak memory 241956 kb
Host smart-f78ce79f-7140-4333-ab9a-5f7e6c327158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537716212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.537716212
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.2350971145
Short name T107
Test name
Test status
Simulation time 155898425 ps
CPU time 4.17 seconds
Started Aug 06 05:37:51 PM PDT 24
Finished Aug 06 05:37:55 PM PDT 24
Peak memory 241924 kb
Host smart-89551105-6a04-46c8-aec6-c27a31520606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350971145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2350971145
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.3511117337
Short name T154
Test name
Test status
Simulation time 336844970 ps
CPU time 10.47 seconds
Started Aug 06 05:37:46 PM PDT 24
Finished Aug 06 05:37:56 PM PDT 24
Peak memory 241800 kb
Host smart-0297a4f9-019b-439d-b0a2-db60aabe1c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511117337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3511117337
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.84913104
Short name T1155
Test name
Test status
Simulation time 1544543514 ps
CPU time 4.65 seconds
Started Aug 06 05:37:46 PM PDT 24
Finished Aug 06 05:37:50 PM PDT 24
Peak memory 242400 kb
Host smart-8aad73a2-8ac8-4ea7-bf67-bc920bf3a48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84913104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.84913104
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.4283269834
Short name T911
Test name
Test status
Simulation time 345492384 ps
CPU time 4.81 seconds
Started Aug 06 05:37:46 PM PDT 24
Finished Aug 06 05:37:51 PM PDT 24
Peak memory 241972 kb
Host smart-18bcbe02-f723-4f77-969e-d521f438e4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283269834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.4283269834
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.810517876
Short name T1151
Test name
Test status
Simulation time 2696813192 ps
CPU time 5.49 seconds
Started Aug 06 05:37:52 PM PDT 24
Finished Aug 06 05:37:58 PM PDT 24
Peak memory 242044 kb
Host smart-b42f64fb-8d2e-41a3-b5b8-8943d723d36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810517876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.810517876
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.2806438934
Short name T503
Test name
Test status
Simulation time 489742138 ps
CPU time 19.58 seconds
Started Aug 06 05:37:50 PM PDT 24
Finished Aug 06 05:38:09 PM PDT 24
Peak memory 242344 kb
Host smart-f0023616-f54c-4730-9a23-59c009ad0b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806438934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.2806438934
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.2265227904
Short name T624
Test name
Test status
Simulation time 227657552 ps
CPU time 3.17 seconds
Started Aug 06 05:37:47 PM PDT 24
Finished Aug 06 05:37:50 PM PDT 24
Peak memory 242296 kb
Host smart-8d06712f-0e82-443a-8ed2-dabef4f6073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265227904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.2265227904
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.2176217712
Short name T1144
Test name
Test status
Simulation time 4186170304 ps
CPU time 18.92 seconds
Started Aug 06 05:37:46 PM PDT 24
Finished Aug 06 05:38:05 PM PDT 24
Peak memory 242084 kb
Host smart-e1f0baac-7608-4e5a-ba09-79e13c3fe0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176217712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.2176217712
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.1133172326
Short name T183
Test name
Test status
Simulation time 276495687 ps
CPU time 3.73 seconds
Started Aug 06 05:37:55 PM PDT 24
Finished Aug 06 05:37:59 PM PDT 24
Peak memory 241888 kb
Host smart-efc3fcd1-621e-46d0-a07b-faef6996905b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133172326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.1133172326
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.3518721935
Short name T838
Test name
Test status
Simulation time 191261245 ps
CPU time 9.67 seconds
Started Aug 06 05:37:47 PM PDT 24
Finished Aug 06 05:37:56 PM PDT 24
Peak memory 247400 kb
Host smart-69d81a7f-1946-4e8d-a0f5-f2eac9766037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518721935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.3518721935
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.61436561
Short name T169
Test name
Test status
Simulation time 1973167751 ps
CPU time 5.93 seconds
Started Aug 06 05:37:56 PM PDT 24
Finished Aug 06 05:38:02 PM PDT 24
Peak memory 241944 kb
Host smart-7f73c5a5-251c-42a5-8de9-59c174db4ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61436561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.61436561
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.2645560534
Short name T417
Test name
Test status
Simulation time 4762913022 ps
CPU time 16.34 seconds
Started Aug 06 05:37:48 PM PDT 24
Finished Aug 06 05:38:05 PM PDT 24
Peak memory 242404 kb
Host smart-41c4fced-f219-4f50-81a2-4afc5024f8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645560534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.2645560534
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.3636948266
Short name T1161
Test name
Test status
Simulation time 1712923540 ps
CPU time 4.92 seconds
Started Aug 06 05:37:55 PM PDT 24
Finished Aug 06 05:38:00 PM PDT 24
Peak memory 241836 kb
Host smart-a9ca2f8a-109c-4aec-9c54-55b5537cac07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636948266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.3636948266
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.2112727988
Short name T135
Test name
Test status
Simulation time 140571818 ps
CPU time 4.3 seconds
Started Aug 06 05:37:56 PM PDT 24
Finished Aug 06 05:38:00 PM PDT 24
Peak memory 241824 kb
Host smart-00e3cb0a-f47e-40d2-8785-4bb09db63cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112727988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.2112727988
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.3128081273
Short name T400
Test name
Test status
Simulation time 120049650 ps
CPU time 3.23 seconds
Started Aug 06 05:37:50 PM PDT 24
Finished Aug 06 05:37:53 PM PDT 24
Peak memory 242280 kb
Host smart-d17914a7-b05b-455a-9d67-27588802ae93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128081273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.3128081273
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.4279502457
Short name T54
Test name
Test status
Simulation time 126437841 ps
CPU time 4.93 seconds
Started Aug 06 05:37:47 PM PDT 24
Finished Aug 06 05:37:52 PM PDT 24
Peak memory 242212 kb
Host smart-90cca1e9-2f34-456c-a490-bd8204e11544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279502457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.4279502457
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.2308110303
Short name T453
Test name
Test status
Simulation time 221537156 ps
CPU time 5.73 seconds
Started Aug 06 05:37:52 PM PDT 24
Finished Aug 06 05:37:58 PM PDT 24
Peak memory 242020 kb
Host smart-ec5a54fd-17ce-4865-941f-97d45bf7ba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308110303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2308110303
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.4272511132
Short name T725
Test name
Test status
Simulation time 627861619 ps
CPU time 2.17 seconds
Started Aug 06 05:33:01 PM PDT 24
Finished Aug 06 05:33:03 PM PDT 24
Peak memory 240744 kb
Host smart-c34e5baf-fc19-4aff-a1af-e0ae4dd61634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272511132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.4272511132
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.900814113
Short name T650
Test name
Test status
Simulation time 424093291 ps
CPU time 6.17 seconds
Started Aug 06 05:33:01 PM PDT 24
Finished Aug 06 05:33:07 PM PDT 24
Peak memory 242608 kb
Host smart-acd583be-6933-4a03-b057-d45a751c880a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900814113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.900814113
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.2045244926
Short name T1002
Test name
Test status
Simulation time 434294161 ps
CPU time 15.33 seconds
Started Aug 06 05:33:02 PM PDT 24
Finished Aug 06 05:33:17 PM PDT 24
Peak memory 241824 kb
Host smart-b6317cbb-a48b-40ae-9f6e-76d7105bfb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045244926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.2045244926
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.988069200
Short name T727
Test name
Test status
Simulation time 10302079618 ps
CPU time 88.96 seconds
Started Aug 06 05:33:05 PM PDT 24
Finished Aug 06 05:34:34 PM PDT 24
Peak memory 243160 kb
Host smart-685ba339-54ed-4ab3-899e-bdcd034dd12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988069200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.988069200
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.611141670
Short name T1127
Test name
Test status
Simulation time 523377305 ps
CPU time 5.39 seconds
Started Aug 06 05:32:44 PM PDT 24
Finished Aug 06 05:32:50 PM PDT 24
Peak memory 242076 kb
Host smart-b47e5c7d-ecbf-4697-bfb8-1586289bd8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611141670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.611141670
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.3202959518
Short name T975
Test name
Test status
Simulation time 356287863 ps
CPU time 11.66 seconds
Started Aug 06 05:33:01 PM PDT 24
Finished Aug 06 05:33:12 PM PDT 24
Peak memory 242200 kb
Host smart-412ace9e-60dd-4142-baf6-7943d87ec5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202959518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.3202959518
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.2192236304
Short name T96
Test name
Test status
Simulation time 8927368567 ps
CPU time 24.25 seconds
Started Aug 06 05:33:02 PM PDT 24
Finished Aug 06 05:33:26 PM PDT 24
Peak memory 242216 kb
Host smart-b6f265a3-d825-4a1f-94c0-f7093e5ff10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192236304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.2192236304
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.2312681270
Short name T980
Test name
Test status
Simulation time 360796938 ps
CPU time 6.58 seconds
Started Aug 06 05:33:00 PM PDT 24
Finished Aug 06 05:33:06 PM PDT 24
Peak memory 241888 kb
Host smart-af254308-f0bf-4211-ba5b-63c92cfd58a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312681270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.2312681270
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.957037879
Short name T653
Test name
Test status
Simulation time 5357817986 ps
CPU time 14.31 seconds
Started Aug 06 05:33:01 PM PDT 24
Finished Aug 06 05:33:15 PM PDT 24
Peak memory 242088 kb
Host smart-3b02fefd-2a5a-4098-8bd1-1330ea0ca35a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957037879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.957037879
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.1182152552
Short name T763
Test name
Test status
Simulation time 3830019790 ps
CPU time 11.07 seconds
Started Aug 06 05:33:02 PM PDT 24
Finished Aug 06 05:33:13 PM PDT 24
Peak memory 241868 kb
Host smart-ceae6839-47b6-437a-bbe2-714d47589456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182152552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.1182152552
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.2500590332
Short name T774
Test name
Test status
Simulation time 291234949 ps
CPU time 6.1 seconds
Started Aug 06 05:32:45 PM PDT 24
Finished Aug 06 05:32:51 PM PDT 24
Peak memory 241940 kb
Host smart-be96953d-dd34-424e-86bd-0d372071bbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500590332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.2500590332
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.169972585
Short name T934
Test name
Test status
Simulation time 2335844810 ps
CPU time 51.35 seconds
Started Aug 06 05:33:01 PM PDT 24
Finished Aug 06 05:33:52 PM PDT 24
Peak memory 262696 kb
Host smart-4d3e356b-ef52-4157-9eb0-0ac83a21d885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169972585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.
169972585
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.2604526990
Short name T1074
Test name
Test status
Simulation time 97589339006 ps
CPU time 1232.35 seconds
Started Aug 06 05:33:01 PM PDT 24
Finished Aug 06 05:53:33 PM PDT 24
Peak memory 265164 kb
Host smart-1c9d8c8b-3c98-4c8a-82e9-06b2fd1f306d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604526990 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.2604526990
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.423415521
Short name T1064
Test name
Test status
Simulation time 1611839855 ps
CPU time 27.75 seconds
Started Aug 06 05:33:02 PM PDT 24
Finished Aug 06 05:33:30 PM PDT 24
Peak memory 241944 kb
Host smart-ed164c68-fd14-4e04-9bee-16e631b5c726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423415521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.423415521
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.3122275992
Short name T212
Test name
Test status
Simulation time 2069065741 ps
CPU time 5.68 seconds
Started Aug 06 05:37:46 PM PDT 24
Finished Aug 06 05:37:51 PM PDT 24
Peak memory 241988 kb
Host smart-53487b3f-9a1f-418c-921c-bf9fd658c04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122275992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.3122275992
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.3443565525
Short name T1096
Test name
Test status
Simulation time 112421439 ps
CPU time 3.38 seconds
Started Aug 06 05:37:46 PM PDT 24
Finished Aug 06 05:37:50 PM PDT 24
Peak memory 242380 kb
Host smart-96ae0ab9-ab8f-4f74-bec4-123e857bb727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443565525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.3443565525
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.3865425646
Short name T625
Test name
Test status
Simulation time 431517724 ps
CPU time 14.68 seconds
Started Aug 06 05:37:46 PM PDT 24
Finished Aug 06 05:38:01 PM PDT 24
Peak memory 241848 kb
Host smart-888cafae-8545-4b3c-8cf9-b2b4566d29ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865425646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3865425646
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.598074895
Short name T136
Test name
Test status
Simulation time 370614715 ps
CPU time 5.23 seconds
Started Aug 06 05:37:53 PM PDT 24
Finished Aug 06 05:37:58 PM PDT 24
Peak memory 241976 kb
Host smart-d62a7202-c275-43c4-9773-a17084eedfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598074895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.598074895
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.20653921
Short name T932
Test name
Test status
Simulation time 156421248 ps
CPU time 4.4 seconds
Started Aug 06 05:37:49 PM PDT 24
Finished Aug 06 05:37:53 PM PDT 24
Peak memory 241964 kb
Host smart-ef905b42-47f7-40b9-8fae-4912e2152351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20653921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.20653921
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.2397784122
Short name T846
Test name
Test status
Simulation time 1977625095 ps
CPU time 6.63 seconds
Started Aug 06 05:37:52 PM PDT 24
Finished Aug 06 05:37:59 PM PDT 24
Peak memory 242284 kb
Host smart-be2f0e97-0896-4c68-8dff-feced87a4d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397784122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.2397784122
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.2721243982
Short name T898
Test name
Test status
Simulation time 7343381402 ps
CPU time 12.92 seconds
Started Aug 06 05:37:48 PM PDT 24
Finished Aug 06 05:38:01 PM PDT 24
Peak memory 242352 kb
Host smart-3095e1c9-be5f-4746-83fb-938fb7e21e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721243982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.2721243982
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.2028648002
Short name T115
Test name
Test status
Simulation time 105535651 ps
CPU time 4.23 seconds
Started Aug 06 05:37:52 PM PDT 24
Finished Aug 06 05:37:56 PM PDT 24
Peak memory 241928 kb
Host smart-d8d8dbd3-f54d-4b7f-a5c9-afced146f24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028648002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.2028648002
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.4117030104
Short name T312
Test name
Test status
Simulation time 106445906 ps
CPU time 4.31 seconds
Started Aug 06 05:37:50 PM PDT 24
Finished Aug 06 05:37:54 PM PDT 24
Peak memory 242296 kb
Host smart-a27b2a50-1c26-4f1c-afbf-8e06bd85aadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117030104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.4117030104
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.3805975230
Short name T787
Test name
Test status
Simulation time 161689250 ps
CPU time 2.9 seconds
Started Aug 06 05:37:54 PM PDT 24
Finished Aug 06 05:37:57 PM PDT 24
Peak memory 241972 kb
Host smart-a6aea9b6-457b-4065-ba87-96c2292a12eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805975230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.3805975230
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.773348932
Short name T1089
Test name
Test status
Simulation time 457349489 ps
CPU time 16.72 seconds
Started Aug 06 05:37:51 PM PDT 24
Finished Aug 06 05:38:08 PM PDT 24
Peak memory 241972 kb
Host smart-09a0f62c-610e-4c33-8b67-365db6441183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773348932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.773348932
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.380387032
Short name T863
Test name
Test status
Simulation time 630158766 ps
CPU time 13.18 seconds
Started Aug 06 05:37:52 PM PDT 24
Finished Aug 06 05:38:05 PM PDT 24
Peak memory 242020 kb
Host smart-378a675b-43c8-48ef-bf40-b213773d9b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380387032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.380387032
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.1536086621
Short name T692
Test name
Test status
Simulation time 2004636225 ps
CPU time 6.02 seconds
Started Aug 06 05:37:51 PM PDT 24
Finished Aug 06 05:37:58 PM PDT 24
Peak memory 241868 kb
Host smart-95955596-a3a0-4608-934e-3573f21545b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536086621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.1536086621
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.402919096
Short name T890
Test name
Test status
Simulation time 3024513908 ps
CPU time 7.46 seconds
Started Aug 06 05:37:50 PM PDT 24
Finished Aug 06 05:37:58 PM PDT 24
Peak memory 242224 kb
Host smart-d6d08008-6bc2-40ec-ba9d-a7c01dccda21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402919096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.402919096
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.99876619
Short name T499
Test name
Test status
Simulation time 254064023 ps
CPU time 4 seconds
Started Aug 06 05:37:51 PM PDT 24
Finished Aug 06 05:37:55 PM PDT 24
Peak memory 242036 kb
Host smart-afe8177e-5930-4915-a244-4e0ae340ab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99876619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.99876619
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.1744793501
Short name T147
Test name
Test status
Simulation time 175392022 ps
CPU time 3.59 seconds
Started Aug 06 05:37:48 PM PDT 24
Finished Aug 06 05:37:51 PM PDT 24
Peak memory 242196 kb
Host smart-a82036b0-0465-433c-81e7-0458660b8d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744793501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.1744793501
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.1788466726
Short name T241
Test name
Test status
Simulation time 100518345 ps
CPU time 3.78 seconds
Started Aug 06 05:37:59 PM PDT 24
Finished Aug 06 05:38:03 PM PDT 24
Peak memory 242244 kb
Host smart-5166524d-0260-40e0-af08-074b21d2946b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788466726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.1788466726
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.1843132367
Short name T254
Test name
Test status
Simulation time 883981565 ps
CPU time 12.32 seconds
Started Aug 06 05:37:58 PM PDT 24
Finished Aug 06 05:38:10 PM PDT 24
Peak memory 242472 kb
Host smart-f02986d7-d56d-4df9-8159-a6e698e2d88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843132367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.1843132367
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.88664575
Short name T382
Test name
Test status
Simulation time 58857557 ps
CPU time 1.86 seconds
Started Aug 06 05:33:04 PM PDT 24
Finished Aug 06 05:33:07 PM PDT 24
Peak memory 240384 kb
Host smart-ca6e651d-9311-491f-bfea-95b9e80e8bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88664575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.88664575
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.1228582734
Short name T469
Test name
Test status
Simulation time 4275319056 ps
CPU time 19.12 seconds
Started Aug 06 05:33:01 PM PDT 24
Finished Aug 06 05:33:21 PM PDT 24
Peak memory 241916 kb
Host smart-8e585640-9ef1-47f6-b22a-53c7c8455586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228582734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.1228582734
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.2150636479
Short name T104
Test name
Test status
Simulation time 552103946 ps
CPU time 5.76 seconds
Started Aug 06 05:33:06 PM PDT 24
Finished Aug 06 05:33:12 PM PDT 24
Peak memory 241972 kb
Host smart-92ab023e-74c2-4432-85ab-4fd902dd44db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150636479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.2150636479
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.222770815
Short name T938
Test name
Test status
Simulation time 2959056911 ps
CPU time 15.28 seconds
Started Aug 06 05:33:05 PM PDT 24
Finished Aug 06 05:33:21 PM PDT 24
Peak memory 248592 kb
Host smart-d074f832-d741-4576-accf-e850f8727315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222770815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.222770815
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.3652098490
Short name T703
Test name
Test status
Simulation time 895583521 ps
CPU time 29.34 seconds
Started Aug 06 05:33:06 PM PDT 24
Finished Aug 06 05:33:36 PM PDT 24
Peak memory 242584 kb
Host smart-44a6ef75-ceb2-48f3-98cb-7e0915a184ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652098490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.3652098490
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.926533108
Short name T829
Test name
Test status
Simulation time 401327619 ps
CPU time 10.45 seconds
Started Aug 06 05:33:04 PM PDT 24
Finished Aug 06 05:33:15 PM PDT 24
Peak memory 241884 kb
Host smart-8452ff99-3a3f-452c-91ab-18bb879c7262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926533108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.926533108
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.3123103377
Short name T1171
Test name
Test status
Simulation time 113370254 ps
CPU time 3.36 seconds
Started Aug 06 05:33:04 PM PDT 24
Finished Aug 06 05:33:07 PM PDT 24
Peak memory 242108 kb
Host smart-27b8331e-3d3c-4bb8-853d-c4950d3e379a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3123103377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.3123103377
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.2298728401
Short name T103
Test name
Test status
Simulation time 909272534 ps
CPU time 7.58 seconds
Started Aug 06 05:33:03 PM PDT 24
Finished Aug 06 05:33:11 PM PDT 24
Peak memory 241960 kb
Host smart-f36de2d0-261f-496b-9f83-8c4dcdb4a409
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2298728401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.2298728401
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.1992289956
Short name T908
Test name
Test status
Simulation time 907778353 ps
CPU time 10.85 seconds
Started Aug 06 05:33:03 PM PDT 24
Finished Aug 06 05:33:14 PM PDT 24
Peak memory 242268 kb
Host smart-2055c3cd-53b9-4c82-b29b-1c9fb3d3db4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992289956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1992289956
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.4191141432
Short name T983
Test name
Test status
Simulation time 3250883151 ps
CPU time 29.28 seconds
Started Aug 06 05:33:04 PM PDT 24
Finished Aug 06 05:33:33 PM PDT 24
Peak memory 241920 kb
Host smart-ecabf1a6-0270-4e97-b067-100bfc834b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191141432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.4191141432
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.3160661254
Short name T152
Test name
Test status
Simulation time 116467238 ps
CPU time 4.4 seconds
Started Aug 06 05:37:58 PM PDT 24
Finished Aug 06 05:38:03 PM PDT 24
Peak memory 241828 kb
Host smart-f3f34099-9b3e-4f73-aa80-3e0382cca9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160661254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.3160661254
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.3515174104
Short name T460
Test name
Test status
Simulation time 633806752 ps
CPU time 4.81 seconds
Started Aug 06 05:38:00 PM PDT 24
Finished Aug 06 05:38:05 PM PDT 24
Peak memory 241880 kb
Host smart-8ae0a1d1-8c8f-4bde-8f52-bf6e00ffd9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515174104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.3515174104
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.1536209946
Short name T784
Test name
Test status
Simulation time 121678804 ps
CPU time 3.65 seconds
Started Aug 06 05:37:58 PM PDT 24
Finished Aug 06 05:38:02 PM PDT 24
Peak memory 242256 kb
Host smart-7db1ccfc-ae62-41ed-92b3-08ad1bf4fe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536209946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.1536209946
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.2120539502
Short name T484
Test name
Test status
Simulation time 185806373 ps
CPU time 4.63 seconds
Started Aug 06 05:38:01 PM PDT 24
Finished Aug 06 05:38:06 PM PDT 24
Peak memory 242168 kb
Host smart-26ada035-66d9-4161-bbaa-726e1200db66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120539502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.2120539502
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.4255431930
Short name T250
Test name
Test status
Simulation time 835021964 ps
CPU time 6.51 seconds
Started Aug 06 05:37:58 PM PDT 24
Finished Aug 06 05:38:05 PM PDT 24
Peak memory 242164 kb
Host smart-d0cb1922-e5c1-48cf-b12e-a3b3f17262ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255431930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.4255431930
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.3592867057
Short name T1134
Test name
Test status
Simulation time 149223178 ps
CPU time 3.83 seconds
Started Aug 06 05:38:02 PM PDT 24
Finished Aug 06 05:38:06 PM PDT 24
Peak memory 242128 kb
Host smart-dfd72973-2574-4202-af25-30e3f639a6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592867057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3592867057
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.2777605922
Short name T379
Test name
Test status
Simulation time 185656541 ps
CPU time 3.24 seconds
Started Aug 06 05:37:59 PM PDT 24
Finished Aug 06 05:38:02 PM PDT 24
Peak memory 241888 kb
Host smart-420b10ec-4ac1-4214-b0be-e4d1c80b0c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777605922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.2777605922
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.3009283792
Short name T171
Test name
Test status
Simulation time 635289622 ps
CPU time 4.58 seconds
Started Aug 06 05:38:00 PM PDT 24
Finished Aug 06 05:38:05 PM PDT 24
Peak memory 242244 kb
Host smart-eefa470b-4c7e-4b31-97b1-5d7f180f2ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009283792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.3009283792
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.4070443366
Short name T849
Test name
Test status
Simulation time 117994131 ps
CPU time 4.7 seconds
Started Aug 06 05:38:02 PM PDT 24
Finished Aug 06 05:38:07 PM PDT 24
Peak memory 241972 kb
Host smart-dd54dcd6-7b65-473e-a4db-2960f96ec6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070443366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.4070443366
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.2041206996
Short name T896
Test name
Test status
Simulation time 183697670 ps
CPU time 3.7 seconds
Started Aug 06 05:37:58 PM PDT 24
Finished Aug 06 05:38:02 PM PDT 24
Peak memory 242356 kb
Host smart-1b9a8a10-6ba4-441f-b5e5-e31e9cdd4ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041206996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.2041206996
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.1926020113
Short name T970
Test name
Test status
Simulation time 259517555 ps
CPU time 7.95 seconds
Started Aug 06 05:38:00 PM PDT 24
Finished Aug 06 05:38:08 PM PDT 24
Peak memory 241924 kb
Host smart-9ca1e8ac-99d8-496e-966e-14380609b011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926020113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.1926020113
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.2808629180
Short name T859
Test name
Test status
Simulation time 316399210 ps
CPU time 3.85 seconds
Started Aug 06 05:38:00 PM PDT 24
Finished Aug 06 05:38:04 PM PDT 24
Peak memory 242332 kb
Host smart-7b88995c-eaca-4dd2-8918-c5b3b1603cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808629180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2808629180
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.2199400137
Short name T151
Test name
Test status
Simulation time 321678750 ps
CPU time 4.59 seconds
Started Aug 06 05:38:02 PM PDT 24
Finished Aug 06 05:38:06 PM PDT 24
Peak memory 242072 kb
Host smart-1c2f601c-d54d-4782-bfdc-9e1cbe977b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199400137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.2199400137
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.3714393259
Short name T492
Test name
Test status
Simulation time 182626511 ps
CPU time 4.11 seconds
Started Aug 06 05:38:02 PM PDT 24
Finished Aug 06 05:38:06 PM PDT 24
Peak memory 242200 kb
Host smart-430e9730-3d2a-4701-806a-104a8503918f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714393259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.3714393259
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.959755188
Short name T809
Test name
Test status
Simulation time 478623225 ps
CPU time 5.96 seconds
Started Aug 06 05:37:58 PM PDT 24
Finished Aug 06 05:38:04 PM PDT 24
Peak memory 242464 kb
Host smart-def252aa-3b4d-4272-b973-218ec3c44b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959755188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.959755188
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.1514836306
Short name T48
Test name
Test status
Simulation time 353787293 ps
CPU time 4.62 seconds
Started Aug 06 05:37:59 PM PDT 24
Finished Aug 06 05:38:04 PM PDT 24
Peak memory 241960 kb
Host smart-185fce7e-c677-4df5-85e0-9caf0ccdcce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514836306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.1514836306
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.2946424030
Short name T507
Test name
Test status
Simulation time 501011522 ps
CPU time 11.05 seconds
Started Aug 06 05:38:00 PM PDT 24
Finished Aug 06 05:38:11 PM PDT 24
Peak memory 242284 kb
Host smart-11e849b4-d245-405e-adfa-c58cc0c4f11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946424030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.2946424030
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.3069262863
Short name T1167
Test name
Test status
Simulation time 151554535 ps
CPU time 3.79 seconds
Started Aug 06 05:38:01 PM PDT 24
Finished Aug 06 05:38:05 PM PDT 24
Peak memory 242208 kb
Host smart-fd45083e-9daf-4c78-bef8-2071360c4336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069262863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.3069262863
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.2594286849
Short name T986
Test name
Test status
Simulation time 1463550350 ps
CPU time 4.54 seconds
Started Aug 06 05:38:00 PM PDT 24
Finished Aug 06 05:38:04 PM PDT 24
Peak memory 242216 kb
Host smart-976db9a0-bca9-4f56-845f-36e46a70166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594286849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.2594286849
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.774372139
Short name T328
Test name
Test status
Simulation time 783222779 ps
CPU time 11.71 seconds
Started Aug 06 05:33:04 PM PDT 24
Finished Aug 06 05:33:16 PM PDT 24
Peak memory 242316 kb
Host smart-a8f011f9-4966-4487-a26a-7e5baac3d571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774372139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.774372139
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.1033862295
Short name T100
Test name
Test status
Simulation time 4277507241 ps
CPU time 27.82 seconds
Started Aug 06 05:33:04 PM PDT 24
Finished Aug 06 05:33:33 PM PDT 24
Peak memory 242304 kb
Host smart-1ea272d8-8a3e-448e-bdaa-541a70dfad15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033862295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.1033862295
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.1318114634
Short name T684
Test name
Test status
Simulation time 28360401576 ps
CPU time 45.47 seconds
Started Aug 06 05:33:06 PM PDT 24
Finished Aug 06 05:33:52 PM PDT 24
Peak memory 258604 kb
Host smart-39c791d4-ea6c-41df-a23a-24871633cfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318114634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1318114634
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.1186629795
Short name T623
Test name
Test status
Simulation time 823125373 ps
CPU time 38.05 seconds
Started Aug 06 05:33:05 PM PDT 24
Finished Aug 06 05:33:43 PM PDT 24
Peak memory 242344 kb
Host smart-eb8d3359-68df-4eef-8a2f-9aeec078a61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186629795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.1186629795
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.86326342
Short name T1045
Test name
Test status
Simulation time 833971743 ps
CPU time 12.34 seconds
Started Aug 06 05:33:05 PM PDT 24
Finished Aug 06 05:33:17 PM PDT 24
Peak memory 242256 kb
Host smart-1d2ac0c6-00a8-4299-83c3-262251cfdfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86326342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.86326342
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.4061035776
Short name T757
Test name
Test status
Simulation time 4486399944 ps
CPU time 12.97 seconds
Started Aug 06 05:33:04 PM PDT 24
Finished Aug 06 05:33:17 PM PDT 24
Peak memory 242056 kb
Host smart-5b9be08c-b672-4ce2-830f-68f73e2cdff6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061035776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.4061035776
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.2908950154
Short name T1152
Test name
Test status
Simulation time 248918423 ps
CPU time 5.03 seconds
Started Aug 06 05:33:05 PM PDT 24
Finished Aug 06 05:33:11 PM PDT 24
Peak memory 241900 kb
Host smart-a2ddaef8-4464-4efe-b21d-5d8971a2c2bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908950154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.2908950154
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.2892600141
Short name T455
Test name
Test status
Simulation time 469948844 ps
CPU time 9.9 seconds
Started Aug 06 05:33:05 PM PDT 24
Finished Aug 06 05:33:15 PM PDT 24
Peak memory 242000 kb
Host smart-e1910769-0d5d-4b18-ad7d-f055714d52b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892600141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2892600141
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.1274629922
Short name T1159
Test name
Test status
Simulation time 16981348119 ps
CPU time 89.72 seconds
Started Aug 06 05:33:06 PM PDT 24
Finished Aug 06 05:34:36 PM PDT 24
Peak memory 248472 kb
Host smart-bbd7f086-9cac-4c6b-9216-3f9617a9f2a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274629922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.1274629922
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.706196894
Short name T286
Test name
Test status
Simulation time 53639459160 ps
CPU time 462.56 seconds
Started Aug 06 05:33:07 PM PDT 24
Finished Aug 06 05:40:49 PM PDT 24
Peak memory 256796 kb
Host smart-dc220c51-43f5-4920-b32c-e8d4b440afc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706196894 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.706196894
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.307385561
Short name T729
Test name
Test status
Simulation time 3998314894 ps
CPU time 9.43 seconds
Started Aug 06 05:33:06 PM PDT 24
Finished Aug 06 05:33:15 PM PDT 24
Peak memory 242396 kb
Host smart-73d48983-bdbe-4f08-bd00-c23d410fc17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307385561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.307385561
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.417133515
Short name T30
Test name
Test status
Simulation time 289678886 ps
CPU time 4.05 seconds
Started Aug 06 05:38:02 PM PDT 24
Finished Aug 06 05:38:06 PM PDT 24
Peak memory 242204 kb
Host smart-11958088-6918-4373-a46d-0adf6506e9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417133515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.417133515
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.930170537
Short name T269
Test name
Test status
Simulation time 1100226148 ps
CPU time 3.73 seconds
Started Aug 06 05:38:03 PM PDT 24
Finished Aug 06 05:38:07 PM PDT 24
Peak memory 241948 kb
Host smart-58a38c3d-f73b-4d43-8c2a-d8dd4bf5a9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930170537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.930170537
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.3143647505
Short name T610
Test name
Test status
Simulation time 183134644 ps
CPU time 4.04 seconds
Started Aug 06 05:38:02 PM PDT 24
Finished Aug 06 05:38:06 PM PDT 24
Peak memory 242188 kb
Host smart-76423b38-1338-4f0c-b1e0-34b721934de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143647505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.3143647505
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.3926377295
Short name T72
Test name
Test status
Simulation time 347480542 ps
CPU time 6.75 seconds
Started Aug 06 05:38:03 PM PDT 24
Finished Aug 06 05:38:10 PM PDT 24
Peak memory 242428 kb
Host smart-6cea0547-a936-4051-85a0-3cdbe03ffe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926377295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.3926377295
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.2142850339
Short name T63
Test name
Test status
Simulation time 241268512 ps
CPU time 3.97 seconds
Started Aug 06 05:37:59 PM PDT 24
Finished Aug 06 05:38:04 PM PDT 24
Peak memory 241904 kb
Host smart-a1befbe7-4efe-44e7-9b49-83ab26dcf8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142850339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.2142850339
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.1263314943
Short name T964
Test name
Test status
Simulation time 2175643446 ps
CPU time 9.77 seconds
Started Aug 06 05:37:59 PM PDT 24
Finished Aug 06 05:38:09 PM PDT 24
Peak memory 242128 kb
Host smart-a431ceae-f930-4cbf-ba0d-098474ea5db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263314943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.1263314943
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.2724044216
Short name T937
Test name
Test status
Simulation time 133596478 ps
CPU time 4.42 seconds
Started Aug 06 05:37:59 PM PDT 24
Finished Aug 06 05:38:03 PM PDT 24
Peak memory 241852 kb
Host smart-497721a2-bf9b-4793-9c6a-f7b4c7dc211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724044216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.2724044216
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.1565571161
Short name T826
Test name
Test status
Simulation time 318085963 ps
CPU time 17.52 seconds
Started Aug 06 05:37:59 PM PDT 24
Finished Aug 06 05:38:17 PM PDT 24
Peak memory 242060 kb
Host smart-d41e1d8a-c1f4-4d21-81ce-148b58db4fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565571161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.1565571161
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.814742950
Short name T772
Test name
Test status
Simulation time 253907466 ps
CPU time 3.65 seconds
Started Aug 06 05:38:02 PM PDT 24
Finished Aug 06 05:38:05 PM PDT 24
Peak memory 242268 kb
Host smart-142b80c0-7cfb-44e0-89f3-e7f11dc68389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814742950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.814742950
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.3004915808
Short name T797
Test name
Test status
Simulation time 153471338 ps
CPU time 4.31 seconds
Started Aug 06 05:38:00 PM PDT 24
Finished Aug 06 05:38:04 PM PDT 24
Peak memory 241996 kb
Host smart-5c95b34b-a6a6-4f0b-a2ad-c9c251ffca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004915808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.3004915808
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.2825297368
Short name T810
Test name
Test status
Simulation time 280179221 ps
CPU time 5.34 seconds
Started Aug 06 05:38:02 PM PDT 24
Finished Aug 06 05:38:07 PM PDT 24
Peak memory 242152 kb
Host smart-cc1bd9ad-04a0-4620-8f7a-d77748ec8813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825297368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2825297368
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.3033624352
Short name T253
Test name
Test status
Simulation time 762435956 ps
CPU time 9.65 seconds
Started Aug 06 05:38:00 PM PDT 24
Finished Aug 06 05:38:10 PM PDT 24
Peak memory 242468 kb
Host smart-6dbc27de-c0b3-42c2-8896-3ec4b8285459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033624352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3033624352
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.1910364352
Short name T719
Test name
Test status
Simulation time 406329593 ps
CPU time 4.53 seconds
Started Aug 06 05:38:03 PM PDT 24
Finished Aug 06 05:38:07 PM PDT 24
Peak memory 241812 kb
Host smart-6a53de3a-d71e-490f-9460-df27466afbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910364352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.1910364352
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.719028297
Short name T419
Test name
Test status
Simulation time 106545636 ps
CPU time 4.2 seconds
Started Aug 06 05:38:02 PM PDT 24
Finished Aug 06 05:38:06 PM PDT 24
Peak memory 241812 kb
Host smart-03e4380c-15a2-4441-9827-7326ff2d24cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719028297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.719028297
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.1207406791
Short name T56
Test name
Test status
Simulation time 322825482 ps
CPU time 4.84 seconds
Started Aug 06 05:38:00 PM PDT 24
Finished Aug 06 05:38:05 PM PDT 24
Peak memory 242132 kb
Host smart-392ec76e-3f36-45e7-ab2d-d13607e98b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207406791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.1207406791
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.1402967655
Short name T910
Test name
Test status
Simulation time 1242233848 ps
CPU time 32.22 seconds
Started Aug 06 05:37:59 PM PDT 24
Finished Aug 06 05:38:31 PM PDT 24
Peak memory 242264 kb
Host smart-439836da-12f7-460c-808b-2d47f0d5c2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402967655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.1402967655
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.2291351796
Short name T798
Test name
Test status
Simulation time 133332274 ps
CPU time 4.17 seconds
Started Aug 06 05:38:02 PM PDT 24
Finished Aug 06 05:38:06 PM PDT 24
Peak memory 241960 kb
Host smart-8ea93f97-2ae8-42e3-be5e-b8f43b15caf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291351796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.2291351796
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.1662644883
Short name T478
Test name
Test status
Simulation time 311788889 ps
CPU time 4.68 seconds
Started Aug 06 05:38:03 PM PDT 24
Finished Aug 06 05:38:08 PM PDT 24
Peak memory 242216 kb
Host smart-c2f796b2-cd28-4c14-94fa-34f6dfe22420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662644883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.1662644883
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.1902256322
Short name T711
Test name
Test status
Simulation time 90280638 ps
CPU time 3.18 seconds
Started Aug 06 05:38:12 PM PDT 24
Finished Aug 06 05:38:16 PM PDT 24
Peak memory 242144 kb
Host smart-9842022b-7109-47e0-9283-6a8b4023adcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902256322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1902256322
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.333495106
Short name T150
Test name
Test status
Simulation time 3119516877 ps
CPU time 10.09 seconds
Started Aug 06 05:38:13 PM PDT 24
Finished Aug 06 05:38:23 PM PDT 24
Peak memory 242268 kb
Host smart-c06f5462-dfd8-4204-85a3-1e1a7b15bfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333495106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.333495106
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.549691665
Short name T647
Test name
Test status
Simulation time 71306537 ps
CPU time 1.99 seconds
Started Aug 06 05:33:01 PM PDT 24
Finished Aug 06 05:33:03 PM PDT 24
Peak memory 240324 kb
Host smart-5bfc9274-95c4-443a-81dc-d00d660a7aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549691665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.549691665
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.2940988619
Short name T126
Test name
Test status
Simulation time 3795869857 ps
CPU time 11.85 seconds
Started Aug 06 05:33:09 PM PDT 24
Finished Aug 06 05:33:21 PM PDT 24
Peak memory 242656 kb
Host smart-ad27c474-f06c-4cd4-8366-782ee68b876d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940988619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.2940988619
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.988447731
Short name T641
Test name
Test status
Simulation time 1019052255 ps
CPU time 32.41 seconds
Started Aug 06 05:33:05 PM PDT 24
Finished Aug 06 05:33:38 PM PDT 24
Peak memory 247312 kb
Host smart-13dfe284-55fd-4b56-ae9b-ffc15e460ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988447731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.988447731
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.579344434
Short name T744
Test name
Test status
Simulation time 6834974708 ps
CPU time 36.81 seconds
Started Aug 06 05:33:06 PM PDT 24
Finished Aug 06 05:33:43 PM PDT 24
Peak memory 243248 kb
Host smart-18cdfe34-00fd-401d-a615-044a23be81fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579344434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.579344434
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.2809508573
Short name T1123
Test name
Test status
Simulation time 211910982 ps
CPU time 4.15 seconds
Started Aug 06 05:33:06 PM PDT 24
Finished Aug 06 05:33:10 PM PDT 24
Peak memory 242176 kb
Host smart-02c97b55-1434-49bf-8367-81a467b21508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809508573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2809508573
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.3975422240
Short name T163
Test name
Test status
Simulation time 8041126872 ps
CPU time 50.1 seconds
Started Aug 06 05:33:05 PM PDT 24
Finished Aug 06 05:33:56 PM PDT 24
Peak memory 248712 kb
Host smart-5a590057-5b3a-4fb8-9909-0f31f0836c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975422240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.3975422240
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.3192957357
Short name T836
Test name
Test status
Simulation time 117082653 ps
CPU time 4.56 seconds
Started Aug 06 05:33:09 PM PDT 24
Finished Aug 06 05:33:13 PM PDT 24
Peak memory 242164 kb
Host smart-276aec05-9417-4ee3-a6df-f465cfaed657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192957357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.3192957357
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.901891837
Short name T1183
Test name
Test status
Simulation time 447866299 ps
CPU time 6.61 seconds
Started Aug 06 05:33:03 PM PDT 24
Finished Aug 06 05:33:10 PM PDT 24
Peak memory 242252 kb
Host smart-35e0ebfc-cbc9-4bd7-bf15-0c62181a7af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901891837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.901891837
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.89395049
Short name T816
Test name
Test status
Simulation time 512981381 ps
CPU time 15.34 seconds
Started Aug 06 05:33:09 PM PDT 24
Finished Aug 06 05:33:24 PM PDT 24
Peak memory 241956 kb
Host smart-596edeab-bb2b-458f-8599-5b70511b7e15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89395049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.89395049
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.99785884
Short name T197
Test name
Test status
Simulation time 1059361934 ps
CPU time 11.65 seconds
Started Aug 06 05:33:05 PM PDT 24
Finished Aug 06 05:33:17 PM PDT 24
Peak memory 241948 kb
Host smart-12160593-ab74-4eed-b201-89977c702a7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99785884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.99785884
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.1925878636
Short name T712
Test name
Test status
Simulation time 4975963343 ps
CPU time 11.93 seconds
Started Aug 06 05:33:06 PM PDT 24
Finished Aug 06 05:33:18 PM PDT 24
Peak memory 241960 kb
Host smart-633fbaef-0cbd-4a67-82ce-694b840e252d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925878636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.1925878636
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.930227469
Short name T993
Test name
Test status
Simulation time 9744224944 ps
CPU time 31.67 seconds
Started Aug 06 05:33:01 PM PDT 24
Finished Aug 06 05:33:32 PM PDT 24
Peak memory 243720 kb
Host smart-98dcb8d5-a5b5-4325-a926-da8ed13097bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930227469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.
930227469
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.1235265171
Short name T259
Test name
Test status
Simulation time 168422289285 ps
CPU time 1062.64 seconds
Started Aug 06 05:33:05 PM PDT 24
Finished Aug 06 05:50:48 PM PDT 24
Peak memory 326900 kb
Host smart-5183158c-d9d7-46fa-b95f-62b7149e4e41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235265171 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.1235265171
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.603397037
Short name T434
Test name
Test status
Simulation time 916999491 ps
CPU time 9.4 seconds
Started Aug 06 05:33:10 PM PDT 24
Finished Aug 06 05:33:20 PM PDT 24
Peak memory 248536 kb
Host smart-f548b02d-17b2-4bd3-95d5-4315b6ac4a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603397037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.603397037
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.766758888
Short name T34
Test name
Test status
Simulation time 314283477 ps
CPU time 4.47 seconds
Started Aug 06 05:38:12 PM PDT 24
Finished Aug 06 05:38:16 PM PDT 24
Peak memory 241892 kb
Host smart-4faf5aac-020f-4649-aaba-cf5bc6e1b5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766758888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.766758888
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.3215664636
Short name T1120
Test name
Test status
Simulation time 136226842 ps
CPU time 3.53 seconds
Started Aug 06 05:38:16 PM PDT 24
Finished Aug 06 05:38:20 PM PDT 24
Peak memory 242220 kb
Host smart-f46307a3-716b-4ba0-a402-fe49d5310c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215664636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3215664636
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.3363883906
Short name T1040
Test name
Test status
Simulation time 2586966631 ps
CPU time 9.85 seconds
Started Aug 06 05:38:13 PM PDT 24
Finished Aug 06 05:38:23 PM PDT 24
Peak memory 242056 kb
Host smart-66057615-bfbd-4dbb-940d-3a5a2c1b510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363883906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.3363883906
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.2623130752
Short name T740
Test name
Test status
Simulation time 246620247 ps
CPU time 3.83 seconds
Started Aug 06 05:38:13 PM PDT 24
Finished Aug 06 05:38:17 PM PDT 24
Peak memory 242160 kb
Host smart-08d2312a-09ad-449b-8c66-05afcfc7a898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623130752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.2623130752
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.3618647345
Short name T1
Test name
Test status
Simulation time 310076294 ps
CPU time 6.52 seconds
Started Aug 06 05:38:11 PM PDT 24
Finished Aug 06 05:38:18 PM PDT 24
Peak memory 241648 kb
Host smart-44663626-06c9-4809-926a-39d9eda99f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618647345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.3618647345
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.3474784493
Short name T963
Test name
Test status
Simulation time 426881776 ps
CPU time 8.52 seconds
Started Aug 06 05:38:12 PM PDT 24
Finished Aug 06 05:38:21 PM PDT 24
Peak memory 241728 kb
Host smart-f97fcf9a-3e3f-4e85-bcbf-d9b75fa7eb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474784493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.3474784493
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.48721248
Short name T543
Test name
Test status
Simulation time 2380690714 ps
CPU time 7.59 seconds
Started Aug 06 05:38:18 PM PDT 24
Finished Aug 06 05:38:26 PM PDT 24
Peak memory 241996 kb
Host smart-e69a41c8-a732-45b9-abd9-af72c3cbb280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48721248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.48721248
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.3096770292
Short name T471
Test name
Test status
Simulation time 327428821 ps
CPU time 6.27 seconds
Started Aug 06 05:38:12 PM PDT 24
Finished Aug 06 05:38:18 PM PDT 24
Peak memory 242072 kb
Host smart-b8cf5be7-7694-425b-a9b6-17ab9904b349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096770292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.3096770292
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.2582609291
Short name T1020
Test name
Test status
Simulation time 164124208 ps
CPU time 4.72 seconds
Started Aug 06 05:38:11 PM PDT 24
Finished Aug 06 05:38:16 PM PDT 24
Peak memory 242256 kb
Host smart-215a90e3-56a3-4764-9d5f-384df01496a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582609291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2582609291
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.3465227908
Short name T1136
Test name
Test status
Simulation time 362695026 ps
CPU time 8.7 seconds
Started Aug 06 05:38:11 PM PDT 24
Finished Aug 06 05:38:20 PM PDT 24
Peak memory 241892 kb
Host smart-6c9b084f-fb38-47ae-b696-1295b47643b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465227908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3465227908
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.2449166863
Short name T409
Test name
Test status
Simulation time 123108164 ps
CPU time 3.49 seconds
Started Aug 06 05:38:11 PM PDT 24
Finished Aug 06 05:38:14 PM PDT 24
Peak memory 241976 kb
Host smart-4a4d837b-84d6-4cc7-b284-d93b5f06d935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449166863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.2449166863
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.4176781500
Short name T144
Test name
Test status
Simulation time 258864424 ps
CPU time 3.79 seconds
Started Aug 06 05:38:11 PM PDT 24
Finished Aug 06 05:38:15 PM PDT 24
Peak memory 241776 kb
Host smart-0653611d-c7ef-4ce3-a2db-ee9ab14c975e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176781500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.4176781500
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.3615680080
Short name T177
Test name
Test status
Simulation time 1721007841 ps
CPU time 5.74 seconds
Started Aug 06 05:38:14 PM PDT 24
Finished Aug 06 05:38:20 PM PDT 24
Peak memory 241988 kb
Host smart-6d790e41-2383-427b-a2ec-1a1498f80bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615680080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.3615680080
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.760271512
Short name T192
Test name
Test status
Simulation time 140681195 ps
CPU time 3.77 seconds
Started Aug 06 05:38:11 PM PDT 24
Finished Aug 06 05:38:15 PM PDT 24
Peak memory 242172 kb
Host smart-e1356cc6-80c6-4534-be8c-e14188d726a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760271512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.760271512
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.3552354455
Short name T567
Test name
Test status
Simulation time 169984308 ps
CPU time 8.85 seconds
Started Aug 06 05:38:13 PM PDT 24
Finished Aug 06 05:38:21 PM PDT 24
Peak memory 242076 kb
Host smart-693a7612-bbff-49b7-a862-236741694fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552354455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.3552354455
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.2445929345
Short name T752
Test name
Test status
Simulation time 188657913 ps
CPU time 4.66 seconds
Started Aug 06 05:38:12 PM PDT 24
Finished Aug 06 05:38:17 PM PDT 24
Peak memory 241976 kb
Host smart-016f881d-b87b-46ce-8e49-faf3e7c9490b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445929345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.2445929345
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.1764558188
Short name T324
Test name
Test status
Simulation time 402038332 ps
CPU time 3.13 seconds
Started Aug 06 05:38:13 PM PDT 24
Finished Aug 06 05:38:16 PM PDT 24
Peak memory 241936 kb
Host smart-7bb89fda-78ad-481d-ae37-22e5feda4365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764558188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.1764558188
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.4175421747
Short name T239
Test name
Test status
Simulation time 152256647 ps
CPU time 1.97 seconds
Started Aug 06 05:33:23 PM PDT 24
Finished Aug 06 05:33:25 PM PDT 24
Peak memory 240644 kb
Host smart-92bad0da-8a8f-4566-b496-b80f89a07e5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175421747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.4175421747
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.4237798532
Short name T28
Test name
Test status
Simulation time 1110358012 ps
CPU time 14.49 seconds
Started Aug 06 05:33:00 PM PDT 24
Finished Aug 06 05:33:15 PM PDT 24
Peak memory 242500 kb
Host smart-bef174db-b03a-47d9-b77a-a9eb1eb0a4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237798532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.4237798532
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.2564129281
Short name T1080
Test name
Test status
Simulation time 927690368 ps
CPU time 12.21 seconds
Started Aug 06 05:33:01 PM PDT 24
Finished Aug 06 05:33:13 PM PDT 24
Peak memory 242192 kb
Host smart-68c869f2-20bd-45fb-936a-88132071cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564129281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.2564129281
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.2066458082
Short name T673
Test name
Test status
Simulation time 575611374 ps
CPU time 7.52 seconds
Started Aug 06 05:33:01 PM PDT 24
Finished Aug 06 05:33:09 PM PDT 24
Peak memory 248496 kb
Host smart-18e9554f-194c-4775-bae5-1434518f8ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066458082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.2066458082
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.3855275314
Short name T698
Test name
Test status
Simulation time 16688527699 ps
CPU time 41.22 seconds
Started Aug 06 05:33:03 PM PDT 24
Finished Aug 06 05:33:44 PM PDT 24
Peak memory 248600 kb
Host smart-008ba6ce-d51e-420b-b792-dafbb9e1094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855275314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3855275314
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.542382692
Short name T1118
Test name
Test status
Simulation time 10992265433 ps
CPU time 19.24 seconds
Started Aug 06 05:33:03 PM PDT 24
Finished Aug 06 05:33:22 PM PDT 24
Peak memory 243212 kb
Host smart-ad55e09a-57cc-4b91-9654-ebdf0cc42469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542382692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.542382692
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.3412601247
Short name T326
Test name
Test status
Simulation time 108208761 ps
CPU time 3.24 seconds
Started Aug 06 05:33:03 PM PDT 24
Finished Aug 06 05:33:06 PM PDT 24
Peak memory 241936 kb
Host smart-2eedcc7c-a0a5-4f1a-93bf-7a75c801682e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412601247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3412601247
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.153196342
Short name T899
Test name
Test status
Simulation time 192137939 ps
CPU time 5.27 seconds
Started Aug 06 05:33:02 PM PDT 24
Finished Aug 06 05:33:07 PM PDT 24
Peak memory 248384 kb
Host smart-0ca589de-a4b7-4a0c-b2dd-038958ce08ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=153196342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.153196342
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.3929620331
Short name T351
Test name
Test status
Simulation time 406957619 ps
CPU time 6.45 seconds
Started Aug 06 05:33:03 PM PDT 24
Finished Aug 06 05:33:10 PM PDT 24
Peak memory 241864 kb
Host smart-517de634-73ef-4225-a7ca-b24f0ef8995b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3929620331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.3929620331
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.1460798739
Short name T867
Test name
Test status
Simulation time 481794894 ps
CPU time 10.16 seconds
Started Aug 06 05:33:00 PM PDT 24
Finished Aug 06 05:33:10 PM PDT 24
Peak memory 248644 kb
Host smart-296a3289-e217-4c36-83a0-a1aafd278929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460798739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.1460798739
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.3915603162
Short name T988
Test name
Test status
Simulation time 21822836581 ps
CPU time 54.79 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:34:15 PM PDT 24
Peak memory 245068 kb
Host smart-04b31368-a3b7-4ec0-8cf0-288123c6c468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915603162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.3915603162
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.1399603266
Short name T101
Test name
Test status
Simulation time 831128118 ps
CPU time 28.63 seconds
Started Aug 06 05:33:03 PM PDT 24
Finished Aug 06 05:33:32 PM PDT 24
Peak memory 242060 kb
Host smart-9106ebb5-6fc8-41cd-9a8b-be71da7a1731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399603266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.1399603266
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.2112115497
Short name T913
Test name
Test status
Simulation time 159454505 ps
CPU time 4.22 seconds
Started Aug 06 05:38:15 PM PDT 24
Finished Aug 06 05:38:19 PM PDT 24
Peak memory 242152 kb
Host smart-b9cc7ac2-1b2e-4f7b-ab6f-f487630a1885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112115497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.2112115497
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.2123282103
Short name T1032
Test name
Test status
Simulation time 294858112 ps
CPU time 3.21 seconds
Started Aug 06 05:38:11 PM PDT 24
Finished Aug 06 05:38:14 PM PDT 24
Peak memory 242028 kb
Host smart-6c369d1b-528d-43c0-8d83-20177057947e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123282103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.2123282103
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.3861707909
Short name T145
Test name
Test status
Simulation time 223208928 ps
CPU time 3.82 seconds
Started Aug 06 05:38:26 PM PDT 24
Finished Aug 06 05:38:29 PM PDT 24
Peak memory 241712 kb
Host smart-4c1c4205-b9e5-40ff-a9a9-d0baabefdc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861707909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.3861707909
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.1458021989
Short name T668
Test name
Test status
Simulation time 2211959883 ps
CPU time 6.08 seconds
Started Aug 06 05:38:26 PM PDT 24
Finished Aug 06 05:38:32 PM PDT 24
Peak memory 242032 kb
Host smart-4733263d-65d4-4c42-b41b-349949d62fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458021989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1458021989
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.2391066685
Short name T176
Test name
Test status
Simulation time 288997610 ps
CPU time 3.55 seconds
Started Aug 06 05:38:27 PM PDT 24
Finished Aug 06 05:38:30 PM PDT 24
Peak memory 241776 kb
Host smart-4e2c6e11-548a-4f6d-b954-9556767011fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391066685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.2391066685
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.530947301
Short name T974
Test name
Test status
Simulation time 230650946 ps
CPU time 3.01 seconds
Started Aug 06 05:38:25 PM PDT 24
Finished Aug 06 05:38:28 PM PDT 24
Peak memory 242364 kb
Host smart-81569e3f-1f67-406d-ba65-cf4249acfa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530947301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.530947301
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.3709687017
Short name T909
Test name
Test status
Simulation time 177324485 ps
CPU time 5.05 seconds
Started Aug 06 05:38:26 PM PDT 24
Finished Aug 06 05:38:31 PM PDT 24
Peak memory 241976 kb
Host smart-a3e9f71a-07f9-43c0-9264-e6ae8a0fdcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709687017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3709687017
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.663188994
Short name T380
Test name
Test status
Simulation time 271846432 ps
CPU time 3.76 seconds
Started Aug 06 05:38:28 PM PDT 24
Finished Aug 06 05:38:32 PM PDT 24
Peak memory 241916 kb
Host smart-16f9b91a-d45f-4fe7-a93c-7e7069197103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663188994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.663188994
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.17005174
Short name T25
Test name
Test status
Simulation time 154735251 ps
CPU time 4.14 seconds
Started Aug 06 05:38:26 PM PDT 24
Finished Aug 06 05:38:30 PM PDT 24
Peak memory 241964 kb
Host smart-718b6270-15ea-4603-9b7c-e749ecded188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17005174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.17005174
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.3664159884
Short name T199
Test name
Test status
Simulation time 207843454 ps
CPU time 11.85 seconds
Started Aug 06 05:38:25 PM PDT 24
Finished Aug 06 05:38:37 PM PDT 24
Peak memory 241928 kb
Host smart-88cae57c-e71a-4680-8474-379ff3c59db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664159884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.3664159884
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.3141060958
Short name T174
Test name
Test status
Simulation time 1498423742 ps
CPU time 3.38 seconds
Started Aug 06 05:38:24 PM PDT 24
Finished Aug 06 05:38:28 PM PDT 24
Peak memory 242060 kb
Host smart-2f178c84-983c-49c0-8609-4d5bc865e81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141060958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3141060958
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.3393816275
Short name T518
Test name
Test status
Simulation time 192848122 ps
CPU time 3.75 seconds
Started Aug 06 05:38:29 PM PDT 24
Finished Aug 06 05:38:33 PM PDT 24
Peak memory 241832 kb
Host smart-0dab2e16-9a80-4418-bcca-c144b2c882e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393816275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.3393816275
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.888725459
Short name T644
Test name
Test status
Simulation time 1931407225 ps
CPU time 4.41 seconds
Started Aug 06 05:38:27 PM PDT 24
Finished Aug 06 05:38:31 PM PDT 24
Peak memory 242288 kb
Host smart-750d3f6b-d9dc-4e82-aca7-8ee35326359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888725459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.888725459
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.1972810286
Short name T1070
Test name
Test status
Simulation time 466698947 ps
CPU time 6.66 seconds
Started Aug 06 05:38:27 PM PDT 24
Finished Aug 06 05:38:34 PM PDT 24
Peak memory 242208 kb
Host smart-ed2ee1a7-d1df-4e9a-a527-013fb2c95e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972810286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.1972810286
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.727245073
Short name T540
Test name
Test status
Simulation time 132667735 ps
CPU time 3.52 seconds
Started Aug 06 05:38:27 PM PDT 24
Finished Aug 06 05:38:31 PM PDT 24
Peak memory 242324 kb
Host smart-508dbd28-4265-4e21-bafa-e301f6699b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727245073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.727245073
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.785948541
Short name T132
Test name
Test status
Simulation time 449516707 ps
CPU time 11.94 seconds
Started Aug 06 05:38:26 PM PDT 24
Finished Aug 06 05:38:38 PM PDT 24
Peak memory 242280 kb
Host smart-bc65bf87-c907-4b40-aabd-f9aa2488152d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785948541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.785948541
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.3219918671
Short name T1039
Test name
Test status
Simulation time 292659519 ps
CPU time 3.1 seconds
Started Aug 06 05:38:26 PM PDT 24
Finished Aug 06 05:38:30 PM PDT 24
Peak memory 242000 kb
Host smart-d7b625cf-1fe9-4df1-9121-901387995517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219918671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.3219918671
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.2620398041
Short name T1117
Test name
Test status
Simulation time 206868111 ps
CPU time 4.11 seconds
Started Aug 06 05:38:27 PM PDT 24
Finished Aug 06 05:38:31 PM PDT 24
Peak memory 242200 kb
Host smart-073b84f6-cd94-4d39-93f7-eca5b2567752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620398041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.2620398041
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.3091176107
Short name T855
Test name
Test status
Simulation time 114010568 ps
CPU time 1.87 seconds
Started Aug 06 05:33:16 PM PDT 24
Finished Aug 06 05:33:18 PM PDT 24
Peak memory 240288 kb
Host smart-18d324f4-9b8f-4ca6-99d8-b2808c5d94a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091176107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.3091176107
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.3310801684
Short name T29
Test name
Test status
Simulation time 727006776 ps
CPU time 10.04 seconds
Started Aug 06 05:33:21 PM PDT 24
Finished Aug 06 05:33:31 PM PDT 24
Peak memory 248680 kb
Host smart-b3aa15e5-cade-4b4e-831f-8e4a933ad11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310801684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.3310801684
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.260143324
Short name T562
Test name
Test status
Simulation time 783816335 ps
CPU time 27.02 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:47 PM PDT 24
Peak memory 242656 kb
Host smart-e732a7d4-dd7f-4964-8241-1a92b47a96c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260143324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.260143324
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.644716917
Short name T620
Test name
Test status
Simulation time 2063620195 ps
CPU time 24.24 seconds
Started Aug 06 05:33:16 PM PDT 24
Finished Aug 06 05:33:41 PM PDT 24
Peak memory 242172 kb
Host smart-69524e80-b030-42d8-aa87-8c49d20fad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644716917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.644716917
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.3111335970
Short name T633
Test name
Test status
Simulation time 1609147458 ps
CPU time 4.52 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:25 PM PDT 24
Peak memory 241912 kb
Host smart-362ae14b-3b5f-4732-a249-e5ca17388a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111335970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.3111335970
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.1830287148
Short name T962
Test name
Test status
Simulation time 16707412752 ps
CPU time 44.16 seconds
Started Aug 06 05:33:19 PM PDT 24
Finished Aug 06 05:34:03 PM PDT 24
Peak memory 246328 kb
Host smart-36fac726-c9d6-4160-8a1e-520af2b51294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830287148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1830287148
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.2989980739
Short name T696
Test name
Test status
Simulation time 199617422 ps
CPU time 4.34 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:25 PM PDT 24
Peak memory 242104 kb
Host smart-763b4d7c-df11-4ac2-9732-c7d45c7c3eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989980739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.2989980739
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.1522887380
Short name T148
Test name
Test status
Simulation time 253068680 ps
CPU time 6.96 seconds
Started Aug 06 05:33:19 PM PDT 24
Finished Aug 06 05:33:26 PM PDT 24
Peak memory 242172 kb
Host smart-5ec065d6-2267-418b-af10-9038a43ef104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522887380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.1522887380
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.1436847946
Short name T482
Test name
Test status
Simulation time 631546260 ps
CPU time 23.18 seconds
Started Aug 06 05:33:15 PM PDT 24
Finished Aug 06 05:33:38 PM PDT 24
Peak memory 242016 kb
Host smart-fa293af7-a6b5-4500-bee4-19fe40cd87f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1436847946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.1436847946
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.1097726777
Short name T882
Test name
Test status
Simulation time 221223573 ps
CPU time 5.93 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:26 PM PDT 24
Peak memory 241936 kb
Host smart-032b0c24-3321-4f40-ab31-47f9c37d2c61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1097726777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1097726777
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.1465471164
Short name T415
Test name
Test status
Simulation time 289024217 ps
CPU time 3.47 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:23 PM PDT 24
Peak memory 241996 kb
Host smart-140d311e-96cc-49b4-bd68-b0434b12dbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465471164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.1465471164
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.709807230
Short name T470
Test name
Test status
Simulation time 12405176377 ps
CPU time 42.1 seconds
Started Aug 06 05:33:19 PM PDT 24
Finished Aug 06 05:34:01 PM PDT 24
Peak memory 242788 kb
Host smart-9d394553-7ad4-48ee-8af1-455cf8d1362d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709807230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.
709807230
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.943261464
Short name T256
Test name
Test status
Simulation time 46523006444 ps
CPU time 787.52 seconds
Started Aug 06 05:33:19 PM PDT 24
Finished Aug 06 05:46:27 PM PDT 24
Peak memory 286660 kb
Host smart-8b8fb794-e07a-417c-87d3-072841bc4513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943261464 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.943261464
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.2979360943
Short name T820
Test name
Test status
Simulation time 2287452914 ps
CPU time 16.06 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:36 PM PDT 24
Peak memory 241924 kb
Host smart-123db8a2-12b0-4d33-980f-29a7bd14eec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979360943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.2979360943
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.2924448687
Short name T1112
Test name
Test status
Simulation time 251342652 ps
CPU time 4.84 seconds
Started Aug 06 05:38:28 PM PDT 24
Finished Aug 06 05:38:33 PM PDT 24
Peak memory 241792 kb
Host smart-4668e9e9-5dd9-4e9f-bae9-9283518613eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924448687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.2924448687
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.3269714816
Short name T857
Test name
Test status
Simulation time 239729026 ps
CPU time 3.77 seconds
Started Aug 06 05:38:26 PM PDT 24
Finished Aug 06 05:38:30 PM PDT 24
Peak memory 241992 kb
Host smart-b2ffcccc-2cb6-4a26-8ed4-f48d3bf8fd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269714816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3269714816
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.2784867989
Short name T257
Test name
Test status
Simulation time 1476190724 ps
CPU time 9.61 seconds
Started Aug 06 05:38:28 PM PDT 24
Finished Aug 06 05:38:38 PM PDT 24
Peak memory 242016 kb
Host smart-7f08cf30-e57c-4fb6-aeac-f95ae1f8b840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784867989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.2784867989
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.3690267817
Short name T875
Test name
Test status
Simulation time 166162680 ps
CPU time 4.36 seconds
Started Aug 06 05:38:27 PM PDT 24
Finished Aug 06 05:38:31 PM PDT 24
Peak memory 241928 kb
Host smart-3f99ffff-69a5-4f2b-b1d5-181681330497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690267817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.3690267817
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.1045560111
Short name T1065
Test name
Test status
Simulation time 118014476 ps
CPU time 4.6 seconds
Started Aug 06 05:38:26 PM PDT 24
Finished Aug 06 05:38:31 PM PDT 24
Peak memory 242328 kb
Host smart-da5634d1-b299-4548-955b-5e0f6127c3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045560111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.1045560111
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.3276362694
Short name T1180
Test name
Test status
Simulation time 2427038644 ps
CPU time 7.64 seconds
Started Aug 06 05:38:27 PM PDT 24
Finished Aug 06 05:38:34 PM PDT 24
Peak memory 242112 kb
Host smart-ebe4d8f3-504e-412a-a65f-5770d503be3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276362694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.3276362694
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.1647576894
Short name T242
Test name
Test status
Simulation time 271218917 ps
CPU time 8.78 seconds
Started Aug 06 05:38:27 PM PDT 24
Finished Aug 06 05:38:35 PM PDT 24
Peak memory 241752 kb
Host smart-9353fd6f-b9c0-44ee-bad5-a1191dce0354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647576894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1647576894
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.2434601338
Short name T929
Test name
Test status
Simulation time 2344324782 ps
CPU time 6.98 seconds
Started Aug 06 05:38:26 PM PDT 24
Finished Aug 06 05:38:33 PM PDT 24
Peak memory 241948 kb
Host smart-4ad21ef4-bb57-4685-b466-67652dbe4999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434601338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.2434601338
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.2190257423
Short name T71
Test name
Test status
Simulation time 225553981 ps
CPU time 4.33 seconds
Started Aug 06 05:38:27 PM PDT 24
Finished Aug 06 05:38:31 PM PDT 24
Peak memory 241992 kb
Host smart-c6a755e2-177a-401c-aa5c-1c79a47719c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190257423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.2190257423
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.491580626
Short name T675
Test name
Test status
Simulation time 1969395000 ps
CPU time 4.31 seconds
Started Aug 06 05:38:27 PM PDT 24
Finished Aug 06 05:38:31 PM PDT 24
Peak memory 242132 kb
Host smart-36e058ff-1dab-4372-8906-d1e1e1051d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491580626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.491580626
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.2267837946
Short name T133
Test name
Test status
Simulation time 1072280748 ps
CPU time 15.26 seconds
Started Aug 06 05:38:28 PM PDT 24
Finished Aug 06 05:38:44 PM PDT 24
Peak memory 241808 kb
Host smart-0f499cf7-af90-4287-91b4-ff5c7fa397a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267837946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.2267837946
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.3078274444
Short name T521
Test name
Test status
Simulation time 2187650926 ps
CPU time 5.9 seconds
Started Aug 06 05:38:29 PM PDT 24
Finished Aug 06 05:38:35 PM PDT 24
Peak memory 241928 kb
Host smart-285b8147-71fe-4cbb-950b-7d0ec1f7be5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078274444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.3078274444
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.3776546091
Short name T885
Test name
Test status
Simulation time 885784735 ps
CPU time 6.37 seconds
Started Aug 06 05:38:28 PM PDT 24
Finished Aug 06 05:38:34 PM PDT 24
Peak memory 241888 kb
Host smart-8265e45c-9ea3-4e31-a30d-97c5818b0864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776546091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.3776546091
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.1492127570
Short name T586
Test name
Test status
Simulation time 249592718 ps
CPU time 3.78 seconds
Started Aug 06 05:38:30 PM PDT 24
Finished Aug 06 05:38:34 PM PDT 24
Peak memory 242156 kb
Host smart-38af5570-fdcc-46fd-9273-6549db7c8687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492127570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1492127570
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.2490696936
Short name T375
Test name
Test status
Simulation time 418919205 ps
CPU time 10.5 seconds
Started Aug 06 05:38:27 PM PDT 24
Finished Aug 06 05:38:37 PM PDT 24
Peak memory 241892 kb
Host smart-e3aebcb5-0427-40c1-8c6e-070789c39ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490696936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.2490696936
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.3504381651
Short name T165
Test name
Test status
Simulation time 550986180 ps
CPU time 4.05 seconds
Started Aug 06 05:38:26 PM PDT 24
Finished Aug 06 05:38:31 PM PDT 24
Peak memory 242232 kb
Host smart-ce11954d-2625-43f7-ae8e-2f9e366818da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504381651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.3504381651
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.1895285230
Short name T466
Test name
Test status
Simulation time 423458088 ps
CPU time 14.03 seconds
Started Aug 06 05:38:28 PM PDT 24
Finished Aug 06 05:38:42 PM PDT 24
Peak memory 242408 kb
Host smart-007549db-5a69-447f-9228-e15b85c370fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895285230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.1895285230
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.1723026279
Short name T778
Test name
Test status
Simulation time 411345692 ps
CPU time 3.84 seconds
Started Aug 06 05:38:28 PM PDT 24
Finished Aug 06 05:38:32 PM PDT 24
Peak memory 242228 kb
Host smart-ff39f8d9-e355-4339-8479-087c8eb90b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723026279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.1723026279
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.1268382254
Short name T1029
Test name
Test status
Simulation time 3930899762 ps
CPU time 12.89 seconds
Started Aug 06 05:38:30 PM PDT 24
Finished Aug 06 05:38:43 PM PDT 24
Peak memory 242080 kb
Host smart-e1e88c62-c306-43eb-8a68-3a3c904dace8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268382254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.1268382254
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.3348180572
Short name T504
Test name
Test status
Simulation time 866112564 ps
CPU time 2.1 seconds
Started Aug 06 05:33:22 PM PDT 24
Finished Aug 06 05:33:24 PM PDT 24
Peak memory 240240 kb
Host smart-700ac815-d0f3-4b7a-9ff0-489205fef808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348180572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.3348180572
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.1621119075
Short name T79
Test name
Test status
Simulation time 4072526303 ps
CPU time 24.12 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:44 PM PDT 24
Peak memory 248648 kb
Host smart-c4382a7a-720f-4e38-8359-8a0c5de9a316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621119075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.1621119075
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.2129083682
Short name T558
Test name
Test status
Simulation time 1624750824 ps
CPU time 25.88 seconds
Started Aug 06 05:33:22 PM PDT 24
Finished Aug 06 05:33:48 PM PDT 24
Peak memory 242096 kb
Host smart-628b4ec7-a3b5-403f-ab2f-ae906206d911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129083682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.2129083682
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.2382687054
Short name T927
Test name
Test status
Simulation time 14670003749 ps
CPU time 27.76 seconds
Started Aug 06 05:33:16 PM PDT 24
Finished Aug 06 05:33:44 PM PDT 24
Peak memory 242716 kb
Host smart-28a412a5-ef87-46fe-ab7e-9bce7b3288d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382687054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.2382687054
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.3451930070
Short name T89
Test name
Test status
Simulation time 309447005 ps
CPU time 3.5 seconds
Started Aug 06 05:33:15 PM PDT 24
Finished Aug 06 05:33:19 PM PDT 24
Peak memory 241920 kb
Host smart-21906da2-9a77-46bd-836d-acfa1f66edec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451930070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.3451930070
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.3847786887
Short name T667
Test name
Test status
Simulation time 1200313389 ps
CPU time 19.15 seconds
Started Aug 06 05:33:16 PM PDT 24
Finished Aug 06 05:33:35 PM PDT 24
Peak memory 242036 kb
Host smart-936253fc-0eb8-4c06-875a-8e9840b46d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847786887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.3847786887
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.3817184349
Short name T1088
Test name
Test status
Simulation time 627055726 ps
CPU time 7.13 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:27 PM PDT 24
Peak memory 242104 kb
Host smart-c874049e-99b5-4068-ae25-d51f5d87899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817184349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.3817184349
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.2124813660
Short name T389
Test name
Test status
Simulation time 227703589 ps
CPU time 6.27 seconds
Started Aug 06 05:33:15 PM PDT 24
Finished Aug 06 05:33:21 PM PDT 24
Peak memory 242192 kb
Host smart-9bb1a2a7-9e15-4658-8b1a-80729e0323fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124813660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.2124813660
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.1626474561
Short name T321
Test name
Test status
Simulation time 2248267278 ps
CPU time 24.24 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:45 PM PDT 24
Peak memory 242228 kb
Host smart-75ce470b-2efc-4303-9934-1c69644780bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1626474561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.1626474561
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.3833230080
Short name T428
Test name
Test status
Simulation time 447814943 ps
CPU time 3.43 seconds
Started Aug 06 05:33:24 PM PDT 24
Finished Aug 06 05:33:27 PM PDT 24
Peak memory 242216 kb
Host smart-47cdae52-402e-46c6-9957-62f0b27c684e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3833230080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.3833230080
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.2468702255
Short name T915
Test name
Test status
Simulation time 3146849824 ps
CPU time 7.07 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:27 PM PDT 24
Peak memory 242184 kb
Host smart-e4812801-6791-4de7-b2b1-7245ce1516a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468702255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.2468702255
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.1350317500
Short name T1066
Test name
Test status
Simulation time 95997103108 ps
CPU time 2385.56 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 06:13:06 PM PDT 24
Peak memory 386776 kb
Host smart-1d618a06-f46d-4d94-a398-4b6910a024ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350317500 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.1350317500
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.2885869963
Short name T681
Test name
Test status
Simulation time 1572975337 ps
CPU time 28.65 seconds
Started Aug 06 05:33:19 PM PDT 24
Finished Aug 06 05:33:48 PM PDT 24
Peak memory 242256 kb
Host smart-23c8b731-b4fb-4643-886b-12798bb93039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885869963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.2885869963
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.1412514340
Short name T1178
Test name
Test status
Simulation time 113375592 ps
CPU time 3.59 seconds
Started Aug 06 05:38:29 PM PDT 24
Finished Aug 06 05:38:33 PM PDT 24
Peak memory 242036 kb
Host smart-f9e2bd9f-52c9-4b57-8fd0-d398fbdcd6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412514340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1412514340
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.3737447828
Short name T153
Test name
Test status
Simulation time 353851207 ps
CPU time 11.02 seconds
Started Aug 06 05:38:30 PM PDT 24
Finished Aug 06 05:38:41 PM PDT 24
Peak memory 241816 kb
Host smart-a8d64417-e4a1-4224-8c44-0a3b4562ebc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737447828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3737447828
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.910919395
Short name T57
Test name
Test status
Simulation time 191800387 ps
CPU time 4.56 seconds
Started Aug 06 05:38:29 PM PDT 24
Finished Aug 06 05:38:34 PM PDT 24
Peak memory 242128 kb
Host smart-e11f11f8-47e2-401c-9484-41ec4c4ca5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910919395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.910919395
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.2255392632
Short name T595
Test name
Test status
Simulation time 1633896963 ps
CPU time 14.48 seconds
Started Aug 06 05:38:30 PM PDT 24
Finished Aug 06 05:38:44 PM PDT 24
Peak memory 241712 kb
Host smart-6188cc7e-3034-4d4c-b614-2508b033c2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255392632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2255392632
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.3709117775
Short name T893
Test name
Test status
Simulation time 476898105 ps
CPU time 6.86 seconds
Started Aug 06 05:38:28 PM PDT 24
Finished Aug 06 05:38:35 PM PDT 24
Peak memory 242216 kb
Host smart-1b19d2c9-b8c7-450e-8966-a18a0e25ed00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709117775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.3709117775
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.2931098359
Short name T185
Test name
Test status
Simulation time 132048358 ps
CPU time 3.25 seconds
Started Aug 06 05:38:29 PM PDT 24
Finished Aug 06 05:38:32 PM PDT 24
Peak memory 242380 kb
Host smart-64dbb0b1-b5ba-4a04-a032-5e9221d56b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931098359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.2931098359
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.3387601752
Short name T1099
Test name
Test status
Simulation time 526851976 ps
CPU time 15.62 seconds
Started Aug 06 05:38:29 PM PDT 24
Finished Aug 06 05:38:45 PM PDT 24
Peak memory 241868 kb
Host smart-7ddc1e7c-82ec-441a-baea-8cfde47520c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387601752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.3387601752
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.2364309028
Short name T609
Test name
Test status
Simulation time 509893644 ps
CPU time 3.89 seconds
Started Aug 06 05:38:29 PM PDT 24
Finished Aug 06 05:38:33 PM PDT 24
Peak memory 241964 kb
Host smart-9681859d-03b1-419c-a0f5-2b0caf6add55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364309028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.2364309028
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.2246576883
Short name T267
Test name
Test status
Simulation time 689690096 ps
CPU time 8.63 seconds
Started Aug 06 05:38:39 PM PDT 24
Finished Aug 06 05:38:48 PM PDT 24
Peak memory 241928 kb
Host smart-69cbbf38-4e96-4a13-adf4-804f987fbcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246576883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.2246576883
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.903011415
Short name T102
Test name
Test status
Simulation time 203976651 ps
CPU time 3.84 seconds
Started Aug 06 05:38:41 PM PDT 24
Finished Aug 06 05:38:45 PM PDT 24
Peak memory 242004 kb
Host smart-87621032-b927-42c9-a8e1-2925b96f3940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903011415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.903011415
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.2524560517
Short name T630
Test name
Test status
Simulation time 312391233 ps
CPU time 7.9 seconds
Started Aug 06 05:38:41 PM PDT 24
Finished Aug 06 05:38:49 PM PDT 24
Peak memory 242268 kb
Host smart-18efe9a0-c990-44f3-af1e-aed7f49f9237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524560517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.2524560517
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.4019518142
Short name T888
Test name
Test status
Simulation time 202005156 ps
CPU time 3.08 seconds
Started Aug 06 05:38:39 PM PDT 24
Finished Aug 06 05:38:42 PM PDT 24
Peak memory 242060 kb
Host smart-2bb628b6-59fc-40b8-8b5a-528d01f83d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019518142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.4019518142
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.871408328
Short name T198
Test name
Test status
Simulation time 132004653 ps
CPU time 4.52 seconds
Started Aug 06 05:38:39 PM PDT 24
Finished Aug 06 05:38:43 PM PDT 24
Peak memory 242316 kb
Host smart-5bc7b33e-d946-4ab4-8bc8-b726e8000a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871408328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.871408328
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.4126067680
Short name T645
Test name
Test status
Simulation time 181906349 ps
CPU time 4.34 seconds
Started Aug 06 05:38:39 PM PDT 24
Finished Aug 06 05:38:44 PM PDT 24
Peak memory 241868 kb
Host smart-ab1fb516-d24a-4804-b23e-b1a3ac9a9b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126067680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.4126067680
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.1148424563
Short name T688
Test name
Test status
Simulation time 190595827 ps
CPU time 3.73 seconds
Started Aug 06 05:38:39 PM PDT 24
Finished Aug 06 05:38:43 PM PDT 24
Peak memory 242436 kb
Host smart-da442bc1-38e0-4eb8-b1e7-5b9d4241b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148424563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1148424563
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.1364027830
Short name T505
Test name
Test status
Simulation time 208919223 ps
CPU time 4.5 seconds
Started Aug 06 05:38:45 PM PDT 24
Finished Aug 06 05:38:49 PM PDT 24
Peak memory 241824 kb
Host smart-9e41148e-d3cd-40ef-a573-a8fece861e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364027830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1364027830
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.3241673805
Short name T208
Test name
Test status
Simulation time 398873627 ps
CPU time 8.36 seconds
Started Aug 06 05:38:38 PM PDT 24
Finished Aug 06 05:38:47 PM PDT 24
Peak memory 241936 kb
Host smart-893d835c-a16f-48c5-a21f-c8f2850ddc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241673805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.3241673805
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.1118050157
Short name T755
Test name
Test status
Simulation time 406304973 ps
CPU time 4.16 seconds
Started Aug 06 05:38:42 PM PDT 24
Finished Aug 06 05:38:47 PM PDT 24
Peak memory 241952 kb
Host smart-0e33d505-f745-4ba5-aac1-0ae41e29b28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118050157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.1118050157
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.3665353111
Short name T354
Test name
Test status
Simulation time 3697254362 ps
CPU time 8.42 seconds
Started Aug 06 05:38:38 PM PDT 24
Finished Aug 06 05:38:47 PM PDT 24
Peak memory 242404 kb
Host smart-744898a8-f4e6-41ae-b06d-6223fc8907a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665353111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.3665353111
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.2538408607
Short name T891
Test name
Test status
Simulation time 49602868 ps
CPU time 1.57 seconds
Started Aug 06 05:31:28 PM PDT 24
Finished Aug 06 05:31:30 PM PDT 24
Peak memory 240316 kb
Host smart-2a8e9772-d382-463b-a7b8-12061dad7cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538408607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2538408607
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.3119473375
Short name T589
Test name
Test status
Simulation time 2015199474 ps
CPU time 21.46 seconds
Started Aug 06 05:31:05 PM PDT 24
Finished Aug 06 05:31:26 PM PDT 24
Peak memory 242520 kb
Host smart-3cb68483-5cef-4211-a280-84b73b50f0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119473375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.3119473375
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.3805208788
Short name T170
Test name
Test status
Simulation time 3561614337 ps
CPU time 27.14 seconds
Started Aug 06 05:31:07 PM PDT 24
Finished Aug 06 05:31:35 PM PDT 24
Peak memory 248584 kb
Host smart-abfd56db-1f65-465c-9260-cbc11ce8f6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805208788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.3805208788
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.1722285391
Short name T600
Test name
Test status
Simulation time 188717209 ps
CPU time 8.87 seconds
Started Aug 06 05:31:07 PM PDT 24
Finished Aug 06 05:31:16 PM PDT 24
Peak memory 241808 kb
Host smart-f2a4c0d1-9851-46bb-b470-4ab8eb24901b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722285391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1722285391
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.3440337814
Short name T616
Test name
Test status
Simulation time 24048777787 ps
CPU time 57.05 seconds
Started Aug 06 05:31:06 PM PDT 24
Finished Aug 06 05:32:03 PM PDT 24
Peak memory 242508 kb
Host smart-5fbad7a5-cc5a-49c1-ac39-4cfef416d962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440337814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.3440337814
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.319051846
Short name T435
Test name
Test status
Simulation time 276456420 ps
CPU time 5.06 seconds
Started Aug 06 05:31:06 PM PDT 24
Finished Aug 06 05:31:11 PM PDT 24
Peak memory 242344 kb
Host smart-98bfb3d6-0baf-4e61-b86e-5d02059cd9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319051846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.319051846
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.1233985101
Short name T159
Test name
Test status
Simulation time 6537297068 ps
CPU time 44.99 seconds
Started Aug 06 05:31:10 PM PDT 24
Finished Aug 06 05:31:55 PM PDT 24
Peak memory 248676 kb
Host smart-a9d933a5-151f-4528-b676-5dcabd87bfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233985101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.1233985101
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.2023147745
Short name T617
Test name
Test status
Simulation time 3990334793 ps
CPU time 24.77 seconds
Started Aug 06 05:31:08 PM PDT 24
Finished Aug 06 05:31:33 PM PDT 24
Peak memory 242464 kb
Host smart-12393df6-1871-40de-90d8-f1c1a162279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023147745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2023147745
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.2148977954
Short name T968
Test name
Test status
Simulation time 247831185 ps
CPU time 3.81 seconds
Started Aug 06 05:31:06 PM PDT 24
Finished Aug 06 05:31:10 PM PDT 24
Peak memory 241824 kb
Host smart-7b772b6f-96f1-4b19-9329-409300a29dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148977954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2148977954
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.4039904840
Short name T690
Test name
Test status
Simulation time 923297082 ps
CPU time 14.45 seconds
Started Aug 06 05:31:05 PM PDT 24
Finished Aug 06 05:31:19 PM PDT 24
Peak memory 242220 kb
Host smart-b24b0fb2-2e89-46ee-ac81-0297876bb1f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039904840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.4039904840
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.795725726
Short name T672
Test name
Test status
Simulation time 203175915 ps
CPU time 6.55 seconds
Started Aug 06 05:31:10 PM PDT 24
Finished Aug 06 05:31:16 PM PDT 24
Peak memory 242032 kb
Host smart-fe97ac75-506f-4a24-9ac0-a9f8936f6991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795725726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.795725726
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.1842844750
Short name T21
Test name
Test status
Simulation time 11351154527 ps
CPU time 174.73 seconds
Started Aug 06 05:31:29 PM PDT 24
Finished Aug 06 05:34:24 PM PDT 24
Peak memory 272208 kb
Host smart-9782bcb9-656d-45cd-bdae-1de4a7c6afe7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842844750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.1842844750
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.1797525814
Short name T992
Test name
Test status
Simulation time 582229250 ps
CPU time 11.68 seconds
Started Aug 06 05:31:06 PM PDT 24
Finished Aug 06 05:31:18 PM PDT 24
Peak memory 242004 kb
Host smart-ee69dcb0-dc36-4631-b668-3ec3b9f46805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797525814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1797525814
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.3451538170
Short name T716
Test name
Test status
Simulation time 16346905815 ps
CPU time 200.53 seconds
Started Aug 06 05:31:31 PM PDT 24
Finished Aug 06 05:34:51 PM PDT 24
Peak memory 262568 kb
Host smart-9c9c40d6-d3fb-43ad-8d00-4221c064e296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451538170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
3451538170
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.656067223
Short name T319
Test name
Test status
Simulation time 396520627847 ps
CPU time 798.78 seconds
Started Aug 06 05:31:07 PM PDT 24
Finished Aug 06 05:44:26 PM PDT 24
Peak memory 275888 kb
Host smart-ebe39510-52aa-415a-88ae-3a9519ce5b9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656067223 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.656067223
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.34271298
Short name T576
Test name
Test status
Simulation time 2167133834 ps
CPU time 33.31 seconds
Started Aug 06 05:31:06 PM PDT 24
Finished Aug 06 05:31:39 PM PDT 24
Peak memory 242060 kb
Host smart-41b62264-2766-4165-9b6d-53b273212860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34271298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.34271298
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.2517270086
Short name T847
Test name
Test status
Simulation time 57951195 ps
CPU time 1.55 seconds
Started Aug 06 05:33:23 PM PDT 24
Finished Aug 06 05:33:25 PM PDT 24
Peak memory 240772 kb
Host smart-fede733d-9956-435a-a75b-c46d434c2896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517270086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.2517270086
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.764432512
Short name T437
Test name
Test status
Simulation time 184101542 ps
CPU time 5.54 seconds
Started Aug 06 05:33:23 PM PDT 24
Finished Aug 06 05:33:29 PM PDT 24
Peak memory 242004 kb
Host smart-456e59b4-9500-480c-a85e-b4885fe8f223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764432512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.764432512
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.2845260190
Short name T408
Test name
Test status
Simulation time 570581129 ps
CPU time 17.42 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:37 PM PDT 24
Peak memory 241972 kb
Host smart-d0ea968d-9dac-4df1-8975-1cfc6ecb49e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845260190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.2845260190
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.3811966594
Short name T1068
Test name
Test status
Simulation time 1017055016 ps
CPU time 29.39 seconds
Started Aug 06 05:33:19 PM PDT 24
Finished Aug 06 05:33:48 PM PDT 24
Peak memory 242044 kb
Host smart-76b07f70-6c92-429e-8ce0-f5d6247e831a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811966594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3811966594
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.3386586354
Short name T665
Test name
Test status
Simulation time 274647393 ps
CPU time 3.75 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:24 PM PDT 24
Peak memory 241888 kb
Host smart-d2a3fa41-ba8a-40df-8824-d0be0b5518e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386586354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.3386586354
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.2136453888
Short name T334
Test name
Test status
Simulation time 969152198 ps
CPU time 16.81 seconds
Started Aug 06 05:33:22 PM PDT 24
Finished Aug 06 05:33:38 PM PDT 24
Peak memory 244152 kb
Host smart-7449a631-941f-4ec0-a96c-18265bcfdb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136453888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.2136453888
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.1978026584
Short name T811
Test name
Test status
Simulation time 2104353088 ps
CPU time 24.21 seconds
Started Aug 06 05:33:21 PM PDT 24
Finished Aug 06 05:33:45 PM PDT 24
Peak memory 241904 kb
Host smart-24e09a53-563c-4fdc-a6a3-cb9efa01d354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978026584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.1978026584
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.2192293060
Short name T200
Test name
Test status
Simulation time 873232489 ps
CPU time 12.7 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:33 PM PDT 24
Peak memory 241752 kb
Host smart-043afbb0-4eb0-4447-83b7-1e1e05fd5590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192293060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.2192293060
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.793746866
Short name T631
Test name
Test status
Simulation time 251517187 ps
CPU time 4.56 seconds
Started Aug 06 05:33:20 PM PDT 24
Finished Aug 06 05:33:25 PM PDT 24
Peak memory 242072 kb
Host smart-b1c2fa02-d160-496f-9dfd-004bea60210e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793746866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.793746866
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.3768047722
Short name T877
Test name
Test status
Simulation time 163712612 ps
CPU time 3.55 seconds
Started Aug 06 05:33:19 PM PDT 24
Finished Aug 06 05:33:23 PM PDT 24
Peak memory 241868 kb
Host smart-7a8c4b89-58f2-4ea6-bfdb-d19b2e577d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768047722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.3768047722
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.2814393605
Short name T714
Test name
Test status
Simulation time 18853341277 ps
CPU time 182.53 seconds
Started Aug 06 05:33:24 PM PDT 24
Finished Aug 06 05:36:26 PM PDT 24
Peak memory 256816 kb
Host smart-7444a6e1-a7a7-46a5-8c87-464c48dae512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814393605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.2814393605
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.3915493343
Short name T1177
Test name
Test status
Simulation time 32366504942 ps
CPU time 473.39 seconds
Started Aug 06 05:33:24 PM PDT 24
Finished Aug 06 05:41:17 PM PDT 24
Peak memory 285924 kb
Host smart-87d17bde-cf0f-4af6-ada0-b869da9d2aea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915493343 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.3915493343
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.2169911063
Short name T178
Test name
Test status
Simulation time 18003950721 ps
CPU time 38.13 seconds
Started Aug 06 05:33:21 PM PDT 24
Finished Aug 06 05:33:59 PM PDT 24
Peak memory 243188 kb
Host smart-428a9a34-0d58-4318-98eb-a905877f8c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169911063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.2169911063
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.288843120
Short name T627
Test name
Test status
Simulation time 1439049461 ps
CPU time 4.77 seconds
Started Aug 06 05:38:39 PM PDT 24
Finished Aug 06 05:38:44 PM PDT 24
Peak memory 242332 kb
Host smart-4cd8f9b5-b747-41fc-9efd-948fd08af8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288843120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.288843120
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.569690489
Short name T802
Test name
Test status
Simulation time 171389355 ps
CPU time 4.58 seconds
Started Aug 06 05:38:41 PM PDT 24
Finished Aug 06 05:38:45 PM PDT 24
Peak memory 242164 kb
Host smart-2b5682cc-52c9-4e0e-bddd-e48df372f9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569690489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.569690489
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.468910825
Short name T1051
Test name
Test status
Simulation time 124287055 ps
CPU time 5.64 seconds
Started Aug 06 05:38:39 PM PDT 24
Finished Aug 06 05:38:44 PM PDT 24
Peak memory 241976 kb
Host smart-326ab17d-d0fb-4d99-9de2-0c9ed2e1f531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468910825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.468910825
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.663318269
Short name T189
Test name
Test status
Simulation time 140007173 ps
CPU time 3.99 seconds
Started Aug 06 05:38:40 PM PDT 24
Finished Aug 06 05:38:44 PM PDT 24
Peak memory 242312 kb
Host smart-8977803c-b67c-4d4f-9c8a-049b69ac3a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663318269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.663318269
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.2906485288
Short name T724
Test name
Test status
Simulation time 2051521421 ps
CPU time 5.33 seconds
Started Aug 06 05:38:40 PM PDT 24
Finished Aug 06 05:38:46 PM PDT 24
Peak memory 242320 kb
Host smart-c023cbf4-9f09-439d-8718-4219aacd94e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906485288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.2906485288
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.4036643797
Short name T998
Test name
Test status
Simulation time 159795040 ps
CPU time 4.45 seconds
Started Aug 06 05:38:38 PM PDT 24
Finished Aug 06 05:38:43 PM PDT 24
Peak memory 241948 kb
Host smart-c284fbc3-5185-4d64-a67c-6d94be00db94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036643797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.4036643797
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.1173014521
Short name T119
Test name
Test status
Simulation time 198021184 ps
CPU time 3.65 seconds
Started Aug 06 05:38:42 PM PDT 24
Finished Aug 06 05:38:46 PM PDT 24
Peak memory 241952 kb
Host smart-3941fec2-7e4d-4d68-8016-5ff68e2780d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173014521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.1173014521
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.355434038
Short name T585
Test name
Test status
Simulation time 104563530 ps
CPU time 4.3 seconds
Started Aug 06 05:38:44 PM PDT 24
Finished Aug 06 05:38:48 PM PDT 24
Peak memory 241864 kb
Host smart-e48dec9a-cec1-478f-b340-5ff2d3de9a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355434038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.355434038
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.1936623079
Short name T886
Test name
Test status
Simulation time 1717575117 ps
CPU time 4.44 seconds
Started Aug 06 05:38:40 PM PDT 24
Finished Aug 06 05:38:45 PM PDT 24
Peak memory 242456 kb
Host smart-e0b35832-c952-4b1f-8a5c-19325ff5314e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936623079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.1936623079
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.3239549610
Short name T1160
Test name
Test status
Simulation time 277019822 ps
CPU time 3.84 seconds
Started Aug 06 05:38:42 PM PDT 24
Finished Aug 06 05:38:46 PM PDT 24
Peak memory 241996 kb
Host smart-9c0e43cd-4ab1-4fb5-8826-85d64ea4a9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239549610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3239549610
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.2502454356
Short name T1008
Test name
Test status
Simulation time 87777206 ps
CPU time 1.47 seconds
Started Aug 06 05:33:30 PM PDT 24
Finished Aug 06 05:33:31 PM PDT 24
Peak memory 240336 kb
Host smart-a4602ca2-8d20-42f9-8d83-e0e8bdcf337b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502454356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.2502454356
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.1827665813
Short name T120
Test name
Test status
Simulation time 2501114535 ps
CPU time 26.13 seconds
Started Aug 06 05:33:33 PM PDT 24
Finished Aug 06 05:33:59 PM PDT 24
Peak memory 248564 kb
Host smart-479f79d7-49dc-424b-9de7-717f1830f2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827665813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.1827665813
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.3290526877
Short name T880
Test name
Test status
Simulation time 3727207177 ps
CPU time 24.25 seconds
Started Aug 06 05:33:33 PM PDT 24
Finished Aug 06 05:33:57 PM PDT 24
Peak memory 242100 kb
Host smart-3a3657e3-3f1c-4bdf-b1a8-7b5cfc4e3a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290526877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3290526877
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.4183924732
Short name T440
Test name
Test status
Simulation time 669300681 ps
CPU time 10.18 seconds
Started Aug 06 05:33:30 PM PDT 24
Finished Aug 06 05:33:41 PM PDT 24
Peak memory 242356 kb
Host smart-38d91a8c-2b00-4acc-bf36-99504d0219ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183924732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.4183924732
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.3979159272
Short name T1090
Test name
Test status
Simulation time 143519032 ps
CPU time 3.01 seconds
Started Aug 06 05:33:23 PM PDT 24
Finished Aug 06 05:33:26 PM PDT 24
Peak memory 241980 kb
Host smart-24440ec4-1d16-43ef-ae45-dc4e99a498b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979159272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.3979159272
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.3234267380
Short name T137
Test name
Test status
Simulation time 1271653043 ps
CPU time 10.52 seconds
Started Aug 06 05:33:32 PM PDT 24
Finished Aug 06 05:33:43 PM PDT 24
Peak memory 242408 kb
Host smart-d4541f20-b4f1-4a24-8efe-9f21883ddc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234267380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.3234267380
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.4260662425
Short name T1072
Test name
Test status
Simulation time 5507244979 ps
CPU time 21.17 seconds
Started Aug 06 05:33:31 PM PDT 24
Finished Aug 06 05:33:53 PM PDT 24
Peak memory 242032 kb
Host smart-58ba1f48-3117-418d-9a83-ca2611a8b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260662425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.4260662425
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.2765530803
Short name T75
Test name
Test status
Simulation time 2135170453 ps
CPU time 15.61 seconds
Started Aug 06 05:33:29 PM PDT 24
Finished Aug 06 05:33:45 PM PDT 24
Peak memory 242300 kb
Host smart-db350d7d-f806-4a90-b5ae-a9db5bec08d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765530803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.2765530803
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.4073665942
Short name T1010
Test name
Test status
Simulation time 812740785 ps
CPU time 13.78 seconds
Started Aug 06 05:33:24 PM PDT 24
Finished Aug 06 05:33:38 PM PDT 24
Peak memory 241932 kb
Host smart-fcfaafe5-6ee6-49ee-9c08-7a6976d08c91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073665942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.4073665942
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.763913149
Short name T346
Test name
Test status
Simulation time 258935966 ps
CPU time 4.88 seconds
Started Aug 06 05:33:30 PM PDT 24
Finished Aug 06 05:33:35 PM PDT 24
Peak memory 248488 kb
Host smart-30efd60f-8b3a-45d8-ac53-bf702df757cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=763913149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.763913149
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.1719912011
Short name T238
Test name
Test status
Simulation time 418158253 ps
CPU time 5.98 seconds
Started Aug 06 05:33:23 PM PDT 24
Finished Aug 06 05:33:29 PM PDT 24
Peak memory 242196 kb
Host smart-a0ff00e3-58eb-4883-ab27-adcf14de9cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719912011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1719912011
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.1867653564
Short name T1104
Test name
Test status
Simulation time 161252886592 ps
CPU time 637.45 seconds
Started Aug 06 05:33:30 PM PDT 24
Finished Aug 06 05:44:07 PM PDT 24
Peak memory 263628 kb
Host smart-4e838c93-1261-48d8-9298-d2383287c405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867653564 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.1867653564
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.1988078110
Short name T264
Test name
Test status
Simulation time 1774104309 ps
CPU time 9.87 seconds
Started Aug 06 05:33:31 PM PDT 24
Finished Aug 06 05:33:41 PM PDT 24
Peak memory 242644 kb
Host smart-c8f09a7f-1ea8-4671-90b7-4929d37514e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988078110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.1988078110
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.1271228033
Short name T713
Test name
Test status
Simulation time 137628203 ps
CPU time 4.81 seconds
Started Aug 06 05:38:42 PM PDT 24
Finished Aug 06 05:38:47 PM PDT 24
Peak memory 242180 kb
Host smart-86249fe6-acd3-4c88-8240-d3ecac2f0eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271228033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1271228033
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.4047504839
Short name T818
Test name
Test status
Simulation time 413536537 ps
CPU time 3.6 seconds
Started Aug 06 05:38:41 PM PDT 24
Finished Aug 06 05:38:45 PM PDT 24
Peak memory 242036 kb
Host smart-8662116c-fccc-4b05-939f-5f22ac1c401b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047504839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.4047504839
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.3903443944
Short name T848
Test name
Test status
Simulation time 240854990 ps
CPU time 3.79 seconds
Started Aug 06 05:38:45 PM PDT 24
Finished Aug 06 05:38:49 PM PDT 24
Peak memory 241972 kb
Host smart-662605be-2d68-4a76-b051-dbe6a314fd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903443944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.3903443944
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.933559868
Short name T1084
Test name
Test status
Simulation time 2073724515 ps
CPU time 6.26 seconds
Started Aug 06 05:38:43 PM PDT 24
Finished Aug 06 05:38:49 PM PDT 24
Peak memory 241708 kb
Host smart-8d6a9ab7-4984-407c-ba59-9180decaeb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933559868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.933559868
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.544980382
Short name T443
Test name
Test status
Simulation time 157008983 ps
CPU time 3.56 seconds
Started Aug 06 05:38:45 PM PDT 24
Finished Aug 06 05:38:49 PM PDT 24
Peak memory 242220 kb
Host smart-f5d1b1d9-2ce8-468a-99af-1ae7021cc654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544980382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.544980382
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.1186677422
Short name T1122
Test name
Test status
Simulation time 117698255 ps
CPU time 3.49 seconds
Started Aug 06 05:38:42 PM PDT 24
Finished Aug 06 05:38:46 PM PDT 24
Peak memory 242060 kb
Host smart-2f1e03ba-a9e7-4d86-85cb-0ae293986a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186677422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.1186677422
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.2338174220
Short name T67
Test name
Test status
Simulation time 1887226099 ps
CPU time 4.28 seconds
Started Aug 06 05:38:43 PM PDT 24
Finished Aug 06 05:38:48 PM PDT 24
Peak memory 242184 kb
Host smart-1968c46f-acd7-410e-a37d-2e487d744c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338174220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2338174220
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.3392855472
Short name T475
Test name
Test status
Simulation time 252232775 ps
CPU time 3.88 seconds
Started Aug 06 05:38:44 PM PDT 24
Finished Aug 06 05:38:48 PM PDT 24
Peak memory 242324 kb
Host smart-5cec7953-4b0e-4d54-888c-ac1600ea29b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392855472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3392855472
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.3334891559
Short name T489
Test name
Test status
Simulation time 359211796 ps
CPU time 4.09 seconds
Started Aug 06 05:38:42 PM PDT 24
Finished Aug 06 05:38:47 PM PDT 24
Peak memory 242176 kb
Host smart-9071ab83-28ae-4919-80f2-d02a3cf8a111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334891559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.3334891559
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.1205419711
Short name T506
Test name
Test status
Simulation time 70725655 ps
CPU time 1.55 seconds
Started Aug 06 05:33:48 PM PDT 24
Finished Aug 06 05:33:50 PM PDT 24
Peak memory 240840 kb
Host smart-ee6c672f-10a8-4cd3-b2d2-a9ff72f35abe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205419711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.1205419711
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.4119272978
Short name T3
Test name
Test status
Simulation time 1878220839 ps
CPU time 11.7 seconds
Started Aug 06 05:33:31 PM PDT 24
Finished Aug 06 05:33:43 PM PDT 24
Peak memory 248460 kb
Host smart-0ddee05f-73b1-4049-b440-957bf7e869db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119272978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.4119272978
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.3617956793
Short name T646
Test name
Test status
Simulation time 3825852867 ps
CPU time 30.16 seconds
Started Aug 06 05:33:31 PM PDT 24
Finished Aug 06 05:34:01 PM PDT 24
Peak memory 247292 kb
Host smart-d592fb8e-c58d-43f8-bf37-d34466f4432d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617956793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.3617956793
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.3643873131
Short name T1173
Test name
Test status
Simulation time 301883756 ps
CPU time 7.48 seconds
Started Aug 06 05:33:31 PM PDT 24
Finished Aug 06 05:33:38 PM PDT 24
Peak memory 242088 kb
Host smart-db08e1f6-66ba-4cd4-ae45-c8dd84536873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643873131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.3643873131
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.576673397
Short name T1186
Test name
Test status
Simulation time 387464118 ps
CPU time 4.71 seconds
Started Aug 06 05:33:31 PM PDT 24
Finished Aug 06 05:33:36 PM PDT 24
Peak memory 241900 kb
Host smart-738bc620-21cb-410c-91f6-688a08f8d82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576673397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.576673397
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.3591609641
Short name T573
Test name
Test status
Simulation time 356335540 ps
CPU time 9.45 seconds
Started Aug 06 05:33:30 PM PDT 24
Finished Aug 06 05:33:39 PM PDT 24
Peak memory 242168 kb
Host smart-6d1ca7eb-9a2f-4b7e-b249-309f63b2d09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591609641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.3591609641
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.544546452
Short name T726
Test name
Test status
Simulation time 1002885092 ps
CPU time 15.94 seconds
Started Aug 06 05:33:32 PM PDT 24
Finished Aug 06 05:33:48 PM PDT 24
Peak memory 242352 kb
Host smart-5aa1fab0-e88b-4128-a625-eadbb084fc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544546452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.544546452
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.2440470955
Short name T777
Test name
Test status
Simulation time 324547165 ps
CPU time 7.45 seconds
Started Aug 06 05:33:30 PM PDT 24
Finished Aug 06 05:33:37 PM PDT 24
Peak memory 242080 kb
Host smart-41d9ff4f-394d-4c42-a7eb-97690fd06925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440470955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.2440470955
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.2482552194
Short name T360
Test name
Test status
Simulation time 793515081 ps
CPU time 19.29 seconds
Started Aug 06 05:33:32 PM PDT 24
Finished Aug 06 05:33:52 PM PDT 24
Peak memory 242080 kb
Host smart-7ac7c5c2-4403-48ca-ace7-1bc690df63d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2482552194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.2482552194
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.2817149718
Short name T109
Test name
Test status
Simulation time 252336462 ps
CPU time 7.69 seconds
Started Aug 06 05:33:47 PM PDT 24
Finished Aug 06 05:33:54 PM PDT 24
Peak memory 241964 kb
Host smart-fe0a8878-0a04-482b-92dd-ce021e231db5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2817149718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.2817149718
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.1538932750
Short name T472
Test name
Test status
Simulation time 147334808 ps
CPU time 5.54 seconds
Started Aug 06 05:33:31 PM PDT 24
Finished Aug 06 05:33:37 PM PDT 24
Peak memory 241908 kb
Host smart-c4148083-e5f5-4e26-8103-14f77972902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538932750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.1538932750
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.2736157537
Short name T284
Test name
Test status
Simulation time 159903497742 ps
CPU time 2016.22 seconds
Started Aug 06 05:33:47 PM PDT 24
Finished Aug 06 06:07:24 PM PDT 24
Peak memory 479544 kb
Host smart-287854eb-e5ac-41cc-9d1d-38017bf3786e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736157537 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.2736157537
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.3158993414
Short name T1170
Test name
Test status
Simulation time 11654738132 ps
CPU time 19.31 seconds
Started Aug 06 05:33:47 PM PDT 24
Finished Aug 06 05:34:06 PM PDT 24
Peak memory 242376 kb
Host smart-77602de2-a952-41c9-99b6-e56b7ba0eb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158993414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.3158993414
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.215545586
Short name T869
Test name
Test status
Simulation time 298482907 ps
CPU time 4.61 seconds
Started Aug 06 05:38:38 PM PDT 24
Finished Aug 06 05:38:43 PM PDT 24
Peak memory 242364 kb
Host smart-7d62ad74-908f-40f3-8b4d-7163d90b8ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215545586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.215545586
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.1455321397
Short name T552
Test name
Test status
Simulation time 381841176 ps
CPU time 4.08 seconds
Started Aug 06 05:38:43 PM PDT 24
Finished Aug 06 05:38:47 PM PDT 24
Peak memory 242008 kb
Host smart-6952a9c5-26a7-4f7f-a587-33ee3a17ad16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455321397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.1455321397
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.3915544560
Short name T542
Test name
Test status
Simulation time 446640960 ps
CPU time 5.26 seconds
Started Aug 06 05:38:43 PM PDT 24
Finished Aug 06 05:38:49 PM PDT 24
Peak memory 241988 kb
Host smart-955db559-39b9-40f9-a77a-ed66b246dd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915544560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3915544560
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.2674924613
Short name T1166
Test name
Test status
Simulation time 122307933 ps
CPU time 4 seconds
Started Aug 06 05:38:45 PM PDT 24
Finished Aug 06 05:38:50 PM PDT 24
Peak memory 242304 kb
Host smart-5510321a-3e8e-4ba1-a326-2dbe21a0ff0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674924613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.2674924613
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.1053193420
Short name T488
Test name
Test status
Simulation time 645685876 ps
CPU time 5.49 seconds
Started Aug 06 05:38:59 PM PDT 24
Finished Aug 06 05:39:05 PM PDT 24
Peak memory 241888 kb
Host smart-2897a1d1-6875-4a25-9e87-8da6e01dad0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053193420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.1053193420
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.3254238073
Short name T952
Test name
Test status
Simulation time 610249493 ps
CPU time 4.38 seconds
Started Aug 06 05:38:55 PM PDT 24
Finished Aug 06 05:38:59 PM PDT 24
Peak memory 241860 kb
Host smart-13ddb4c8-9468-4060-82d5-8ffba7769936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254238073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.3254238073
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.570164383
Short name T219
Test name
Test status
Simulation time 588050005 ps
CPU time 4.34 seconds
Started Aug 06 05:38:59 PM PDT 24
Finished Aug 06 05:39:03 PM PDT 24
Peak memory 241956 kb
Host smart-7a07bfe7-4d48-4343-b92e-63a8250598c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570164383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.570164383
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.3078264041
Short name T730
Test name
Test status
Simulation time 2171677083 ps
CPU time 5.33 seconds
Started Aug 06 05:38:58 PM PDT 24
Finished Aug 06 05:39:03 PM PDT 24
Peak memory 242424 kb
Host smart-1d36dc42-7750-4f52-9c3e-59a4199dc9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078264041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.3078264041
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.856434580
Short name T1022
Test name
Test status
Simulation time 162174912 ps
CPU time 4.85 seconds
Started Aug 06 05:39:03 PM PDT 24
Finished Aug 06 05:39:08 PM PDT 24
Peak memory 242176 kb
Host smart-a835826c-a5f3-4d4b-acb2-c460881273d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856434580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.856434580
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.476279545
Short name T476
Test name
Test status
Simulation time 65528868 ps
CPU time 1.85 seconds
Started Aug 06 05:33:48 PM PDT 24
Finished Aug 06 05:33:50 PM PDT 24
Peak memory 240616 kb
Host smart-184193b2-6434-4227-a3a3-78f5f8a94db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476279545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.476279545
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.3848294534
Short name T134
Test name
Test status
Simulation time 388807400 ps
CPU time 15.01 seconds
Started Aug 06 05:33:47 PM PDT 24
Finished Aug 06 05:34:02 PM PDT 24
Peak memory 242828 kb
Host smart-d3631390-8d3b-43e9-b20a-928ef1db0634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848294534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.3848294534
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.2689138148
Short name T327
Test name
Test status
Simulation time 1393603127 ps
CPU time 38.88 seconds
Started Aug 06 05:33:48 PM PDT 24
Finished Aug 06 05:34:27 PM PDT 24
Peak memory 247296 kb
Host smart-ec51c293-f927-46a4-a0aa-1b0eaca98923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689138148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.2689138148
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.1397329533
Short name T733
Test name
Test status
Simulation time 3286327355 ps
CPU time 10.11 seconds
Started Aug 06 05:33:48 PM PDT 24
Finished Aug 06 05:33:59 PM PDT 24
Peak memory 242024 kb
Host smart-ce146649-0a61-4845-857e-25f0828da49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397329533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.1397329533
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.464838312
Short name T611
Test name
Test status
Simulation time 288233874 ps
CPU time 4.05 seconds
Started Aug 06 05:33:46 PM PDT 24
Finished Aug 06 05:33:50 PM PDT 24
Peak memory 242164 kb
Host smart-94db7cd7-c061-4736-8ff0-58fcab177b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464838312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.464838312
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.4183133065
Short name T333
Test name
Test status
Simulation time 904523940 ps
CPU time 7.72 seconds
Started Aug 06 05:33:48 PM PDT 24
Finished Aug 06 05:33:56 PM PDT 24
Peak memory 248576 kb
Host smart-41130694-dbfe-4cc4-bca4-5170c48a58b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183133065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.4183133065
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.3488653593
Short name T10
Test name
Test status
Simulation time 8160016713 ps
CPU time 31.95 seconds
Started Aug 06 05:33:48 PM PDT 24
Finished Aug 06 05:34:20 PM PDT 24
Peak memory 248704 kb
Host smart-909c8342-88da-45ec-bbea-4cdbf1b69df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488653593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.3488653593
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.324864944
Short name T563
Test name
Test status
Simulation time 471344639 ps
CPU time 13.04 seconds
Started Aug 06 05:33:46 PM PDT 24
Finished Aug 06 05:33:59 PM PDT 24
Peak memory 241804 kb
Host smart-c51af3fd-8cd7-47f7-b192-4403d2b09701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324864944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.324864944
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.4240483207
Short name T1164
Test name
Test status
Simulation time 5733349673 ps
CPU time 22.64 seconds
Started Aug 06 05:33:49 PM PDT 24
Finished Aug 06 05:34:12 PM PDT 24
Peak memory 242120 kb
Host smart-f752e112-6778-49b5-9044-5e021b584831
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4240483207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.4240483207
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.3567619507
Short name T903
Test name
Test status
Simulation time 4926248243 ps
CPU time 9.61 seconds
Started Aug 06 05:33:47 PM PDT 24
Finished Aug 06 05:33:57 PM PDT 24
Peak memory 242300 kb
Host smart-e0b3f067-ae8e-46b8-bca8-68695ae5221d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567619507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.3567619507
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.1438595045
Short name T246
Test name
Test status
Simulation time 117068176244 ps
CPU time 228.61 seconds
Started Aug 06 05:33:46 PM PDT 24
Finished Aug 06 05:37:34 PM PDT 24
Peak memory 256892 kb
Host smart-ec580c2a-01eb-4330-a3e4-b9eb1bfb1b25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438595045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.1438595045
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.2160399008
Short name T685
Test name
Test status
Simulation time 42545461155 ps
CPU time 827.09 seconds
Started Aug 06 05:33:48 PM PDT 24
Finished Aug 06 05:47:36 PM PDT 24
Peak memory 281460 kb
Host smart-5c14611c-0c02-4841-80b1-c723daf3b193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160399008 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.2160399008
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.527472
Short name T721
Test name
Test status
Simulation time 677701727 ps
CPU time 24.35 seconds
Started Aug 06 05:33:47 PM PDT 24
Finished Aug 06 05:34:11 PM PDT 24
Peak memory 248584 kb
Host smart-1184f0fb-09e3-4a93-9bbf-0e624bef1361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.527472
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.3316266245
Short name T512
Test name
Test status
Simulation time 364322104 ps
CPU time 4.08 seconds
Started Aug 06 05:38:57 PM PDT 24
Finished Aug 06 05:39:01 PM PDT 24
Peak memory 242144 kb
Host smart-2ece2ba5-0a78-4c95-8526-2d77d181dafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316266245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.3316266245
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.2831752258
Short name T65
Test name
Test status
Simulation time 136258492 ps
CPU time 3.2 seconds
Started Aug 06 05:38:56 PM PDT 24
Finished Aug 06 05:38:59 PM PDT 24
Peak memory 241984 kb
Host smart-6dadc289-4db2-40f0-8a8e-4841b29dda3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831752258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.2831752258
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.1140990793
Short name T570
Test name
Test status
Simulation time 438662018 ps
CPU time 4.53 seconds
Started Aug 06 05:38:58 PM PDT 24
Finished Aug 06 05:39:03 PM PDT 24
Peak memory 241968 kb
Host smart-2cc5d68f-3c64-456c-80e3-c3d578058de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140990793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.1140990793
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.3270277296
Short name T594
Test name
Test status
Simulation time 125213839 ps
CPU time 4.03 seconds
Started Aug 06 05:38:56 PM PDT 24
Finished Aug 06 05:39:00 PM PDT 24
Peak memory 242292 kb
Host smart-e20736ec-b933-4b52-bce2-a644f1f8b1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270277296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.3270277296
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.3342208431
Short name T554
Test name
Test status
Simulation time 2067556956 ps
CPU time 4.24 seconds
Started Aug 06 05:38:58 PM PDT 24
Finished Aug 06 05:39:02 PM PDT 24
Peak memory 241972 kb
Host smart-8755a9e6-f15f-4e9b-85ba-49e29e485a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342208431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3342208431
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.4220126568
Short name T837
Test name
Test status
Simulation time 504783975 ps
CPU time 4.42 seconds
Started Aug 06 05:39:03 PM PDT 24
Finished Aug 06 05:39:07 PM PDT 24
Peak memory 241948 kb
Host smart-4798cd3e-19da-4249-aa7e-05275cfff835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220126568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.4220126568
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.2128392782
Short name T578
Test name
Test status
Simulation time 1516407743 ps
CPU time 6.19 seconds
Started Aug 06 05:39:06 PM PDT 24
Finished Aug 06 05:39:12 PM PDT 24
Peak memory 241808 kb
Host smart-bae0178a-591f-493e-879f-e634f540ec7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128392782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2128392782
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.2522350626
Short name T1067
Test name
Test status
Simulation time 204178209 ps
CPU time 3.63 seconds
Started Aug 06 05:39:00 PM PDT 24
Finished Aug 06 05:39:04 PM PDT 24
Peak memory 242308 kb
Host smart-1686024f-a9bf-4dd6-8320-8fe5c6060c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522350626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.2522350626
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.422980759
Short name T977
Test name
Test status
Simulation time 172601874 ps
CPU time 4.45 seconds
Started Aug 06 05:39:02 PM PDT 24
Finished Aug 06 05:39:06 PM PDT 24
Peak memory 242120 kb
Host smart-4ec80b86-090c-42a5-b4ff-ad5c48d1c197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422980759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.422980759
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.44145698
Short name T26
Test name
Test status
Simulation time 224381703 ps
CPU time 4.5 seconds
Started Aug 06 05:39:02 PM PDT 24
Finished Aug 06 05:39:07 PM PDT 24
Peak memory 242212 kb
Host smart-de7dd309-ab26-4405-aaae-b01ec43199b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44145698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.44145698
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.1991410363
Short name T16
Test name
Test status
Simulation time 101415404 ps
CPU time 2.02 seconds
Started Aug 06 05:34:07 PM PDT 24
Finished Aug 06 05:34:09 PM PDT 24
Peak memory 240228 kb
Host smart-d54ae28a-ae57-43e7-bc92-1cdcc810918d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991410363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.1991410363
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.507929317
Short name T117
Test name
Test status
Simulation time 1269045128 ps
CPU time 17.11 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:23 PM PDT 24
Peak memory 242168 kb
Host smart-2dfaeef6-dc70-46ef-bc50-601e9df08662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507929317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.507929317
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.585100899
Short name T754
Test name
Test status
Simulation time 2168785477 ps
CPU time 27.86 seconds
Started Aug 06 05:34:04 PM PDT 24
Finished Aug 06 05:34:32 PM PDT 24
Peak memory 242280 kb
Host smart-6c583c92-e08a-4061-971e-00e30a5ddef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585100899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.585100899
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.1879750903
Short name T430
Test name
Test status
Simulation time 6317325975 ps
CPU time 45.61 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:52 PM PDT 24
Peak memory 242952 kb
Host smart-03148c02-8b9e-42fd-bdc0-d4638aad2122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879750903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.1879750903
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.145541266
Short name T941
Test name
Test status
Simulation time 84770689 ps
CPU time 3.29 seconds
Started Aug 06 05:34:07 PM PDT 24
Finished Aug 06 05:34:10 PM PDT 24
Peak memory 242104 kb
Host smart-4cc736a5-0539-4436-b822-7f2e695eabea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145541266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.145541266
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.181058361
Short name T424
Test name
Test status
Simulation time 1106989680 ps
CPU time 7.23 seconds
Started Aug 06 05:34:13 PM PDT 24
Finished Aug 06 05:34:20 PM PDT 24
Peak memory 248532 kb
Host smart-e7d01b67-68ba-4c9f-856b-94f110912dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181058361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.181058361
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.2508616113
Short name T1083
Test name
Test status
Simulation time 1554142915 ps
CPU time 17.24 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:24 PM PDT 24
Peak memory 242304 kb
Host smart-95cb3a06-7031-4d30-b49d-f9080409156b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508616113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.2508616113
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.721917199
Short name T936
Test name
Test status
Simulation time 1601290422 ps
CPU time 29.44 seconds
Started Aug 06 05:34:03 PM PDT 24
Finished Aug 06 05:34:33 PM PDT 24
Peak memory 242268 kb
Host smart-36cc34c1-a965-41c0-9b4d-9bc97312b443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721917199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.721917199
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.1114023326
Short name T367
Test name
Test status
Simulation time 3001744610 ps
CPU time 23.91 seconds
Started Aug 06 05:34:07 PM PDT 24
Finished Aug 06 05:34:31 PM PDT 24
Peak memory 248712 kb
Host smart-f8ec4863-109e-4097-a9f3-b8a8f10769e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114023326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.1114023326
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.199264288
Short name T743
Test name
Test status
Simulation time 1088274406 ps
CPU time 9.77 seconds
Started Aug 06 05:34:07 PM PDT 24
Finished Aug 06 05:34:17 PM PDT 24
Peak memory 242116 kb
Host smart-7d3d927e-0f44-42ce-8dc3-353e29cc9ec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=199264288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.199264288
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.932158719
Short name T739
Test name
Test status
Simulation time 2794602205 ps
CPU time 10.37 seconds
Started Aug 06 05:33:49 PM PDT 24
Finished Aug 06 05:34:00 PM PDT 24
Peak memory 242044 kb
Host smart-25e9b89f-2184-4a83-82b3-1e5c781f1080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932158719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.932158719
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.3435741715
Short name T1055
Test name
Test status
Simulation time 31724402366 ps
CPU time 163.87 seconds
Started Aug 06 05:34:11 PM PDT 24
Finished Aug 06 05:36:55 PM PDT 24
Peak memory 274276 kb
Host smart-147be0c0-12bf-4f4b-8d55-1451e027521f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435741715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.3435741715
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.2225431855
Short name T916
Test name
Test status
Simulation time 219710800663 ps
CPU time 817.07 seconds
Started Aug 06 05:34:05 PM PDT 24
Finished Aug 06 05:47:42 PM PDT 24
Peak memory 297856 kb
Host smart-d1d3475b-ae5a-47f6-869e-4671af524c15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225431855 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.2225431855
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.981934758
Short name T1100
Test name
Test status
Simulation time 664955597 ps
CPU time 13.64 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:20 PM PDT 24
Peak memory 242320 kb
Host smart-24ce2a08-cdc5-4363-b73a-32510aa26ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981934758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.981934758
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.2073474285
Short name T702
Test name
Test status
Simulation time 126077867 ps
CPU time 3.39 seconds
Started Aug 06 05:39:06 PM PDT 24
Finished Aug 06 05:39:09 PM PDT 24
Peak memory 242084 kb
Host smart-fe17f81f-0fe7-41a1-a5ac-3562bc1256bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073474285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.2073474285
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.827543801
Short name T187
Test name
Test status
Simulation time 288615126 ps
CPU time 3.76 seconds
Started Aug 06 05:39:08 PM PDT 24
Finished Aug 06 05:39:12 PM PDT 24
Peak memory 242184 kb
Host smart-fe13f72c-2f53-49b9-8a3c-59e8af2a5c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827543801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.827543801
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.1060201341
Short name T539
Test name
Test status
Simulation time 568837975 ps
CPU time 4.49 seconds
Started Aug 06 05:38:55 PM PDT 24
Finished Aug 06 05:38:59 PM PDT 24
Peak memory 242056 kb
Host smart-8d39ab90-fa39-46d0-97d7-6eb7e2b2161d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060201341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.1060201341
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.2773565758
Short name T615
Test name
Test status
Simulation time 171671454 ps
CPU time 3.89 seconds
Started Aug 06 05:38:55 PM PDT 24
Finished Aug 06 05:38:59 PM PDT 24
Peak memory 242200 kb
Host smart-45c60143-0c66-4283-bf55-91836c9d3ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773565758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.2773565758
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.1514459051
Short name T1132
Test name
Test status
Simulation time 2097723268 ps
CPU time 4.9 seconds
Started Aug 06 05:39:08 PM PDT 24
Finished Aug 06 05:39:13 PM PDT 24
Peak memory 242140 kb
Host smart-4214d1a5-76a2-49a0-a7c3-cf2990ff7912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514459051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.1514459051
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.2344224946
Short name T477
Test name
Test status
Simulation time 109648879 ps
CPU time 4 seconds
Started Aug 06 05:39:03 PM PDT 24
Finished Aug 06 05:39:07 PM PDT 24
Peak memory 242084 kb
Host smart-18542eb8-7a2a-4c3f-8f0e-eaba473e941a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344224946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.2344224946
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.255666483
Short name T842
Test name
Test status
Simulation time 598597683 ps
CPU time 4.48 seconds
Started Aug 06 05:39:07 PM PDT 24
Finished Aug 06 05:39:12 PM PDT 24
Peak memory 241976 kb
Host smart-76da22a3-3214-4f4d-b834-f7504e65876a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255666483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.255666483
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.1031543420
Short name T794
Test name
Test status
Simulation time 375203353 ps
CPU time 4.15 seconds
Started Aug 06 05:39:06 PM PDT 24
Finished Aug 06 05:39:11 PM PDT 24
Peak memory 242208 kb
Host smart-b7cbc940-20cd-4caa-aa89-516dc67b6022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031543420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.1031543420
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.3054003462
Short name T1053
Test name
Test status
Simulation time 264537067 ps
CPU time 4.61 seconds
Started Aug 06 05:38:54 PM PDT 24
Finished Aug 06 05:38:59 PM PDT 24
Peak memory 241864 kb
Host smart-9e64da65-c646-48ff-aca6-c76739342928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054003462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3054003462
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.1992633214
Short name T661
Test name
Test status
Simulation time 86561548 ps
CPU time 1.62 seconds
Started Aug 06 05:34:04 PM PDT 24
Finished Aug 06 05:34:06 PM PDT 24
Peak memory 240264 kb
Host smart-8eea82aa-f58c-4c0d-a587-cd248578bb7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992633214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1992633214
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.572320613
Short name T795
Test name
Test status
Simulation time 1233168900 ps
CPU time 14.48 seconds
Started Aug 06 05:34:05 PM PDT 24
Finished Aug 06 05:34:19 PM PDT 24
Peak memory 246276 kb
Host smart-c7e64299-629a-4b51-b3ac-cde4da249683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572320613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.572320613
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.1563139792
Short name T789
Test name
Test status
Simulation time 8573951172 ps
CPU time 32.19 seconds
Started Aug 06 05:34:10 PM PDT 24
Finished Aug 06 05:34:42 PM PDT 24
Peak memory 242064 kb
Host smart-bd503aab-e9d9-4e63-9b11-9a2e4bceaf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563139792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.1563139792
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.2363460446
Short name T535
Test name
Test status
Simulation time 9679870662 ps
CPU time 86.83 seconds
Started Aug 06 05:34:07 PM PDT 24
Finished Aug 06 05:35:34 PM PDT 24
Peak memory 243528 kb
Host smart-552fc655-28c0-478d-83d7-8519e0b52cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363460446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.2363460446
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.3094720195
Short name T865
Test name
Test status
Simulation time 2924634817 ps
CPU time 38.43 seconds
Started Aug 06 05:34:03 PM PDT 24
Finished Aug 06 05:34:41 PM PDT 24
Peak memory 261712 kb
Host smart-13f4578d-2841-4efa-8a9c-78fa153cac86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094720195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.3094720195
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.457396590
Short name T636
Test name
Test status
Simulation time 8152623320 ps
CPU time 20.45 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:27 PM PDT 24
Peak memory 242944 kb
Host smart-7cd754a9-18cc-4b42-a098-3849df55c696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457396590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.457396590
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.3416971554
Short name T990
Test name
Test status
Simulation time 670305757 ps
CPU time 15.57 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:22 PM PDT 24
Peak memory 242176 kb
Host smart-304a8ec7-7f8c-4e29-8821-ab5d6f89ea6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416971554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.3416971554
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.3922301359
Short name T202
Test name
Test status
Simulation time 446746511 ps
CPU time 8.22 seconds
Started Aug 06 05:34:04 PM PDT 24
Finished Aug 06 05:34:12 PM PDT 24
Peak memory 248636 kb
Host smart-2a3ca585-e787-4250-af3b-814c5b0893f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922301359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.3922301359
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.825394830
Short name T878
Test name
Test status
Simulation time 203432438 ps
CPU time 3.33 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:10 PM PDT 24
Peak memory 248192 kb
Host smart-7a310a0c-2b30-496c-b81e-972724c4a36c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825394830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.825394830
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.2369450410
Short name T1169
Test name
Test status
Simulation time 637251685 ps
CPU time 4.87 seconds
Started Aug 06 05:34:03 PM PDT 24
Finished Aug 06 05:34:08 PM PDT 24
Peak memory 242144 kb
Host smart-c2123abc-7534-4987-9dac-da56963332d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369450410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.2369450410
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.1139312715
Short name T1037
Test name
Test status
Simulation time 18767915742 ps
CPU time 222.3 seconds
Started Aug 06 05:34:05 PM PDT 24
Finished Aug 06 05:37:48 PM PDT 24
Peak memory 259236 kb
Host smart-a201bc13-374f-4076-aa92-9227efb0552a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139312715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.1139312715
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.4257895182
Short name T125
Test name
Test status
Simulation time 291282296232 ps
CPU time 1305.28 seconds
Started Aug 06 05:34:03 PM PDT 24
Finished Aug 06 05:55:48 PM PDT 24
Peak memory 329616 kb
Host smart-abc3e83f-8170-4068-b646-81345bd9247b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257895182 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.4257895182
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.1051750957
Short name T355
Test name
Test status
Simulation time 4667473331 ps
CPU time 30.39 seconds
Started Aug 06 05:34:10 PM PDT 24
Finished Aug 06 05:34:41 PM PDT 24
Peak memory 248512 kb
Host smart-2caafe36-6068-4db1-a2d0-1ffc3cfce003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051750957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.1051750957
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.2969341453
Short name T619
Test name
Test status
Simulation time 1632459959 ps
CPU time 4.94 seconds
Started Aug 06 05:39:05 PM PDT 24
Finished Aug 06 05:39:10 PM PDT 24
Peak memory 242344 kb
Host smart-72f1087f-2c58-403a-8b61-4cc0ea8fd487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969341453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.2969341453
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.2137671067
Short name T167
Test name
Test status
Simulation time 149109154 ps
CPU time 4.27 seconds
Started Aug 06 05:39:02 PM PDT 24
Finished Aug 06 05:39:06 PM PDT 24
Peak memory 241908 kb
Host smart-87a62c4f-a1ca-4a10-9698-6ef224b25de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137671067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.2137671067
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.4029972088
Short name T549
Test name
Test status
Simulation time 129262859 ps
CPU time 3.37 seconds
Started Aug 06 05:38:56 PM PDT 24
Finished Aug 06 05:39:00 PM PDT 24
Peak memory 242028 kb
Host smart-8cfe86b1-8e2c-4575-9ab4-c92197fcf7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029972088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.4029972088
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.4275066218
Short name T66
Test name
Test status
Simulation time 1656162224 ps
CPU time 5.39 seconds
Started Aug 06 05:39:01 PM PDT 24
Finished Aug 06 05:39:07 PM PDT 24
Peak memory 242080 kb
Host smart-a41ae49e-97c4-48c5-b33a-8d6776562489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275066218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.4275066218
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.1501203732
Short name T47
Test name
Test status
Simulation time 607078963 ps
CPU time 5.27 seconds
Started Aug 06 05:38:57 PM PDT 24
Finished Aug 06 05:39:02 PM PDT 24
Peak memory 242256 kb
Host smart-22db741a-99f8-4458-b4a8-2aad544532ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501203732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.1501203732
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.1670390074
Short name T735
Test name
Test status
Simulation time 101459344 ps
CPU time 3.05 seconds
Started Aug 06 05:39:08 PM PDT 24
Finished Aug 06 05:39:11 PM PDT 24
Peak memory 242256 kb
Host smart-99ce6614-784b-481a-a7ba-ff26cc4751da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670390074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.1670390074
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.2103006960
Short name T1031
Test name
Test status
Simulation time 404196780 ps
CPU time 3.94 seconds
Started Aug 06 05:39:03 PM PDT 24
Finished Aug 06 05:39:07 PM PDT 24
Peak memory 242232 kb
Host smart-866d9ea2-1115-4d0e-8b9d-7dab53e9157a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103006960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2103006960
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.2486330731
Short name T1021
Test name
Test status
Simulation time 591873080 ps
CPU time 4.97 seconds
Started Aug 06 05:39:03 PM PDT 24
Finished Aug 06 05:39:08 PM PDT 24
Peak memory 241888 kb
Host smart-5f8bb2b0-07cd-4b33-a97f-406f836bfbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486330731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.2486330731
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.333684022
Short name T643
Test name
Test status
Simulation time 268062604 ps
CPU time 4.25 seconds
Started Aug 06 05:39:06 PM PDT 24
Finished Aug 06 05:39:11 PM PDT 24
Peak memory 241964 kb
Host smart-b021d260-996b-41e3-9d79-78c9a050e98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333684022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.333684022
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.1300880030
Short name T511
Test name
Test status
Simulation time 230438519 ps
CPU time 1.67 seconds
Started Aug 06 05:34:05 PM PDT 24
Finished Aug 06 05:34:07 PM PDT 24
Peak memory 240516 kb
Host smart-1c6f94c7-a815-44be-bf12-6d63fa3a8ca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300880030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.1300880030
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.3536393114
Short name T969
Test name
Test status
Simulation time 20426605715 ps
CPU time 42.93 seconds
Started Aug 06 05:34:05 PM PDT 24
Finished Aug 06 05:34:48 PM PDT 24
Peak memory 248628 kb
Host smart-9ef97399-f7bc-44e9-98c4-ce3d6ccb1414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536393114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3536393114
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.266140668
Short name T138
Test name
Test status
Simulation time 270508431 ps
CPU time 14.4 seconds
Started Aug 06 05:34:05 PM PDT 24
Finished Aug 06 05:34:19 PM PDT 24
Peak memory 241964 kb
Host smart-60e302f9-4c15-489c-8487-df5917f5a9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266140668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.266140668
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.2542247400
Short name T426
Test name
Test status
Simulation time 14364909042 ps
CPU time 29.6 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:36 PM PDT 24
Peak memory 248736 kb
Host smart-9f773491-5c2d-490f-a1ca-7f0072ad88da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542247400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.2542247400
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.3071568913
Short name T1004
Test name
Test status
Simulation time 189467280 ps
CPU time 4.69 seconds
Started Aug 06 05:34:05 PM PDT 24
Finished Aug 06 05:34:10 PM PDT 24
Peak memory 242124 kb
Host smart-fd450744-47b1-4011-bf56-dce15291158e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071568913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.3071568913
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.2626484537
Short name T1076
Test name
Test status
Simulation time 1588949256 ps
CPU time 38.55 seconds
Started Aug 06 05:34:03 PM PDT 24
Finished Aug 06 05:34:42 PM PDT 24
Peak memory 242044 kb
Host smart-8fc18a65-d128-43bc-90f6-542f509293bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626484537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2626484537
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.2149296705
Short name T1060
Test name
Test status
Simulation time 243603779 ps
CPU time 9.34 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:16 PM PDT 24
Peak memory 242160 kb
Host smart-f9c6ba66-43b8-4b84-9e0e-42873c659ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149296705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.2149296705
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.461329845
Short name T799
Test name
Test status
Simulation time 570375823 ps
CPU time 15.9 seconds
Started Aug 06 05:34:04 PM PDT 24
Finished Aug 06 05:34:20 PM PDT 24
Peak memory 241992 kb
Host smart-60d0ba68-b4aa-48a9-95e1-4899d273003a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461329845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.461329845
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.2724157281
Short name T352
Test name
Test status
Simulation time 422498241 ps
CPU time 4.14 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:10 PM PDT 24
Peak memory 241896 kb
Host smart-b816e4e7-2800-4141-9bab-139f73c3b2fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724157281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.2724157281
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.1204245679
Short name T581
Test name
Test status
Simulation time 302729366 ps
CPU time 9.19 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:16 PM PDT 24
Peak memory 241976 kb
Host smart-f620c7e9-888e-4a85-b451-9369aaf054cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204245679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.1204245679
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.77568540
Short name T228
Test name
Test status
Simulation time 4213697305 ps
CPU time 33.27 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:40 PM PDT 24
Peak memory 243948 kb
Host smart-fe434209-08a9-4e32-9762-96f45790caae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77568540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.77568540
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.1696528144
Short name T317
Test name
Test status
Simulation time 20200237848 ps
CPU time 243.97 seconds
Started Aug 06 05:34:07 PM PDT 24
Finished Aug 06 05:38:11 PM PDT 24
Peak memory 256960 kb
Host smart-88da725d-318f-473c-8f9f-3315ae95f9c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696528144 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.1696528144
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.702055549
Short name T705
Test name
Test status
Simulation time 1918268166 ps
CPU time 18.98 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:25 PM PDT 24
Peak memory 242284 kb
Host smart-f1fe15c6-9988-4962-b118-bf3d3e389e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702055549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.702055549
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.162162265
Short name T580
Test name
Test status
Simulation time 311807305 ps
CPU time 4.26 seconds
Started Aug 06 05:39:07 PM PDT 24
Finished Aug 06 05:39:11 PM PDT 24
Peak memory 241996 kb
Host smart-96a6625c-78b7-4579-8179-98445ae41d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162162265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.162162265
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.2345881659
Short name T420
Test name
Test status
Simulation time 229712928 ps
CPU time 3.65 seconds
Started Aug 06 05:39:03 PM PDT 24
Finished Aug 06 05:39:07 PM PDT 24
Peak memory 241968 kb
Host smart-0014e16b-4a9d-4737-8a4c-4fe6e84c8c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345881659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.2345881659
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.3230770867
Short name T444
Test name
Test status
Simulation time 497049731 ps
CPU time 4.45 seconds
Started Aug 06 05:39:03 PM PDT 24
Finished Aug 06 05:39:07 PM PDT 24
Peak memory 242460 kb
Host smart-ddbf6993-2129-4a80-aa4a-e72660b3846d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230770867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3230770867
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.1251046840
Short name T663
Test name
Test status
Simulation time 96540339 ps
CPU time 3.9 seconds
Started Aug 06 05:39:02 PM PDT 24
Finished Aug 06 05:39:06 PM PDT 24
Peak memory 241908 kb
Host smart-7b73a2a5-92bc-4330-991c-ec821dd42bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251046840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.1251046840
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.1007191760
Short name T574
Test name
Test status
Simulation time 118098603 ps
CPU time 3.11 seconds
Started Aug 06 05:39:02 PM PDT 24
Finished Aug 06 05:39:05 PM PDT 24
Peak memory 242156 kb
Host smart-f54ac99e-5b8f-40b0-9655-82eeb5f9d228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007191760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.1007191760
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.414015172
Short name T654
Test name
Test status
Simulation time 136232979 ps
CPU time 4.09 seconds
Started Aug 06 05:39:03 PM PDT 24
Finished Aug 06 05:39:07 PM PDT 24
Peak memory 241884 kb
Host smart-d41e89b6-9eff-4fa5-b9ff-1f1f22726ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414015172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.414015172
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.1060206457
Short name T651
Test name
Test status
Simulation time 124620961 ps
CPU time 4.28 seconds
Started Aug 06 05:38:55 PM PDT 24
Finished Aug 06 05:39:00 PM PDT 24
Peak memory 241984 kb
Host smart-00121f89-aca2-4ad7-a45f-14a5910d4cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060206457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.1060206457
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.1453585343
Short name T791
Test name
Test status
Simulation time 482096125 ps
CPU time 4.83 seconds
Started Aug 06 05:38:58 PM PDT 24
Finished Aug 06 05:39:02 PM PDT 24
Peak memory 242220 kb
Host smart-fc5bad71-b582-4c09-854b-b60ed266a9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453585343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.1453585343
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.3585553144
Short name T422
Test name
Test status
Simulation time 224553934 ps
CPU time 2.45 seconds
Started Aug 06 05:34:25 PM PDT 24
Finished Aug 06 05:34:27 PM PDT 24
Peak memory 240496 kb
Host smart-2a7d6cf6-80df-4a78-99a1-46c7beb370f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585553144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.3585553144
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.3372390358
Short name T331
Test name
Test status
Simulation time 2579403582 ps
CPU time 27.23 seconds
Started Aug 06 05:34:07 PM PDT 24
Finished Aug 06 05:34:34 PM PDT 24
Peak memory 242048 kb
Host smart-4c220caf-182f-4729-a675-739f618ca0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372390358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.3372390358
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.1333860158
Short name T956
Test name
Test status
Simulation time 1034179990 ps
CPU time 17.33 seconds
Started Aug 06 05:34:10 PM PDT 24
Finished Aug 06 05:34:28 PM PDT 24
Peak memory 241864 kb
Host smart-27bb68ca-c66c-4604-9256-437fc66ad0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333860158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.1333860158
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.747854145
Short name T852
Test name
Test status
Simulation time 2241287682 ps
CPU time 3.91 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:11 PM PDT 24
Peak memory 242320 kb
Host smart-d16446b9-83af-4c2a-9afd-c75c6829f494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747854145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.747854145
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.3963214815
Short name T160
Test name
Test status
Simulation time 1987588963 ps
CPU time 31 seconds
Started Aug 06 05:34:25 PM PDT 24
Finished Aug 06 05:34:56 PM PDT 24
Peak memory 256872 kb
Host smart-754f0346-2391-43d1-8d32-67d9e8d74aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963214815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.3963214815
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.1397549963
Short name T897
Test name
Test status
Simulation time 2177812932 ps
CPU time 12.78 seconds
Started Aug 06 05:34:26 PM PDT 24
Finished Aug 06 05:34:39 PM PDT 24
Peak memory 242084 kb
Host smart-cc915b2d-c89b-4533-91e6-a7847bb1a11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397549963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.1397549963
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.2007907506
Short name T601
Test name
Test status
Simulation time 418537866 ps
CPU time 4.56 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:11 PM PDT 24
Peak memory 241936 kb
Host smart-0680937f-bc6f-4d12-9267-b168133b5878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007907506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.2007907506
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.4075946202
Short name T608
Test name
Test status
Simulation time 5976902954 ps
CPU time 14.54 seconds
Started Aug 06 05:34:06 PM PDT 24
Finished Aug 06 05:34:20 PM PDT 24
Peak memory 242408 kb
Host smart-2f9f837d-8790-497c-b7e6-d572350e53fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4075946202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.4075946202
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.1167805321
Short name T345
Test name
Test status
Simulation time 278109594 ps
CPU time 10.24 seconds
Started Aug 06 05:34:24 PM PDT 24
Finished Aug 06 05:34:34 PM PDT 24
Peak memory 241940 kb
Host smart-0740ffed-02ef-4208-8b18-b6dbfe90451e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167805321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.1167805321
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.3917927925
Short name T1108
Test name
Test status
Simulation time 1664840194 ps
CPU time 3.61 seconds
Started Aug 06 05:34:04 PM PDT 24
Finished Aug 06 05:34:08 PM PDT 24
Peak memory 246732 kb
Host smart-646562d9-d4fc-4167-9ab2-66297c4a7ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917927925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.3917927925
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.1231026339
Short name T935
Test name
Test status
Simulation time 914731724 ps
CPU time 27.4 seconds
Started Aug 06 05:34:27 PM PDT 24
Finished Aug 06 05:34:55 PM PDT 24
Peak memory 242360 kb
Host smart-2e824351-c523-4063-bf1c-9ae0922405d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231026339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.1231026339
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.122962741
Short name T381
Test name
Test status
Simulation time 1682377445 ps
CPU time 5.25 seconds
Started Aug 06 05:34:23 PM PDT 24
Finished Aug 06 05:34:29 PM PDT 24
Peak memory 242208 kb
Host smart-bd9dae2f-4180-4fa7-9d5a-0392c6fe3904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122962741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.122962741
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.1307624511
Short name T544
Test name
Test status
Simulation time 406800690 ps
CPU time 4.38 seconds
Started Aug 06 05:38:55 PM PDT 24
Finished Aug 06 05:38:59 PM PDT 24
Peak memory 242076 kb
Host smart-ddac8845-d7a5-4e9b-857d-52b34894f455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307624511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.1307624511
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.1481481122
Short name T629
Test name
Test status
Simulation time 96896377 ps
CPU time 3.36 seconds
Started Aug 06 05:38:57 PM PDT 24
Finished Aug 06 05:39:00 PM PDT 24
Peak memory 242056 kb
Host smart-b495d74f-f303-4c68-b9b9-1facfdc27d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481481122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.1481481122
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.2881394819
Short name T1154
Test name
Test status
Simulation time 325901986 ps
CPU time 4.19 seconds
Started Aug 06 05:39:05 PM PDT 24
Finished Aug 06 05:39:09 PM PDT 24
Peak memory 241972 kb
Host smart-56f3568e-53d1-4d86-91c0-108df38a2eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881394819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.2881394819
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.528656013
Short name T116
Test name
Test status
Simulation time 604714240 ps
CPU time 4.29 seconds
Started Aug 06 05:38:58 PM PDT 24
Finished Aug 06 05:39:02 PM PDT 24
Peak memory 241972 kb
Host smart-c859d791-b908-414a-b644-9e0766283695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528656013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.528656013
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.2810843790
Short name T954
Test name
Test status
Simulation time 376851721 ps
CPU time 3.72 seconds
Started Aug 06 05:39:01 PM PDT 24
Finished Aug 06 05:39:05 PM PDT 24
Peak memory 241972 kb
Host smart-a6136abd-94f2-4de1-8fcf-bbe1697aaae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810843790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2810843790
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.1325144030
Short name T689
Test name
Test status
Simulation time 318663987 ps
CPU time 4.43 seconds
Started Aug 06 05:39:02 PM PDT 24
Finished Aug 06 05:39:07 PM PDT 24
Peak memory 242140 kb
Host smart-31f97350-6418-4798-af17-5adcf35adc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325144030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.1325144030
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.3024534286
Short name T496
Test name
Test status
Simulation time 140982677 ps
CPU time 3.71 seconds
Started Aug 06 05:39:00 PM PDT 24
Finished Aug 06 05:39:03 PM PDT 24
Peak memory 242268 kb
Host smart-f8db19d5-019f-4160-b142-76573b0ac1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024534286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3024534286
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.943107484
Short name T1034
Test name
Test status
Simulation time 165406499 ps
CPU time 4.51 seconds
Started Aug 06 05:39:05 PM PDT 24
Finished Aug 06 05:39:10 PM PDT 24
Peak memory 242220 kb
Host smart-9319a4d2-d2be-4be8-af94-b55b9f8211c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943107484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.943107484
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.1917540317
Short name T220
Test name
Test status
Simulation time 614367709 ps
CPU time 4.52 seconds
Started Aug 06 05:39:04 PM PDT 24
Finished Aug 06 05:39:08 PM PDT 24
Peak memory 242224 kb
Host smart-7c6c477a-9740-4a60-9aec-50f4215682e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917540317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.1917540317
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.3354762198
Short name T762
Test name
Test status
Simulation time 2223579814 ps
CPU time 6.96 seconds
Started Aug 06 05:39:05 PM PDT 24
Finished Aug 06 05:39:12 PM PDT 24
Peak memory 241984 kb
Host smart-d9dc08be-ef6e-4e35-ab41-d95bb7d73393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354762198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.3354762198
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.3912874784
Short name T579
Test name
Test status
Simulation time 921066321 ps
CPU time 2.25 seconds
Started Aug 06 05:34:25 PM PDT 24
Finished Aug 06 05:34:27 PM PDT 24
Peak memory 240636 kb
Host smart-f7135788-42ca-4d7c-bd85-78260baef911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912874784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.3912874784
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.2708575438
Short name T451
Test name
Test status
Simulation time 785077706 ps
CPU time 9.22 seconds
Started Aug 06 05:34:29 PM PDT 24
Finished Aug 06 05:34:38 PM PDT 24
Peak memory 242400 kb
Host smart-9968947a-b0a7-464f-937d-d44c1bd62ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708575438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.2708575438
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.2357379673
Short name T1050
Test name
Test status
Simulation time 1148985451 ps
CPU time 22.19 seconds
Started Aug 06 05:34:22 PM PDT 24
Finished Aug 06 05:34:44 PM PDT 24
Peak memory 241968 kb
Host smart-af8c6467-a64f-4c68-94cd-0d7e52504e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357379673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.2357379673
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.4086933942
Short name T895
Test name
Test status
Simulation time 2508904286 ps
CPU time 40.33 seconds
Started Aug 06 05:34:28 PM PDT 24
Finished Aug 06 05:35:08 PM PDT 24
Peak memory 248648 kb
Host smart-614aa846-527a-4ce6-bc7b-09a31c4e546b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086933942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.4086933942
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.1169215092
Short name T227
Test name
Test status
Simulation time 287343401 ps
CPU time 3.96 seconds
Started Aug 06 05:34:23 PM PDT 24
Finished Aug 06 05:34:27 PM PDT 24
Peak memory 241940 kb
Host smart-043a9870-a951-4106-be46-53ba3e99eb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169215092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.1169215092
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.2300497322
Short name T164
Test name
Test status
Simulation time 663065554 ps
CPU time 16.94 seconds
Started Aug 06 05:34:23 PM PDT 24
Finished Aug 06 05:34:40 PM PDT 24
Peak memory 248648 kb
Host smart-33617247-ecc7-401c-873e-be51b49cf282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300497322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.2300497322
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.540323259
Short name T410
Test name
Test status
Simulation time 703022916 ps
CPU time 28.51 seconds
Started Aug 06 05:34:25 PM PDT 24
Finished Aug 06 05:34:53 PM PDT 24
Peak memory 248644 kb
Host smart-ee2dd83d-3b98-4590-817a-891ad53ce3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540323259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.540323259
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.3818993087
Short name T418
Test name
Test status
Simulation time 280411868 ps
CPU time 5.65 seconds
Started Aug 06 05:34:23 PM PDT 24
Finished Aug 06 05:34:29 PM PDT 24
Peak memory 241788 kb
Host smart-d4e1b29e-3e23-42cf-9c47-926e1c531369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818993087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.3818993087
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.1427660792
Short name T850
Test name
Test status
Simulation time 408180102 ps
CPU time 11.17 seconds
Started Aug 06 05:34:29 PM PDT 24
Finished Aug 06 05:34:40 PM PDT 24
Peak memory 242172 kb
Host smart-ba9f4c20-8282-4fd1-838b-95b21c8d3481
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1427660792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.1427660792
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.3064572131
Short name T196
Test name
Test status
Simulation time 416751749 ps
CPU time 5.77 seconds
Started Aug 06 05:34:23 PM PDT 24
Finished Aug 06 05:34:29 PM PDT 24
Peak memory 242196 kb
Host smart-6399cd28-928f-4771-be5b-fbcf7bda29f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3064572131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.3064572131
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.269557221
Short name T1079
Test name
Test status
Simulation time 220375130 ps
CPU time 4.83 seconds
Started Aug 06 05:34:23 PM PDT 24
Finished Aug 06 05:34:27 PM PDT 24
Peak memory 248416 kb
Host smart-20bf35e8-9c63-4674-b330-03a68aa2ea67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269557221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.269557221
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.3029803338
Short name T658
Test name
Test status
Simulation time 809140310 ps
CPU time 8.87 seconds
Started Aug 06 05:34:23 PM PDT 24
Finished Aug 06 05:34:32 PM PDT 24
Peak memory 242404 kb
Host smart-792ed2c8-f102-4383-9cea-09b1b65bca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029803338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.3029803338
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.3247902848
Short name T429
Test name
Test status
Simulation time 1396021206 ps
CPU time 4.42 seconds
Started Aug 06 05:38:56 PM PDT 24
Finished Aug 06 05:39:01 PM PDT 24
Peak memory 242300 kb
Host smart-7d36d1ce-32d2-439b-9e1c-b3e9f1bc418b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247902848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3247902848
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.1664171638
Short name T406
Test name
Test status
Simulation time 263955152 ps
CPU time 4.03 seconds
Started Aug 06 05:38:56 PM PDT 24
Finished Aug 06 05:39:00 PM PDT 24
Peak memory 241832 kb
Host smart-1a3f8825-685c-422d-b263-a0374302f72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664171638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.1664171638
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.3742132911
Short name T883
Test name
Test status
Simulation time 155041588 ps
CPU time 4.49 seconds
Started Aug 06 05:39:06 PM PDT 24
Finished Aug 06 05:39:10 PM PDT 24
Peak memory 241852 kb
Host smart-480a8cff-238b-4c33-b337-f23886f1d8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742132911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.3742132911
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.1870162758
Short name T445
Test name
Test status
Simulation time 277195958 ps
CPU time 4.15 seconds
Started Aug 06 05:39:05 PM PDT 24
Finished Aug 06 05:39:10 PM PDT 24
Peak memory 242388 kb
Host smart-7bc2533f-e73c-4c9b-867a-b6dbcac75262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870162758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1870162758
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.2924563803
Short name T1078
Test name
Test status
Simulation time 2097387152 ps
CPU time 5.29 seconds
Started Aug 06 05:38:56 PM PDT 24
Finished Aug 06 05:39:01 PM PDT 24
Peak memory 241984 kb
Host smart-2affdf4e-8505-46cc-b07f-5e5fe219b036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924563803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.2924563803
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.3323671952
Short name T8
Test name
Test status
Simulation time 161784446 ps
CPU time 4.1 seconds
Started Aug 06 05:39:09 PM PDT 24
Finished Aug 06 05:39:13 PM PDT 24
Peak memory 242012 kb
Host smart-8f451128-5a6c-45b8-b466-a962b34f800c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323671952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.3323671952
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.1989729254
Short name T693
Test name
Test status
Simulation time 2254360040 ps
CPU time 5.11 seconds
Started Aug 06 05:39:12 PM PDT 24
Finished Aug 06 05:39:17 PM PDT 24
Peak memory 242116 kb
Host smart-a6f64223-631a-4ddf-a38e-2f0b163e6ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989729254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.1989729254
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.1329852367
Short name T61
Test name
Test status
Simulation time 249218387 ps
CPU time 3.58 seconds
Started Aug 06 05:39:10 PM PDT 24
Finished Aug 06 05:39:14 PM PDT 24
Peak memory 242260 kb
Host smart-82dba42c-43f0-4203-b369-35eca5cd2b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329852367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.1329852367
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.101960436
Short name T1140
Test name
Test status
Simulation time 2428467692 ps
CPU time 6.17 seconds
Started Aug 06 05:39:10 PM PDT 24
Finished Aug 06 05:39:16 PM PDT 24
Peak memory 242232 kb
Host smart-5639af11-f95d-427e-910c-089461d654fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101960436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.101960436
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.4223317093
Short name T1153
Test name
Test status
Simulation time 550152010 ps
CPU time 4.36 seconds
Started Aug 06 05:39:09 PM PDT 24
Finished Aug 06 05:39:14 PM PDT 24
Peak memory 242180 kb
Host smart-af1f0fe9-d081-40dc-80d2-0afc5d25817d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223317093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.4223317093
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.3506550578
Short name T828
Test name
Test status
Simulation time 55331675 ps
CPU time 1.74 seconds
Started Aug 06 05:34:29 PM PDT 24
Finished Aug 06 05:34:31 PM PDT 24
Peak memory 240912 kb
Host smart-195619c4-ebbb-45cf-87fd-dc39bd609ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506550578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3506550578
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.4067509570
Short name T1043
Test name
Test status
Simulation time 719101124 ps
CPU time 14.66 seconds
Started Aug 06 05:34:25 PM PDT 24
Finished Aug 06 05:34:40 PM PDT 24
Peak memory 241940 kb
Host smart-d11dacb2-7deb-4f88-8eb1-c42cfc8f6968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067509570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.4067509570
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.2816202210
Short name T1082
Test name
Test status
Simulation time 344079549 ps
CPU time 10.37 seconds
Started Aug 06 05:34:25 PM PDT 24
Finished Aug 06 05:34:35 PM PDT 24
Peak memory 242012 kb
Host smart-e9638f6c-493b-4211-b49f-3946f0d5e4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816202210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.2816202210
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.3630844117
Short name T556
Test name
Test status
Simulation time 100427593 ps
CPU time 4.16 seconds
Started Aug 06 05:34:24 PM PDT 24
Finished Aug 06 05:34:29 PM PDT 24
Peak memory 241964 kb
Host smart-ab906ab4-1d16-4ab2-94b6-86317599e9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630844117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3630844117
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.2766854764
Short name T768
Test name
Test status
Simulation time 471276687 ps
CPU time 10.63 seconds
Started Aug 06 05:34:28 PM PDT 24
Finished Aug 06 05:34:38 PM PDT 24
Peak memory 242252 kb
Host smart-960b4973-7d66-4608-a9e7-6999b0d8eb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766854764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.2766854764
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.107679173
Short name T1028
Test name
Test status
Simulation time 186288824 ps
CPU time 4.21 seconds
Started Aug 06 05:34:22 PM PDT 24
Finished Aug 06 05:34:26 PM PDT 24
Peak memory 242020 kb
Host smart-93be604b-afa3-4d42-9d8c-c229c79bbf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107679173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.107679173
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.1266348983
Short name T1006
Test name
Test status
Simulation time 512313541 ps
CPU time 8.17 seconds
Started Aug 06 05:34:26 PM PDT 24
Finished Aug 06 05:34:35 PM PDT 24
Peak memory 241816 kb
Host smart-30505125-c303-43b3-9f25-09adc4b43b18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1266348983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1266348983
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.1761544371
Short name T2
Test name
Test status
Simulation time 1242210367 ps
CPU time 10.7 seconds
Started Aug 06 05:34:25 PM PDT 24
Finished Aug 06 05:34:36 PM PDT 24
Peak memory 241840 kb
Host smart-16bde52d-99b1-48d9-b9c7-a1d5f082564d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761544371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.1761544371
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.2142586841
Short name T483
Test name
Test status
Simulation time 1169880573 ps
CPU time 11.19 seconds
Started Aug 06 05:34:24 PM PDT 24
Finished Aug 06 05:34:35 PM PDT 24
Peak memory 242156 kb
Host smart-1c09926b-59a6-4730-9c69-901b65b6df92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142586841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.2142586841
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.91268975
Short name T701
Test name
Test status
Simulation time 15105678504 ps
CPU time 168.05 seconds
Started Aug 06 05:34:29 PM PDT 24
Finished Aug 06 05:37:17 PM PDT 24
Peak memory 248864 kb
Host smart-0482c8f7-a587-42a7-9357-79ff472eaffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91268975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.91268975
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.3117464200
Short name T873
Test name
Test status
Simulation time 442602970453 ps
CPU time 873.98 seconds
Started Aug 06 05:34:22 PM PDT 24
Finished Aug 06 05:48:56 PM PDT 24
Peak memory 257988 kb
Host smart-448f9f8b-f6bb-4e6d-9c8c-b29218dee215
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117464200 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.3117464200
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.3097059604
Short name T1098
Test name
Test status
Simulation time 267031542 ps
CPU time 4.44 seconds
Started Aug 06 05:34:25 PM PDT 24
Finished Aug 06 05:34:30 PM PDT 24
Peak memory 242120 kb
Host smart-8525a7dc-c81e-48c9-8280-41a5cf7518a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097059604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.3097059604
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.381308912
Short name T1077
Test name
Test status
Simulation time 2718655792 ps
CPU time 8.49 seconds
Started Aug 06 05:39:10 PM PDT 24
Finished Aug 06 05:39:19 PM PDT 24
Peak memory 242288 kb
Host smart-d81095d4-a261-4274-9436-04a03df55b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381308912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.381308912
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.1138091095
Short name T989
Test name
Test status
Simulation time 187784552 ps
CPU time 4.06 seconds
Started Aug 06 05:39:11 PM PDT 24
Finished Aug 06 05:39:15 PM PDT 24
Peak memory 242196 kb
Host smart-6f694f59-4635-4b21-8928-942f77ea82ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138091095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.1138091095
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.1929856168
Short name T462
Test name
Test status
Simulation time 164077812 ps
CPU time 5.06 seconds
Started Aug 06 05:39:12 PM PDT 24
Finished Aug 06 05:39:17 PM PDT 24
Peak memory 242048 kb
Host smart-01519888-1857-4c18-90a1-32cdf30443d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929856168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.1929856168
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.3875239355
Short name T436
Test name
Test status
Simulation time 270785180 ps
CPU time 3.88 seconds
Started Aug 06 05:39:09 PM PDT 24
Finished Aug 06 05:39:13 PM PDT 24
Peak memory 242348 kb
Host smart-81025734-b306-494e-ac49-cbb23b923f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875239355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.3875239355
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.1583547717
Short name T709
Test name
Test status
Simulation time 1393048796 ps
CPU time 4.35 seconds
Started Aug 06 05:39:10 PM PDT 24
Finished Aug 06 05:39:14 PM PDT 24
Peak memory 242000 kb
Host smart-78bf0e70-ae38-4570-a369-d9e92587281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583547717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.1583547717
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.772648044
Short name T1048
Test name
Test status
Simulation time 117438771 ps
CPU time 3.2 seconds
Started Aug 06 05:39:06 PM PDT 24
Finished Aug 06 05:39:10 PM PDT 24
Peak memory 242024 kb
Host smart-f1fd418a-5fb0-4fb0-9755-0c9989faf831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772648044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.772648044
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.2525289807
Short name T168
Test name
Test status
Simulation time 1983126573 ps
CPU time 3.89 seconds
Started Aug 06 05:39:09 PM PDT 24
Finished Aug 06 05:39:13 PM PDT 24
Peak memory 242288 kb
Host smart-513a5263-9787-4611-ab47-f44cd0296afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525289807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.2525289807
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.3309635348
Short name T486
Test name
Test status
Simulation time 621839152 ps
CPU time 6.59 seconds
Started Aug 06 05:39:09 PM PDT 24
Finished Aug 06 05:39:16 PM PDT 24
Peak memory 241984 kb
Host smart-51bf8d6b-bd2c-4b3c-9cda-43bd9032920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309635348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.3309635348
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.1567494644
Short name T450
Test name
Test status
Simulation time 146406413 ps
CPU time 3.96 seconds
Started Aug 06 05:39:11 PM PDT 24
Finished Aug 06 05:39:15 PM PDT 24
Peak memory 241888 kb
Host smart-15f75e6c-835c-41dd-bb44-b92b6dde1d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567494644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.1567494644
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.3978697840
Short name T1110
Test name
Test status
Simulation time 504391046 ps
CPU time 4.19 seconds
Started Aug 06 05:39:09 PM PDT 24
Finished Aug 06 05:39:13 PM PDT 24
Peak memory 241960 kb
Host smart-64f58c9f-1f2b-4751-8452-81117efa2b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978697840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.3978697840
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.1682073408
Short name T648
Test name
Test status
Simulation time 680409214 ps
CPU time 2.07 seconds
Started Aug 06 05:31:29 PM PDT 24
Finished Aug 06 05:31:31 PM PDT 24
Peak memory 239616 kb
Host smart-8e52541f-4032-4c0d-b50b-4fc169fa824d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682073408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1682073408
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.982811669
Short name T1124
Test name
Test status
Simulation time 980970570 ps
CPU time 23.42 seconds
Started Aug 06 05:31:28 PM PDT 24
Finished Aug 06 05:31:52 PM PDT 24
Peak memory 242404 kb
Host smart-29c9b2e6-c9f9-471c-9660-3e92c03cd634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982811669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.982811669
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1932233808
Short name T513
Test name
Test status
Simulation time 3332099893 ps
CPU time 6.4 seconds
Started Aug 06 05:31:28 PM PDT 24
Finished Aug 06 05:31:35 PM PDT 24
Peak memory 248472 kb
Host smart-22b6be01-b1ab-4688-9846-c32e3f79ef85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932233808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1932233808
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.1048538076
Short name T839
Test name
Test status
Simulation time 1774869521 ps
CPU time 19.64 seconds
Started Aug 06 05:31:30 PM PDT 24
Finished Aug 06 05:31:50 PM PDT 24
Peak memory 241952 kb
Host smart-7c4c586f-f7d6-4e53-8f0c-9167b1c940a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048538076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.1048538076
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.3841819008
Short name T364
Test name
Test status
Simulation time 18178924655 ps
CPU time 34.01 seconds
Started Aug 06 05:31:29 PM PDT 24
Finished Aug 06 05:32:03 PM PDT 24
Peak memory 242804 kb
Host smart-79ec90da-0c72-4f92-9e07-849221e6cf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841819008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.3841819008
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.2099796431
Short name T31
Test name
Test status
Simulation time 261950011 ps
CPU time 4.22 seconds
Started Aug 06 05:31:28 PM PDT 24
Finished Aug 06 05:31:33 PM PDT 24
Peak memory 241880 kb
Host smart-476093d7-5b15-4d9d-805e-479101ed54f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099796431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.2099796431
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.1041559059
Short name T997
Test name
Test status
Simulation time 478058123 ps
CPU time 4.2 seconds
Started Aug 06 05:31:28 PM PDT 24
Finished Aug 06 05:31:33 PM PDT 24
Peak memory 242024 kb
Host smart-eb122088-b839-4e1d-a060-9145c4c4b016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041559059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.1041559059
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.1475714210
Short name T1105
Test name
Test status
Simulation time 997502950 ps
CPU time 17.51 seconds
Started Aug 06 05:31:31 PM PDT 24
Finished Aug 06 05:31:48 PM PDT 24
Peak memory 241900 kb
Host smart-0fb0322b-1b51-40e1-a913-ae1bf5c3d958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475714210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.1475714210
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.2746222990
Short name T363
Test name
Test status
Simulation time 745040115 ps
CPU time 19.53 seconds
Started Aug 06 05:31:29 PM PDT 24
Finished Aug 06 05:31:48 PM PDT 24
Peak memory 242200 kb
Host smart-a64a4e94-9c94-4b46-aa6c-1e38c6be3fbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746222990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.2746222990
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.3139072349
Short name T377
Test name
Test status
Simulation time 1990189526 ps
CPU time 5.33 seconds
Started Aug 06 05:31:31 PM PDT 24
Finished Aug 06 05:31:37 PM PDT 24
Peak memory 241912 kb
Host smart-64b49d3c-eeff-4513-9385-feb0d27d64a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3139072349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3139072349
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.2691049717
Short name T738
Test name
Test status
Simulation time 530189955 ps
CPU time 9.74 seconds
Started Aug 06 05:31:29 PM PDT 24
Finished Aug 06 05:31:39 PM PDT 24
Peak memory 241972 kb
Host smart-8b155325-af53-42d7-be73-295dd748fd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691049717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2691049717
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.104364042
Short name T373
Test name
Test status
Simulation time 17925542660 ps
CPU time 109.98 seconds
Started Aug 06 05:31:29 PM PDT 24
Finished Aug 06 05:33:19 PM PDT 24
Peak memory 258100 kb
Host smart-ec8d7e70-53ba-4d9c-bd6d-b669d1944711
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104364042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.104364042
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.1057867238
Short name T786
Test name
Test status
Simulation time 633132684 ps
CPU time 15.59 seconds
Started Aug 06 05:31:28 PM PDT 24
Finished Aug 06 05:31:44 PM PDT 24
Peak memory 242020 kb
Host smart-c5681916-d3d3-4e55-8297-32b53944437f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057867238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.1057867238
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.2458789743
Short name T179
Test name
Test status
Simulation time 92080321 ps
CPU time 1.66 seconds
Started Aug 06 05:34:39 PM PDT 24
Finished Aug 06 05:34:40 PM PDT 24
Peak memory 240468 kb
Host smart-ec547e87-af9d-4cd6-afa9-51d0e9f7bd6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458789743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.2458789743
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.2838530046
Short name T1059
Test name
Test status
Simulation time 2573309888 ps
CPU time 27.85 seconds
Started Aug 06 05:34:29 PM PDT 24
Finished Aug 06 05:34:57 PM PDT 24
Peak memory 244900 kb
Host smart-0132e306-b3f8-4f80-838f-5e97b3a6e411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838530046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.2838530046
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.2432826523
Short name T1042
Test name
Test status
Simulation time 283927828 ps
CPU time 18.51 seconds
Started Aug 06 05:34:22 PM PDT 24
Finished Aug 06 05:34:41 PM PDT 24
Peak memory 241900 kb
Host smart-b8aaf73c-49a1-4396-a10d-31a0e2b19d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432826523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.2432826523
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.239784513
Short name T1182
Test name
Test status
Simulation time 422108889 ps
CPU time 6 seconds
Started Aug 06 05:34:22 PM PDT 24
Finished Aug 06 05:34:28 PM PDT 24
Peak memory 242312 kb
Host smart-8830dfab-b2d1-4345-8ffb-65ef73ada0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239784513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.239784513
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.1228990876
Short name T222
Test name
Test status
Simulation time 141808037 ps
CPU time 3.77 seconds
Started Aug 06 05:34:32 PM PDT 24
Finished Aug 06 05:34:36 PM PDT 24
Peak memory 242180 kb
Host smart-8775fa0f-7e05-44c5-91e5-c2071a575df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228990876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1228990876
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.2943946870
Short name T188
Test name
Test status
Simulation time 1213847757 ps
CPU time 21.35 seconds
Started Aug 06 05:34:22 PM PDT 24
Finished Aug 06 05:34:43 PM PDT 24
Peak memory 243968 kb
Host smart-a9bad334-0782-4f20-95f4-2e0e1e34cbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943946870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.2943946870
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.3820137772
Short name T666
Test name
Test status
Simulation time 725122949 ps
CPU time 25.96 seconds
Started Aug 06 05:34:22 PM PDT 24
Finished Aug 06 05:34:48 PM PDT 24
Peak memory 241968 kb
Host smart-da7a6db2-7db3-48e3-b6bd-043a5b8785bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820137772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.3820137772
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.1099536145
Short name T639
Test name
Test status
Simulation time 193422437 ps
CPU time 4.69 seconds
Started Aug 06 05:34:25 PM PDT 24
Finished Aug 06 05:34:29 PM PDT 24
Peak memory 241708 kb
Host smart-f65e0855-5a8c-4b7c-a41b-7fd14e94e21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099536145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.1099536145
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.243842736
Short name T180
Test name
Test status
Simulation time 1139719096 ps
CPU time 17.42 seconds
Started Aug 06 05:34:29 PM PDT 24
Finished Aug 06 05:34:47 PM PDT 24
Peak memory 241952 kb
Host smart-c9f98f53-a0cc-412c-a728-c1b4811b58a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=243842736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.243842736
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.3641710492
Short name T1033
Test name
Test status
Simulation time 180173076 ps
CPU time 5.26 seconds
Started Aug 06 05:34:22 PM PDT 24
Finished Aug 06 05:34:27 PM PDT 24
Peak memory 241928 kb
Host smart-90151bdb-6ad0-4221-b2c5-cf9f84d61418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3641710492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.3641710492
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.3724347158
Short name T1015
Test name
Test status
Simulation time 2084410635 ps
CPU time 13.31 seconds
Started Aug 06 05:34:25 PM PDT 24
Finished Aug 06 05:34:38 PM PDT 24
Peak memory 241936 kb
Host smart-9d8c9f56-8ec9-4291-ae06-6c07029f85cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724347158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.3724347158
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.419819130
Short name T575
Test name
Test status
Simulation time 2590095097 ps
CPU time 90.22 seconds
Started Aug 06 05:34:27 PM PDT 24
Finished Aug 06 05:35:57 PM PDT 24
Peak memory 246476 kb
Host smart-0c679f42-68c9-4f72-a1c2-b56c28eeb394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419819130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.
419819130
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.3881430575
Short name T920
Test name
Test status
Simulation time 6981361642 ps
CPU time 34.73 seconds
Started Aug 06 05:34:25 PM PDT 24
Finished Aug 06 05:35:00 PM PDT 24
Peak memory 242352 kb
Host smart-d2a3c13d-970d-4400-9bfc-4418cc4b8c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881430575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.3881430575
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.3771100594
Short name T628
Test name
Test status
Simulation time 310578226 ps
CPU time 3.12 seconds
Started Aug 06 05:34:43 PM PDT 24
Finished Aug 06 05:34:46 PM PDT 24
Peak memory 240484 kb
Host smart-84265b7f-1644-4b9b-9075-4bc580b00f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771100594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.3771100594
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.3193342534
Short name T45
Test name
Test status
Simulation time 3646749735 ps
CPU time 33.9 seconds
Started Aug 06 05:34:49 PM PDT 24
Finished Aug 06 05:35:23 PM PDT 24
Peak memory 242584 kb
Host smart-987cb7ab-b5e8-4146-90fe-a358bacfcf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193342534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3193342534
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.4061048234
Short name T386
Test name
Test status
Simulation time 883810861 ps
CPU time 29.77 seconds
Started Aug 06 05:34:40 PM PDT 24
Finished Aug 06 05:35:10 PM PDT 24
Peak memory 242264 kb
Host smart-089964af-3601-4269-9dfc-5b82e067e807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061048234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.4061048234
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.845359952
Short name T95
Test name
Test status
Simulation time 2551021623 ps
CPU time 14.38 seconds
Started Aug 06 05:34:40 PM PDT 24
Finished Aug 06 05:34:55 PM PDT 24
Peak memory 241912 kb
Host smart-a6ad88d3-7d95-465c-bd0b-a63b0e94282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845359952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.845359952
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.1702244566
Short name T473
Test name
Test status
Simulation time 123438736 ps
CPU time 3.61 seconds
Started Aug 06 05:34:46 PM PDT 24
Finished Aug 06 05:34:50 PM PDT 24
Peak memory 242028 kb
Host smart-2fa01664-597f-47cd-8ba1-1088758bb394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702244566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.1702244566
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.2963548679
Short name T224
Test name
Test status
Simulation time 2017911690 ps
CPU time 24.11 seconds
Started Aug 06 05:34:41 PM PDT 24
Finished Aug 06 05:35:06 PM PDT 24
Peak memory 248660 kb
Host smart-ec5a6f38-188d-47f2-974c-03f8a55b50bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963548679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2963548679
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.2646771987
Short name T1131
Test name
Test status
Simulation time 1139217116 ps
CPU time 20.24 seconds
Started Aug 06 05:34:40 PM PDT 24
Finished Aug 06 05:35:01 PM PDT 24
Peak memory 241800 kb
Host smart-fa643557-db26-4d38-b4c6-95c0457fdf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646771987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.2646771987
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.1436321739
Short name T1111
Test name
Test status
Simulation time 114697481 ps
CPU time 4.78 seconds
Started Aug 06 05:34:38 PM PDT 24
Finished Aug 06 05:34:43 PM PDT 24
Peak memory 242036 kb
Host smart-35df9e41-25e2-471c-9d47-beb262166555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436321739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1436321739
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.2751737498
Short name T732
Test name
Test status
Simulation time 678276944 ps
CPU time 23.73 seconds
Started Aug 06 05:34:40 PM PDT 24
Finished Aug 06 05:35:04 PM PDT 24
Peak memory 242104 kb
Host smart-f4b53b0b-5f07-40a5-afd9-6619dddc8660
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2751737498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.2751737498
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.2487566963
Short name T555
Test name
Test status
Simulation time 577736683 ps
CPU time 11.12 seconds
Started Aug 06 05:34:45 PM PDT 24
Finished Aug 06 05:34:56 PM PDT 24
Peak memory 248572 kb
Host smart-eff2254d-2a08-45c2-8c60-b7c8a56a5436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487566963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2487566963
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.3184736657
Short name T821
Test name
Test status
Simulation time 446904577 ps
CPU time 10.83 seconds
Started Aug 06 05:34:40 PM PDT 24
Finished Aug 06 05:34:51 PM PDT 24
Peak memory 241984 kb
Host smart-135fe8dc-497f-49f0-bbd0-264cd49b2ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184736657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3184736657
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.3698699660
Short name T894
Test name
Test status
Simulation time 68688906520 ps
CPU time 206.14 seconds
Started Aug 06 05:34:47 PM PDT 24
Finished Aug 06 05:38:13 PM PDT 24
Peak memory 249120 kb
Host smart-6668a23f-af0b-4d8f-8e75-ac48b4330c25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698699660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.3698699660
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.2276144557
Short name T307
Test name
Test status
Simulation time 197497092964 ps
CPU time 2565.58 seconds
Started Aug 06 05:34:46 PM PDT 24
Finished Aug 06 06:17:32 PM PDT 24
Peak memory 479440 kb
Host smart-005c2c3c-9fe7-413a-ae29-a698a7c9cb63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276144557 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.2276144557
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.344016058
Short name T459
Test name
Test status
Simulation time 1825869199 ps
CPU time 12.63 seconds
Started Aug 06 05:34:39 PM PDT 24
Finished Aug 06 05:34:52 PM PDT 24
Peak memory 241996 kb
Host smart-8ed2033f-3f90-4581-b526-469451d947c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344016058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.344016058
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.2016615276
Short name T844
Test name
Test status
Simulation time 235026385 ps
CPU time 2.03 seconds
Started Aug 06 05:34:46 PM PDT 24
Finished Aug 06 05:34:48 PM PDT 24
Peak memory 240476 kb
Host smart-84746b66-fe4a-4509-b60c-e1082941ef68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016615276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.2016615276
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.3637494346
Short name T60
Test name
Test status
Simulation time 915989547 ps
CPU time 27.73 seconds
Started Aug 06 05:34:42 PM PDT 24
Finished Aug 06 05:35:09 PM PDT 24
Peak memory 242344 kb
Host smart-f2b7c8d1-5d4b-4194-ab8c-11715d3c59b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637494346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.3637494346
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.3566305111
Short name T1106
Test name
Test status
Simulation time 761450436 ps
CPU time 22.05 seconds
Started Aug 06 05:34:38 PM PDT 24
Finished Aug 06 05:35:01 PM PDT 24
Peak memory 241896 kb
Host smart-24adac28-4e53-4e3c-8062-bf3ba2f1b59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566305111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.3566305111
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.2448266599
Short name T1176
Test name
Test status
Simulation time 476228239 ps
CPU time 15.28 seconds
Started Aug 06 05:34:45 PM PDT 24
Finished Aug 06 05:35:00 PM PDT 24
Peak memory 241960 kb
Host smart-250a3075-d6b8-4c12-942c-4f764aad0098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448266599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.2448266599
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.997205330
Short name T1162
Test name
Test status
Simulation time 196497474 ps
CPU time 3.82 seconds
Started Aug 06 05:34:49 PM PDT 24
Finished Aug 06 05:34:53 PM PDT 24
Peak memory 242032 kb
Host smart-160ecbcf-f54d-4224-8569-62e8af18300f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997205330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.997205330
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.4269147671
Short name T1114
Test name
Test status
Simulation time 1053652831 ps
CPU time 9.9 seconds
Started Aug 06 05:34:45 PM PDT 24
Finished Aug 06 05:34:55 PM PDT 24
Peak memory 242132 kb
Host smart-2e119577-fd5c-4ae3-a479-45d60cba56c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269147671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.4269147671
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.2016496485
Short name T984
Test name
Test status
Simulation time 5121244668 ps
CPU time 34.32 seconds
Started Aug 06 05:34:40 PM PDT 24
Finished Aug 06 05:35:15 PM PDT 24
Peak memory 242444 kb
Host smart-13a8f1f3-3e66-42a2-82ba-9daf689d3f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016496485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.2016496485
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.990488715
Short name T268
Test name
Test status
Simulation time 173530742 ps
CPU time 8.21 seconds
Started Aug 06 05:34:50 PM PDT 24
Finished Aug 06 05:34:59 PM PDT 24
Peak memory 241936 kb
Host smart-1893c522-0d92-4237-b2fc-9f1ffdbefeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990488715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.990488715
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.551725730
Short name T577
Test name
Test status
Simulation time 8245560824 ps
CPU time 21.57 seconds
Started Aug 06 05:34:49 PM PDT 24
Finished Aug 06 05:35:11 PM PDT 24
Peak memory 248708 kb
Host smart-4cedc1bf-87c3-4b00-aad4-e9b1b0196958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=551725730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.551725730
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.1570080952
Short name T493
Test name
Test status
Simulation time 537568624 ps
CPU time 5.5 seconds
Started Aug 06 05:34:46 PM PDT 24
Finished Aug 06 05:34:51 PM PDT 24
Peak memory 248552 kb
Host smart-5ed3aba5-b393-42de-ae0a-9dc019b0b908
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570080952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1570080952
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.675968779
Short name T979
Test name
Test status
Simulation time 306495365 ps
CPU time 12.07 seconds
Started Aug 06 05:34:39 PM PDT 24
Finished Aug 06 05:34:52 PM PDT 24
Peak memory 241904 kb
Host smart-f5e277e3-4da6-479b-a8ec-6e29e5990e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675968779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.675968779
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.2871000375
Short name T315
Test name
Test status
Simulation time 451767967706 ps
CPU time 767.05 seconds
Started Aug 06 05:34:39 PM PDT 24
Finished Aug 06 05:47:26 PM PDT 24
Peak memory 249136 kb
Host smart-3d57d7fb-00c3-4a5a-a3d8-dad94ebb5893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871000375 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.2871000375
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.815529513
Short name T785
Test name
Test status
Simulation time 2659060076 ps
CPU time 18.27 seconds
Started Aug 06 05:34:39 PM PDT 24
Finished Aug 06 05:34:57 PM PDT 24
Peak memory 248736 kb
Host smart-9fceaf3c-25aa-4b9e-9b4d-bc21eccc169c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815529513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.815529513
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.3303276349
Short name T560
Test name
Test status
Simulation time 63381771 ps
CPU time 1.91 seconds
Started Aug 06 05:35:00 PM PDT 24
Finished Aug 06 05:35:02 PM PDT 24
Peak memory 240460 kb
Host smart-704c04f3-4018-4f05-93a4-051329a13bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303276349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3303276349
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.3855289814
Short name T995
Test name
Test status
Simulation time 8008942329 ps
CPU time 22.97 seconds
Started Aug 06 05:34:40 PM PDT 24
Finished Aug 06 05:35:03 PM PDT 24
Peak memory 242692 kb
Host smart-e4a0e8c7-14cd-4e47-b824-2a6af6c1813f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855289814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.3855289814
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.4229270227
Short name T93
Test name
Test status
Simulation time 1289044323 ps
CPU time 10.13 seconds
Started Aug 06 05:34:40 PM PDT 24
Finished Aug 06 05:34:51 PM PDT 24
Peak memory 241912 kb
Host smart-abdf9c52-a630-49d2-8c57-9319110102c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229270227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.4229270227
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.1411890575
Short name T1149
Test name
Test status
Simulation time 1901379839 ps
CPU time 19.16 seconds
Started Aug 06 05:34:39 PM PDT 24
Finished Aug 06 05:34:58 PM PDT 24
Peak memory 242984 kb
Host smart-526e3383-d5a4-4527-87bc-7cfba4e8d363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411890575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.1411890575
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.389974949
Short name T592
Test name
Test status
Simulation time 130192801 ps
CPU time 3.57 seconds
Started Aug 06 05:34:43 PM PDT 24
Finished Aug 06 05:34:46 PM PDT 24
Peak memory 241976 kb
Host smart-bfbea2ef-5015-486b-9896-b7b73919da7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389974949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.389974949
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.3954661585
Short name T213
Test name
Test status
Simulation time 1916171348 ps
CPU time 12.28 seconds
Started Aug 06 05:34:42 PM PDT 24
Finished Aug 06 05:34:54 PM PDT 24
Peak memory 244176 kb
Host smart-c863897e-d76e-4700-910a-631a32de49f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954661585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.3954661585
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.4152825730
Short name T843
Test name
Test status
Simulation time 7861946413 ps
CPU time 30.98 seconds
Started Aug 06 05:34:40 PM PDT 24
Finished Aug 06 05:35:11 PM PDT 24
Peak memory 243464 kb
Host smart-bc863101-1845-4d02-b5bf-52aedb5de4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152825730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.4152825730
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.1777147553
Short name T266
Test name
Test status
Simulation time 173602031 ps
CPU time 5.5 seconds
Started Aug 06 05:34:39 PM PDT 24
Finished Aug 06 05:34:44 PM PDT 24
Peak memory 242344 kb
Host smart-dc8f5926-d478-42ae-82e9-10b784d2b484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777147553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.1777147553
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.2119714000
Short name T394
Test name
Test status
Simulation time 5447941077 ps
CPU time 14.16 seconds
Started Aug 06 05:34:40 PM PDT 24
Finished Aug 06 05:34:54 PM PDT 24
Peak memory 248688 kb
Host smart-0729f146-b5c6-4a12-9bcb-febee628f1f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119714000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.2119714000
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.1900863629
Short name T497
Test name
Test status
Simulation time 501016581 ps
CPU time 4.48 seconds
Started Aug 06 05:34:43 PM PDT 24
Finished Aug 06 05:34:48 PM PDT 24
Peak memory 242148 kb
Host smart-acbfb164-f98c-447b-b322-c3e123cee9a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900863629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.1900863629
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.507777540
Short name T1184
Test name
Test status
Simulation time 249370040 ps
CPU time 5.85 seconds
Started Aug 06 05:34:49 PM PDT 24
Finished Aug 06 05:34:55 PM PDT 24
Peak memory 242244 kb
Host smart-da99e39a-43c3-475d-a85c-eee0d750e4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507777540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.507777540
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.1493778552
Short name T981
Test name
Test status
Simulation time 43804353697 ps
CPU time 88.95 seconds
Started Aug 06 05:34:40 PM PDT 24
Finished Aug 06 05:36:09 PM PDT 24
Peak memory 262320 kb
Host smart-b5539026-4f55-47da-8d56-bd48e78a2ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493778552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.1493778552
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.1112596718
Short name T1035
Test name
Test status
Simulation time 156156738421 ps
CPU time 1274.89 seconds
Started Aug 06 05:34:49 PM PDT 24
Finished Aug 06 05:56:04 PM PDT 24
Peak memory 383372 kb
Host smart-98300bf9-1390-4759-8220-04d0f243357e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112596718 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.1112596718
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.3987040325
Short name T807
Test name
Test status
Simulation time 4485756725 ps
CPU time 30.98 seconds
Started Aug 06 05:34:41 PM PDT 24
Finished Aug 06 05:35:13 PM PDT 24
Peak memory 242636 kb
Host smart-67e0bf92-4953-4b21-afea-1cbcc07f6227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987040325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.3987040325
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.54533938
Short name T1000
Test name
Test status
Simulation time 90723833 ps
CPU time 1.69 seconds
Started Aug 06 05:35:01 PM PDT 24
Finished Aug 06 05:35:02 PM PDT 24
Peak memory 240672 kb
Host smart-9d6dd2d6-3e7e-4fce-8e64-197f909829db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54533938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.54533938
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.1248037970
Short name T912
Test name
Test status
Simulation time 806593106 ps
CPU time 8.28 seconds
Started Aug 06 05:35:01 PM PDT 24
Finished Aug 06 05:35:09 PM PDT 24
Peak memory 242224 kb
Host smart-94f8ec2a-0b55-413a-85b1-f30d712080f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248037970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1248037970
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.2497310137
Short name T553
Test name
Test status
Simulation time 374303478 ps
CPU time 9.61 seconds
Started Aug 06 05:35:01 PM PDT 24
Finished Aug 06 05:35:11 PM PDT 24
Peak memory 241900 kb
Host smart-953e3643-ba4b-42ca-8345-504cc4b43fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497310137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2497310137
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.3458929172
Short name T881
Test name
Test status
Simulation time 1976839609 ps
CPU time 11.51 seconds
Started Aug 06 05:35:02 PM PDT 24
Finished Aug 06 05:35:14 PM PDT 24
Peak memory 242452 kb
Host smart-f7a5c2e2-ed3b-46f1-88a3-b36e438d1727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458929172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3458929172
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.3762288408
Short name T487
Test name
Test status
Simulation time 206251521 ps
CPU time 3.51 seconds
Started Aug 06 05:35:01 PM PDT 24
Finished Aug 06 05:35:05 PM PDT 24
Peak memory 242172 kb
Host smart-7b13b829-7bfa-4349-81f7-20633c76fd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762288408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.3762288408
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.331379356
Short name T210
Test name
Test status
Simulation time 5529921174 ps
CPU time 25.56 seconds
Started Aug 06 05:35:01 PM PDT 24
Finished Aug 06 05:35:26 PM PDT 24
Peak memory 248592 kb
Host smart-94c87dde-78f7-4996-9ff4-d7262e0b6c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331379356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.331379356
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.3409353561
Short name T783
Test name
Test status
Simulation time 1406849956 ps
CPU time 36.09 seconds
Started Aug 06 05:35:04 PM PDT 24
Finished Aug 06 05:35:40 PM PDT 24
Peak memory 242080 kb
Host smart-c91d874b-b292-435e-aaed-43be6bd9ad80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409353561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3409353561
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.1156106886
Short name T372
Test name
Test status
Simulation time 739134632 ps
CPU time 23.01 seconds
Started Aug 06 05:35:01 PM PDT 24
Finished Aug 06 05:35:24 PM PDT 24
Peak memory 241880 kb
Host smart-79ec98b9-2678-4b2b-8bc2-a979f401f4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156106886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.1156106886
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.949871951
Short name T771
Test name
Test status
Simulation time 2647852396 ps
CPU time 29.77 seconds
Started Aug 06 05:35:01 PM PDT 24
Finished Aug 06 05:35:31 PM PDT 24
Peak memory 242188 kb
Host smart-e59babd9-1189-4261-9755-c611a0c9d9c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=949871951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.949871951
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.2758250096
Short name T395
Test name
Test status
Simulation time 588589031 ps
CPU time 5.4 seconds
Started Aug 06 05:35:01 PM PDT 24
Finished Aug 06 05:35:06 PM PDT 24
Peak memory 241880 kb
Host smart-f019980e-c66e-400b-b5d4-54638d263e6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758250096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2758250096
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.2619434799
Short name T216
Test name
Test status
Simulation time 195439296 ps
CPU time 2.94 seconds
Started Aug 06 05:35:03 PM PDT 24
Finished Aug 06 05:35:06 PM PDT 24
Peak memory 248200 kb
Host smart-5e3da476-e580-41ed-b148-2eda9dcc2f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619434799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.2619434799
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.3061996352
Short name T1014
Test name
Test status
Simulation time 80807005663 ps
CPU time 164.98 seconds
Started Aug 06 05:35:02 PM PDT 24
Finished Aug 06 05:37:47 PM PDT 24
Peak memory 248568 kb
Host smart-bb6e3fd7-2296-4411-9c95-8afe5c0f4415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061996352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.3061996352
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.64969180
Short name T528
Test name
Test status
Simulation time 838493011 ps
CPU time 15.37 seconds
Started Aug 06 05:35:07 PM PDT 24
Finished Aug 06 05:35:22 PM PDT 24
Peak memory 248480 kb
Host smart-8b74c49e-e362-42b9-b62f-cd0fe4d4ef12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64969180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.64969180
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.2099327659
Short name T229
Test name
Test status
Simulation time 225810006 ps
CPU time 1.98 seconds
Started Aug 06 05:35:04 PM PDT 24
Finished Aug 06 05:35:06 PM PDT 24
Peak memory 240432 kb
Host smart-f954bd69-4032-4bfd-b39b-c6d8093088a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099327659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2099327659
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.1465333295
Short name T39
Test name
Test status
Simulation time 579815839 ps
CPU time 13.07 seconds
Started Aug 06 05:35:05 PM PDT 24
Finished Aug 06 05:35:18 PM PDT 24
Peak memory 242232 kb
Host smart-faba3fd3-23a5-4ced-a36f-5456b2fe5a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465333295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.1465333295
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.430427640
Short name T564
Test name
Test status
Simulation time 1282878259 ps
CPU time 15.5 seconds
Started Aug 06 05:35:05 PM PDT 24
Finished Aug 06 05:35:21 PM PDT 24
Peak memory 241820 kb
Host smart-2f6423fb-9018-4697-943a-177ac6259b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430427640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.430427640
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.794986918
Short name T530
Test name
Test status
Simulation time 1062343364 ps
CPU time 9.78 seconds
Started Aug 06 05:35:04 PM PDT 24
Finished Aug 06 05:35:13 PM PDT 24
Peak memory 241944 kb
Host smart-253bda37-52ba-479d-bf51-800908620f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794986918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.794986918
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.4244552931
Short name T792
Test name
Test status
Simulation time 120743354 ps
CPU time 3.17 seconds
Started Aug 06 05:35:01 PM PDT 24
Finished Aug 06 05:35:05 PM PDT 24
Peak memory 242308 kb
Host smart-7da3492a-d0cb-4cd8-8b0a-5afc94a6f618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244552931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.4244552931
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.3656217332
Short name T866
Test name
Test status
Simulation time 1266170436 ps
CPU time 9.88 seconds
Started Aug 06 05:35:07 PM PDT 24
Finished Aug 06 05:35:17 PM PDT 24
Peak memory 242144 kb
Host smart-54c16ecf-98df-44fb-a704-c73e86a0a6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656217332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3656217332
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.2865234105
Short name T677
Test name
Test status
Simulation time 4456608220 ps
CPU time 32.56 seconds
Started Aug 06 05:35:02 PM PDT 24
Finished Aug 06 05:35:34 PM PDT 24
Peak memory 243760 kb
Host smart-b6185540-3c6f-4ead-9b89-4bdfdeaf76d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865234105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.2865234105
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.3298229110
Short name T402
Test name
Test status
Simulation time 577649112 ps
CPU time 4.47 seconds
Started Aug 06 05:34:59 PM PDT 24
Finished Aug 06 05:35:04 PM PDT 24
Peak memory 241952 kb
Host smart-59661936-b978-404c-8581-acd0eb3c14a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298229110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.3298229110
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.1265111583
Short name T494
Test name
Test status
Simulation time 816792644 ps
CPU time 22.85 seconds
Started Aug 06 05:35:00 PM PDT 24
Finished Aug 06 05:35:23 PM PDT 24
Peak memory 241876 kb
Host smart-439d8d54-b184-4cad-85e5-60addcdc11c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265111583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.1265111583
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.2585000146
Short name T854
Test name
Test status
Simulation time 100873338 ps
CPU time 3.05 seconds
Started Aug 06 05:35:03 PM PDT 24
Finished Aug 06 05:35:06 PM PDT 24
Peak memory 241884 kb
Host smart-95f51ebe-f949-4b77-8730-6c4c9d5d9314
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2585000146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.2585000146
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.3147448288
Short name T679
Test name
Test status
Simulation time 468343422 ps
CPU time 5.24 seconds
Started Aug 06 05:35:02 PM PDT 24
Finished Aug 06 05:35:07 PM PDT 24
Peak memory 242180 kb
Host smart-d4ee7391-13cd-40fc-8238-d36b73effafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147448288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.3147448288
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.1139536359
Short name T320
Test name
Test status
Simulation time 7792587801 ps
CPU time 69.45 seconds
Started Aug 06 05:35:03 PM PDT 24
Finished Aug 06 05:36:13 PM PDT 24
Peak memory 244552 kb
Host smart-cf632863-5887-4cc0-b525-671e7cf6b268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139536359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.1139536359
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.2920143282
Short name T960
Test name
Test status
Simulation time 288154930159 ps
CPU time 2183.08 seconds
Started Aug 06 05:35:05 PM PDT 24
Finished Aug 06 06:11:28 PM PDT 24
Peak memory 536016 kb
Host smart-c9474445-d8a0-4928-b0d8-5fc011989a36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920143282 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.2920143282
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.550157561
Short name T458
Test name
Test status
Simulation time 2147286980 ps
CPU time 20.73 seconds
Started Aug 06 05:35:07 PM PDT 24
Finished Aug 06 05:35:28 PM PDT 24
Peak memory 242220 kb
Host smart-7eec8e45-aca8-43d0-ba8f-4238bd6efc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550157561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.550157561
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.377677948
Short name T805
Test name
Test status
Simulation time 82328690 ps
CPU time 1.71 seconds
Started Aug 06 05:35:21 PM PDT 24
Finished Aug 06 05:35:22 PM PDT 24
Peak memory 240612 kb
Host smart-3589efff-dd0b-4559-b208-15f93f3b05bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377677948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.377677948
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.1065102960
Short name T37
Test name
Test status
Simulation time 773746310 ps
CPU time 11.71 seconds
Started Aug 06 05:35:20 PM PDT 24
Finished Aug 06 05:35:32 PM PDT 24
Peak memory 248612 kb
Host smart-47ebeeb5-7208-47f9-a81d-4d7cba9e5a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065102960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.1065102960
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.2629552562
Short name T1101
Test name
Test status
Simulation time 2197198927 ps
CPU time 36.33 seconds
Started Aug 06 05:35:00 PM PDT 24
Finished Aug 06 05:35:36 PM PDT 24
Peak memory 248336 kb
Host smart-86c9db00-f199-42e4-8ab1-af187ac0d808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629552562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.2629552562
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.2313964568
Short name T383
Test name
Test status
Simulation time 503546538 ps
CPU time 7.05 seconds
Started Aug 06 05:35:01 PM PDT 24
Finished Aug 06 05:35:09 PM PDT 24
Peak memory 242216 kb
Host smart-2dc617fa-69ee-4d1c-af07-f0e1068df376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313964568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.2313964568
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.3285570052
Short name T973
Test name
Test status
Simulation time 308666280 ps
CPU time 4.55 seconds
Started Aug 06 05:35:01 PM PDT 24
Finished Aug 06 05:35:06 PM PDT 24
Peak memory 241876 kb
Host smart-7c21db06-214a-472b-999e-e15c96fb42d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285570052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3285570052
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.1922922332
Short name T158
Test name
Test status
Simulation time 1796350371 ps
CPU time 27.97 seconds
Started Aug 06 05:35:22 PM PDT 24
Finished Aug 06 05:35:50 PM PDT 24
Peak memory 244308 kb
Host smart-144ae9f8-a5cb-4a8f-8ffe-a73c07d8565f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922922332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.1922922332
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.1512611446
Short name T248
Test name
Test status
Simulation time 653627961 ps
CPU time 16.17 seconds
Started Aug 06 05:35:19 PM PDT 24
Finished Aug 06 05:35:36 PM PDT 24
Peak memory 248552 kb
Host smart-8f0863ef-0ca6-433d-a63a-eb68b53c04ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512611446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1512611446
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.2146734914
Short name T933
Test name
Test status
Simulation time 216446527 ps
CPU time 5.95 seconds
Started Aug 06 05:35:03 PM PDT 24
Finished Aug 06 05:35:09 PM PDT 24
Peak memory 242216 kb
Host smart-96de2b0c-0227-4f69-a572-cf01a2eef378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146734914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.2146734914
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.3211870049
Short name T529
Test name
Test status
Simulation time 253515461 ps
CPU time 5.18 seconds
Started Aug 06 05:35:24 PM PDT 24
Finished Aug 06 05:35:30 PM PDT 24
Peak memory 242008 kb
Host smart-b562a39f-e1e7-4fda-abee-8314133ebf8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211870049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.3211870049
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.3839120963
Short name T682
Test name
Test status
Simulation time 3039913961 ps
CPU time 8.21 seconds
Started Aug 06 05:35:07 PM PDT 24
Finished Aug 06 05:35:15 PM PDT 24
Peak memory 248444 kb
Host smart-0bf6c154-8921-4793-94d7-475a8620ff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839120963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3839120963
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.1128210891
Short name T1175
Test name
Test status
Simulation time 7153996845 ps
CPU time 90.94 seconds
Started Aug 06 05:35:19 PM PDT 24
Finished Aug 06 05:36:50 PM PDT 24
Peak memory 248488 kb
Host smart-2c5deedb-8464-439d-af79-4dc508e82514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128210891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.1128210891
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.2640927850
Short name T285
Test name
Test status
Simulation time 825962184 ps
CPU time 16.21 seconds
Started Aug 06 05:35:22 PM PDT 24
Finished Aug 06 05:35:38 PM PDT 24
Peak memory 248560 kb
Host smart-03a39207-2ea3-4489-9c3c-01f496a7a224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640927850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.2640927850
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.1432051822
Short name T991
Test name
Test status
Simulation time 59346661 ps
CPU time 1.7 seconds
Started Aug 06 05:35:24 PM PDT 24
Finished Aug 06 05:35:26 PM PDT 24
Peak memory 240308 kb
Host smart-ad94dee8-05ed-4104-874a-890eba13590e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432051822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.1432051822
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.3412051922
Short name T84
Test name
Test status
Simulation time 6906480252 ps
CPU time 13.48 seconds
Started Aug 06 05:35:21 PM PDT 24
Finished Aug 06 05:35:34 PM PDT 24
Peak memory 242060 kb
Host smart-e262a994-d94a-4026-8e20-5b6b710e420c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412051922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.3412051922
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.3879961910
Short name T773
Test name
Test status
Simulation time 572112732 ps
CPU time 18.28 seconds
Started Aug 06 05:35:19 PM PDT 24
Finished Aug 06 05:35:38 PM PDT 24
Peak memory 241840 kb
Host smart-bf541c95-ed61-4303-8fa0-7a989c741fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879961910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.3879961910
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.626731402
Short name T965
Test name
Test status
Simulation time 466261434 ps
CPU time 8.94 seconds
Started Aug 06 05:35:20 PM PDT 24
Finished Aug 06 05:35:30 PM PDT 24
Peak memory 242236 kb
Host smart-9955c07f-d366-4361-9cdc-8c7689e14b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626731402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.626731402
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.2572077231
Short name T796
Test name
Test status
Simulation time 140488790 ps
CPU time 3.61 seconds
Started Aug 06 05:35:24 PM PDT 24
Finished Aug 06 05:35:27 PM PDT 24
Peak memory 242216 kb
Host smart-ed1d1a5e-0126-46e5-abdf-f0865a071b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572077231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2572077231
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.928086673
Short name T173
Test name
Test status
Simulation time 447820774 ps
CPU time 4.13 seconds
Started Aug 06 05:35:21 PM PDT 24
Finished Aug 06 05:35:25 PM PDT 24
Peak memory 242040 kb
Host smart-df2cf003-876f-4cf5-a4ab-e86cfef2b76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928086673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.928086673
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.3191570551
Short name T1137
Test name
Test status
Simulation time 1506890019 ps
CPU time 43.24 seconds
Started Aug 06 05:35:19 PM PDT 24
Finished Aug 06 05:36:03 PM PDT 24
Peak memory 241948 kb
Host smart-b111fb52-2609-4da3-b058-d1a020cc3062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191570551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.3191570551
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.1109739858
Short name T522
Test name
Test status
Simulation time 2852469632 ps
CPU time 11.39 seconds
Started Aug 06 05:35:23 PM PDT 24
Finished Aug 06 05:35:35 PM PDT 24
Peak memory 241888 kb
Host smart-a5be0c8e-6b8a-4000-919d-2350178329df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109739858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.1109739858
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.2127182645
Short name T1013
Test name
Test status
Simulation time 697236449 ps
CPU time 4.77 seconds
Started Aug 06 05:35:22 PM PDT 24
Finished Aug 06 05:35:26 PM PDT 24
Peak memory 241904 kb
Host smart-b6e44221-65cd-47c8-9066-e46107d0cad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2127182645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.2127182645
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.134730644
Short name T996
Test name
Test status
Simulation time 233837303 ps
CPU time 4.47 seconds
Started Aug 06 05:35:23 PM PDT 24
Finished Aug 06 05:35:27 PM PDT 24
Peak memory 242328 kb
Host smart-0ac237da-0dd7-4806-bdef-6fa38fafd4fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=134730644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.134730644
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.1253444531
Short name T1119
Test name
Test status
Simulation time 340028298 ps
CPU time 4.22 seconds
Started Aug 06 05:35:19 PM PDT 24
Finished Aug 06 05:35:23 PM PDT 24
Peak memory 242340 kb
Host smart-25e5ac3e-4969-4729-96ce-9748bfc95324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253444531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.1253444531
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.3279683719
Short name T1038
Test name
Test status
Simulation time 14289289144 ps
CPU time 157.63 seconds
Started Aug 06 05:35:19 PM PDT 24
Finished Aug 06 05:37:57 PM PDT 24
Peak memory 264996 kb
Host smart-1c290893-f3b4-455f-8746-8e517931bb77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279683719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.3279683719
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.1276703392
Short name T746
Test name
Test status
Simulation time 647467131 ps
CPU time 5.8 seconds
Started Aug 06 05:35:24 PM PDT 24
Finished Aug 06 05:35:30 PM PDT 24
Peak memory 241968 kb
Host smart-6854758a-0df5-47c7-b627-dc2696fbfc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276703392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.1276703392
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.826278468
Short name T906
Test name
Test status
Simulation time 807843634 ps
CPU time 1.97 seconds
Started Aug 06 05:35:21 PM PDT 24
Finished Aug 06 05:35:23 PM PDT 24
Peak memory 240884 kb
Host smart-c09a7a50-b448-482e-a707-02c353dab214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826278468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.826278468
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3041842279
Short name T736
Test name
Test status
Simulation time 545714733 ps
CPU time 14.75 seconds
Started Aug 06 05:35:24 PM PDT 24
Finished Aug 06 05:35:39 PM PDT 24
Peak memory 242556 kb
Host smart-d0ec2bfc-0c61-4249-a7ad-681fcad8815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041842279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3041842279
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.3540225423
Short name T231
Test name
Test status
Simulation time 339621353 ps
CPU time 20.66 seconds
Started Aug 06 05:35:20 PM PDT 24
Finished Aug 06 05:35:41 PM PDT 24
Peak memory 241940 kb
Host smart-5d8a2d34-0988-46b4-9ec1-0425a0d0f05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540225423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.3540225423
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.91618261
Short name T800
Test name
Test status
Simulation time 573329267 ps
CPU time 13.34 seconds
Started Aug 06 05:35:20 PM PDT 24
Finished Aug 06 05:35:33 PM PDT 24
Peak memory 241928 kb
Host smart-31bce8b3-a2b4-4c04-a6b4-8dc1d82a14e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91618261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.91618261
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.355250541
Short name T825
Test name
Test status
Simulation time 487731685 ps
CPU time 4.53 seconds
Started Aug 06 05:35:20 PM PDT 24
Finished Aug 06 05:35:24 PM PDT 24
Peak memory 242128 kb
Host smart-d1de5278-f9d2-47c6-8783-3376371b1085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355250541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.355250541
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.2002237921
Short name T464
Test name
Test status
Simulation time 469258644 ps
CPU time 10 seconds
Started Aug 06 05:35:22 PM PDT 24
Finished Aug 06 05:35:32 PM PDT 24
Peak memory 244812 kb
Host smart-a8b654e6-0a37-4837-920a-73c0dd56fa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002237921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.2002237921
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.331735883
Short name T756
Test name
Test status
Simulation time 887223135 ps
CPU time 27.5 seconds
Started Aug 06 05:35:24 PM PDT 24
Finished Aug 06 05:35:51 PM PDT 24
Peak memory 242360 kb
Host smart-4a3f92b7-c7a2-403a-b5fc-cee406e9b26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331735883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.331735883
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.2739073216
Short name T245
Test name
Test status
Simulation time 2082439073 ps
CPU time 19.37 seconds
Started Aug 06 05:35:20 PM PDT 24
Finished Aug 06 05:35:39 PM PDT 24
Peak memory 248668 kb
Host smart-0c5a8e7b-1561-462d-80a7-a8373e5266e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2739073216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.2739073216
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.3986513043
Short name T500
Test name
Test status
Simulation time 224859306 ps
CPU time 7.45 seconds
Started Aug 06 05:35:21 PM PDT 24
Finished Aug 06 05:35:29 PM PDT 24
Peak memory 241924 kb
Host smart-720accbb-68e5-47cd-9092-44d783aa51d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986513043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3986513043
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.1704585007
Short name T1172
Test name
Test status
Simulation time 4083616825 ps
CPU time 8.56 seconds
Started Aug 06 05:35:22 PM PDT 24
Finished Aug 06 05:35:30 PM PDT 24
Peak memory 241948 kb
Host smart-94a7b64c-e38b-4c90-a321-5aa5e253aba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704585007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1704585007
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.2190853349
Short name T1158
Test name
Test status
Simulation time 3249574867 ps
CPU time 33.34 seconds
Started Aug 06 05:35:23 PM PDT 24
Finished Aug 06 05:35:56 PM PDT 24
Peak memory 243512 kb
Host smart-c1ab78f2-b3bc-4678-bcac-4cc62243ffff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190853349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.2190853349
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.3644030951
Short name T288
Test name
Test status
Simulation time 71122747379 ps
CPU time 959.2 seconds
Started Aug 06 05:35:23 PM PDT 24
Finished Aug 06 05:51:22 PM PDT 24
Peak memory 302448 kb
Host smart-22e2fa26-d45d-47ad-8f55-0fd7853f45eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644030951 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.3644030951
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.1966857684
Short name T365
Test name
Test status
Simulation time 6483991548 ps
CPU time 13.88 seconds
Started Aug 06 05:35:22 PM PDT 24
Finished Aug 06 05:35:36 PM PDT 24
Peak memory 243264 kb
Host smart-ac60091c-db3b-42e9-ba7d-516c696463d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966857684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.1966857684
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.841508721
Short name T565
Test name
Test status
Simulation time 162676214 ps
CPU time 1.59 seconds
Started Aug 06 05:35:42 PM PDT 24
Finished Aug 06 05:35:44 PM PDT 24
Peak memory 240320 kb
Host smart-bffdd042-750b-4736-a569-6fe5ff53d9e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841508721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.841508721
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.591178730
Short name T508
Test name
Test status
Simulation time 319365515 ps
CPU time 4.04 seconds
Started Aug 06 05:35:24 PM PDT 24
Finished Aug 06 05:35:29 PM PDT 24
Peak memory 248484 kb
Host smart-99746491-e438-4fa4-ad4b-efaf07e18171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591178730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.591178730
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.3788102063
Short name T330
Test name
Test status
Simulation time 1945128472 ps
CPU time 20.5 seconds
Started Aug 06 05:35:23 PM PDT 24
Finished Aug 06 05:35:44 PM PDT 24
Peak memory 241916 kb
Host smart-165cce96-b865-4154-ad69-57b8cae90f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788102063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.3788102063
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.3492678413
Short name T827
Test name
Test status
Simulation time 836232467 ps
CPU time 12.54 seconds
Started Aug 06 05:35:23 PM PDT 24
Finished Aug 06 05:35:36 PM PDT 24
Peak memory 242336 kb
Host smart-ce50c711-00be-413e-a94c-60764132b9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492678413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.3492678413
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.3833857156
Short name T889
Test name
Test status
Simulation time 469551256 ps
CPU time 3.73 seconds
Started Aug 06 05:35:23 PM PDT 24
Finished Aug 06 05:35:27 PM PDT 24
Peak memory 242152 kb
Host smart-965ed38c-6fc3-42ce-880e-81a730d27859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833857156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.3833857156
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.806986800
Short name T1129
Test name
Test status
Simulation time 459523814 ps
CPU time 10.13 seconds
Started Aug 06 05:35:32 PM PDT 24
Finished Aug 06 05:35:42 PM PDT 24
Peak memory 242140 kb
Host smart-c4255f34-3bc8-4b51-91a4-b9913d2ea8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806986800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.806986800
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.2141438984
Short name T750
Test name
Test status
Simulation time 1891007845 ps
CPU time 24.99 seconds
Started Aug 06 05:35:23 PM PDT 24
Finished Aug 06 05:35:48 PM PDT 24
Peak memory 242192 kb
Host smart-a4b6151d-87f2-46f4-a2e0-f4d698a8177a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141438984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.2141438984
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.4172445111
Short name T699
Test name
Test status
Simulation time 427205075 ps
CPU time 4.6 seconds
Started Aug 06 05:35:25 PM PDT 24
Finished Aug 06 05:35:30 PM PDT 24
Peak memory 241948 kb
Host smart-6544aa72-0257-4bf7-a2cb-5d063554cdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172445111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.4172445111
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.2958166429
Short name T358
Test name
Test status
Simulation time 883979004 ps
CPU time 20.84 seconds
Started Aug 06 05:35:24 PM PDT 24
Finished Aug 06 05:35:46 PM PDT 24
Peak memory 242008 kb
Host smart-efd83b22-3656-4433-95ee-4904cb91fd1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2958166429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.2958166429
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.2057185066
Short name T1116
Test name
Test status
Simulation time 468220194 ps
CPU time 4.81 seconds
Started Aug 06 05:35:24 PM PDT 24
Finished Aug 06 05:35:29 PM PDT 24
Peak memory 241760 kb
Host smart-47f962e9-89e2-4116-b367-257b510b245d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057185066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.2057185066
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.2767158318
Short name T695
Test name
Test status
Simulation time 4555655426 ps
CPU time 8.83 seconds
Started Aug 06 05:35:22 PM PDT 24
Finished Aug 06 05:35:31 PM PDT 24
Peak memory 242416 kb
Host smart-db445fc6-060f-4938-a29d-2717b791a44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767158318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.2767158318
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.3040724518
Short name T1142
Test name
Test status
Simulation time 6010582176 ps
CPU time 47.25 seconds
Started Aug 06 05:35:44 PM PDT 24
Finished Aug 06 05:36:31 PM PDT 24
Peak memory 244148 kb
Host smart-49f18e96-83c1-4ed4-a804-09c65d5d955e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040724518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.3040724518
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.2446634600
Short name T313
Test name
Test status
Simulation time 60301762905 ps
CPU time 806.51 seconds
Started Aug 06 05:35:43 PM PDT 24
Finished Aug 06 05:49:09 PM PDT 24
Peak memory 330628 kb
Host smart-c501ae61-4f8f-46bb-b9ba-428e423026d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446634600 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.2446634600
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.2555111932
Short name T707
Test name
Test status
Simulation time 1966702217 ps
CPU time 21.55 seconds
Started Aug 06 05:35:51 PM PDT 24
Finished Aug 06 05:36:13 PM PDT 24
Peak memory 242440 kb
Host smart-57554758-6425-4612-8b60-0473520e17f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555111932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.2555111932
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.2288613393
Short name T230
Test name
Test status
Simulation time 247479169 ps
CPU time 1.83 seconds
Started Aug 06 05:31:48 PM PDT 24
Finished Aug 06 05:31:50 PM PDT 24
Peak memory 240716 kb
Host smart-90a150a5-025c-4589-b3e8-6240f3d49b5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288613393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.2288613393
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.4107103975
Short name T751
Test name
Test status
Simulation time 748499178 ps
CPU time 15.38 seconds
Started Aug 06 05:31:27 PM PDT 24
Finished Aug 06 05:31:43 PM PDT 24
Peak memory 248652 kb
Host smart-b9b64b9c-7571-4db1-b5e1-7f754eeb930b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107103975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.4107103975
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.1033499906
Short name T780
Test name
Test status
Simulation time 521268773 ps
CPU time 14.44 seconds
Started Aug 06 05:31:48 PM PDT 24
Finished Aug 06 05:32:02 PM PDT 24
Peak memory 242580 kb
Host smart-f2b246b0-1fd7-4815-961a-dd8f4d39f8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033499906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1033499906
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.457370573
Short name T329
Test name
Test status
Simulation time 2979990512 ps
CPU time 12.14 seconds
Started Aug 06 05:31:28 PM PDT 24
Finished Aug 06 05:31:40 PM PDT 24
Peak memory 242056 kb
Host smart-822c3cb1-5cc8-4a65-bcdc-185a78aa13dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457370573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.457370573
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.2915606374
Short name T233
Test name
Test status
Simulation time 12648843032 ps
CPU time 34.35 seconds
Started Aug 06 05:31:28 PM PDT 24
Finished Aug 06 05:32:03 PM PDT 24
Peak memory 243268 kb
Host smart-3155975f-1d67-4a97-9eef-ae0c0fd63149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915606374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.2915606374
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.1712708469
Short name T731
Test name
Test status
Simulation time 1671543439 ps
CPU time 4.15 seconds
Started Aug 06 05:31:28 PM PDT 24
Finished Aug 06 05:31:32 PM PDT 24
Peak memory 242388 kb
Host smart-0e759a2f-a7b8-464c-a49f-f43cac447d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712708469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.1712708469
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.3613332966
Short name T1056
Test name
Test status
Simulation time 850295440 ps
CPU time 24.3 seconds
Started Aug 06 05:31:44 PM PDT 24
Finished Aug 06 05:32:09 PM PDT 24
Peak memory 242324 kb
Host smart-8f3ebfcf-6c65-4422-a769-edd432dc3fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613332966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3613332966
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.4063066351
Short name T670
Test name
Test status
Simulation time 2087291114 ps
CPU time 10.07 seconds
Started Aug 06 05:31:29 PM PDT 24
Finished Aug 06 05:31:39 PM PDT 24
Peak memory 241832 kb
Host smart-c6e3156a-8ca7-45a6-af50-91e06ec02055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063066351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.4063066351
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.397682103
Short name T769
Test name
Test status
Simulation time 939345818 ps
CPU time 24.94 seconds
Started Aug 06 05:31:30 PM PDT 24
Finished Aug 06 05:31:55 PM PDT 24
Peak memory 241864 kb
Host smart-8e217225-f013-4e4d-856b-3d488d6f7976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=397682103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.397682103
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.3034701428
Short name T349
Test name
Test status
Simulation time 260415568 ps
CPU time 11.38 seconds
Started Aug 06 05:31:47 PM PDT 24
Finished Aug 06 05:31:58 PM PDT 24
Peak memory 248404 kb
Host smart-8f8c664e-c626-4af7-806d-2589b7547357
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3034701428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.3034701428
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.772781298
Short name T237
Test name
Test status
Simulation time 23979290351 ps
CPU time 190.08 seconds
Started Aug 06 05:31:47 PM PDT 24
Finished Aug 06 05:34:57 PM PDT 24
Peak memory 268132 kb
Host smart-2dfec66e-a3e6-4a12-a25a-b651f6752042
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772781298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.772781298
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.3710583053
Short name T949
Test name
Test status
Simulation time 928621854 ps
CPU time 7.32 seconds
Started Aug 06 05:31:29 PM PDT 24
Finished Aug 06 05:31:36 PM PDT 24
Peak memory 247680 kb
Host smart-5b2786c2-5a90-48ec-a433-60fa9d9df749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710583053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.3710583053
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.2439849982
Short name T35
Test name
Test status
Simulation time 1733424059 ps
CPU time 20.93 seconds
Started Aug 06 05:31:45 PM PDT 24
Finished Aug 06 05:32:06 PM PDT 24
Peak memory 242492 kb
Host smart-7bd0eaf8-8083-4f3a-a51c-0cdeffb1e7e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439849982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
2439849982
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.1931507339
Short name T20
Test name
Test status
Simulation time 2059420265556 ps
CPU time 2739.08 seconds
Started Aug 06 05:31:46 PM PDT 24
Finished Aug 06 06:17:26 PM PDT 24
Peak memory 265164 kb
Host smart-53a753ba-3269-4e86-9af9-fea89c3ead86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931507339 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.1931507339
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.794558565
Short name T584
Test name
Test status
Simulation time 1777816461 ps
CPU time 16.16 seconds
Started Aug 06 05:31:53 PM PDT 24
Finished Aug 06 05:32:09 PM PDT 24
Peak memory 241936 kb
Host smart-66fdd09d-41b6-480a-9032-dd0058f2655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794558565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.794558565
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.1269456254
Short name T392
Test name
Test status
Simulation time 343831308 ps
CPU time 2.08 seconds
Started Aug 06 05:35:47 PM PDT 24
Finished Aug 06 05:35:49 PM PDT 24
Peak memory 240540 kb
Host smart-b6c073d5-6aeb-44a7-a979-7108d2de795d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269456254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.1269456254
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.2790957777
Short name T70
Test name
Test status
Simulation time 1604796118 ps
CPU time 11.99 seconds
Started Aug 06 05:35:42 PM PDT 24
Finished Aug 06 05:35:54 PM PDT 24
Peak memory 244540 kb
Host smart-df75bcca-fe78-49e1-9dd2-9ddc3ab181f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790957777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.2790957777
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.2263595168
Short name T1073
Test name
Test status
Simulation time 1324067025 ps
CPU time 18.42 seconds
Started Aug 06 05:35:52 PM PDT 24
Finished Aug 06 05:36:10 PM PDT 24
Peak memory 242348 kb
Host smart-feaa8ae0-4ef6-4e9d-a936-78a3d47dfe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263595168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.2263595168
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.3323619523
Short name T748
Test name
Test status
Simulation time 402382852 ps
CPU time 7.18 seconds
Started Aug 06 05:35:41 PM PDT 24
Finished Aug 06 05:35:48 PM PDT 24
Peak memory 241852 kb
Host smart-ae749244-e7a3-4cfa-bfcd-a3d537e95817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323619523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.3323619523
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.1474665172
Short name T753
Test name
Test status
Simulation time 1533726267 ps
CPU time 3.98 seconds
Started Aug 06 05:35:41 PM PDT 24
Finished Aug 06 05:35:45 PM PDT 24
Peak memory 241828 kb
Host smart-667e5fc1-00cc-4e2c-b72b-45a52ce0991b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474665172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1474665172
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.1619693177
Short name T587
Test name
Test status
Simulation time 2478468615 ps
CPU time 51.94 seconds
Started Aug 06 05:35:40 PM PDT 24
Finished Aug 06 05:36:32 PM PDT 24
Peak memory 248516 kb
Host smart-508c1f29-0e50-4e57-97e5-2c221a7ea3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619693177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.1619693177
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.335854471
Short name T613
Test name
Test status
Simulation time 787004527 ps
CPU time 7.56 seconds
Started Aug 06 05:35:52 PM PDT 24
Finished Aug 06 05:36:00 PM PDT 24
Peak memory 248648 kb
Host smart-e4abb6bf-5b42-4cf4-987b-185b43d88544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335854471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.335854471
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.3506700907
Short name T987
Test name
Test status
Simulation time 228876341 ps
CPU time 5.03 seconds
Started Aug 06 05:35:40 PM PDT 24
Finished Aug 06 05:35:45 PM PDT 24
Peak memory 241736 kb
Host smart-4824fa03-4636-4638-924c-bf005c64a05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506700907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.3506700907
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.1302846953
Short name T369
Test name
Test status
Simulation time 5221036803 ps
CPU time 15.07 seconds
Started Aug 06 05:35:42 PM PDT 24
Finished Aug 06 05:35:57 PM PDT 24
Peak memory 248744 kb
Host smart-bee4a8c8-c717-447a-852d-dab4d2098322
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302846953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.1302846953
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.1335863112
Short name T708
Test name
Test status
Simulation time 679267285 ps
CPU time 6.65 seconds
Started Aug 06 05:35:42 PM PDT 24
Finished Aug 06 05:35:49 PM PDT 24
Peak memory 241892 kb
Host smart-7638de6e-264b-46d4-b985-b5cc68e6e734
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1335863112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.1335863112
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.4090325168
Short name T390
Test name
Test status
Simulation time 2264400328 ps
CPU time 4.29 seconds
Started Aug 06 05:35:41 PM PDT 24
Finished Aug 06 05:35:45 PM PDT 24
Peak memory 242048 kb
Host smart-401d9c81-f278-444d-aaae-0997041f5bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090325168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.4090325168
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.2272381706
Short name T958
Test name
Test status
Simulation time 20288559697 ps
CPU time 109.18 seconds
Started Aug 06 05:35:45 PM PDT 24
Finished Aug 06 05:37:34 PM PDT 24
Peak memory 248760 kb
Host smart-a41f2618-3231-45f3-9a82-365fe30aee16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272381706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.2272381706
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.3699519601
Short name T1094
Test name
Test status
Simulation time 3033962594 ps
CPU time 7.75 seconds
Started Aug 06 05:35:41 PM PDT 24
Finished Aug 06 05:35:49 PM PDT 24
Peak memory 242432 kb
Host smart-6114edbd-ac40-4112-977b-db817649a719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699519601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.3699519601
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.4290176548
Short name T940
Test name
Test status
Simulation time 119089300 ps
CPU time 1.77 seconds
Started Aug 06 05:35:47 PM PDT 24
Finished Aug 06 05:35:49 PM PDT 24
Peak memory 240808 kb
Host smart-7873b4ea-477e-4856-9fa3-290b09bdb3b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290176548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.4290176548
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.791083433
Short name T114
Test name
Test status
Simulation time 400372569 ps
CPU time 9.07 seconds
Started Aug 06 05:35:45 PM PDT 24
Finished Aug 06 05:35:54 PM PDT 24
Peak memory 248496 kb
Host smart-8e5bc897-d6dc-43a1-b432-ba784452d71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791083433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.791083433
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.2087011949
Short name T240
Test name
Test status
Simulation time 1644723957 ps
CPU time 24.11 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:27 PM PDT 24
Peak memory 242180 kb
Host smart-9b05d6e8-7efc-4cb6-bc02-5a40b3e6056b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087011949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.2087011949
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.2204515160
Short name T728
Test name
Test status
Simulation time 644042125 ps
CPU time 7.07 seconds
Started Aug 06 05:35:46 PM PDT 24
Finished Aug 06 05:35:53 PM PDT 24
Peak memory 242004 kb
Host smart-1ab8a130-7f4b-4285-8ad2-a54e0f93a532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204515160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.2204515160
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.3581682065
Short name T447
Test name
Test status
Simulation time 138594278 ps
CPU time 5.43 seconds
Started Aug 06 05:35:54 PM PDT 24
Finished Aug 06 05:35:59 PM PDT 24
Peak memory 242148 kb
Host smart-05416ebb-3213-4702-bada-96dc54ee8954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581682065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.3581682065
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.3670832271
Short name T221
Test name
Test status
Simulation time 3427884933 ps
CPU time 23.38 seconds
Started Aug 06 05:35:47 PM PDT 24
Finished Aug 06 05:36:11 PM PDT 24
Peak memory 248664 kb
Host smart-1332783e-0ca2-4b73-b142-6fe4eefe2a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670832271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.3670832271
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.1638925323
Short name T99
Test name
Test status
Simulation time 8207763785 ps
CPU time 37.69 seconds
Started Aug 06 05:35:58 PM PDT 24
Finished Aug 06 05:36:36 PM PDT 24
Peak memory 243636 kb
Host smart-88ded2dd-4c42-41bf-a8fb-673993a29d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638925323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1638925323
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.3431876844
Short name T583
Test name
Test status
Simulation time 137770452 ps
CPU time 6.65 seconds
Started Aug 06 05:35:44 PM PDT 24
Finished Aug 06 05:35:51 PM PDT 24
Peak memory 241756 kb
Host smart-c27c2b6c-03db-411e-bfed-132d62923d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431876844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.3431876844
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.2399064850
Short name T597
Test name
Test status
Simulation time 520435857 ps
CPU time 15.08 seconds
Started Aug 06 05:35:44 PM PDT 24
Finished Aug 06 05:35:59 PM PDT 24
Peak memory 242120 kb
Host smart-c888fcd7-afd8-4ec4-b703-46591830001c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399064850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.2399064850
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.2374632610
Short name T652
Test name
Test status
Simulation time 228724155 ps
CPU time 7.55 seconds
Started Aug 06 05:35:46 PM PDT 24
Finished Aug 06 05:35:53 PM PDT 24
Peak memory 248588 kb
Host smart-a652e742-9562-41dc-b113-d8ce831daeae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2374632610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.2374632610
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.512761556
Short name T972
Test name
Test status
Simulation time 688318713 ps
CPU time 4.73 seconds
Started Aug 06 05:35:47 PM PDT 24
Finished Aug 06 05:35:52 PM PDT 24
Peak memory 242020 kb
Host smart-a446c51b-9764-48e9-9eeb-095f1ec6fe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512761556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.512761556
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.3526702537
Short name T255
Test name
Test status
Simulation time 122121393582 ps
CPU time 234.06 seconds
Started Aug 06 05:36:05 PM PDT 24
Finished Aug 06 05:39:59 PM PDT 24
Peak memory 267416 kb
Host smart-43d194a2-8b96-4949-9b01-492129059b3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526702537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.3526702537
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.1595795792
Short name T280
Test name
Test status
Simulation time 9619876873 ps
CPU time 29.06 seconds
Started Aug 06 05:35:45 PM PDT 24
Finished Aug 06 05:36:15 PM PDT 24
Peak memory 242012 kb
Host smart-0f7a5a6e-98ec-499e-9212-80df8359425a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595795792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.1595795792
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.1383907766
Short name T374
Test name
Test status
Simulation time 201595546 ps
CPU time 1.96 seconds
Started Aug 06 05:35:59 PM PDT 24
Finished Aug 06 05:36:01 PM PDT 24
Peak memory 240492 kb
Host smart-91727adb-e0fc-48d2-b02d-8bd4a2b92107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383907766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.1383907766
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.3061910745
Short name T217
Test name
Test status
Simulation time 7137027802 ps
CPU time 16.36 seconds
Started Aug 06 05:35:57 PM PDT 24
Finished Aug 06 05:36:13 PM PDT 24
Peak memory 244100 kb
Host smart-e83f299f-6661-45e1-811c-a343d557f3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061910745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.3061910745
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.3652248795
Short name T232
Test name
Test status
Simulation time 703534231 ps
CPU time 9.48 seconds
Started Aug 06 05:35:54 PM PDT 24
Finished Aug 06 05:36:03 PM PDT 24
Peak memory 241928 kb
Host smart-a2133716-2cf0-48f1-978a-0595d7ea53e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652248795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.3652248795
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.1114282290
Short name T622
Test name
Test status
Simulation time 957448941 ps
CPU time 19.07 seconds
Started Aug 06 05:35:53 PM PDT 24
Finished Aug 06 05:36:12 PM PDT 24
Peak memory 248436 kb
Host smart-b9b55ff7-73c7-4d3a-a13f-4fec528bc265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114282290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.1114282290
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.3998190141
Short name T42
Test name
Test status
Simulation time 1556029527 ps
CPU time 6.23 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:08 PM PDT 24
Peak memory 242128 kb
Host smart-5a55d5e9-003c-4768-9968-aa4f9165d42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998190141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.3998190141
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.1702975011
Short name T446
Test name
Test status
Simulation time 6062239432 ps
CPU time 11.97 seconds
Started Aug 06 05:35:54 PM PDT 24
Finished Aug 06 05:36:06 PM PDT 24
Peak memory 242252 kb
Host smart-dc54485e-4843-4877-a45d-3eb912ee680a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702975011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1702975011
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.1756474087
Short name T211
Test name
Test status
Simulation time 426914566 ps
CPU time 4.62 seconds
Started Aug 06 05:36:09 PM PDT 24
Finished Aug 06 05:36:13 PM PDT 24
Peak memory 242172 kb
Host smart-90c60cfe-918a-4968-b147-5550cf8d4b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756474087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.1756474087
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.2962713453
Short name T900
Test name
Test status
Simulation time 547579268 ps
CPU time 6.07 seconds
Started Aug 06 05:35:52 PM PDT 24
Finished Aug 06 05:35:58 PM PDT 24
Peak memory 241876 kb
Host smart-35ac95d4-008a-4b4a-8631-0aeb52f2f5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962713453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.2962713453
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.3290585250
Short name T782
Test name
Test status
Simulation time 952530725 ps
CPU time 13.46 seconds
Started Aug 06 05:35:51 PM PDT 24
Finished Aug 06 05:36:05 PM PDT 24
Peak memory 242076 kb
Host smart-d4c337b3-ffc4-4888-a7e2-e4923afd9ef4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290585250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.3290585250
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.1643549039
Short name T347
Test name
Test status
Simulation time 1175926448 ps
CPU time 11.21 seconds
Started Aug 06 05:35:53 PM PDT 24
Finished Aug 06 05:36:04 PM PDT 24
Peak memory 242288 kb
Host smart-85ae3acb-fa55-4152-8356-0993bd80e47d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643549039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.1643549039
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.1914006526
Short name T461
Test name
Test status
Simulation time 645206728 ps
CPU time 4.34 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:06 PM PDT 24
Peak memory 241976 kb
Host smart-ff37a12a-7dc4-4503-80ba-605cac4b1073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914006526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.1914006526
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.3132296751
Short name T870
Test name
Test status
Simulation time 1068003074771 ps
CPU time 2358.14 seconds
Started Aug 06 05:35:59 PM PDT 24
Finished Aug 06 06:15:17 PM PDT 24
Peak memory 608084 kb
Host smart-69aec122-f0b5-49d4-89b7-f4f496a431c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132296751 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.3132296751
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.671753090
Short name T942
Test name
Test status
Simulation time 1950026855 ps
CPU time 11.06 seconds
Started Aug 06 05:35:57 PM PDT 24
Finished Aug 06 05:36:08 PM PDT 24
Peak memory 242296 kb
Host smart-8ddb8076-1b1e-4203-b442-af9901914ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671753090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.671753090
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.1570997364
Short name T1141
Test name
Test status
Simulation time 680765968 ps
CPU time 2.29 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:04 PM PDT 24
Peak memory 240284 kb
Host smart-6896dca2-61f8-4607-8189-a334419bcd9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570997364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.1570997364
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.1057420897
Short name T887
Test name
Test status
Simulation time 9229261858 ps
CPU time 12.95 seconds
Started Aug 06 05:35:42 PM PDT 24
Finished Aug 06 05:35:55 PM PDT 24
Peak memory 248612 kb
Host smart-45e4158f-50f7-4f83-840d-e31f9212df66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057420897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.1057420897
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.576703324
Short name T1041
Test name
Test status
Simulation time 640089978 ps
CPU time 7.49 seconds
Started Aug 06 05:35:42 PM PDT 24
Finished Aug 06 05:35:50 PM PDT 24
Peak memory 241912 kb
Host smart-a824a54a-09d7-45f9-9ce5-74fd872564b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576703324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.576703324
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.3556377262
Short name T1165
Test name
Test status
Simulation time 2370710204 ps
CPU time 20.66 seconds
Started Aug 06 05:35:43 PM PDT 24
Finished Aug 06 05:36:04 PM PDT 24
Peak memory 242484 kb
Host smart-97957b0a-b7e0-41e4-9807-bec5827ed03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556377262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.3556377262
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.1541832279
Short name T950
Test name
Test status
Simulation time 162281660 ps
CPU time 4.22 seconds
Started Aug 06 05:36:00 PM PDT 24
Finished Aug 06 05:36:04 PM PDT 24
Peak memory 242048 kb
Host smart-c98986a9-fe9d-404d-b0ad-2d607534b0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541832279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.1541832279
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.590747519
Short name T467
Test name
Test status
Simulation time 2323392426 ps
CPU time 20.48 seconds
Started Aug 06 05:35:42 PM PDT 24
Finished Aug 06 05:36:02 PM PDT 24
Peak memory 244112 kb
Host smart-31fb26c1-82c1-4dde-870b-3902645e525c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590747519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.590747519
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.2740237820
Short name T1130
Test name
Test status
Simulation time 651758659 ps
CPU time 26.93 seconds
Started Aug 06 05:35:41 PM PDT 24
Finished Aug 06 05:36:08 PM PDT 24
Peak memory 242040 kb
Host smart-3df86ba6-640b-4bc1-bd2b-0c0eaa22eec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740237820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.2740237820
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.2367352123
Short name T397
Test name
Test status
Simulation time 13887885947 ps
CPU time 29.6 seconds
Started Aug 06 05:35:59 PM PDT 24
Finished Aug 06 05:36:29 PM PDT 24
Peak memory 242284 kb
Host smart-47c51e7e-cd05-4d02-9f0e-46dda7a44fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367352123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.2367352123
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.3716921004
Short name T353
Test name
Test status
Simulation time 211201228 ps
CPU time 4.41 seconds
Started Aug 06 05:35:54 PM PDT 24
Finished Aug 06 05:35:59 PM PDT 24
Peak memory 241772 kb
Host smart-b7010386-6fbb-4956-aef9-c29f4e720df8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716921004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.3716921004
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.3023867261
Short name T976
Test name
Test status
Simulation time 251129233 ps
CPU time 6.06 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:07 PM PDT 24
Peak memory 242308 kb
Host smart-955b85d2-f13a-4237-a3c6-f999e1a225e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023867261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.3023867261
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.3394572357
Short name T840
Test name
Test status
Simulation time 35396530622 ps
CPU time 230.02 seconds
Started Aug 06 05:35:56 PM PDT 24
Finished Aug 06 05:39:46 PM PDT 24
Peak memory 250204 kb
Host smart-0ab929d8-633d-4646-a935-1d44a637c70d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394572357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.3394572357
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.4149018128
Short name T999
Test name
Test status
Simulation time 45522606380 ps
CPU time 1332.5 seconds
Started Aug 06 05:36:06 PM PDT 24
Finished Aug 06 05:58:19 PM PDT 24
Peak memory 270140 kb
Host smart-261607d6-e962-4266-a916-1f3787468204
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149018128 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.4149018128
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.4110103614
Short name T465
Test name
Test status
Simulation time 551113592 ps
CPU time 6.07 seconds
Started Aug 06 05:35:40 PM PDT 24
Finished Aug 06 05:35:46 PM PDT 24
Peak memory 242036 kb
Host smart-080043cb-869b-4d5a-b596-e6c8479a9866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110103614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.4110103614
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.2877234472
Short name T951
Test name
Test status
Simulation time 41820849 ps
CPU time 1.62 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:05 PM PDT 24
Peak memory 240436 kb
Host smart-e34b456e-fc08-4aa3-a482-b8b1ca06cb87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877234472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.2877234472
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.2109075257
Short name T85
Test name
Test status
Simulation time 592827308 ps
CPU time 16.02 seconds
Started Aug 06 05:36:04 PM PDT 24
Finished Aug 06 05:36:20 PM PDT 24
Peak memory 242028 kb
Host smart-90338d83-ef02-4785-812b-1ced3e9c7d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109075257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.2109075257
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.1224943212
Short name T1146
Test name
Test status
Simulation time 2219525877 ps
CPU time 25.29 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:26 PM PDT 24
Peak memory 242056 kb
Host smart-f757addf-2b6b-412d-b5a0-87f02b83c0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224943212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.1224943212
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.1888628212
Short name T491
Test name
Test status
Simulation time 21618926777 ps
CPU time 72.17 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:37:13 PM PDT 24
Peak memory 248452 kb
Host smart-55eea57b-6ea8-4efb-95ed-9d00ae57919e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888628212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.1888628212
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.3701205026
Short name T448
Test name
Test status
Simulation time 173584291 ps
CPU time 5.54 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:06 PM PDT 24
Peak memory 242052 kb
Host smart-32a3c8ba-6d16-419d-a07a-cfeb298c46f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701205026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.3701205026
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.2708843727
Short name T1003
Test name
Test status
Simulation time 445249878 ps
CPU time 3.55 seconds
Started Aug 06 05:36:05 PM PDT 24
Finished Aug 06 05:36:09 PM PDT 24
Peak memory 242380 kb
Host smart-b3ae7c6e-7685-4b10-a93f-027a8b7fb8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708843727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2708843727
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.1974860316
Short name T1009
Test name
Test status
Simulation time 269854526 ps
CPU time 7.36 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:08 PM PDT 24
Peak memory 242108 kb
Host smart-a473ffd1-025b-4df0-abea-3935fc2f5962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974860316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.1974860316
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.3906101206
Short name T1001
Test name
Test status
Simulation time 236690151 ps
CPU time 7.32 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:08 PM PDT 24
Peak memory 242248 kb
Host smart-970595a0-5b45-4957-9a11-c4f196c9ab0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906101206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.3906101206
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.2404126236
Short name T982
Test name
Test status
Simulation time 678405951 ps
CPU time 18.45 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:22 PM PDT 24
Peak memory 242144 kb
Host smart-6c598f0d-6968-4f43-be3d-37955bc0eff0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2404126236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.2404126236
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.1282293192
Short name T348
Test name
Test status
Simulation time 439928008 ps
CPU time 8.85 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:10 PM PDT 24
Peak memory 242180 kb
Host smart-104a49b9-2f43-40a1-83d6-9667105cd4ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1282293192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.1282293192
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.3686786972
Short name T884
Test name
Test status
Simulation time 312144103 ps
CPU time 6.61 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:10 PM PDT 24
Peak memory 248560 kb
Host smart-ce681bad-bca8-4af8-a0b9-34eb9f56a97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686786972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.3686786972
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.3939896778
Short name T905
Test name
Test status
Simulation time 15315315181 ps
CPU time 100.79 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:37:42 PM PDT 24
Peak memory 281472 kb
Host smart-50df866c-5a93-4164-bec7-0ae8e8044714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939896778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.3939896778
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2950113207
Short name T501
Test name
Test status
Simulation time 50615074897 ps
CPU time 1374.96 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:58:56 PM PDT 24
Peak memory 330056 kb
Host smart-df9bc853-7f88-44ae-abfb-48c20d3171a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950113207 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.2950113207
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.1910644070
Short name T985
Test name
Test status
Simulation time 1301033224 ps
CPU time 26.03 seconds
Started Aug 06 05:36:02 PM PDT 24
Finished Aug 06 05:36:28 PM PDT 24
Peak memory 242252 kb
Host smart-2c10751e-1db9-422a-8f07-8439cd2bbf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910644070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.1910644070
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.2238813071
Short name T767
Test name
Test status
Simulation time 194529324 ps
CPU time 1.9 seconds
Started Aug 06 05:36:06 PM PDT 24
Finished Aug 06 05:36:08 PM PDT 24
Peak memory 240536 kb
Host smart-2f8bd94d-516e-43bf-adcb-bbd0082311cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238813071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.2238813071
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.498991899
Short name T44
Test name
Test status
Simulation time 3729755935 ps
CPU time 12.44 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:13 PM PDT 24
Peak memory 248540 kb
Host smart-39eb2511-a4a0-488b-bf8a-1d4570bf86d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498991899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.498991899
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.1356939732
Short name T723
Test name
Test status
Simulation time 393795671 ps
CPU time 24.98 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:29 PM PDT 24
Peak memory 241880 kb
Host smart-06a64eca-9690-47c8-ae41-2b41e9c5643a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356939732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.1356939732
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.3817180973
Short name T432
Test name
Test status
Simulation time 133432865 ps
CPU time 4.97 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:08 PM PDT 24
Peak memory 242156 kb
Host smart-c2cfd865-2fb7-4649-89d8-723d03e4f1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817180973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.3817180973
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.584588938
Short name T106
Test name
Test status
Simulation time 174992389 ps
CPU time 3.31 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:04 PM PDT 24
Peak memory 242324 kb
Host smart-63b323b4-ffd4-4d32-927b-372c946b3638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584588938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.584588938
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.3024751211
Short name T788
Test name
Test status
Simulation time 2289581178 ps
CPU time 45.29 seconds
Started Aug 06 05:36:02 PM PDT 24
Finished Aug 06 05:36:47 PM PDT 24
Peak memory 248676 kb
Host smart-81a0367e-b08c-466b-9813-e42b29928ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024751211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.3024751211
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.2448102234
Short name T715
Test name
Test status
Simulation time 315006340 ps
CPU time 13.8 seconds
Started Aug 06 05:36:04 PM PDT 24
Finished Aug 06 05:36:18 PM PDT 24
Peak memory 241804 kb
Host smart-1ab47108-c328-4bb2-9112-1c2ef9a8bd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448102234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.2448102234
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.2994262071
Short name T946
Test name
Test status
Simulation time 3707799340 ps
CPU time 9.01 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:10 PM PDT 24
Peak memory 241964 kb
Host smart-99f5ea6b-def1-44e7-bbae-812ac8e94f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994262071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.2994262071
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.2850070436
Short name T605
Test name
Test status
Simulation time 784274555 ps
CPU time 14.76 seconds
Started Aug 06 05:35:58 PM PDT 24
Finished Aug 06 05:36:13 PM PDT 24
Peak memory 242088 kb
Host smart-358c210b-87fe-4f8e-aa60-2a639f236a62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2850070436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.2850070436
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.3458036452
Short name T391
Test name
Test status
Simulation time 484241502 ps
CPU time 5.55 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:09 PM PDT 24
Peak memory 248568 kb
Host smart-1bc29215-b20a-4766-b943-7ce42eb28cbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458036452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.3458036452
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.2979560966
Short name T498
Test name
Test status
Simulation time 508483640 ps
CPU time 6.01 seconds
Started Aug 06 05:36:06 PM PDT 24
Finished Aug 06 05:36:12 PM PDT 24
Peak memory 242004 kb
Host smart-7b77ffeb-0efa-4105-bdd9-fa94aa976642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979560966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.2979560966
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.665075283
Short name T156
Test name
Test status
Simulation time 13876603589 ps
CPU time 75.72 seconds
Started Aug 06 05:36:05 PM PDT 24
Finished Aug 06 05:37:21 PM PDT 24
Peak memory 249344 kb
Host smart-f0a3e105-ebbe-444e-bafb-e207fa267404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665075283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.
665075283
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.325676984
Short name T359
Test name
Test status
Simulation time 36454758130 ps
CPU time 984.77 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:52:27 PM PDT 24
Peak memory 256968 kb
Host smart-64bf61ef-da7f-43a2-ac05-dcf6e8c569f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325676984 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.325676984
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.1709193917
Short name T856
Test name
Test status
Simulation time 27480514682 ps
CPU time 63.82 seconds
Started Aug 06 05:36:04 PM PDT 24
Finished Aug 06 05:37:08 PM PDT 24
Peak memory 243052 kb
Host smart-0d2677a7-5ec0-4a53-bfdb-2cb7cf025c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709193917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.1709193917
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.1015164071
Short name T776
Test name
Test status
Simulation time 129480478 ps
CPU time 1.98 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:05 PM PDT 24
Peak memory 240664 kb
Host smart-82a5fe76-b492-44db-ac75-cdb018932618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015164071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1015164071
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.960145084
Short name T514
Test name
Test status
Simulation time 530043361 ps
CPU time 8.4 seconds
Started Aug 06 05:35:59 PM PDT 24
Finished Aug 06 05:36:07 PM PDT 24
Peak memory 241988 kb
Host smart-0fa28a70-6598-4171-9409-a555d38945dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960145084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.960145084
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.1901362387
Short name T612
Test name
Test status
Simulation time 1039974146 ps
CPU time 21.77 seconds
Started Aug 06 05:36:04 PM PDT 24
Finished Aug 06 05:36:26 PM PDT 24
Peak memory 242352 kb
Host smart-cc66b503-f49c-49c4-b8b1-c546366889f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901362387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.1901362387
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.1111742241
Short name T812
Test name
Test status
Simulation time 2238894008 ps
CPU time 26.66 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:27 PM PDT 24
Peak memory 242328 kb
Host smart-b995c95c-fdcc-4ba3-b33c-d28b6a78c58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111742241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.1111742241
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.2940702986
Short name T551
Test name
Test status
Simulation time 1762278210 ps
CPU time 3.9 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:07 PM PDT 24
Peak memory 241904 kb
Host smart-00ccd9ea-51dd-4de1-8a15-9667c731b96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940702986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2940702986
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.389626743
Short name T1018
Test name
Test status
Simulation time 1339609681 ps
CPU time 3.11 seconds
Started Aug 06 05:36:02 PM PDT 24
Finished Aug 06 05:36:05 PM PDT 24
Peak memory 242012 kb
Host smart-98471295-2a48-42b3-829b-db0a8cead79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389626743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.389626743
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.1796764965
Short name T943
Test name
Test status
Simulation time 1059228827 ps
CPU time 19.72 seconds
Started Aug 06 05:36:00 PM PDT 24
Finished Aug 06 05:36:20 PM PDT 24
Peak memory 242252 kb
Host smart-e09d21fe-35ec-4f21-aba4-89490dfded79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796764965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1796764965
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.4224554797
Short name T759
Test name
Test status
Simulation time 1917697096 ps
CPU time 31.93 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:33 PM PDT 24
Peak memory 242072 kb
Host smart-910f7011-c4bb-4ae7-a932-34dff82f9e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224554797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.4224554797
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.2623219153
Short name T720
Test name
Test status
Simulation time 747995154 ps
CPU time 17.16 seconds
Started Aug 06 05:36:01 PM PDT 24
Finished Aug 06 05:36:18 PM PDT 24
Peak memory 241968 kb
Host smart-7698f486-708d-41e5-8f69-a6fd1fa98ff3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623219153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.2623219153
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.3278889768
Short name T923
Test name
Test status
Simulation time 710377189 ps
CPU time 6.3 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:09 PM PDT 24
Peak memory 242212 kb
Host smart-2127ad26-4c57-4f77-9a26-67e6e36da01a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3278889768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.3278889768
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.2913726154
Short name T971
Test name
Test status
Simulation time 1337022158 ps
CPU time 6.4 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:09 PM PDT 24
Peak memory 241996 kb
Host smart-d9eeb31a-3acc-40d5-bb5e-fd8ba932e88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913726154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.2913726154
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.1189058994
Short name T686
Test name
Test status
Simulation time 2594314720 ps
CPU time 23.44 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:27 PM PDT 24
Peak memory 243844 kb
Host smart-ee65cf7a-6195-442a-9cb2-d958e3665ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189058994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.1189058994
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.3437145179
Short name T704
Test name
Test status
Simulation time 267659945736 ps
CPU time 2051.76 seconds
Started Aug 06 05:36:00 PM PDT 24
Finished Aug 06 06:10:12 PM PDT 24
Peak memory 328380 kb
Host smart-e563594e-aedd-45ef-a7a5-7aa8f49ec0d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437145179 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.3437145179
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.3812443275
Short name T747
Test name
Test status
Simulation time 298536319 ps
CPU time 6.47 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:09 PM PDT 24
Peak memory 241868 kb
Host smart-835ddbc6-1423-4688-a3b7-f6233490131e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812443275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.3812443275
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.3362168674
Short name T790
Test name
Test status
Simulation time 562684689 ps
CPU time 2.6 seconds
Started Aug 06 05:36:15 PM PDT 24
Finished Aug 06 05:36:18 PM PDT 24
Peak memory 240568 kb
Host smart-4881176a-7f76-4a85-b0e0-15dedc90bf75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362168674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.3362168674
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.1054425081
Short name T765
Test name
Test status
Simulation time 3965593345 ps
CPU time 32.15 seconds
Started Aug 06 05:36:15 PM PDT 24
Finished Aug 06 05:36:47 PM PDT 24
Peak memory 242380 kb
Host smart-94b575ee-e417-4660-a934-014532ca4677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054425081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.1054425081
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.2926359717
Short name T205
Test name
Test status
Simulation time 1566990672 ps
CPU time 30.01 seconds
Started Aug 06 05:36:03 PM PDT 24
Finished Aug 06 05:36:33 PM PDT 24
Peak memory 242496 kb
Host smart-10c3b854-ee79-415d-be64-a0c97cd2fb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926359717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.2926359717
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.368444460
Short name T945
Test name
Test status
Simulation time 1818031146 ps
CPU time 4.13 seconds
Started Aug 06 05:36:02 PM PDT 24
Finished Aug 06 05:36:07 PM PDT 24
Peak memory 242352 kb
Host smart-bf836f10-991e-45de-9431-e9a4cf3771ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368444460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.368444460
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.3027411219
Short name T509
Test name
Test status
Simulation time 2750285072 ps
CPU time 20.92 seconds
Started Aug 06 05:36:27 PM PDT 24
Finished Aug 06 05:36:48 PM PDT 24
Peak memory 248340 kb
Host smart-199819f3-c64d-4982-9e8a-9a6cf450e90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027411219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.3027411219
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.81907029
Short name T694
Test name
Test status
Simulation time 634972049 ps
CPU time 14.41 seconds
Started Aug 06 05:36:27 PM PDT 24
Finished Aug 06 05:36:42 PM PDT 24
Peak memory 242480 kb
Host smart-9d8ec959-70e7-4728-ac7b-ef6b1c672ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81907029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.81907029
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.2081509530
Short name T404
Test name
Test status
Simulation time 174929089 ps
CPU time 5.16 seconds
Started Aug 06 05:36:02 PM PDT 24
Finished Aug 06 05:36:07 PM PDT 24
Peak memory 248360 kb
Host smart-9dd891fb-440e-4582-bb10-7f9e813efb52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081509530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.2081509530
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.1083122141
Short name T582
Test name
Test status
Simulation time 2924905860 ps
CPU time 10.46 seconds
Started Aug 06 05:36:28 PM PDT 24
Finished Aug 06 05:36:38 PM PDT 24
Peak memory 242108 kb
Host smart-0c565e8b-9816-4003-8a7d-ae7cbedaa500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1083122141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.1083122141
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.3081203281
Short name T978
Test name
Test status
Simulation time 311546596 ps
CPU time 4.95 seconds
Started Aug 06 05:36:04 PM PDT 24
Finished Aug 06 05:36:09 PM PDT 24
Peak memory 242312 kb
Host smart-1caab607-8aa7-42a6-9b01-8bfa27d540e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081203281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3081203281
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.2438959286
Short name T621
Test name
Test status
Simulation time 4299091373 ps
CPU time 96.24 seconds
Started Aug 06 05:36:26 PM PDT 24
Finished Aug 06 05:38:03 PM PDT 24
Peak memory 244912 kb
Host smart-d6cde1b8-ed89-4e7a-ae57-32a6b603a401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438959286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.2438959286
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.4276905734
Short name T860
Test name
Test status
Simulation time 436896299 ps
CPU time 6.74 seconds
Started Aug 06 05:36:13 PM PDT 24
Finished Aug 06 05:36:20 PM PDT 24
Peak memory 242008 kb
Host smart-46900838-520c-4e47-8761-81c76addd77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276905734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.4276905734
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.3918952797
Short name T603
Test name
Test status
Simulation time 100535539 ps
CPU time 1.97 seconds
Started Aug 06 05:36:18 PM PDT 24
Finished Aug 06 05:36:20 PM PDT 24
Peak memory 240396 kb
Host smart-f69ebc2d-7918-48f6-bb41-3da816517fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918952797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.3918952797
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.352263716
Short name T425
Test name
Test status
Simulation time 1821549846 ps
CPU time 27.96 seconds
Started Aug 06 05:36:16 PM PDT 24
Finished Aug 06 05:36:44 PM PDT 24
Peak memory 244412 kb
Host smart-b249959d-755e-43fd-a614-e8859ec6de15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352263716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.352263716
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.3777642488
Short name T1092
Test name
Test status
Simulation time 2888086434 ps
CPU time 22.68 seconds
Started Aug 06 05:36:28 PM PDT 24
Finished Aug 06 05:36:50 PM PDT 24
Peak memory 242224 kb
Host smart-3fb6e776-4cc8-4ac1-b9eb-c57fc3f4733e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777642488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.3777642488
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.1397944200
Short name T804
Test name
Test status
Simulation time 1748290324 ps
CPU time 4.27 seconds
Started Aug 06 05:36:15 PM PDT 24
Finished Aug 06 05:36:19 PM PDT 24
Peak memory 242132 kb
Host smart-b239e2a5-0975-4082-b96e-9759ac57a298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397944200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.1397944200
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.2869838664
Short name T862
Test name
Test status
Simulation time 725496908 ps
CPU time 21.47 seconds
Started Aug 06 05:36:27 PM PDT 24
Finished Aug 06 05:36:49 PM PDT 24
Peak memory 242944 kb
Host smart-f2a40eb0-1c95-4e67-a623-e943c7ed4488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869838664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2869838664
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.3295410237
Short name T1024
Test name
Test status
Simulation time 382969417 ps
CPU time 11.08 seconds
Started Aug 06 05:36:14 PM PDT 24
Finished Aug 06 05:36:25 PM PDT 24
Peak memory 242408 kb
Host smart-33688b40-aab8-4862-a1d4-e5e3197bdd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295410237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.3295410237
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.215033192
Short name T593
Test name
Test status
Simulation time 109932830 ps
CPU time 4.84 seconds
Started Aug 06 05:36:14 PM PDT 24
Finished Aug 06 05:36:19 PM PDT 24
Peak memory 241796 kb
Host smart-d581139d-a951-42f1-a767-3c176a2cf3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215033192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.215033192
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.3409689584
Short name T36
Test name
Test status
Simulation time 342476240 ps
CPU time 9.25 seconds
Started Aug 06 05:36:28 PM PDT 24
Finished Aug 06 05:36:38 PM PDT 24
Peak memory 248572 kb
Host smart-adcafbc9-8e57-42c1-8774-7dd122883418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409689584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.3409689584
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.2902482665
Short name T835
Test name
Test status
Simulation time 3473342205 ps
CPU time 12.2 seconds
Started Aug 06 05:36:26 PM PDT 24
Finished Aug 06 05:36:38 PM PDT 24
Peak memory 241868 kb
Host smart-1a9bdb4a-c043-4173-aeda-2ca3d04d3fb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902482665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.2902482665
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.265890710
Short name T1185
Test name
Test status
Simulation time 412183013 ps
CPU time 5.15 seconds
Started Aug 06 05:36:13 PM PDT 24
Finished Aug 06 05:36:18 PM PDT 24
Peak memory 241976 kb
Host smart-d1f5ea56-1879-44d8-92c3-bf8e47501821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265890710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.265890710
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.2636909494
Short name T1075
Test name
Test status
Simulation time 25030840973 ps
CPU time 108.67 seconds
Started Aug 06 05:36:26 PM PDT 24
Finished Aug 06 05:38:15 PM PDT 24
Peak memory 247312 kb
Host smart-9cfb600d-dcd4-4e30-b472-c302127b8300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636909494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all
.2636909494
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3073390938
Short name T316
Test name
Test status
Simulation time 257056631636 ps
CPU time 528.52 seconds
Started Aug 06 05:36:14 PM PDT 24
Finished Aug 06 05:45:03 PM PDT 24
Peak memory 270108 kb
Host smart-8c5095ca-1251-4eb5-895b-9e207e4947e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073390938 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.3073390938
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.2796005976
Short name T637
Test name
Test status
Simulation time 870524805 ps
CPU time 16.64 seconds
Started Aug 06 05:36:13 PM PDT 24
Finished Aug 06 05:36:30 PM PDT 24
Peak memory 242268 kb
Host smart-f3c10ce8-a518-44f9-9d1c-d6d5156fe07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796005976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.2796005976
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.650185596
Short name T931
Test name
Test status
Simulation time 122753111 ps
CPU time 1.94 seconds
Started Aug 06 05:36:32 PM PDT 24
Finished Aug 06 05:36:34 PM PDT 24
Peak memory 240700 kb
Host smart-16effa55-6f09-4aaa-848f-90f451f613cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650185596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.650185596
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.940132035
Short name T1071
Test name
Test status
Simulation time 677801964 ps
CPU time 10.68 seconds
Started Aug 06 05:36:30 PM PDT 24
Finished Aug 06 05:36:41 PM PDT 24
Peak memory 242436 kb
Host smart-f4a95c87-4e4c-43cc-9792-bb2d08fc6249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940132035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.940132035
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.876508759
Short name T815
Test name
Test status
Simulation time 946047966 ps
CPU time 17.35 seconds
Started Aug 06 05:36:28 PM PDT 24
Finished Aug 06 05:36:46 PM PDT 24
Peak memory 241860 kb
Host smart-8ed1cfef-98eb-4931-80c3-17105cd0d249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876508759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.876508759
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.2034380087
Short name T412
Test name
Test status
Simulation time 837093186 ps
CPU time 5.85 seconds
Started Aug 06 05:36:29 PM PDT 24
Finished Aug 06 05:36:35 PM PDT 24
Peak memory 241852 kb
Host smart-eff060b0-1095-4a98-a0a2-5dd94bd06054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034380087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.2034380087
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.2623055601
Short name T813
Test name
Test status
Simulation time 111638003 ps
CPU time 3.89 seconds
Started Aug 06 05:36:28 PM PDT 24
Finished Aug 06 05:36:32 PM PDT 24
Peak memory 241968 kb
Host smart-a106b13a-8b6f-47f6-b470-27e1be4c1547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623055601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.2623055601
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.1975654073
Short name T516
Test name
Test status
Simulation time 132814118 ps
CPU time 4.17 seconds
Started Aug 06 05:36:30 PM PDT 24
Finished Aug 06 05:36:34 PM PDT 24
Peak memory 242304 kb
Host smart-df530a2e-0168-42b5-963a-2e4c867f2718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975654073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.1975654073
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.1120238753
Short name T356
Test name
Test status
Simulation time 499490392 ps
CPU time 11.07 seconds
Started Aug 06 05:36:31 PM PDT 24
Finished Aug 06 05:36:42 PM PDT 24
Peak memory 242036 kb
Host smart-0c4eb81c-6870-4a57-92b4-6fe3275901a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120238753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.1120238753
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.1170883586
Short name T907
Test name
Test status
Simulation time 242639208 ps
CPU time 4.83 seconds
Started Aug 06 05:36:30 PM PDT 24
Finished Aug 06 05:36:35 PM PDT 24
Peak memory 242000 kb
Host smart-0a18cc18-b52e-45ce-b681-b755208f82b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170883586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.1170883586
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.943911819
Short name T745
Test name
Test status
Simulation time 318983841 ps
CPU time 10.38 seconds
Started Aug 06 05:36:31 PM PDT 24
Finished Aug 06 05:36:42 PM PDT 24
Peak memory 241740 kb
Host smart-402cfa5d-839a-40ee-8e66-16eab181a180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943911819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.943911819
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.558030744
Short name T851
Test name
Test status
Simulation time 187430522 ps
CPU time 3.12 seconds
Started Aug 06 05:36:30 PM PDT 24
Finished Aug 06 05:36:33 PM PDT 24
Peak memory 241704 kb
Host smart-8eda505e-6d02-42ea-ba1f-2fda08063a70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558030744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.558030744
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.256945476
Short name T1179
Test name
Test status
Simulation time 494753787 ps
CPU time 8.55 seconds
Started Aug 06 05:36:25 PM PDT 24
Finished Aug 06 05:36:34 PM PDT 24
Peak memory 241876 kb
Host smart-9ab55b57-e926-41e2-bbfa-ffe5179bc3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256945476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.256945476
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.106429425
Short name T659
Test name
Test status
Simulation time 329570625248 ps
CPU time 2098.44 seconds
Started Aug 06 05:36:34 PM PDT 24
Finished Aug 06 06:11:32 PM PDT 24
Peak memory 315644 kb
Host smart-407d05c4-e17f-40e3-860c-c3c1b6fd3e6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106429425 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.106429425
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.298066179
Short name T357
Test name
Test status
Simulation time 2266078372 ps
CPU time 20.1 seconds
Started Aug 06 05:36:30 PM PDT 24
Finished Aug 06 05:36:50 PM PDT 24
Peak memory 248644 kb
Host smart-d8903f85-c0b3-4749-8d51-24c92a5ed2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298066179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.298066179
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.1995241831
Short name T642
Test name
Test status
Simulation time 67682505 ps
CPU time 1.7 seconds
Started Aug 06 05:31:48 PM PDT 24
Finished Aug 06 05:31:50 PM PDT 24
Peak memory 240352 kb
Host smart-d0c19aee-a526-45bf-a312-6a90b7fe5388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995241831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.1995241831
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.84355987
Short name T7
Test name
Test status
Simulation time 288912829 ps
CPU time 10.06 seconds
Started Aug 06 05:31:47 PM PDT 24
Finished Aug 06 05:31:57 PM PDT 24
Peak memory 248468 kb
Host smart-d5eac1be-39bb-4436-ac30-b077a5f0020a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84355987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.84355987
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.2858115954
Short name T122
Test name
Test status
Simulation time 509795802 ps
CPU time 17.57 seconds
Started Aug 06 05:31:48 PM PDT 24
Finished Aug 06 05:32:05 PM PDT 24
Peak memory 242168 kb
Host smart-bd4287f5-599e-49b8-bd7f-2518714110a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858115954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2858115954
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.3250704407
Short name T510
Test name
Test status
Simulation time 358948900 ps
CPU time 8.01 seconds
Started Aug 06 05:31:46 PM PDT 24
Finished Aug 06 05:31:54 PM PDT 24
Peak memory 242248 kb
Host smart-854c6c30-137e-4519-90ac-d0fe73d175f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250704407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.3250704407
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.3456583889
Short name T423
Test name
Test status
Simulation time 864537858 ps
CPU time 14.93 seconds
Started Aug 06 05:31:47 PM PDT 24
Finished Aug 06 05:32:02 PM PDT 24
Peak memory 242080 kb
Host smart-f6dc5a36-7d81-4e52-b276-463701e1abff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456583889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.3456583889
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.2332609167
Short name T411
Test name
Test status
Simulation time 460794415 ps
CPU time 4.33 seconds
Started Aug 06 05:31:45 PM PDT 24
Finished Aug 06 05:31:49 PM PDT 24
Peak memory 241944 kb
Host smart-dd0612d2-60ea-40ac-93a6-0a018739e3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332609167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.2332609167
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.146344764
Short name T717
Test name
Test status
Simulation time 3258083119 ps
CPU time 22.74 seconds
Started Aug 06 05:31:45 PM PDT 24
Finished Aug 06 05:32:08 PM PDT 24
Peak memory 243124 kb
Host smart-82f253dc-c4da-427e-993a-29dce6ba9df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146344764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.146344764
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.1564521405
Short name T948
Test name
Test status
Simulation time 1215734202 ps
CPU time 13.9 seconds
Started Aug 06 05:31:44 PM PDT 24
Finished Aug 06 05:31:58 PM PDT 24
Peak memory 242348 kb
Host smart-33d8dc14-1884-4a1f-8a18-91c5682a4391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564521405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.1564521405
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.1452225156
Short name T155
Test name
Test status
Simulation time 982917372 ps
CPU time 8.5 seconds
Started Aug 06 05:31:48 PM PDT 24
Finished Aug 06 05:31:56 PM PDT 24
Peak memory 241824 kb
Host smart-c9475545-0826-412c-852d-d147767f82e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452225156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.1452225156
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.992680229
Short name T218
Test name
Test status
Simulation time 410626540 ps
CPU time 6.54 seconds
Started Aug 06 05:31:48 PM PDT 24
Finished Aug 06 05:31:54 PM PDT 24
Peak memory 242152 kb
Host smart-090c78bc-12a5-4424-8c94-de300fdd438f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992680229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.992680229
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.2630880491
Short name T761
Test name
Test status
Simulation time 311651438 ps
CPU time 4.49 seconds
Started Aug 06 05:31:48 PM PDT 24
Finished Aug 06 05:31:52 PM PDT 24
Peak memory 242032 kb
Host smart-fda3011a-fde6-4bb4-8a3e-eb5e783cd59f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630880491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.2630880491
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.3129989187
Short name T393
Test name
Test status
Simulation time 1102651314 ps
CPU time 8.43 seconds
Started Aug 06 05:31:45 PM PDT 24
Finished Aug 06 05:31:54 PM PDT 24
Peak memory 242256 kb
Host smart-0c6eecd1-ffc4-482a-b5b7-b6c73d8dd5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129989187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.3129989187
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.3679494262
Short name T602
Test name
Test status
Simulation time 21520779565 ps
CPU time 180.79 seconds
Started Aug 06 05:31:44 PM PDT 24
Finished Aug 06 05:34:45 PM PDT 24
Peak memory 258024 kb
Host smart-50a370cd-1d60-4f20-b310-8eb99609bd1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679494262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
3679494262
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1274985617
Short name T599
Test name
Test status
Simulation time 35392143958 ps
CPU time 441.13 seconds
Started Aug 06 05:31:47 PM PDT 24
Finished Aug 06 05:39:08 PM PDT 24
Peak memory 304728 kb
Host smart-eac87ca0-bb4e-41f3-b501-a1d63dd7e8be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274985617 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.1274985617
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.3288857285
Short name T830
Test name
Test status
Simulation time 1078936885 ps
CPU time 21.15 seconds
Started Aug 06 05:31:46 PM PDT 24
Finished Aug 06 05:32:07 PM PDT 24
Peak memory 242204 kb
Host smart-cf74b44c-6d8a-43cf-a920-e8b9ea027c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288857285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.3288857285
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.3547162754
Short name T190
Test name
Test status
Simulation time 451269774 ps
CPU time 4.47 seconds
Started Aug 06 05:36:34 PM PDT 24
Finished Aug 06 05:36:39 PM PDT 24
Peak memory 242320 kb
Host smart-c6cadc01-449e-477d-b6ad-921941196dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547162754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.3547162754
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.3553736256
Short name T1087
Test name
Test status
Simulation time 857982655 ps
CPU time 7 seconds
Started Aug 06 05:36:34 PM PDT 24
Finished Aug 06 05:36:41 PM PDT 24
Peak memory 241788 kb
Host smart-188b35d8-0859-4158-87fd-e5a8451452c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553736256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.3553736256
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.3428882202
Short name T318
Test name
Test status
Simulation time 201016970172 ps
CPU time 1988.2 seconds
Started Aug 06 05:36:34 PM PDT 24
Finished Aug 06 06:09:42 PM PDT 24
Peak memory 658024 kb
Host smart-dc661529-ac6b-426d-9472-116b45585eb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428882202 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.3428882202
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.2158562690
Short name T921
Test name
Test status
Simulation time 168155738 ps
CPU time 3.49 seconds
Started Aug 06 05:36:32 PM PDT 24
Finished Aug 06 05:36:36 PM PDT 24
Peak memory 242080 kb
Host smart-a17c3952-ff93-44fc-a6d9-f0345d1a8100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158562690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.2158562690
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.107456352
Short name T953
Test name
Test status
Simulation time 751550894527 ps
CPU time 1590.26 seconds
Started Aug 06 05:36:28 PM PDT 24
Finished Aug 06 06:02:59 PM PDT 24
Peak memory 364356 kb
Host smart-07e31ae1-a826-4472-9a09-cfd9a5589574
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107456352 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.107456352
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.1079360516
Short name T1093
Test name
Test status
Simulation time 143641937 ps
CPU time 5.4 seconds
Started Aug 06 05:36:31 PM PDT 24
Finished Aug 06 05:36:37 PM PDT 24
Peak memory 241816 kb
Host smart-65dc493b-aa75-486d-975d-2349ec296562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079360516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.1079360516
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.2620628510
Short name T311
Test name
Test status
Simulation time 223654517 ps
CPU time 4.7 seconds
Started Aug 06 05:36:33 PM PDT 24
Finished Aug 06 05:36:38 PM PDT 24
Peak memory 242396 kb
Host smart-b8cfe079-d9f2-46dc-9dcb-9e4f7d8c1fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620628510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.2620628510
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.524095503
Short name T858
Test name
Test status
Simulation time 406830319347 ps
CPU time 1357.97 seconds
Started Aug 06 05:36:28 PM PDT 24
Finished Aug 06 05:59:06 PM PDT 24
Peak memory 445664 kb
Host smart-38efd427-5732-483d-a30a-2c48e93111b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524095503 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.524095503
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.312258225
Short name T770
Test name
Test status
Simulation time 181442255 ps
CPU time 3.08 seconds
Started Aug 06 05:36:27 PM PDT 24
Finished Aug 06 05:36:30 PM PDT 24
Peak memory 242160 kb
Host smart-219bd835-0ce4-4386-8160-0fcc85a7c404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312258225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.312258225
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.313186005
Short name T515
Test name
Test status
Simulation time 737342902 ps
CPU time 9.57 seconds
Started Aug 06 05:36:28 PM PDT 24
Finished Aug 06 05:36:38 PM PDT 24
Peak memory 241988 kb
Host smart-4c8a065f-cfa0-4d91-b6c2-7401927c6a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313186005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.313186005
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.1357198987
Short name T868
Test name
Test status
Simulation time 28907373521 ps
CPU time 427.49 seconds
Started Aug 06 05:36:32 PM PDT 24
Finished Aug 06 05:43:40 PM PDT 24
Peak memory 256912 kb
Host smart-dba75405-55cc-40a8-a0f2-070b9522015b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357198987 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.1357198987
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.2762470527
Short name T861
Test name
Test status
Simulation time 558771904 ps
CPU time 5.21 seconds
Started Aug 06 05:36:29 PM PDT 24
Finished Aug 06 05:36:35 PM PDT 24
Peak memory 242128 kb
Host smart-3f55f903-e80f-40a4-829e-1aac9f23d879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762470527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.2762470527
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.510154577
Short name T864
Test name
Test status
Simulation time 238632680 ps
CPU time 5.67 seconds
Started Aug 06 05:36:32 PM PDT 24
Finished Aug 06 05:36:38 PM PDT 24
Peak memory 242224 kb
Host smart-a7231ec2-b826-43b4-bede-6959f37c3ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510154577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.510154577
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.3512624350
Short name T1019
Test name
Test status
Simulation time 54085011991 ps
CPU time 873.43 seconds
Started Aug 06 05:36:32 PM PDT 24
Finished Aug 06 05:51:06 PM PDT 24
Peak memory 358308 kb
Host smart-844a36bb-88d0-45ce-a014-2dfd62f906ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512624350 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.3512624350
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.2776360781
Short name T32
Test name
Test status
Simulation time 335221082 ps
CPU time 4.5 seconds
Started Aug 06 05:36:30 PM PDT 24
Finished Aug 06 05:36:35 PM PDT 24
Peak memory 241912 kb
Host smart-e2d46a44-81cb-41fe-a9d1-4148d1f6cca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776360781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2776360781
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.3209202242
Short name T741
Test name
Test status
Simulation time 159751834 ps
CPU time 3.99 seconds
Started Aug 06 05:36:29 PM PDT 24
Finished Aug 06 05:36:33 PM PDT 24
Peak memory 242248 kb
Host smart-8b468d7c-d860-44fb-85c2-a3f3e7af6c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209202242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.3209202242
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.3266845994
Short name T1011
Test name
Test status
Simulation time 2197400076 ps
CPU time 6.09 seconds
Started Aug 06 05:36:30 PM PDT 24
Finished Aug 06 05:36:37 PM PDT 24
Peak memory 242028 kb
Host smart-44a0426e-625c-4e2b-883d-669afaa2fa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266845994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.3266845994
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.3282710099
Short name T385
Test name
Test status
Simulation time 774602696 ps
CPU time 9.78 seconds
Started Aug 06 05:36:31 PM PDT 24
Finished Aug 06 05:36:41 PM PDT 24
Peak memory 241860 kb
Host smart-8bbc326b-df59-455b-8c5f-22147a18ea46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282710099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.3282710099
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.2520629777
Short name T569
Test name
Test status
Simulation time 21434613225 ps
CPU time 424.67 seconds
Started Aug 06 05:36:32 PM PDT 24
Finished Aug 06 05:43:37 PM PDT 24
Peak memory 248776 kb
Host smart-41ca0142-1dd7-405b-83b3-ef4c466f2264
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520629777 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.2520629777
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.1491060021
Short name T749
Test name
Test status
Simulation time 463956749 ps
CPU time 4.31 seconds
Started Aug 06 05:36:30 PM PDT 24
Finished Aug 06 05:36:34 PM PDT 24
Peak memory 242104 kb
Host smart-3fc210bb-cf9f-47fb-a896-7b41023eb096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491060021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1491060021
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.2471974479
Short name T495
Test name
Test status
Simulation time 366414593 ps
CPU time 3.1 seconds
Started Aug 06 05:36:29 PM PDT 24
Finished Aug 06 05:36:32 PM PDT 24
Peak memory 241908 kb
Host smart-6867911e-00d0-4384-92c3-7825472a3542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471974479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.2471974479
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.4218818158
Short name T803
Test name
Test status
Simulation time 227628082898 ps
CPU time 2893.26 seconds
Started Aug 06 05:36:31 PM PDT 24
Finished Aug 06 06:24:45 PM PDT 24
Peak memory 368032 kb
Host smart-e78602a7-9b62-4396-ac43-8900c2cd5917
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218818158 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.4218818158
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.3142668823
Short name T485
Test name
Test status
Simulation time 112938083 ps
CPU time 4.04 seconds
Started Aug 06 05:36:33 PM PDT 24
Finished Aug 06 05:36:37 PM PDT 24
Peak memory 241924 kb
Host smart-e6360562-c5d0-4ba8-a54f-457dd99a0cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142668823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.3142668823
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.2319127512
Short name T926
Test name
Test status
Simulation time 146884587 ps
CPU time 5.82 seconds
Started Aug 06 05:36:32 PM PDT 24
Finished Aug 06 05:36:38 PM PDT 24
Peak memory 242204 kb
Host smart-d23fea89-2aae-4435-82ae-fa34b972a391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319127512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.2319127512
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.1333326261
Short name T1062
Test name
Test status
Simulation time 195929334860 ps
CPU time 745.71 seconds
Started Aug 06 05:36:34 PM PDT 24
Finished Aug 06 05:49:00 PM PDT 24
Peak memory 269816 kb
Host smart-b8b39aa7-12b3-4fef-a9fe-8c6d9e308ad1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333326261 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.1333326261
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.832648656
Short name T50
Test name
Test status
Simulation time 2228418385 ps
CPU time 7.26 seconds
Started Aug 06 05:36:33 PM PDT 24
Finished Aug 06 05:36:40 PM PDT 24
Peak memory 242232 kb
Host smart-0aa89232-ea8e-418b-80d0-7bb92cf4a9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832648656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.832648656
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.1618237553
Short name T481
Test name
Test status
Simulation time 492085317 ps
CPU time 15.19 seconds
Started Aug 06 05:36:33 PM PDT 24
Finished Aug 06 05:36:49 PM PDT 24
Peak memory 241844 kb
Host smart-4a9a7e12-5a43-4c25-adb8-8e24bed70655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618237553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.1618237553
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.4200089691
Short name T1097
Test name
Test status
Simulation time 120635373111 ps
CPU time 332.92 seconds
Started Aug 06 05:36:30 PM PDT 24
Finished Aug 06 05:42:03 PM PDT 24
Peak memory 281540 kb
Host smart-73c7a2e0-8df2-4260-bd93-f7dd6c7bdc83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200089691 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.4200089691
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.1706534992
Short name T442
Test name
Test status
Simulation time 59470055 ps
CPU time 1.83 seconds
Started Aug 06 05:32:02 PM PDT 24
Finished Aug 06 05:32:04 PM PDT 24
Peak memory 240400 kb
Host smart-79bd50a7-e16e-45f0-a3a7-150e9c5269cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706534992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.1706534992
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.1534197979
Short name T559
Test name
Test status
Simulation time 9437018139 ps
CPU time 17.64 seconds
Started Aug 06 05:31:45 PM PDT 24
Finished Aug 06 05:32:03 PM PDT 24
Peak memory 243000 kb
Host smart-b72c54d8-0fe3-4b29-ac37-76570b68d763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534197979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.1534197979
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.3536644208
Short name T1139
Test name
Test status
Simulation time 2504957416 ps
CPU time 30.21 seconds
Started Aug 06 05:31:47 PM PDT 24
Finished Aug 06 05:32:18 PM PDT 24
Peak memory 248616 kb
Host smart-b1099e41-7e16-4088-9c8f-16fd0445b8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536644208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.3536644208
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.989692919
Short name T892
Test name
Test status
Simulation time 911693860 ps
CPU time 14.45 seconds
Started Aug 06 05:31:47 PM PDT 24
Finished Aug 06 05:32:01 PM PDT 24
Peak memory 241916 kb
Host smart-e5e6bdb2-7e5d-4ca2-b78e-6450ab99023f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989692919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.989692919
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.1566310839
Short name T1125
Test name
Test status
Simulation time 7939957015 ps
CPU time 17.59 seconds
Started Aug 06 05:31:47 PM PDT 24
Finished Aug 06 05:32:05 PM PDT 24
Peak memory 242760 kb
Host smart-1edc9c90-581e-4c91-a205-60deb2243189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566310839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.1566310839
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.2969158692
Short name T1168
Test name
Test status
Simulation time 123193576 ps
CPU time 3.2 seconds
Started Aug 06 05:31:48 PM PDT 24
Finished Aug 06 05:31:51 PM PDT 24
Peak memory 242276 kb
Host smart-613b9241-ed04-408c-bab8-68f86e02b3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969158692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.2969158692
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.1733997534
Short name T874
Test name
Test status
Simulation time 2274541834 ps
CPU time 22.09 seconds
Started Aug 06 05:31:46 PM PDT 24
Finished Aug 06 05:32:08 PM PDT 24
Peak memory 242372 kb
Host smart-7f74f0a4-da50-4223-abde-5ac18d24e4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733997534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.1733997534
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.1074477618
Short name T105
Test name
Test status
Simulation time 793599908 ps
CPU time 21.57 seconds
Started Aug 06 05:31:45 PM PDT 24
Finished Aug 06 05:32:06 PM PDT 24
Peak memory 248452 kb
Host smart-3469adeb-b078-4b78-9997-39cb4d0a6856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074477618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.1074477618
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.1196762252
Short name T614
Test name
Test status
Simulation time 436711632 ps
CPU time 5.93 seconds
Started Aug 06 05:31:47 PM PDT 24
Finished Aug 06 05:31:53 PM PDT 24
Peak memory 242164 kb
Host smart-d67edfed-3b64-45b5-b16f-8ef8cb2cecb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196762252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.1196762252
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.1493511548
Short name T1054
Test name
Test status
Simulation time 773939827 ps
CPU time 7.94 seconds
Started Aug 06 05:31:45 PM PDT 24
Finished Aug 06 05:31:53 PM PDT 24
Peak memory 248536 kb
Host smart-6ac6066f-99fa-4a37-8bc5-b4a3c643ebbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1493511548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.1493511548
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.3181267857
Short name T110
Test name
Test status
Simulation time 617757617 ps
CPU time 9.33 seconds
Started Aug 06 05:31:44 PM PDT 24
Finished Aug 06 05:31:53 PM PDT 24
Peak memory 242224 kb
Host smart-829d58ce-7f6a-4d72-94fa-dc41381b89bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3181267857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.3181267857
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.2982821152
Short name T457
Test name
Test status
Simulation time 2184151906 ps
CPU time 4.69 seconds
Started Aug 06 05:31:45 PM PDT 24
Finished Aug 06 05:31:50 PM PDT 24
Peak memory 248120 kb
Host smart-828159e9-2305-420b-8375-6577e40c7cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982821152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.2982821152
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.1654149418
Short name T479
Test name
Test status
Simulation time 3429284537 ps
CPU time 16.19 seconds
Started Aug 06 05:31:58 PM PDT 24
Finished Aug 06 05:32:14 PM PDT 24
Peak memory 241660 kb
Host smart-20e7cbff-b20b-439f-a7e1-06305ed1f559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654149418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
1654149418
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.3506139508
Short name T955
Test name
Test status
Simulation time 998413122737 ps
CPU time 3210.48 seconds
Started Aug 06 05:31:45 PM PDT 24
Finished Aug 06 06:25:16 PM PDT 24
Peak memory 344536 kb
Host smart-96842fc6-f121-4032-98fe-ba8a71f2dbb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506139508 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.3506139508
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.3150316558
Short name T824
Test name
Test status
Simulation time 2887936219 ps
CPU time 19.84 seconds
Started Aug 06 05:31:49 PM PDT 24
Finished Aug 06 05:32:09 PM PDT 24
Peak memory 242152 kb
Host smart-ad361cd1-8f4d-4789-9733-15c8f5fb6c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150316558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.3150316558
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.1002685969
Short name T456
Test name
Test status
Simulation time 255990678 ps
CPU time 7.13 seconds
Started Aug 06 05:36:30 PM PDT 24
Finished Aug 06 05:36:37 PM PDT 24
Peak memory 242172 kb
Host smart-2cce4481-033c-4e2c-8964-a30b93f538d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002685969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1002685969
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.2579266439
Short name T287
Test name
Test status
Simulation time 868566914341 ps
CPU time 1954.8 seconds
Started Aug 06 05:36:46 PM PDT 24
Finished Aug 06 06:09:21 PM PDT 24
Peak memory 364524 kb
Host smart-877f105e-fe90-4f76-bfdb-1183a155aa31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579266439 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.2579266439
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.2636793210
Short name T742
Test name
Test status
Simulation time 138947292 ps
CPU time 3.79 seconds
Started Aug 06 05:36:43 PM PDT 24
Finished Aug 06 05:36:47 PM PDT 24
Peak memory 241992 kb
Host smart-b77b56ec-43af-473a-a743-3441e9da1225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636793210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.2636793210
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.2847755388
Short name T764
Test name
Test status
Simulation time 583931085 ps
CPU time 14.92 seconds
Started Aug 06 05:36:43 PM PDT 24
Finished Aug 06 05:36:59 PM PDT 24
Peak memory 242208 kb
Host smart-e46e811c-dbff-4a28-a185-7d363d694f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847755388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.2847755388
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.3999268860
Short name T283
Test name
Test status
Simulation time 346269841916 ps
CPU time 1696.59 seconds
Started Aug 06 05:36:43 PM PDT 24
Finished Aug 06 06:05:00 PM PDT 24
Peak memory 623808 kb
Host smart-13769232-1c18-42de-99f9-9025cc51cd25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999268860 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.3999268860
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.1507944458
Short name T468
Test name
Test status
Simulation time 92365133 ps
CPU time 3.49 seconds
Started Aug 06 05:36:44 PM PDT 24
Finished Aug 06 05:36:47 PM PDT 24
Peak memory 241892 kb
Host smart-e93f755d-eb0c-460d-95c7-00e0c05d4f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507944458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1507944458
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.2106544108
Short name T1058
Test name
Test status
Simulation time 2904842712 ps
CPU time 8.1 seconds
Started Aug 06 05:36:44 PM PDT 24
Finished Aug 06 05:36:53 PM PDT 24
Peak memory 242272 kb
Host smart-e854b6fc-9bc5-49ed-bec1-2cfaf992924d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106544108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.2106544108
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.353737597
Short name T314
Test name
Test status
Simulation time 434308218486 ps
CPU time 1312.04 seconds
Started Aug 06 05:36:44 PM PDT 24
Finished Aug 06 05:58:36 PM PDT 24
Peak memory 286084 kb
Host smart-c873ab3a-4f54-4005-98f8-cd209e754ad8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353737597 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.353737597
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.339607272
Short name T534
Test name
Test status
Simulation time 2543229660 ps
CPU time 6.98 seconds
Started Aug 06 05:36:44 PM PDT 24
Finished Aug 06 05:36:51 PM PDT 24
Peak memory 242076 kb
Host smart-06404624-65ba-4849-ab92-f6c9be4dfb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339607272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.339607272
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.413886985
Short name T823
Test name
Test status
Simulation time 272147623 ps
CPU time 6.18 seconds
Started Aug 06 05:36:43 PM PDT 24
Finished Aug 06 05:36:50 PM PDT 24
Peak memory 242224 kb
Host smart-1dcf2131-bf6e-401d-af7a-47a22be23fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413886985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.413886985
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.3736966182
Short name T1107
Test name
Test status
Simulation time 76776795230 ps
CPU time 473.42 seconds
Started Aug 06 05:36:43 PM PDT 24
Finished Aug 06 05:44:37 PM PDT 24
Peak memory 256940 kb
Host smart-f165a2ee-c18b-4a07-b89a-1d24f4d5fed9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736966182 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.3736966182
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.3032103119
Short name T463
Test name
Test status
Simulation time 2319763120 ps
CPU time 6.98 seconds
Started Aug 06 05:36:45 PM PDT 24
Finished Aug 06 05:36:52 PM PDT 24
Peak memory 242036 kb
Host smart-32a7c2b4-74ef-46af-812c-82d894cb8c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032103119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.3032103119
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.1974285539
Short name T92
Test name
Test status
Simulation time 146086088 ps
CPU time 6.73 seconds
Started Aug 06 05:36:45 PM PDT 24
Finished Aug 06 05:36:52 PM PDT 24
Peak memory 242204 kb
Host smart-c8f346cb-749d-4c3b-9b6b-868be9767295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974285539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.1974285539
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.2050912139
Short name T146
Test name
Test status
Simulation time 126272585531 ps
CPU time 926.6 seconds
Started Aug 06 05:36:48 PM PDT 24
Finished Aug 06 05:52:15 PM PDT 24
Peak memory 317664 kb
Host smart-171d960f-8cd4-4730-86b1-05e1239aff95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050912139 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.2050912139
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.1522084820
Short name T571
Test name
Test status
Simulation time 2465139629 ps
CPU time 24.84 seconds
Started Aug 06 05:36:44 PM PDT 24
Finished Aug 06 05:37:09 PM PDT 24
Peak memory 241848 kb
Host smart-49607984-89a5-4439-8fb8-67b6a50d40fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522084820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.1522084820
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.186780857
Short name T244
Test name
Test status
Simulation time 124624931506 ps
CPU time 974.25 seconds
Started Aug 06 05:36:45 PM PDT 24
Finished Aug 06 05:52:59 PM PDT 24
Peak memory 260092 kb
Host smart-e4f25310-a7f8-40f3-88f6-b3a45ca1f54d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186780857 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.186780857
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.3136464935
Short name T1148
Test name
Test status
Simulation time 268997355 ps
CPU time 3.66 seconds
Started Aug 06 05:36:46 PM PDT 24
Finished Aug 06 05:36:49 PM PDT 24
Peak memory 242036 kb
Host smart-cfd353cf-9f9c-44f7-81a8-b805f834357e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136464935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.3136464935
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.3333169441
Short name T664
Test name
Test status
Simulation time 652771926 ps
CPU time 10.76 seconds
Started Aug 06 05:36:46 PM PDT 24
Finished Aug 06 05:36:57 PM PDT 24
Peak memory 242024 kb
Host smart-00b39638-86f0-4b6d-8a23-04037bf5c3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333169441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3333169441
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.300337933
Short name T545
Test name
Test status
Simulation time 230742605 ps
CPU time 4.48 seconds
Started Aug 06 05:36:48 PM PDT 24
Finished Aug 06 05:36:52 PM PDT 24
Peak memory 242084 kb
Host smart-f18ae54b-0a44-47f6-a05d-173f699beb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300337933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.300337933
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.1297986174
Short name T55
Test name
Test status
Simulation time 459078291 ps
CPU time 4.76 seconds
Started Aug 06 05:36:46 PM PDT 24
Finished Aug 06 05:36:50 PM PDT 24
Peak memory 241992 kb
Host smart-11e48d58-f397-4ee4-ac76-f0e98543adae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297986174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.1297986174
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.1592572358
Short name T872
Test name
Test status
Simulation time 3461020084 ps
CPU time 12.21 seconds
Started Aug 06 05:36:44 PM PDT 24
Finished Aug 06 05:36:56 PM PDT 24
Peak memory 242528 kb
Host smart-b17ecc73-7035-47ba-b777-f1987e3adffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592572358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.1592572358
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.3780233532
Short name T18
Test name
Test status
Simulation time 253490588336 ps
CPU time 1544.87 seconds
Started Aug 06 05:36:48 PM PDT 24
Finished Aug 06 06:02:33 PM PDT 24
Peak memory 322524 kb
Host smart-df07da53-28c1-45d4-b7ad-f97df55f7ca7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780233532 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.3780233532
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.2560359951
Short name T660
Test name
Test status
Simulation time 2751428578 ps
CPU time 5.87 seconds
Started Aug 06 05:36:46 PM PDT 24
Finished Aug 06 05:36:52 PM PDT 24
Peak memory 242000 kb
Host smart-e37ad3db-6176-4579-ae44-321f16a8a523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560359951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.2560359951
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.1268328627
Short name T140
Test name
Test status
Simulation time 37462913073 ps
CPU time 1050.56 seconds
Started Aug 06 05:36:46 PM PDT 24
Finished Aug 06 05:54:17 PM PDT 24
Peak memory 412664 kb
Host smart-88509104-d8a6-4a1e-913f-9f123d437217
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268328627 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.1268328627
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.2617947751
Short name T1115
Test name
Test status
Simulation time 668399743 ps
CPU time 2.33 seconds
Started Aug 06 05:32:00 PM PDT 24
Finished Aug 06 05:32:03 PM PDT 24
Peak memory 240876 kb
Host smart-6a60a3df-507f-453d-a7fa-82c208cdff03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617947751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.2617947751
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.1710159852
Short name T414
Test name
Test status
Simulation time 10845569558 ps
CPU time 30.61 seconds
Started Aug 06 05:32:04 PM PDT 24
Finished Aug 06 05:32:34 PM PDT 24
Peak memory 248676 kb
Host smart-f5a48698-a387-469b-bf0a-3be388131379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710159852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.1710159852
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.2598773466
Short name T80
Test name
Test status
Simulation time 1018618874 ps
CPU time 19.2 seconds
Started Aug 06 05:32:00 PM PDT 24
Finished Aug 06 05:32:19 PM PDT 24
Peak memory 248656 kb
Host smart-a6e82a8e-9b28-48c1-9536-65a9b166de5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598773466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.2598773466
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.1589047601
Short name T1016
Test name
Test status
Simulation time 5695137239 ps
CPU time 45.36 seconds
Started Aug 06 05:32:01 PM PDT 24
Finished Aug 06 05:32:47 PM PDT 24
Peak memory 253276 kb
Host smart-dcd2b08b-8f7a-4915-b7d4-02b1f86250f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589047601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.1589047601
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.774533289
Short name T1036
Test name
Test status
Simulation time 1174675786 ps
CPU time 39.51 seconds
Started Aug 06 05:32:07 PM PDT 24
Finished Aug 06 05:32:47 PM PDT 24
Peak memory 242420 kb
Host smart-bdce0e8e-76c2-4c3b-b0ce-de63872d5d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774533289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.774533289
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.3227730010
Short name T362
Test name
Test status
Simulation time 6814963133 ps
CPU time 22.21 seconds
Started Aug 06 05:32:00 PM PDT 24
Finished Aug 06 05:32:23 PM PDT 24
Peak memory 242036 kb
Host smart-c9682b60-e3e6-4f81-a366-e927d27bf785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227730010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.3227730010
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.3238351319
Short name T649
Test name
Test status
Simulation time 367961294 ps
CPU time 9.11 seconds
Started Aug 06 05:32:00 PM PDT 24
Finished Aug 06 05:32:09 PM PDT 24
Peak memory 241872 kb
Host smart-1cb7da5a-b983-4063-a193-9584842c6e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238351319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3238351319
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.1361430560
Short name T930
Test name
Test status
Simulation time 1219734556 ps
CPU time 9.98 seconds
Started Aug 06 05:32:00 PM PDT 24
Finished Aug 06 05:32:10 PM PDT 24
Peak memory 248644 kb
Host smart-6d1c16e5-358c-47b3-af8d-8327cf75d86e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1361430560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.1361430560
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.4063635911
Short name T524
Test name
Test status
Simulation time 1914894384 ps
CPU time 5.61 seconds
Started Aug 06 05:31:59 PM PDT 24
Finished Aug 06 05:32:04 PM PDT 24
Peak memory 241924 kb
Host smart-928626a6-7a67-4ab6-b708-958945039f15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063635911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.4063635911
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.577256309
Short name T961
Test name
Test status
Simulation time 475985804 ps
CPU time 9.47 seconds
Started Aug 06 05:32:00 PM PDT 24
Finished Aug 06 05:32:10 PM PDT 24
Peak memory 242000 kb
Host smart-61698909-9e87-4d72-a98c-f050a164f85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577256309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.577256309
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.2253743908
Short name T1046
Test name
Test status
Simulation time 44045074830 ps
CPU time 507.74 seconds
Started Aug 06 05:31:59 PM PDT 24
Finished Aug 06 05:40:27 PM PDT 24
Peak memory 258168 kb
Host smart-602e8c2e-dee7-4320-b4d0-1b44505a2c4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253743908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
2253743908
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.720721363
Short name T97
Test name
Test status
Simulation time 3443974204 ps
CPU time 46.89 seconds
Started Aug 06 05:32:00 PM PDT 24
Finished Aug 06 05:32:47 PM PDT 24
Peak memory 242100 kb
Host smart-d6dd222a-5a45-4df5-a684-6ec88ac65b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720721363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.720721363
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.3316308158
Short name T1063
Test name
Test status
Simulation time 209019571 ps
CPU time 3.92 seconds
Started Aug 06 05:36:46 PM PDT 24
Finished Aug 06 05:36:50 PM PDT 24
Peak memory 242300 kb
Host smart-da0ad909-e726-4760-bb6f-3ec65997f655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316308158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.3316308158
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.1131486431
Short name T480
Test name
Test status
Simulation time 3140159128 ps
CPU time 10.34 seconds
Started Aug 06 05:37:00 PM PDT 24
Finished Aug 06 05:37:11 PM PDT 24
Peak memory 241964 kb
Host smart-54775822-c6c3-49bb-8bb9-171c8c5e2e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131486431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.1131486431
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.2133535607
Short name T308
Test name
Test status
Simulation time 168749172731 ps
CPU time 1019.62 seconds
Started Aug 06 05:36:58 PM PDT 24
Finished Aug 06 05:53:58 PM PDT 24
Peak memory 574480 kb
Host smart-d1b9d257-b12d-430e-83d3-c6f756d1fc53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133535607 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.2133535607
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.1089292238
Short name T914
Test name
Test status
Simulation time 90205018 ps
CPU time 3.62 seconds
Started Aug 06 05:36:59 PM PDT 24
Finished Aug 06 05:37:03 PM PDT 24
Peak memory 242384 kb
Host smart-47088d22-9ce4-4dc4-b1b0-fdd1d129293f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089292238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.1089292238
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.3471381220
Short name T441
Test name
Test status
Simulation time 13270050496 ps
CPU time 28.56 seconds
Started Aug 06 05:37:07 PM PDT 24
Finished Aug 06 05:37:35 PM PDT 24
Peak memory 241992 kb
Host smart-2ce62665-4ca5-4e25-a797-59b73738282e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471381220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.3471381220
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2039763470
Short name T1181
Test name
Test status
Simulation time 304789930089 ps
CPU time 1864.75 seconds
Started Aug 06 05:36:57 PM PDT 24
Finished Aug 06 06:08:02 PM PDT 24
Peak memory 347008 kb
Host smart-3ce50509-b1e7-4547-978f-5585708156d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039763470 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.2039763470
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.204611430
Short name T806
Test name
Test status
Simulation time 100256976 ps
CPU time 3.22 seconds
Started Aug 06 05:36:57 PM PDT 24
Finished Aug 06 05:37:00 PM PDT 24
Peak memory 242420 kb
Host smart-2ba3077f-30ee-4dd8-bcab-0dc4cd8a0bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204611430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.204611430
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.3058500470
Short name T378
Test name
Test status
Simulation time 195223614 ps
CPU time 4 seconds
Started Aug 06 05:37:07 PM PDT 24
Finished Aug 06 05:37:11 PM PDT 24
Peak memory 242284 kb
Host smart-58fc939f-d49f-4cae-b5b4-15ce803a1396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058500470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.3058500470
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.3774168355
Short name T671
Test name
Test status
Simulation time 457609661 ps
CPU time 4.97 seconds
Started Aug 06 05:37:04 PM PDT 24
Finished Aug 06 05:37:09 PM PDT 24
Peak memory 242220 kb
Host smart-f40b73a0-f375-46fa-add3-7d4e2f4ac49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774168355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.3774168355
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.2786673727
Short name T779
Test name
Test status
Simulation time 169797717 ps
CPU time 4.53 seconds
Started Aug 06 05:36:57 PM PDT 24
Finished Aug 06 05:37:01 PM PDT 24
Peak memory 241940 kb
Host smart-a73c6494-abb3-47cc-9956-5a8adfdb1d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786673727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.2786673727
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.293680426
Short name T640
Test name
Test status
Simulation time 245703366 ps
CPU time 4.19 seconds
Started Aug 06 05:37:07 PM PDT 24
Finished Aug 06 05:37:11 PM PDT 24
Peak memory 242164 kb
Host smart-8066579e-11c0-49da-a368-9270cb799d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293680426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.293680426
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.1854612061
Short name T871
Test name
Test status
Simulation time 259797334 ps
CPU time 5.38 seconds
Started Aug 06 05:36:59 PM PDT 24
Finished Aug 06 05:37:04 PM PDT 24
Peak memory 241712 kb
Host smart-4047ce6e-3eca-4368-af23-08a2f534f0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854612061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1854612061
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.2006475817
Short name T262
Test name
Test status
Simulation time 192503026259 ps
CPU time 560.59 seconds
Started Aug 06 05:37:08 PM PDT 24
Finished Aug 06 05:46:29 PM PDT 24
Peak memory 283580 kb
Host smart-b9e5a3cd-3103-4bd9-89e4-8c8d7ecb6956
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006475817 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.2006475817
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.3781140402
Short name T700
Test name
Test status
Simulation time 2031312642 ps
CPU time 5.56 seconds
Started Aug 06 05:37:08 PM PDT 24
Finished Aug 06 05:37:14 PM PDT 24
Peak memory 242216 kb
Host smart-efc66fe9-df99-4140-b192-90f0cb2821b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781140402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3781140402
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.3783054276
Short name T1157
Test name
Test status
Simulation time 647109828 ps
CPU time 18.55 seconds
Started Aug 06 05:37:06 PM PDT 24
Finished Aug 06 05:37:25 PM PDT 24
Peak memory 241832 kb
Host smart-2a064858-df15-46d5-a988-0fea8d6e69b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783054276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.3783054276
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.1460177432
Short name T13
Test name
Test status
Simulation time 48851690012 ps
CPU time 1387.88 seconds
Started Aug 06 05:37:08 PM PDT 24
Finished Aug 06 06:00:16 PM PDT 24
Peak memory 314128 kb
Host smart-88146290-0e16-4c46-aeca-825c5c171190
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460177432 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.1460177432
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.1604844267
Short name T604
Test name
Test status
Simulation time 1940929231 ps
CPU time 6.59 seconds
Started Aug 06 05:37:06 PM PDT 24
Finished Aug 06 05:37:13 PM PDT 24
Peak memory 242040 kb
Host smart-147b1c6d-e1e4-4367-b31a-9a9b7199e535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604844267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.1604844267
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.2644479524
Short name T143
Test name
Test status
Simulation time 436156504 ps
CPU time 7.91 seconds
Started Aug 06 05:37:08 PM PDT 24
Finished Aug 06 05:37:16 PM PDT 24
Peak memory 242476 kb
Host smart-de9f40cb-fdb8-4075-8040-3df281670822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644479524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.2644479524
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.476920967
Short name T15
Test name
Test status
Simulation time 279302527555 ps
CPU time 1661.47 seconds
Started Aug 06 05:37:06 PM PDT 24
Finished Aug 06 06:04:48 PM PDT 24
Peak memory 272916 kb
Host smart-967b7736-71b2-496a-8ffc-d8394f95cf29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476920967 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.476920967
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.254819232
Short name T1135
Test name
Test status
Simulation time 156542158 ps
CPU time 4.11 seconds
Started Aug 06 05:37:07 PM PDT 24
Finished Aug 06 05:37:11 PM PDT 24
Peak memory 242320 kb
Host smart-eaf6abd7-548a-4d45-9a08-45d6612500cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254819232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.254819232
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.3351444958
Short name T523
Test name
Test status
Simulation time 3703818259 ps
CPU time 15.4 seconds
Started Aug 06 05:37:11 PM PDT 24
Finished Aug 06 05:37:26 PM PDT 24
Peak memory 241892 kb
Host smart-b8d9dce1-cc21-42af-8dd6-e29e5fa13c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351444958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.3351444958
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.2655114260
Short name T225
Test name
Test status
Simulation time 410899637 ps
CPU time 3.41 seconds
Started Aug 06 05:37:07 PM PDT 24
Finished Aug 06 05:37:11 PM PDT 24
Peak memory 242372 kb
Host smart-7ba5b7bb-b7f7-4f65-8764-9616873ed634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655114260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.2655114260
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.107685850
Short name T817
Test name
Test status
Simulation time 2547597602 ps
CPU time 6.17 seconds
Started Aug 06 05:37:07 PM PDT 24
Finished Aug 06 05:37:13 PM PDT 24
Peak memory 242000 kb
Host smart-e3fe67e9-93ed-404e-86de-8215a11fd415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107685850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.107685850
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.394152309
Short name T919
Test name
Test status
Simulation time 236644849 ps
CPU time 4.8 seconds
Started Aug 06 05:37:06 PM PDT 24
Finished Aug 06 05:37:11 PM PDT 24
Peak memory 242128 kb
Host smart-e9383843-d08c-41c3-af1f-503437152f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394152309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.394152309
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.1387257869
Short name T260
Test name
Test status
Simulation time 681436762 ps
CPU time 9.02 seconds
Started Aug 06 05:37:07 PM PDT 24
Finished Aug 06 05:37:16 PM PDT 24
Peak memory 241888 kb
Host smart-c14157f3-6626-41c9-9da4-27919a6bb787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387257869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.1387257869
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.186168551
Short name T1005
Test name
Test status
Simulation time 59010158162 ps
CPU time 389.87 seconds
Started Aug 06 05:37:07 PM PDT 24
Finished Aug 06 05:43:37 PM PDT 24
Peak memory 256976 kb
Host smart-49553a34-2c77-4fe7-a211-2fa44111290d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186168551 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.186168551
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.358291695
Short name T626
Test name
Test status
Simulation time 256353000 ps
CPU time 2.11 seconds
Started Aug 06 05:31:59 PM PDT 24
Finished Aug 06 05:32:01 PM PDT 24
Peak memory 240816 kb
Host smart-788d0e8c-d724-4597-b768-d62fada48537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358291695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.358291695
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.819504144
Short name T1145
Test name
Test status
Simulation time 14402297073 ps
CPU time 24.57 seconds
Started Aug 06 05:32:07 PM PDT 24
Finished Aug 06 05:32:32 PM PDT 24
Peak memory 243388 kb
Host smart-19454270-1e1b-487b-8266-9838646c2135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819504144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.819504144
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.1252112046
Short name T591
Test name
Test status
Simulation time 4534541213 ps
CPU time 21.22 seconds
Started Aug 06 05:31:58 PM PDT 24
Finished Aug 06 05:32:19 PM PDT 24
Peak memory 242144 kb
Host smart-b8a1249f-84b8-4869-9e57-0722785319c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252112046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.1252112046
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.1026602060
Short name T832
Test name
Test status
Simulation time 420521118 ps
CPU time 6.64 seconds
Started Aug 06 05:31:59 PM PDT 24
Finished Aug 06 05:32:05 PM PDT 24
Peak memory 241960 kb
Host smart-f817aa29-7e27-421e-9d0a-b1ab1fbcbf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026602060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.1026602060
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.4005775795
Short name T214
Test name
Test status
Simulation time 132494151 ps
CPU time 3.43 seconds
Started Aug 06 05:31:58 PM PDT 24
Finished Aug 06 05:32:01 PM PDT 24
Peak memory 242376 kb
Host smart-575cb7f3-1193-4bf8-bf11-5385217ccf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005775795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.4005775795
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.228727101
Short name T1095
Test name
Test status
Simulation time 737161472 ps
CPU time 10.19 seconds
Started Aug 06 05:32:00 PM PDT 24
Finished Aug 06 05:32:11 PM PDT 24
Peak memory 241984 kb
Host smart-e4ab6ec5-92e0-478c-8579-ae9fbb3913b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228727101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.228727101
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.2821624872
Short name T454
Test name
Test status
Simulation time 683592504 ps
CPU time 17.93 seconds
Started Aug 06 05:32:01 PM PDT 24
Finished Aug 06 05:32:19 PM PDT 24
Peak memory 248564 kb
Host smart-9f993e6a-e2e8-4d7b-b09e-9082db0d45c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821624872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2821624872
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.2119079381
Short name T399
Test name
Test status
Simulation time 143762540 ps
CPU time 3.23 seconds
Started Aug 06 05:32:03 PM PDT 24
Finished Aug 06 05:32:06 PM PDT 24
Peak memory 241792 kb
Host smart-d7d7a660-4dc0-443d-9497-dc6bd6ce8644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119079381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2119079381
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.3261683975
Short name T405
Test name
Test status
Simulation time 2782984522 ps
CPU time 22.75 seconds
Started Aug 06 05:32:02 PM PDT 24
Finished Aug 06 05:32:25 PM PDT 24
Peak memory 242412 kb
Host smart-85c10ff8-3627-4be1-80cc-c1835770e92b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261683975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.3261683975
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.1445992602
Short name T676
Test name
Test status
Simulation time 425374156 ps
CPU time 4.11 seconds
Started Aug 06 05:32:01 PM PDT 24
Finished Aug 06 05:32:05 PM PDT 24
Peak memory 248148 kb
Host smart-c0379fe6-4939-444d-8a91-c882034fc672
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445992602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.1445992602
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.1433425196
Short name T691
Test name
Test status
Simulation time 250498364 ps
CPU time 8.22 seconds
Started Aug 06 05:31:59 PM PDT 24
Finished Aug 06 05:32:07 PM PDT 24
Peak memory 241952 kb
Host smart-c82dfef4-098a-44b9-a803-ac2617e7a257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433425196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.1433425196
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.858360501
Short name T1174
Test name
Test status
Simulation time 21729653097 ps
CPU time 194.22 seconds
Started Aug 06 05:32:00 PM PDT 24
Finished Aug 06 05:35:15 PM PDT 24
Peak memory 278160 kb
Host smart-5722f183-e530-4637-b6a1-1aeaa4dc9ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858360501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.858360501
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.2529403432
Short name T17
Test name
Test status
Simulation time 108620298914 ps
CPU time 931.5 seconds
Started Aug 06 05:31:58 PM PDT 24
Finished Aug 06 05:47:30 PM PDT 24
Peak memory 259092 kb
Host smart-bf7f6269-9979-41c8-beac-327dd747175b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529403432 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.2529403432
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.3424451657
Short name T831
Test name
Test status
Simulation time 916275199 ps
CPU time 17.95 seconds
Started Aug 06 05:32:02 PM PDT 24
Finished Aug 06 05:32:20 PM PDT 24
Peak memory 248500 kb
Host smart-b33c7127-c53c-46de-b694-abb933a9d950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424451657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.3424451657
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.2699894413
Short name T1052
Test name
Test status
Simulation time 313733088 ps
CPU time 5.26 seconds
Started Aug 06 05:37:10 PM PDT 24
Finished Aug 06 05:37:15 PM PDT 24
Peak memory 242056 kb
Host smart-963fcb35-2c27-4b33-9402-1df8120e8a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699894413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.2699894413
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.1701010989
Short name T801
Test name
Test status
Simulation time 10276019768 ps
CPU time 31.93 seconds
Started Aug 06 05:37:11 PM PDT 24
Finished Aug 06 05:37:43 PM PDT 24
Peak memory 241828 kb
Host smart-7c69ff11-f3c4-4d14-9334-77da306e0e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701010989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.1701010989
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.2319837525
Short name T536
Test name
Test status
Simulation time 2388770035 ps
CPU time 5.17 seconds
Started Aug 06 05:37:08 PM PDT 24
Finished Aug 06 05:37:13 PM PDT 24
Peak memory 242420 kb
Host smart-bc30ec13-5c32-4874-ad16-a8e99b97de27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319837525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.2319837525
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.2490158257
Short name T175
Test name
Test status
Simulation time 182652278 ps
CPU time 3.53 seconds
Started Aug 06 05:37:10 PM PDT 24
Finished Aug 06 05:37:14 PM PDT 24
Peak memory 242556 kb
Host smart-1e8330b5-c305-4584-a401-76592b0f8e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490158257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.2490158257
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.2473621791
Short name T279
Test name
Test status
Simulation time 485860751302 ps
CPU time 1236.05 seconds
Started Aug 06 05:37:11 PM PDT 24
Finished Aug 06 05:57:47 PM PDT 24
Peak memory 404012 kb
Host smart-64100301-fedc-440f-af3b-3f04dd4eaee7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473621791 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.2473621791
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.3325562175
Short name T193
Test name
Test status
Simulation time 91265262 ps
CPU time 3.49 seconds
Started Aug 06 05:37:10 PM PDT 24
Finished Aug 06 05:37:13 PM PDT 24
Peak memory 242432 kb
Host smart-d97e3329-bb09-4af2-8ea2-62c4fe2a6b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325562175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.3325562175
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.1756612953
Short name T687
Test name
Test status
Simulation time 376915278 ps
CPU time 4.69 seconds
Started Aug 06 05:37:09 PM PDT 24
Finished Aug 06 05:37:14 PM PDT 24
Peak memory 241880 kb
Host smart-4f4fc48b-fb01-4956-874e-d34554f0ddb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756612953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.1756612953
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.3744158927
Short name T944
Test name
Test status
Simulation time 71317758458 ps
CPU time 433.72 seconds
Started Aug 06 05:37:08 PM PDT 24
Finished Aug 06 05:44:21 PM PDT 24
Peak memory 278920 kb
Host smart-41659e3d-5862-4466-8de5-c611f67a3767
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744158927 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.3744158927
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.2562268747
Short name T184
Test name
Test status
Simulation time 94202156 ps
CPU time 3.18 seconds
Started Aug 06 05:37:08 PM PDT 24
Finished Aug 06 05:37:11 PM PDT 24
Peak memory 242140 kb
Host smart-ac7dff56-7b0c-4a69-bebe-e3ce903f20c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562268747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.2562268747
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.542167279
Short name T618
Test name
Test status
Simulation time 2415248899 ps
CPU time 5.6 seconds
Started Aug 06 05:37:10 PM PDT 24
Finished Aug 06 05:37:15 PM PDT 24
Peak memory 242244 kb
Host smart-cbd033a0-b57f-4a98-8a39-e9341fa63167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542167279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.542167279
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.3718369269
Short name T722
Test name
Test status
Simulation time 124615662 ps
CPU time 4.31 seconds
Started Aug 06 05:37:11 PM PDT 24
Finished Aug 06 05:37:15 PM PDT 24
Peak memory 241980 kb
Host smart-0bc35c38-433b-48c4-8e41-73644be712f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718369269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.3718369269
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.4293566045
Short name T181
Test name
Test status
Simulation time 959045819 ps
CPU time 14.4 seconds
Started Aug 06 05:37:11 PM PDT 24
Finished Aug 06 05:37:25 PM PDT 24
Peak memory 242472 kb
Host smart-29600e82-33fb-4219-9f77-238b6ac535b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293566045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.4293566045
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.1730760617
Short name T758
Test name
Test status
Simulation time 266958711832 ps
CPU time 787.57 seconds
Started Aug 06 05:37:11 PM PDT 24
Finished Aug 06 05:50:18 PM PDT 24
Peak memory 297932 kb
Host smart-b6c716c4-5535-4eb9-97b0-709145a4549d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730760617 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.1730760617
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.577237113
Short name T1027
Test name
Test status
Simulation time 218316424 ps
CPU time 3.1 seconds
Started Aug 06 05:37:09 PM PDT 24
Finished Aug 06 05:37:12 PM PDT 24
Peak memory 242120 kb
Host smart-e947ab35-ddf6-445c-a131-a33e91752f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577237113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.577237113
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.1261577065
Short name T526
Test name
Test status
Simulation time 346030537 ps
CPU time 3.6 seconds
Started Aug 06 05:37:08 PM PDT 24
Finished Aug 06 05:37:12 PM PDT 24
Peak memory 242012 kb
Host smart-a7e92758-5ff4-4f90-ae1e-9221d9e7f80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261577065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.1261577065
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.1943408862
Short name T918
Test name
Test status
Simulation time 85027424395 ps
CPU time 1962.44 seconds
Started Aug 06 05:37:10 PM PDT 24
Finished Aug 06 06:09:53 PM PDT 24
Peak memory 484984 kb
Host smart-0ba240a6-f63b-4518-9fd6-bf52f1b78393
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943408862 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.1943408862
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.2743424033
Short name T223
Test name
Test status
Simulation time 142871190 ps
CPU time 3.68 seconds
Started Aug 06 05:37:10 PM PDT 24
Finished Aug 06 05:37:14 PM PDT 24
Peak memory 242376 kb
Host smart-4b3a7ef3-c923-4745-81b5-1c39994d604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743424033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.2743424033
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.309418209
Short name T674
Test name
Test status
Simulation time 1137174954563 ps
CPU time 1982.11 seconds
Started Aug 06 05:37:10 PM PDT 24
Finished Aug 06 06:10:13 PM PDT 24
Peak memory 281552 kb
Host smart-f9141ec9-8abd-40fa-9946-e8107ec2dd5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309418209 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.309418209
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.1181638545
Short name T781
Test name
Test status
Simulation time 571850014 ps
CPU time 3.64 seconds
Started Aug 06 05:36:58 PM PDT 24
Finished Aug 06 05:37:02 PM PDT 24
Peak memory 242120 kb
Host smart-f9ece558-7d6a-4ba7-8e26-4107577446d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181638545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.1181638545
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.2368396123
Short name T91
Test name
Test status
Simulation time 954741141 ps
CPU time 11.72 seconds
Started Aug 06 05:36:58 PM PDT 24
Finished Aug 06 05:37:09 PM PDT 24
Peak memory 241876 kb
Host smart-129cda1b-37a3-4f5d-a4b5-33bc65c2a626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368396123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.2368396123
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.4028429705
Short name T533
Test name
Test status
Simulation time 509746245 ps
CPU time 15.59 seconds
Started Aug 06 05:36:59 PM PDT 24
Finished Aug 06 05:37:15 PM PDT 24
Peak memory 242212 kb
Host smart-db2b888b-25fe-42c1-914e-ee727a4664c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028429705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.4028429705
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.4034855077
Short name T566
Test name
Test status
Simulation time 124433250 ps
CPU time 4.31 seconds
Started Aug 06 05:37:06 PM PDT 24
Finished Aug 06 05:37:10 PM PDT 24
Peak memory 241960 kb
Host smart-80f5d0c3-966d-4b4c-8c23-edd1ff3c3517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034855077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.4034855077
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.4170543399
Short name T845
Test name
Test status
Simulation time 841738931 ps
CPU time 23.33 seconds
Started Aug 06 05:37:13 PM PDT 24
Finished Aug 06 05:37:37 PM PDT 24
Peak memory 242144 kb
Host smart-68f023f1-655b-43e0-9816-8de1732e66f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170543399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.4170543399
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.3871139022
Short name T1109
Test name
Test status
Simulation time 127859596917 ps
CPU time 1827.26 seconds
Started Aug 06 05:37:15 PM PDT 24
Finished Aug 06 06:07:42 PM PDT 24
Peak memory 271100 kb
Host smart-f05b3410-f4c2-4506-a77a-31c7325d62c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871139022 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.3871139022
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.3979372685
Short name T1023
Test name
Test status
Simulation time 144432805 ps
CPU time 1.65 seconds
Started Aug 06 05:32:16 PM PDT 24
Finished Aug 06 05:32:18 PM PDT 24
Peak memory 240408 kb
Host smart-d71b06d1-8e28-4dd5-b604-7c21ab4c9ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979372685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.3979372685
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.1654828762
Short name T1025
Test name
Test status
Simulation time 1123729650 ps
CPU time 11.11 seconds
Started Aug 06 05:32:07 PM PDT 24
Finished Aug 06 05:32:18 PM PDT 24
Peak memory 242048 kb
Host smart-fc072145-da58-4b61-92e8-4f3d784209f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654828762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1654828762
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.244884784
Short name T130
Test name
Test status
Simulation time 376555073 ps
CPU time 5.3 seconds
Started Aug 06 05:32:08 PM PDT 24
Finished Aug 06 05:32:13 PM PDT 24
Peak memory 248584 kb
Host smart-32cc1c7c-ec37-479a-a57f-64bcf6dcedca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244884784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.244884784
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.2210059486
Short name T590
Test name
Test status
Simulation time 1374977401 ps
CPU time 19.06 seconds
Started Aug 06 05:32:03 PM PDT 24
Finished Aug 06 05:32:22 PM PDT 24
Peak memory 241988 kb
Host smart-9b91c74e-e9b6-4e47-9edb-a8e1090977c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210059486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.2210059486
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.344064563
Short name T1156
Test name
Test status
Simulation time 3485307537 ps
CPU time 37.31 seconds
Started Aug 06 05:32:04 PM PDT 24
Finished Aug 06 05:32:41 PM PDT 24
Peak memory 242368 kb
Host smart-2e46b8ca-83bb-47b4-b513-8566c5b507b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344064563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.344064563
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.3700334820
Short name T525
Test name
Test status
Simulation time 2690111039 ps
CPU time 5.56 seconds
Started Aug 06 05:32:04 PM PDT 24
Finished Aug 06 05:32:09 PM PDT 24
Peak memory 242304 kb
Host smart-d248d4cb-9ee1-4f77-854a-49af3fa55086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700334820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.3700334820
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.3287690062
Short name T697
Test name
Test status
Simulation time 7894448753 ps
CPU time 22.72 seconds
Started Aug 06 05:32:08 PM PDT 24
Finished Aug 06 05:32:30 PM PDT 24
Peak memory 245836 kb
Host smart-c447850f-50f6-41c7-bf14-cabf794a12eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287690062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.3287690062
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.3851188812
Short name T520
Test name
Test status
Simulation time 2232481378 ps
CPU time 15.98 seconds
Started Aug 06 05:32:01 PM PDT 24
Finished Aug 06 05:32:17 PM PDT 24
Peak memory 242236 kb
Host smart-30e6de97-424e-4056-a530-91f5eaede9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851188812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.3851188812
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.3596047791
Short name T548
Test name
Test status
Simulation time 227877037 ps
CPU time 3.81 seconds
Started Aug 06 05:32:04 PM PDT 24
Finished Aug 06 05:32:08 PM PDT 24
Peak memory 242244 kb
Host smart-4f2e9429-dfca-4155-89ac-37ccada61094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596047791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.3596047791
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.1448041874
Short name T517
Test name
Test status
Simulation time 2205578942 ps
CPU time 14.86 seconds
Started Aug 06 05:32:04 PM PDT 24
Finished Aug 06 05:32:19 PM PDT 24
Peak memory 241980 kb
Host smart-d332d8df-9fda-4d68-8681-ca296d77f722
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448041874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.1448041874
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.3602516362
Short name T876
Test name
Test status
Simulation time 940489864 ps
CPU time 8.89 seconds
Started Aug 06 05:32:15 PM PDT 24
Finished Aug 06 05:32:24 PM PDT 24
Peak memory 242284 kb
Host smart-ea0fa404-1b65-4347-b91c-95d1ea8a29ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3602516362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3602516362
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.1389131499
Short name T201
Test name
Test status
Simulation time 757700968 ps
CPU time 13.25 seconds
Started Aug 06 05:32:01 PM PDT 24
Finished Aug 06 05:32:14 PM PDT 24
Peak memory 242092 kb
Host smart-ed01072f-9a4e-4099-921d-2c99062b7696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389131499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.1389131499
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.1744349898
Short name T112
Test name
Test status
Simulation time 289033518 ps
CPU time 5.6 seconds
Started Aug 06 05:32:15 PM PDT 24
Finished Aug 06 05:32:21 PM PDT 24
Peak memory 241484 kb
Host smart-d0d1586a-c9f6-47b7-9931-1a0ad44b1a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744349898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
1744349898
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.195316611
Short name T680
Test name
Test status
Simulation time 40976026696 ps
CPU time 865.63 seconds
Started Aug 06 05:32:19 PM PDT 24
Finished Aug 06 05:46:45 PM PDT 24
Peak memory 248744 kb
Host smart-35202e91-cddc-4ede-ac87-383327895783
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195316611 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.195316611
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.1053739328
Short name T814
Test name
Test status
Simulation time 3692268762 ps
CPU time 37.86 seconds
Started Aug 06 05:32:15 PM PDT 24
Finished Aug 06 05:32:53 PM PDT 24
Peak memory 242112 kb
Host smart-3374d064-2798-44c4-8f37-f99a8fb83002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053739328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.1053739328
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.2651284714
Short name T561
Test name
Test status
Simulation time 275575574 ps
CPU time 3.98 seconds
Started Aug 06 05:37:16 PM PDT 24
Finished Aug 06 05:37:20 PM PDT 24
Peak memory 241964 kb
Host smart-64f09f31-7d7f-47e4-95ba-83ddf462245d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651284714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.2651284714
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.3053692938
Short name T1069
Test name
Test status
Simulation time 863586898 ps
CPU time 9.29 seconds
Started Aug 06 05:37:13 PM PDT 24
Finished Aug 06 05:37:22 PM PDT 24
Peak memory 242116 kb
Host smart-55dcd889-680a-46e1-b8c0-5a357ac6b178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053692938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3053692938
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.1882214948
Short name T766
Test name
Test status
Simulation time 354678964375 ps
CPU time 3576.44 seconds
Started Aug 06 05:37:15 PM PDT 24
Finished Aug 06 06:36:52 PM PDT 24
Peak memory 469220 kb
Host smart-076ad0ea-c0ca-4ad1-8352-7f975eac4314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882214948 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.1882214948
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.570417418
Short name T925
Test name
Test status
Simulation time 163898375 ps
CPU time 4.87 seconds
Started Aug 06 05:37:14 PM PDT 24
Finished Aug 06 05:37:19 PM PDT 24
Peak memory 242024 kb
Host smart-59c7e06c-9d74-4d75-a61b-4c357b3c62d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570417418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.570417418
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.2267231867
Short name T322
Test name
Test status
Simulation time 675988643 ps
CPU time 16.3 seconds
Started Aug 06 05:37:15 PM PDT 24
Finished Aug 06 05:37:31 PM PDT 24
Peak memory 241964 kb
Host smart-578bd1d0-eee5-49f3-84ec-060ab7d58490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267231867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.2267231867
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.1276875661
Short name T904
Test name
Test status
Simulation time 17049005770 ps
CPU time 404.37 seconds
Started Aug 06 05:37:15 PM PDT 24
Finished Aug 06 05:43:59 PM PDT 24
Peak memory 258912 kb
Host smart-d58979b4-4cf7-4a42-9f06-54a888726e1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276875661 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.1276875661
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.4285164152
Short name T917
Test name
Test status
Simulation time 2475400452 ps
CPU time 7.19 seconds
Started Aug 06 05:37:14 PM PDT 24
Finished Aug 06 05:37:22 PM PDT 24
Peak memory 241916 kb
Host smart-be9bc88f-7393-483e-88ee-e37f6df347b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285164152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.4285164152
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.3927504686
Short name T502
Test name
Test status
Simulation time 267192398 ps
CPU time 6.78 seconds
Started Aug 06 05:37:14 PM PDT 24
Finished Aug 06 05:37:21 PM PDT 24
Peak memory 241780 kb
Host smart-f23acd90-0974-4281-992b-0e53fe529773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927504686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3927504686
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.847027019
Short name T922
Test name
Test status
Simulation time 44457804496 ps
CPU time 262.11 seconds
Started Aug 06 05:37:14 PM PDT 24
Finished Aug 06 05:41:36 PM PDT 24
Peak memory 315176 kb
Host smart-5f934bef-7fab-4425-852d-b8c7959e5424
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847027019 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.847027019
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.3200939439
Short name T387
Test name
Test status
Simulation time 228603541 ps
CPU time 3.95 seconds
Started Aug 06 05:37:15 PM PDT 24
Finished Aug 06 05:37:19 PM PDT 24
Peak memory 242192 kb
Host smart-2efe7271-da00-4f7b-88e5-56bc57d51d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200939439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.3200939439
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.478486229
Short name T407
Test name
Test status
Simulation time 366126900 ps
CPU time 8.09 seconds
Started Aug 06 05:37:14 PM PDT 24
Finished Aug 06 05:37:23 PM PDT 24
Peak memory 241832 kb
Host smart-97e108a0-bb77-468d-a973-c42faf0e96d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478486229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.478486229
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.2945552829
Short name T928
Test name
Test status
Simulation time 169595332053 ps
CPU time 818.04 seconds
Started Aug 06 05:37:15 PM PDT 24
Finished Aug 06 05:50:53 PM PDT 24
Peak memory 313784 kb
Host smart-6ac9898e-d89f-475b-8ab0-33451afcfae5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945552829 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.2945552829
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.3052048096
Short name T474
Test name
Test status
Simulation time 244528253 ps
CPU time 3.81 seconds
Started Aug 06 05:37:15 PM PDT 24
Finished Aug 06 05:37:19 PM PDT 24
Peak memory 242040 kb
Host smart-9332772c-ac81-4083-a1c8-0759b87322f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052048096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.3052048096
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.2759544205
Short name T737
Test name
Test status
Simulation time 697044014 ps
CPU time 18.36 seconds
Started Aug 06 05:37:15 PM PDT 24
Finished Aug 06 05:37:34 PM PDT 24
Peak memory 241816 kb
Host smart-03e3a6f9-6c48-4ae8-b525-f6640607706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759544205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.2759544205
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.1869696656
Short name T557
Test name
Test status
Simulation time 110190337730 ps
CPU time 1772.65 seconds
Started Aug 06 05:37:14 PM PDT 24
Finished Aug 06 06:06:47 PM PDT 24
Peak memory 615080 kb
Host smart-a54fe550-804b-4e65-a8a1-9ca366b93b5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869696656 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.1869696656
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.1040265471
Short name T1030
Test name
Test status
Simulation time 114709226 ps
CPU time 3.28 seconds
Started Aug 06 05:37:14 PM PDT 24
Finished Aug 06 05:37:17 PM PDT 24
Peak memory 242144 kb
Host smart-a99ed27c-8021-403a-8712-9fc329103694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040265471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.1040265471
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.3524038950
Short name T734
Test name
Test status
Simulation time 313488799 ps
CPU time 3.42 seconds
Started Aug 06 05:37:12 PM PDT 24
Finished Aug 06 05:37:15 PM PDT 24
Peak memory 242000 kb
Host smart-7a45b282-2fe1-496a-b566-6fe9778428fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524038950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.3524038950
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.1718822606
Short name T683
Test name
Test status
Simulation time 247740648360 ps
CPU time 2434.74 seconds
Started Aug 06 05:37:17 PM PDT 24
Finished Aug 06 06:17:53 PM PDT 24
Peak memory 519076 kb
Host smart-f27a63f9-d639-4e1f-b2d7-d59821431b80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718822606 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.1718822606
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.3369258486
Short name T1091
Test name
Test status
Simulation time 2871068231 ps
CPU time 5.45 seconds
Started Aug 06 05:37:14 PM PDT 24
Finished Aug 06 05:37:20 PM PDT 24
Peak memory 242032 kb
Host smart-fc267633-6e84-40ce-8660-0078125c3565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369258486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.3369258486
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.2515594304
Short name T1026
Test name
Test status
Simulation time 182784375 ps
CPU time 4.7 seconds
Started Aug 06 05:37:16 PM PDT 24
Finished Aug 06 05:37:21 PM PDT 24
Peak memory 241960 kb
Host smart-7e1a1bac-3880-4bae-9082-61ba50a73bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515594304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.2515594304
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.2458736136
Short name T78
Test name
Test status
Simulation time 2135645342 ps
CPU time 4.76 seconds
Started Aug 06 05:37:10 PM PDT 24
Finished Aug 06 05:37:15 PM PDT 24
Peak memory 241960 kb
Host smart-52671893-464d-4182-9ac5-5bfcd4bfb908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458736136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2458736136
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.1627517098
Short name T323
Test name
Test status
Simulation time 332126659 ps
CPU time 5.16 seconds
Started Aug 06 05:37:21 PM PDT 24
Finished Aug 06 05:37:26 PM PDT 24
Peak memory 242012 kb
Host smart-7e3ca135-cbf0-48f5-8f65-5aedb960207c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627517098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.1627517098
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.1973853335
Short name T1138
Test name
Test status
Simulation time 67995233957 ps
CPU time 591.05 seconds
Started Aug 06 05:37:15 PM PDT 24
Finished Aug 06 05:47:06 PM PDT 24
Peak memory 269868 kb
Host smart-5bb52625-b486-457f-b867-ca6d93c47ce1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973853335 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.1973853335
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.4293729667
Short name T421
Test name
Test status
Simulation time 485702403 ps
CPU time 5.03 seconds
Started Aug 06 05:37:16 PM PDT 24
Finished Aug 06 05:37:21 PM PDT 24
Peak memory 242156 kb
Host smart-b91e9f3d-ea1f-4e97-a302-09b7b55f755e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293729667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.4293729667
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.122840266
Short name T12
Test name
Test status
Simulation time 134417419 ps
CPU time 4.97 seconds
Started Aug 06 05:37:33 PM PDT 24
Finished Aug 06 05:37:38 PM PDT 24
Peak memory 241916 kb
Host smart-941a12cd-3c35-4a13-ac8d-6d30185eca57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122840266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.122840266
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.2995839135
Short name T1049
Test name
Test status
Simulation time 642088375901 ps
CPU time 1116.84 seconds
Started Aug 06 05:37:32 PM PDT 24
Finished Aug 06 05:56:09 PM PDT 24
Peak memory 285952 kb
Host smart-cf0ea716-8917-4a78-8c56-1636545b0fb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995839135 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.2995839135
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.2842249883
Short name T398
Test name
Test status
Simulation time 450509828 ps
CPU time 4.92 seconds
Started Aug 06 05:37:35 PM PDT 24
Finished Aug 06 05:37:40 PM PDT 24
Peak memory 241956 kb
Host smart-9f7d2397-e4f1-4f98-b7d5-bdb87f549467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842249883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2842249883
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.3308293068
Short name T111
Test name
Test status
Simulation time 1936989485 ps
CPU time 14.86 seconds
Started Aug 06 05:37:39 PM PDT 24
Finished Aug 06 05:37:54 PM PDT 24
Peak memory 242264 kb
Host smart-e600d21a-3d94-4c6b-af01-afddf1599c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308293068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3308293068
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.1478832422
Short name T635
Test name
Test status
Simulation time 34550089908 ps
CPU time 730.19 seconds
Started Aug 06 05:37:35 PM PDT 24
Finished Aug 06 05:49:45 PM PDT 24
Peak memory 248768 kb
Host smart-52ca250e-a069-46b2-b101-e15670d624fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478832422 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.1478832422
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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