Summary for Variable keymgr_rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for keymgr_rd_en
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
3832 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T3 | 
4 | 
 | 
T4 | 
8 | 
| auto[1] | 
2444 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
2 | 
Summary for Variable secret2_lock
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for secret2_lock
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4274 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T2 | 
1 | 
 | 
T3 | 
6 | 
| auto[1] | 
2002 | 
1 | 
 | 
 | 
T6 | 
1 | 
 | 
T35 | 
1 | 
 | 
T21 | 
11 | 
Summary for Cross keymgr_output_conditions
Samples crossed: keymgr_rd_en secret2_lock
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for keymgr_output_conditions
Bins
| keymgr_rd_en | secret2_lock | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
2643 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T3 | 
4 | 
 | 
T4 | 
8 | 
| auto[0] | 
auto[1] | 
1189 | 
1 | 
 | 
 | 
T6 | 
1 | 
 | 
T35 | 
1 | 
 | 
T21 | 
8 | 
| auto[1] | 
auto[0] | 
1631 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
2 | 
| auto[1] | 
auto[1] | 
813 | 
1 | 
 | 
 | 
T21 | 
3 | 
 | 
T118 | 
1 | 
 | 
T123 | 
1 |