Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
lc_prog_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_lc_esc	2	0	2	100.00	100	1	1	0
lc_prog_req_during_otbn_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_otp_idle	2	0	2	100.00	100	1	1	2
lc_prog_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable lc_prog_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27258

1

T1

32

T2

4

T5

10

auto[1]

892

1

T24

5

T179

2

T33

2

---

Summary for Variable lc_prog_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27075

1

T1

32

T2

4

T5

10

auto[1]

1075

1

T24

8

T179

2

T33

1

---

Summary for Variable lc_prog_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lc_prog_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

28111

1

T1

32

T2

4

T5

10

lc_esc_on

39

1

T399

1

T400

1

T253

1

---

Summary for Variable lc_prog_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26306

1

T1

31

T2

3

T5

10

auto[1]

1844

1

T1

1

T2

1

T24

13

---

Summary for Variable lc_prog_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14960

1

T1

16

T2

2

T5

5

auto[1]

13190

1

T1

16

T2

2

T5

5

---

Summary for Variable lc_prog_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26234

1

T1

32

T2

4

T5

10

auto[1]

1916

1

T24

9

T33

3

T34

4

---

Summary for Variable lc_prog_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26342

1

T1

31

T2

4

T5

10

auto[1]

1808

1

T1

1

T24

14

T33

4