Summary for Variable keymgr_rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for keymgr_rd_en
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
3628 | 
1 | 
 | 
 | 
T1 | 
4 | 
 | 
T2 | 
3 | 
 | 
T3 | 
1 | 
| auto[1] | 
2453 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
Summary for Variable secret2_lock
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for secret2_lock
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4280 | 
1 | 
 | 
 | 
T1 | 
6 | 
 | 
T2 | 
4 | 
 | 
T3 | 
1 | 
| auto[1] | 
1801 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T10 | 
5 | 
 | 
T24 | 
7 | 
Summary for Cross keymgr_output_conditions
Samples crossed: keymgr_rd_en secret2_lock
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for keymgr_output_conditions
Bins
| keymgr_rd_en | secret2_lock | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
2551 | 
1 | 
 | 
 | 
T1 | 
4 | 
 | 
T2 | 
3 | 
 | 
T3 | 
1 | 
| auto[0] | 
auto[1] | 
1077 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T10 | 
4 | 
 | 
T24 | 
3 | 
| auto[1] | 
auto[0] | 
1729 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
| auto[1] | 
auto[1] | 
724 | 
1 | 
 | 
 | 
T10 | 
1 | 
 | 
T24 | 
4 | 
 | 
T63 | 
1 |