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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.86 93.79 96.30 95.55 91.65 97.05 96.34 93.35


Total test records in report: 1319
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T1261 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.2236344107 Aug 11 07:02:10 PM PDT 24 Aug 11 07:02:11 PM PDT 24 39290710 ps
T1262 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2900878696 Aug 11 07:02:08 PM PDT 24 Aug 11 07:02:11 PM PDT 24 421337861 ps
T318 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1856930407 Aug 11 07:02:10 PM PDT 24 Aug 11 07:02:11 PM PDT 24 40935733 ps
T1263 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2172049130 Aug 11 07:01:47 PM PDT 24 Aug 11 07:01:49 PM PDT 24 41435241 ps
T1264 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3755294055 Aug 11 07:01:56 PM PDT 24 Aug 11 07:01:58 PM PDT 24 294344308 ps
T1265 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3767475363 Aug 11 07:02:03 PM PDT 24 Aug 11 07:02:11 PM PDT 24 545564791 ps
T281 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3623795131 Aug 11 07:02:15 PM PDT 24 Aug 11 07:02:37 PM PDT 24 3898894958 ps
T1266 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3541303611 Aug 11 07:02:17 PM PDT 24 Aug 11 07:02:18 PM PDT 24 141148330 ps
T1267 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.597926496 Aug 11 07:01:57 PM PDT 24 Aug 11 07:01:59 PM PDT 24 238385178 ps
T319 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2908275915 Aug 11 07:01:57 PM PDT 24 Aug 11 07:01:58 PM PDT 24 58234090 ps
T1268 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2988737624 Aug 11 07:02:07 PM PDT 24 Aug 11 07:02:08 PM PDT 24 41656482 ps
T320 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2129160333 Aug 11 07:02:09 PM PDT 24 Aug 11 07:02:11 PM PDT 24 76367690 ps
T1269 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3465034578 Aug 11 07:02:05 PM PDT 24 Aug 11 07:02:07 PM PDT 24 280554089 ps
T1270 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.596574436 Aug 11 07:01:58 PM PDT 24 Aug 11 07:02:01 PM PDT 24 54717587 ps
T1271 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3000658302 Aug 11 07:01:46 PM PDT 24 Aug 11 07:01:48 PM PDT 24 40677631 ps
T1272 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.98871525 Aug 11 07:02:22 PM PDT 24 Aug 11 07:02:24 PM PDT 24 37767615 ps
T1273 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.1860669028 Aug 11 07:02:15 PM PDT 24 Aug 11 07:02:16 PM PDT 24 42105445 ps
T1274 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.1511100467 Aug 11 07:02:24 PM PDT 24 Aug 11 07:02:26 PM PDT 24 47438069 ps
T1275 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.3470023150 Aug 11 07:02:16 PM PDT 24 Aug 11 07:02:19 PM PDT 24 577049111 ps
T1276 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3662338494 Aug 11 07:01:50 PM PDT 24 Aug 11 07:01:59 PM PDT 24 614288913 ps
T1277 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2450979159 Aug 11 07:01:58 PM PDT 24 Aug 11 07:02:02 PM PDT 24 117366133 ps
T1278 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.1688278323 Aug 11 07:02:16 PM PDT 24 Aug 11 07:02:18 PM PDT 24 567209612 ps
T1279 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1841015945 Aug 11 07:02:07 PM PDT 24 Aug 11 07:02:15 PM PDT 24 734798129 ps
T369 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2603182204 Aug 11 07:02:09 PM PDT 24 Aug 11 07:02:29 PM PDT 24 1563998321 ps
T1280 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3813769961 Aug 11 07:01:58 PM PDT 24 Aug 11 07:02:00 PM PDT 24 294983523 ps
T1281 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.4146629988 Aug 11 07:02:16 PM PDT 24 Aug 11 07:02:18 PM PDT 24 155202249 ps
T1282 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3342748605 Aug 11 07:02:09 PM PDT 24 Aug 11 07:02:12 PM PDT 24 119268228 ps
T1283 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2045121321 Aug 11 07:01:57 PM PDT 24 Aug 11 07:02:02 PM PDT 24 134539121 ps
T321 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2321239193 Aug 11 07:01:53 PM PDT 24 Aug 11 07:01:55 PM PDT 24 78311883 ps
T1284 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3205795315 Aug 11 07:02:12 PM PDT 24 Aug 11 07:02:16 PM PDT 24 289925062 ps
T1285 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2462489929 Aug 11 07:01:55 PM PDT 24 Aug 11 07:01:56 PM PDT 24 142732556 ps
T1286 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.467018444 Aug 11 07:02:14 PM PDT 24 Aug 11 07:02:15 PM PDT 24 77625336 ps
T1287 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.3304637882 Aug 11 07:02:00 PM PDT 24 Aug 11 07:02:01 PM PDT 24 38996268 ps
T1288 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2545534315 Aug 11 07:02:11 PM PDT 24 Aug 11 07:02:13 PM PDT 24 91658360 ps
T1289 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3777822578 Aug 11 07:01:58 PM PDT 24 Aug 11 07:02:00 PM PDT 24 151101488 ps
T1290 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2414378905 Aug 11 07:01:52 PM PDT 24 Aug 11 07:01:55 PM PDT 24 1032709858 ps
T1291 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2393267162 Aug 11 07:02:06 PM PDT 24 Aug 11 07:02:14 PM PDT 24 1976963652 ps
T1292 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.2961588729 Aug 11 07:02:15 PM PDT 24 Aug 11 07:02:16 PM PDT 24 75063576 ps
T1293 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2453515565 Aug 11 07:01:57 PM PDT 24 Aug 11 07:02:02 PM PDT 24 1690657515 ps
T1294 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1930021196 Aug 11 07:01:53 PM PDT 24 Aug 11 07:01:55 PM PDT 24 91256979 ps
T1295 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2757960079 Aug 11 07:02:05 PM PDT 24 Aug 11 07:02:16 PM PDT 24 2333979780 ps
T1296 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.1188202240 Aug 11 07:02:11 PM PDT 24 Aug 11 07:02:13 PM PDT 24 73473431 ps
T1297 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.467972620 Aug 11 07:02:05 PM PDT 24 Aug 11 07:02:07 PM PDT 24 142864016 ps
T1298 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.4291809464 Aug 11 07:01:52 PM PDT 24 Aug 11 07:01:59 PM PDT 24 210098544 ps
T322 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3390379385 Aug 11 07:01:58 PM PDT 24 Aug 11 07:02:00 PM PDT 24 85003853 ps
T279 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.2680817781 Aug 11 07:02:12 PM PDT 24 Aug 11 07:02:23 PM PDT 24 812104877 ps
T323 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1277966337 Aug 11 07:02:09 PM PDT 24 Aug 11 07:02:11 PM PDT 24 609049555 ps
T1299 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.4043251447 Aug 11 07:02:04 PM PDT 24 Aug 11 07:02:05 PM PDT 24 101756047 ps
T1300 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.1284360791 Aug 11 07:02:11 PM PDT 24 Aug 11 07:02:16 PM PDT 24 1440391442 ps
T1301 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2763758609 Aug 11 07:02:10 PM PDT 24 Aug 11 07:02:11 PM PDT 24 73031216 ps
T1302 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.778437342 Aug 11 07:02:21 PM PDT 24 Aug 11 07:02:22 PM PDT 24 42970341 ps
T1303 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1768355489 Aug 11 07:02:03 PM PDT 24 Aug 11 07:02:12 PM PDT 24 2284758717 ps
T1304 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.354212049 Aug 11 07:02:07 PM PDT 24 Aug 11 07:02:09 PM PDT 24 159240622 ps
T1305 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.829957473 Aug 11 07:02:12 PM PDT 24 Aug 11 07:02:14 PM PDT 24 77161461 ps
T1306 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1155691055 Aug 11 07:01:58 PM PDT 24 Aug 11 07:02:00 PM PDT 24 675091582 ps
T1307 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.55124190 Aug 11 07:02:16 PM PDT 24 Aug 11 07:02:18 PM PDT 24 147623816 ps
T1308 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2551326062 Aug 11 07:01:58 PM PDT 24 Aug 11 07:02:24 PM PDT 24 4864013153 ps
T1309 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1576087859 Aug 11 07:02:15 PM PDT 24 Aug 11 07:02:17 PM PDT 24 76537960 ps
T1310 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1333613402 Aug 11 07:02:12 PM PDT 24 Aug 11 07:02:14 PM PDT 24 66729325 ps
T1311 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2602092965 Aug 11 07:02:10 PM PDT 24 Aug 11 07:02:12 PM PDT 24 152097132 ps
T1312 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.4105426122 Aug 11 07:02:06 PM PDT 24 Aug 11 07:02:08 PM PDT 24 46051039 ps
T1313 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.4074421816 Aug 11 07:02:11 PM PDT 24 Aug 11 07:02:13 PM PDT 24 74897574 ps
T1314 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.4045609093 Aug 11 07:01:58 PM PDT 24 Aug 11 07:01:59 PM PDT 24 38397891 ps
T1315 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2741419709 Aug 11 07:02:10 PM PDT 24 Aug 11 07:02:11 PM PDT 24 151364726 ps
T1316 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1463816392 Aug 11 07:02:08 PM PDT 24 Aug 11 07:02:12 PM PDT 24 206999269 ps
T1317 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1911979144 Aug 11 07:02:13 PM PDT 24 Aug 11 07:02:15 PM PDT 24 151428508 ps
T324 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3463416314 Aug 11 07:02:05 PM PDT 24 Aug 11 07:02:06 PM PDT 24 54884963 ps
T1318 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.4163712298 Aug 11 07:02:09 PM PDT 24 Aug 11 07:02:11 PM PDT 24 77813656 ps
T1319 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.607569338 Aug 11 07:02:06 PM PDT 24 Aug 11 07:02:13 PM PDT 24 837445038 ps

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.1929148641
Short name T12
Test name
Test status
Simulation time 24168668949 ps
CPU time 133.17 seconds
Started Aug 11 06:47:20 PM PDT 24
Finished Aug 11 06:49:33 PM PDT 24
Peak memory 256924 kb
Host smart-33bae383-6f41-4bd5-86be-aaf11dbe5050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929148641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.1929148641
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.3618360814
Short name T7
Test name
Test status
Simulation time 20369969813 ps
CPU time 230.35 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:53:21 PM PDT 24
Peak memory 256804 kb
Host smart-12b54105-cbc0-400a-a3c1-76fb0ba0ac80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618360814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all
.3618360814
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.3062969518
Short name T9
Test name
Test status
Simulation time 24633333369 ps
CPU time 639.51 seconds
Started Aug 11 06:47:28 PM PDT 24
Finished Aug 11 06:58:08 PM PDT 24
Peak memory 291960 kb
Host smart-f589bb9d-88f7-4c2a-a314-d1d6fc4a3365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062969518 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.3062969518
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.2797022593
Short name T239
Test name
Test status
Simulation time 19813238944 ps
CPU time 184.55 seconds
Started Aug 11 06:46:15 PM PDT 24
Finished Aug 11 06:49:20 PM PDT 24
Peak memory 265020 kb
Host smart-f45e4156-2923-4581-bcd7-5ae07ae29796
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797022593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.2797022593
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.1545318922
Short name T142
Test name
Test status
Simulation time 11006768952 ps
CPU time 215.92 seconds
Started Aug 11 06:48:55 PM PDT 24
Finished Aug 11 06:52:32 PM PDT 24
Peak memory 256908 kb
Host smart-af7b4028-b1a5-4a6d-9dd6-989cf9d7bdab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545318922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.1545318922
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.2137389320
Short name T60
Test name
Test status
Simulation time 1526035802 ps
CPU time 22.49 seconds
Started Aug 11 06:48:19 PM PDT 24
Finished Aug 11 06:48:41 PM PDT 24
Peak memory 244160 kb
Host smart-c9a70a94-b4c2-4091-beac-ebaec58521f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137389320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.2137389320
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.2371554954
Short name T165
Test name
Test status
Simulation time 474490977 ps
CPU time 3.58 seconds
Started Aug 11 06:50:24 PM PDT 24
Finished Aug 11 06:50:28 PM PDT 24
Peak memory 242016 kb
Host smart-d8aeb33c-b860-4cbe-9d95-7f213b8dac8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371554954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.2371554954
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.2469380046
Short name T69
Test name
Test status
Simulation time 275911750 ps
CPU time 4.22 seconds
Started Aug 11 06:49:30 PM PDT 24
Finished Aug 11 06:49:35 PM PDT 24
Peak memory 242180 kb
Host smart-c3648733-0081-4d57-8034-716856de3a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469380046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2469380046
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.4056740571
Short name T134
Test name
Test status
Simulation time 582849249897 ps
CPU time 1258.89 seconds
Started Aug 11 06:48:00 PM PDT 24
Finished Aug 11 07:09:00 PM PDT 24
Peak memory 416636 kb
Host smart-f1dab6fb-6f52-427a-a9f6-8a689849ae8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056740571 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.4056740571
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1680598179
Short name T275
Test name
Test status
Simulation time 1319361635 ps
CPU time 18.23 seconds
Started Aug 11 07:02:09 PM PDT 24
Finished Aug 11 07:02:28 PM PDT 24
Peak memory 238924 kb
Host smart-9df83ac8-7af6-4b0d-a972-b0214f1f547a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680598179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.1680598179
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.966695459
Short name T161
Test name
Test status
Simulation time 724090574 ps
CPU time 16.39 seconds
Started Aug 11 06:46:01 PM PDT 24
Finished Aug 11 06:46:18 PM PDT 24
Peak memory 242744 kb
Host smart-2b1b0de5-7ecf-43cf-b9bc-18e90f668129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966695459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.966695459
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.1488701154
Short name T26
Test name
Test status
Simulation time 23578934789 ps
CPU time 36.42 seconds
Started Aug 11 06:47:12 PM PDT 24
Finished Aug 11 06:47:49 PM PDT 24
Peak memory 243064 kb
Host smart-6f954a98-961b-4897-856b-4661ebb8c951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488701154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.1488701154
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.849246732
Short name T41
Test name
Test status
Simulation time 132027292 ps
CPU time 4.79 seconds
Started Aug 11 06:51:00 PM PDT 24
Finished Aug 11 06:51:05 PM PDT 24
Peak memory 242192 kb
Host smart-e9a3635b-a7a3-43bf-a1ef-5ae0549435fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849246732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.849246732
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.829757995
Short name T59
Test name
Test status
Simulation time 136657205826 ps
CPU time 230.75 seconds
Started Aug 11 06:45:34 PM PDT 24
Finished Aug 11 06:49:25 PM PDT 24
Peak memory 281468 kb
Host smart-d5e4c4b7-e1be-4dbd-8109-d76703af970c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829757995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.829757995
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.130031401
Short name T151
Test name
Test status
Simulation time 34255235297 ps
CPU time 832.35 seconds
Started Aug 11 06:47:55 PM PDT 24
Finished Aug 11 07:01:47 PM PDT 24
Peak memory 275896 kb
Host smart-bfe156cc-05d1-4514-a341-befaaa944402
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130031401 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.130031401
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.426166509
Short name T37
Test name
Test status
Simulation time 493842933 ps
CPU time 4.44 seconds
Started Aug 11 06:50:37 PM PDT 24
Finished Aug 11 06:50:42 PM PDT 24
Peak memory 241956 kb
Host smart-f1f09941-cfc4-43e3-9a30-b043a5bb750c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426166509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.426166509
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.862867213
Short name T8
Test name
Test status
Simulation time 37906297412 ps
CPU time 843.76 seconds
Started Aug 11 06:50:10 PM PDT 24
Finished Aug 11 07:04:14 PM PDT 24
Peak memory 326668 kb
Host smart-a9c89b9c-1028-4687-b4b7-3da0f1615d3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862867213 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.862867213
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.3142205656
Short name T63
Test name
Test status
Simulation time 133141956 ps
CPU time 4.15 seconds
Started Aug 11 06:50:17 PM PDT 24
Finished Aug 11 06:50:21 PM PDT 24
Peak memory 242408 kb
Host smart-23b0d593-91b7-4cee-9df2-ba597c267159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142205656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.3142205656
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.2279673938
Short name T29
Test name
Test status
Simulation time 2989047096 ps
CPU time 8.55 seconds
Started Aug 11 06:49:48 PM PDT 24
Finished Aug 11 06:49:56 PM PDT 24
Peak memory 242016 kb
Host smart-9a59ca36-3f67-4ada-8286-10a7fc223ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279673938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.2279673938
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.2721837089
Short name T54
Test name
Test status
Simulation time 4026259998 ps
CPU time 42.96 seconds
Started Aug 11 06:48:30 PM PDT 24
Finished Aug 11 06:49:13 PM PDT 24
Peak memory 248668 kb
Host smart-4b004517-7732-4168-8e57-6a735e7b98a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721837089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.2721837089
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.4291586610
Short name T423
Test name
Test status
Simulation time 781720995 ps
CPU time 2.42 seconds
Started Aug 11 06:45:44 PM PDT 24
Finished Aug 11 06:45:47 PM PDT 24
Peak memory 240300 kb
Host smart-374a3341-9f4d-4ca1-8f7b-14bc76dec001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291586610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.4291586610
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.3699861871
Short name T847
Test name
Test status
Simulation time 2709101372 ps
CPU time 24.92 seconds
Started Aug 11 06:45:25 PM PDT 24
Finished Aug 11 06:45:50 PM PDT 24
Peak memory 248688 kb
Host smart-43f70c7c-05a7-470f-8feb-c002e9b3fd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699861871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.3699861871
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.229365556
Short name T68
Test name
Test status
Simulation time 1317137224 ps
CPU time 5.54 seconds
Started Aug 11 06:51:08 PM PDT 24
Finished Aug 11 06:51:14 PM PDT 24
Peak memory 242412 kb
Host smart-86e31c6a-2fa5-44f4-bed0-cb97af10337a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229365556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.229365556
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.2833225026
Short name T95
Test name
Test status
Simulation time 17827533201 ps
CPU time 162.64 seconds
Started Aug 11 06:49:08 PM PDT 24
Finished Aug 11 06:51:51 PM PDT 24
Peak memory 256892 kb
Host smart-3548d8e6-da4f-4a74-8cb6-6b75ac49bea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833225026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.2833225026
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.1589628211
Short name T294
Test name
Test status
Simulation time 69693749234 ps
CPU time 392.82 seconds
Started Aug 11 06:46:58 PM PDT 24
Finished Aug 11 06:53:31 PM PDT 24
Peak memory 248660 kb
Host smart-fc1771f5-001f-4783-a9bf-2569d2e2235f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589628211 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.1589628211
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.456274919
Short name T184
Test name
Test status
Simulation time 142473483 ps
CPU time 3.81 seconds
Started Aug 11 06:46:57 PM PDT 24
Finished Aug 11 06:47:01 PM PDT 24
Peak memory 241956 kb
Host smart-29689c6c-84dc-4e35-8e77-957e5de7d25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456274919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.456274919
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.4072950817
Short name T266
Test name
Test status
Simulation time 604812479 ps
CPU time 4.37 seconds
Started Aug 11 06:50:30 PM PDT 24
Finished Aug 11 06:50:35 PM PDT 24
Peak memory 242248 kb
Host smart-d2a0edaf-9b47-4b84-bc74-0314ccf4deac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072950817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.4072950817
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.3896205788
Short name T876
Test name
Test status
Simulation time 617816395 ps
CPU time 3.98 seconds
Started Aug 11 06:45:24 PM PDT 24
Finished Aug 11 06:45:28 PM PDT 24
Peak memory 241892 kb
Host smart-e96bda3b-84bb-465e-b8d1-df33fd286e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896205788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.3896205788
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.2488396210
Short name T35
Test name
Test status
Simulation time 300731670 ps
CPU time 5.37 seconds
Started Aug 11 06:49:03 PM PDT 24
Finished Aug 11 06:49:08 PM PDT 24
Peak memory 242224 kb
Host smart-fed92a85-f519-4be0-8095-9278d38d2331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488396210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.2488396210
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.2304951474
Short name T135
Test name
Test status
Simulation time 122582568009 ps
CPU time 287.32 seconds
Started Aug 11 06:48:51 PM PDT 24
Finished Aug 11 06:53:39 PM PDT 24
Peak memory 265072 kb
Host smart-a4a9f97d-9cf0-4825-afdf-a09861a41ce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304951474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.2304951474
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.721576180
Short name T120
Test name
Test status
Simulation time 13367545623 ps
CPU time 212.92 seconds
Started Aug 11 06:48:34 PM PDT 24
Finished Aug 11 06:52:07 PM PDT 24
Peak memory 262844 kb
Host smart-5e165e5a-4b53-47e3-a5ae-0089b4ba745b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721576180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.
721576180
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.1854546606
Short name T289
Test name
Test status
Simulation time 8600292489 ps
CPU time 145.17 seconds
Started Aug 11 06:46:40 PM PDT 24
Finished Aug 11 06:49:05 PM PDT 24
Peak memory 248604 kb
Host smart-6050bf4e-84f5-4a80-9339-de6b991971be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854546606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
1854546606
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.1912395054
Short name T160
Test name
Test status
Simulation time 906979905 ps
CPU time 23.4 seconds
Started Aug 11 06:50:29 PM PDT 24
Finished Aug 11 06:50:52 PM PDT 24
Peak memory 242212 kb
Host smart-ee8e732c-976c-4a3b-9cdb-c859eb5d1649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912395054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1912395054
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.385843238
Short name T73
Test name
Test status
Simulation time 1262670084 ps
CPU time 21.69 seconds
Started Aug 11 06:47:43 PM PDT 24
Finished Aug 11 06:48:05 PM PDT 24
Peak memory 242892 kb
Host smart-35b2b9f9-097a-4035-9fd2-cf956175fb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385843238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.385843238
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.3611261856
Short name T288
Test name
Test status
Simulation time 164913587323 ps
CPU time 1437.13 seconds
Started Aug 11 06:48:46 PM PDT 24
Finished Aug 11 07:12:44 PM PDT 24
Peak memory 266348 kb
Host smart-681eae75-91c8-4661-bc53-b221c472bcf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611261856 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.3611261856
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.4018268904
Short name T128
Test name
Test status
Simulation time 114385326 ps
CPU time 4.21 seconds
Started Aug 11 06:50:58 PM PDT 24
Finished Aug 11 06:51:02 PM PDT 24
Peak memory 242028 kb
Host smart-6d806745-fa41-4f56-b8fd-f4ea9898f35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018268904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.4018268904
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.1961444832
Short name T118
Test name
Test status
Simulation time 83023813455 ps
CPU time 1069.71 seconds
Started Aug 11 06:47:40 PM PDT 24
Finished Aug 11 07:05:29 PM PDT 24
Peak memory 360408 kb
Host smart-0f6aa81e-0bd5-4454-8fc7-faeb010fdff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961444832 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.1961444832
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.1515640157
Short name T382
Test name
Test status
Simulation time 337771547 ps
CPU time 8.19 seconds
Started Aug 11 06:45:30 PM PDT 24
Finished Aug 11 06:45:38 PM PDT 24
Peak memory 241864 kb
Host smart-233ba67e-5f1f-45d6-b30a-910326b9e799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515640157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1515640157
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.738784834
Short name T650
Test name
Test status
Simulation time 588001007 ps
CPU time 4.71 seconds
Started Aug 11 06:47:53 PM PDT 24
Finished Aug 11 06:47:58 PM PDT 24
Peak memory 241940 kb
Host smart-b3bb6a1c-699c-4b54-b9a6-93f8ac81c895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738784834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.738784834
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1046267244
Short name T282
Test name
Test status
Simulation time 1306927396 ps
CPU time 18.63 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:29 PM PDT 24
Peak memory 243944 kb
Host smart-ebcc73b8-e449-41d6-8bb1-1813ca321460
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046267244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.1046267244
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.2045027085
Short name T193
Test name
Test status
Simulation time 5482856307 ps
CPU time 34.89 seconds
Started Aug 11 06:46:12 PM PDT 24
Finished Aug 11 06:46:47 PM PDT 24
Peak memory 245360 kb
Host smart-e351b7c7-fd85-472f-b1e4-a9fc6ac38b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045027085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.2045027085
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.1255805056
Short name T168
Test name
Test status
Simulation time 2178532991 ps
CPU time 4.59 seconds
Started Aug 11 06:50:19 PM PDT 24
Finished Aug 11 06:50:24 PM PDT 24
Peak memory 242204 kb
Host smart-051b535e-cd9b-43f0-bbe4-b1bb2f9c048f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255805056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.1255805056
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.279062086
Short name T144
Test name
Test status
Simulation time 263242763 ps
CPU time 5.48 seconds
Started Aug 11 06:49:25 PM PDT 24
Finished Aug 11 06:49:31 PM PDT 24
Peak memory 242264 kb
Host smart-03997d17-dad3-4f06-a9a5-28f89154e2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279062086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.279062086
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.404386352
Short name T44
Test name
Test status
Simulation time 25518499700 ps
CPU time 46.12 seconds
Started Aug 11 06:47:05 PM PDT 24
Finished Aug 11 06:47:52 PM PDT 24
Peak memory 243260 kb
Host smart-1e72d653-fa27-48de-a0ea-b7d51796c894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404386352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.404386352
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.3338252038
Short name T67
Test name
Test status
Simulation time 1187269269 ps
CPU time 18.13 seconds
Started Aug 11 06:50:51 PM PDT 24
Finished Aug 11 06:51:09 PM PDT 24
Peak memory 242452 kb
Host smart-df593bb2-4474-4a90-8df5-4ad157907b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338252038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3338252038
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.3871871591
Short name T81
Test name
Test status
Simulation time 185272013 ps
CPU time 5.15 seconds
Started Aug 11 06:51:13 PM PDT 24
Finished Aug 11 06:51:18 PM PDT 24
Peak memory 242020 kb
Host smart-25782f98-f769-44eb-82f1-c1d082064380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871871591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.3871871591
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.1623851087
Short name T116
Test name
Test status
Simulation time 1484157935 ps
CPU time 15.28 seconds
Started Aug 11 06:49:19 PM PDT 24
Finished Aug 11 06:49:34 PM PDT 24
Peak memory 242252 kb
Host smart-911b2e4b-a139-46f4-8eac-5dd0f5d8f6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623851087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.1623851087
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.4232915588
Short name T150
Test name
Test status
Simulation time 4642832478 ps
CPU time 9.77 seconds
Started Aug 11 06:50:41 PM PDT 24
Finished Aug 11 06:50:51 PM PDT 24
Peak memory 242432 kb
Host smart-8323c260-547e-43e8-a862-d83cd741640c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232915588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.4232915588
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.2534598981
Short name T4
Test name
Test status
Simulation time 1977804150 ps
CPU time 5.84 seconds
Started Aug 11 06:50:22 PM PDT 24
Finished Aug 11 06:50:28 PM PDT 24
Peak memory 242324 kb
Host smart-3cf14577-0383-4743-8486-a2dac97b66df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534598981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2534598981
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.3023348540
Short name T101
Test name
Test status
Simulation time 156932985 ps
CPU time 6.06 seconds
Started Aug 11 06:50:29 PM PDT 24
Finished Aug 11 06:50:35 PM PDT 24
Peak memory 241976 kb
Host smart-41f09093-43e3-4b86-8769-130a879f46d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023348540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.3023348540
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.3716472675
Short name T121
Test name
Test status
Simulation time 339320317642 ps
CPU time 939.24 seconds
Started Aug 11 06:49:55 PM PDT 24
Finished Aug 11 07:05:34 PM PDT 24
Peak memory 313696 kb
Host smart-3d691e37-4187-47c3-b1cb-0020d5a17b12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716472675 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.3716472675
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.965191794
Short name T64
Test name
Test status
Simulation time 335115959 ps
CPU time 9.21 seconds
Started Aug 11 06:49:57 PM PDT 24
Finished Aug 11 06:50:06 PM PDT 24
Peak memory 241932 kb
Host smart-26f4b9d3-8264-4793-b2cb-e3484924d5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965191794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.965191794
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.2742304959
Short name T138
Test name
Test status
Simulation time 506822481 ps
CPU time 6.97 seconds
Started Aug 11 06:50:00 PM PDT 24
Finished Aug 11 06:50:07 PM PDT 24
Peak memory 241876 kb
Host smart-2edba022-8633-4df5-b4d3-6da3dbfe24a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742304959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.2742304959
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.118665280
Short name T309
Test name
Test status
Simulation time 79743117 ps
CPU time 4.59 seconds
Started Aug 11 07:01:53 PM PDT 24
Finished Aug 11 07:01:58 PM PDT 24
Peak memory 238780 kb
Host smart-fe99d3cc-ecc3-4129-93fc-b1fe1403f7c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118665280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alias
ing.118665280
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.1216671793
Short name T408
Test name
Test status
Simulation time 46635934763 ps
CPU time 821.68 seconds
Started Aug 11 06:50:00 PM PDT 24
Finished Aug 11 07:03:42 PM PDT 24
Peak memory 324912 kb
Host smart-8f44fafe-e196-44ef-9197-244176f5c3c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216671793 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.1216671793
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.312025291
Short name T34
Test name
Test status
Simulation time 5663314222 ps
CPU time 14.27 seconds
Started Aug 11 06:48:29 PM PDT 24
Finished Aug 11 06:48:43 PM PDT 24
Peak memory 242172 kb
Host smart-6d7ac07a-b627-4445-ad2a-dd402c032e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312025291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.312025291
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.1525456851
Short name T373
Test name
Test status
Simulation time 436057046 ps
CPU time 7.1 seconds
Started Aug 11 06:46:08 PM PDT 24
Finished Aug 11 06:46:15 PM PDT 24
Peak memory 242204 kb
Host smart-6cb6e8b0-b8cb-4c96-bec4-88d3375fee79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525456851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.1525456851
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1864711533
Short name T365
Test name
Test status
Simulation time 4838249574 ps
CPU time 20.85 seconds
Started Aug 11 07:01:53 PM PDT 24
Finished Aug 11 07:02:14 PM PDT 24
Peak memory 244608 kb
Host smart-daec0da1-0333-4f5f-8345-f0dd856123ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864711533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.1864711533
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.1301638700
Short name T386
Test name
Test status
Simulation time 4385923262 ps
CPU time 13.04 seconds
Started Aug 11 06:48:12 PM PDT 24
Finished Aug 11 06:48:25 PM PDT 24
Peak memory 242712 kb
Host smart-1cdbc636-5efe-4709-baa9-1dab3d87d2e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301638700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.1301638700
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.3205439910
Short name T261
Test name
Test status
Simulation time 50209457572 ps
CPU time 658.69 seconds
Started Aug 11 06:49:02 PM PDT 24
Finished Aug 11 07:00:01 PM PDT 24
Peak memory 306760 kb
Host smart-c60b9a29-26f0-4497-be5f-7b17b5b5bcd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205439910 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.3205439910
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.3520873467
Short name T136
Test name
Test status
Simulation time 69591652270 ps
CPU time 195.55 seconds
Started Aug 11 06:49:18 PM PDT 24
Finished Aug 11 06:52:33 PM PDT 24
Peak memory 260256 kb
Host smart-4d237799-d3f1-4f3a-b51a-be6471c4f677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520873467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.3520873467
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1825967554
Short name T327
Test name
Test status
Simulation time 849617204 ps
CPU time 3.44 seconds
Started Aug 11 07:02:07 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 238796 kb
Host smart-41b4381f-788b-4fa2-96f2-db1ef4c6f9e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825967554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.1825967554
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.2710324190
Short name T119
Test name
Test status
Simulation time 105822176 ps
CPU time 4.12 seconds
Started Aug 11 06:51:12 PM PDT 24
Finished Aug 11 06:51:16 PM PDT 24
Peak memory 242404 kb
Host smart-5889f903-8e25-4990-a8d0-d8cbdfbf0ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710324190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.2710324190
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1395203890
Short name T80
Test name
Test status
Simulation time 288327180 ps
CPU time 4.88 seconds
Started Aug 11 06:46:03 PM PDT 24
Finished Aug 11 06:46:08 PM PDT 24
Peak memory 242192 kb
Host smart-ff7fa0b6-998d-4759-853d-397cfe972347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395203890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1395203890
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.1628683687
Short name T115
Test name
Test status
Simulation time 4638597059 ps
CPU time 35.73 seconds
Started Aug 11 06:49:14 PM PDT 24
Finished Aug 11 06:49:50 PM PDT 24
Peak memory 245872 kb
Host smart-91810cac-6b82-4189-a993-8589792f2222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628683687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.1628683687
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.93862255
Short name T280
Test name
Test status
Simulation time 19985453822 ps
CPU time 36.16 seconds
Started Aug 11 07:02:08 PM PDT 24
Finished Aug 11 07:02:44 PM PDT 24
Peak memory 244480 kb
Host smart-d5175bf9-e0bd-4dc5-a3cd-3c476227027b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93862255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_int
g_err.93862255
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.3631206919
Short name T3
Test name
Test status
Simulation time 479729223 ps
CPU time 3.46 seconds
Started Aug 11 06:50:17 PM PDT 24
Finished Aug 11 06:50:21 PM PDT 24
Peak memory 241936 kb
Host smart-7c868355-9a8c-4310-ac43-c69a5849a44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631206919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.3631206919
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.4231206901
Short name T512
Test name
Test status
Simulation time 433499415 ps
CPU time 3.6 seconds
Started Aug 11 06:50:17 PM PDT 24
Finished Aug 11 06:50:21 PM PDT 24
Peak memory 242140 kb
Host smart-70795e48-6037-43ac-bdc3-debf7f07eae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231206901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.4231206901
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.2296230356
Short name T137
Test name
Test status
Simulation time 110176427386 ps
CPU time 201.61 seconds
Started Aug 11 06:45:51 PM PDT 24
Finished Aug 11 06:49:12 PM PDT 24
Peak memory 286572 kb
Host smart-d527e68c-8a79-43cf-bdcb-933a22aa831f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296230356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
2296230356
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2603182204
Short name T369
Test name
Test status
Simulation time 1563998321 ps
CPU time 19.77 seconds
Started Aug 11 07:02:09 PM PDT 24
Finished Aug 11 07:02:29 PM PDT 24
Peak memory 244036 kb
Host smart-4ba8616a-a498-4757-a06d-66efdbd1ed71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603182204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.2603182204
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3385213979
Short name T370
Test name
Test status
Simulation time 614528196 ps
CPU time 9.39 seconds
Started Aug 11 07:02:04 PM PDT 24
Finished Aug 11 07:02:13 PM PDT 24
Peak memory 238948 kb
Host smart-7aa19355-96aa-4e8c-8aff-50be0230def6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385213979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.3385213979
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.1070337866
Short name T384
Test name
Test status
Simulation time 445613063 ps
CPU time 4.92 seconds
Started Aug 11 06:47:03 PM PDT 24
Finished Aug 11 06:47:08 PM PDT 24
Peak memory 242212 kb
Host smart-b60eaf43-1c54-4d25-97c2-b1eb6073ad50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1070337866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1070337866
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.110731926
Short name T237
Test name
Test status
Simulation time 9201892525 ps
CPU time 104.15 seconds
Started Aug 11 06:46:08 PM PDT 24
Finished Aug 11 06:47:52 PM PDT 24
Peak memory 266580 kb
Host smart-4f4862b8-6d9e-416a-b48a-b42f813d1057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110731926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.110731926
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.540419224
Short name T269
Test name
Test status
Simulation time 984636659661 ps
CPU time 1678.3 seconds
Started Aug 11 06:49:57 PM PDT 24
Finished Aug 11 07:17:55 PM PDT 24
Peak memory 293404 kb
Host smart-c50c2cd8-86fe-4ac6-9808-b4cac1109093
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540419224 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.540419224
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.4045034893
Short name T155
Test name
Test status
Simulation time 65602462 ps
CPU time 1.69 seconds
Started Aug 11 06:45:22 PM PDT 24
Finished Aug 11 06:45:24 PM PDT 24
Peak memory 240452 kb
Host smart-0f6ccca5-4ab4-45da-b871-fc4f36d06310
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4045034893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.4045034893
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.961160526
Short name T91
Test name
Test status
Simulation time 1467426624 ps
CPU time 21.57 seconds
Started Aug 11 06:46:56 PM PDT 24
Finished Aug 11 06:47:18 PM PDT 24
Peak memory 242228 kb
Host smart-fdadaf80-39c6-45fd-918a-fd3ef8f805ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961160526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.961160526
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.3697412051
Short name T264
Test name
Test status
Simulation time 2327879161 ps
CPU time 21.82 seconds
Started Aug 11 06:47:15 PM PDT 24
Finished Aug 11 06:47:37 PM PDT 24
Peak memory 242384 kb
Host smart-db46c841-6533-4103-8cae-a24382456dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697412051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.3697412051
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.2680817781
Short name T279
Test name
Test status
Simulation time 812104877 ps
CPU time 10.48 seconds
Started Aug 11 07:02:12 PM PDT 24
Finished Aug 11 07:02:23 PM PDT 24
Peak memory 243664 kb
Host smart-41984605-9152-44e7-a3b1-179623b9edac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680817781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.2680817781
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3623795131
Short name T281
Test name
Test status
Simulation time 3898894958 ps
CPU time 21.95 seconds
Started Aug 11 07:02:15 PM PDT 24
Finished Aug 11 07:02:37 PM PDT 24
Peak memory 244720 kb
Host smart-e52a19c0-4676-482d-b61d-59093d4092e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623795131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.3623795131
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.3115952348
Short name T21
Test name
Test status
Simulation time 154811778001 ps
CPU time 267.85 seconds
Started Aug 11 06:45:34 PM PDT 24
Finished Aug 11 06:50:02 PM PDT 24
Peak memory 269056 kb
Host smart-075f1adb-d7bd-4dcd-8703-50cb83c5a2a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115952348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.3115952348
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.1892777070
Short name T132
Test name
Test status
Simulation time 16284905886 ps
CPU time 48.73 seconds
Started Aug 11 06:47:14 PM PDT 24
Finished Aug 11 06:48:03 PM PDT 24
Peak memory 248616 kb
Host smart-7ecd3d32-cd2b-4444-b2b9-986440172035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892777070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.1892777070
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.3527411832
Short name T255
Test name
Test status
Simulation time 601427094 ps
CPU time 4.62 seconds
Started Aug 11 06:50:59 PM PDT 24
Finished Aug 11 06:51:04 PM PDT 24
Peak memory 242008 kb
Host smart-a72231c8-721e-4b79-87f4-6cf5129137de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527411832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3527411832
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.2380230243
Short name T65
Test name
Test status
Simulation time 24983390026 ps
CPU time 214.92 seconds
Started Aug 11 06:48:19 PM PDT 24
Finished Aug 11 06:51:54 PM PDT 24
Peak memory 257584 kb
Host smart-78d001e5-2348-4fb0-b170-2731a8037533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380230243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.2380230243
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.1638510424
Short name T257
Test name
Test status
Simulation time 1080681675 ps
CPU time 11.1 seconds
Started Aug 11 06:46:37 PM PDT 24
Finished Aug 11 06:46:49 PM PDT 24
Peak memory 242344 kb
Host smart-42342a4e-3ae4-477b-82ed-d4b452131d59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638510424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.1638510424
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.2652238692
Short name T258
Test name
Test status
Simulation time 23262044219 ps
CPU time 447.09 seconds
Started Aug 11 06:50:08 PM PDT 24
Finished Aug 11 06:57:35 PM PDT 24
Peak memory 265000 kb
Host smart-f9b1cf28-d04c-4c54-ada7-26e97e3dc307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652238692 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.2652238692
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.1226566275
Short name T471
Test name
Test status
Simulation time 406141477 ps
CPU time 5.79 seconds
Started Aug 11 06:48:31 PM PDT 24
Finished Aug 11 06:48:37 PM PDT 24
Peak memory 248504 kb
Host smart-fba97174-f24c-4bcd-9017-6617700c2ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226566275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.1226566275
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.368641508
Short name T83
Test name
Test status
Simulation time 123664730 ps
CPU time 4.21 seconds
Started Aug 11 06:49:44 PM PDT 24
Finished Aug 11 06:49:49 PM PDT 24
Peak memory 242016 kb
Host smart-c6340c89-5a3e-4ccf-b827-7cc4908f3b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368641508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.368641508
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.1200785479
Short name T489
Test name
Test status
Simulation time 28283490584 ps
CPU time 149.28 seconds
Started Aug 11 06:49:18 PM PDT 24
Finished Aug 11 06:51:48 PM PDT 24
Peak memory 245284 kb
Host smart-e57b4bb2-db9a-412d-8a09-2a49df880ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200785479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.1200785479
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.678339607
Short name T32
Test name
Test status
Simulation time 1857143537 ps
CPU time 5.74 seconds
Started Aug 11 06:50:22 PM PDT 24
Finished Aug 11 06:50:28 PM PDT 24
Peak memory 242040 kb
Host smart-6982070b-b460-482f-a853-813814c6392e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678339607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.678339607
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.55487939
Short name T265
Test name
Test status
Simulation time 283888097 ps
CPU time 7.01 seconds
Started Aug 11 06:50:29 PM PDT 24
Finished Aug 11 06:50:36 PM PDT 24
Peak memory 242360 kb
Host smart-15845c19-839b-4f68-af9e-82482afb128f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55487939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.55487939
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.2491318688
Short name T143
Test name
Test status
Simulation time 522897795 ps
CPU time 5.46 seconds
Started Aug 11 06:50:41 PM PDT 24
Finished Aug 11 06:50:46 PM PDT 24
Peak memory 241876 kb
Host smart-e5ccd10a-5f94-4b86-84b4-35cb4becd7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491318688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.2491318688
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.4082990273
Short name T308
Test name
Test status
Simulation time 197767505 ps
CPU time 4.76 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:03 PM PDT 24
Peak memory 238224 kb
Host smart-e039da36-a1ab-484e-b9b4-f503afb79b20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082990273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.4082990273
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.340350169
Short name T1217
Test name
Test status
Simulation time 694901358 ps
CPU time 8.29 seconds
Started Aug 11 07:01:53 PM PDT 24
Finished Aug 11 07:02:02 PM PDT 24
Peak memory 238796 kb
Host smart-31b0afb1-4e72-427d-ba5b-520002d600d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340350169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_b
ash.340350169
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2414378905
Short name T1290
Test name
Test status
Simulation time 1032709858 ps
CPU time 2.92 seconds
Started Aug 11 07:01:52 PM PDT 24
Finished Aug 11 07:01:55 PM PDT 24
Peak memory 240940 kb
Host smart-23198e9e-29c6-486f-ba7f-656423da535f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414378905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.2414378905
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.643323000
Short name T390
Test name
Test status
Simulation time 74956322 ps
CPU time 2.87 seconds
Started Aug 11 07:01:51 PM PDT 24
Finished Aug 11 07:01:54 PM PDT 24
Peak memory 247120 kb
Host smart-e52a3d55-48cb-4687-a672-cb55f10335a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643323000 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.643323000
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2321239193
Short name T321
Test name
Test status
Simulation time 78311883 ps
CPU time 1.64 seconds
Started Aug 11 07:01:53 PM PDT 24
Finished Aug 11 07:01:55 PM PDT 24
Peak memory 241528 kb
Host smart-94f1fb43-6eb2-4a31-8a56-1f95c70c471a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321239193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.2321239193
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3000658302
Short name T1271
Test name
Test status
Simulation time 40677631 ps
CPU time 1.35 seconds
Started Aug 11 07:01:46 PM PDT 24
Finished Aug 11 07:01:48 PM PDT 24
Peak memory 230668 kb
Host smart-f1f8104a-d248-4d86-b867-dd85c1a16ebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000658302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.3000658302
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2172049130
Short name T1263
Test name
Test status
Simulation time 41435241 ps
CPU time 1.38 seconds
Started Aug 11 07:01:47 PM PDT 24
Finished Aug 11 07:01:49 PM PDT 24
Peak memory 230420 kb
Host smart-b2c2efd0-8d12-4fde-bb1a-0a3a8e429d11
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172049130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.2172049130
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.234902717
Short name T1224
Test name
Test status
Simulation time 73420704 ps
CPU time 1.36 seconds
Started Aug 11 07:01:45 PM PDT 24
Finished Aug 11 07:01:47 PM PDT 24
Peak memory 230548 kb
Host smart-e80f32d3-9c51-4148-b7c3-238a2fc2d2e8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234902717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.
234902717
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.597926496
Short name T1267
Test name
Test status
Simulation time 238385178 ps
CPU time 2.29 seconds
Started Aug 11 07:01:57 PM PDT 24
Finished Aug 11 07:01:59 PM PDT 24
Peak memory 238900 kb
Host smart-b682fd4f-ab21-4a2f-b1a3-0a9300749482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597926496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ct
rl_same_csr_outstanding.597926496
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1768871010
Short name T1194
Test name
Test status
Simulation time 73357028 ps
CPU time 4.69 seconds
Started Aug 11 07:01:47 PM PDT 24
Finished Aug 11 07:01:51 PM PDT 24
Peak memory 238848 kb
Host smart-a141526b-7f98-4ddc-ae9e-1ece6b74ff4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768871010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.1768871010
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3662338494
Short name T1276
Test name
Test status
Simulation time 614288913 ps
CPU time 9.22 seconds
Started Aug 11 07:01:50 PM PDT 24
Finished Aug 11 07:01:59 PM PDT 24
Peak memory 243864 kb
Host smart-56927bcc-91bc-4521-8e1d-3c37c5c585ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662338494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.3662338494
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2608075997
Short name T1259
Test name
Test status
Simulation time 4117596358 ps
CPU time 10.44 seconds
Started Aug 11 07:01:55 PM PDT 24
Finished Aug 11 07:02:05 PM PDT 24
Peak memory 238892 kb
Host smart-a3f359a9-0a46-4cb8-9675-6c3ee486b4b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608075997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.2608075997
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3622915115
Short name T304
Test name
Test status
Simulation time 174300397 ps
CPU time 2.35 seconds
Started Aug 11 07:01:52 PM PDT 24
Finished Aug 11 07:01:55 PM PDT 24
Peak memory 240844 kb
Host smart-b06fb568-7f7d-4e89-89bf-fac48f7329df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622915115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.3622915115
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3755294055
Short name T1264
Test name
Test status
Simulation time 294344308 ps
CPU time 2.27 seconds
Started Aug 11 07:01:56 PM PDT 24
Finished Aug 11 07:01:58 PM PDT 24
Peak memory 246356 kb
Host smart-20979ae9-3810-4a45-9abd-a1aacedef2c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755294055 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.3755294055
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3390379385
Short name T322
Test name
Test status
Simulation time 85003853 ps
CPU time 1.49 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:00 PM PDT 24
Peak memory 239956 kb
Host smart-d8918356-8b01-475a-8fc3-55c3bd05710c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390379385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.3390379385
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.4271448171
Short name T1247
Test name
Test status
Simulation time 46208794 ps
CPU time 1.41 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:00 PM PDT 24
Peak memory 230212 kb
Host smart-ffbcef66-7dbc-4b3c-944a-ecd999c20404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271448171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.4271448171
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2034398450
Short name T1256
Test name
Test status
Simulation time 72024236 ps
CPU time 1.36 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:01:59 PM PDT 24
Peak memory 229892 kb
Host smart-02b7949e-45df-4d25-9e40-8fe71dfdbd6c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034398450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.2034398450
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2462489929
Short name T1285
Test name
Test status
Simulation time 142732556 ps
CPU time 1.41 seconds
Started Aug 11 07:01:55 PM PDT 24
Finished Aug 11 07:01:56 PM PDT 24
Peak memory 230668 kb
Host smart-c8e1d83f-cfab-45d3-96a7-6d5da3ccd76b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462489929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.2462489929
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2450979159
Short name T1277
Test name
Test status
Simulation time 117366133 ps
CPU time 3.42 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:02 PM PDT 24
Peak memory 238824 kb
Host smart-8c5be747-75a2-47d5-9801-840093339ca3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450979159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.2450979159
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.596574436
Short name T1270
Test name
Test status
Simulation time 54717587 ps
CPU time 3.13 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:01 PM PDT 24
Peak memory 245632 kb
Host smart-a1aecc20-46fe-4b37-8dd1-fbecf6a1f94d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596574436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.596574436
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2900878696
Short name T1262
Test name
Test status
Simulation time 421337861 ps
CPU time 3.22 seconds
Started Aug 11 07:02:08 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 247112 kb
Host smart-e8f2fc4e-faf7-4a9b-81f8-5f84cbf34654
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900878696 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.2900878696
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2741419709
Short name T1315
Test name
Test status
Simulation time 151364726 ps
CPU time 1.54 seconds
Started Aug 11 07:02:10 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 240868 kb
Host smart-c980bbca-5b76-4868-b2ab-c80d1fec91b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741419709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.2741419709
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3715515515
Short name T1204
Test name
Test status
Simulation time 40692684 ps
CPU time 1.5 seconds
Started Aug 11 07:02:03 PM PDT 24
Finished Aug 11 07:02:04 PM PDT 24
Peak memory 230664 kb
Host smart-6cc06f60-a701-4bee-a7df-b5afe53a3093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715515515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.3715515515
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.4043251447
Short name T1299
Test name
Test status
Simulation time 101756047 ps
CPU time 1.85 seconds
Started Aug 11 07:02:04 PM PDT 24
Finished Aug 11 07:02:05 PM PDT 24
Peak memory 241728 kb
Host smart-1777544f-fc3e-4474-ab01-f72b0d45618b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043251447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.4043251447
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3064269462
Short name T1213
Test name
Test status
Simulation time 295466768 ps
CPU time 5.87 seconds
Started Aug 11 07:02:07 PM PDT 24
Finished Aug 11 07:02:13 PM PDT 24
Peak memory 246216 kb
Host smart-cdebc884-20dd-4036-9f0d-ab36dc4e1600
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064269462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3064269462
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3836030683
Short name T276
Test name
Test status
Simulation time 657170700 ps
CPU time 10.65 seconds
Started Aug 11 07:02:04 PM PDT 24
Finished Aug 11 07:02:14 PM PDT 24
Peak memory 238856 kb
Host smart-7f07f10c-cbdf-4431-8afb-892a862a6076
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836030683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.3836030683
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.628290048
Short name T1216
Test name
Test status
Simulation time 134592379 ps
CPU time 2.36 seconds
Started Aug 11 07:02:04 PM PDT 24
Finished Aug 11 07:02:06 PM PDT 24
Peak memory 247076 kb
Host smart-a377d91a-22bc-4166-a622-d8f24dc4abf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628290048 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.628290048
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2852385772
Short name T305
Test name
Test status
Simulation time 55898854 ps
CPU time 1.67 seconds
Started Aug 11 07:02:07 PM PDT 24
Finished Aug 11 07:02:09 PM PDT 24
Peak memory 238808 kb
Host smart-49f84213-bc0a-444f-907a-da1861ad56c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852385772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.2852385772
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2120336493
Short name T1199
Test name
Test status
Simulation time 41783952 ps
CPU time 1.47 seconds
Started Aug 11 07:02:10 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 230124 kb
Host smart-a8e53c54-151f-4701-b5e8-688c65f5a88c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120336493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2120336493
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3465034578
Short name T1269
Test name
Test status
Simulation time 280554089 ps
CPU time 2.49 seconds
Started Aug 11 07:02:05 PM PDT 24
Finished Aug 11 07:02:07 PM PDT 24
Peak memory 238800 kb
Host smart-a61fc3fe-65ab-432e-918b-8bdc04762a3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465034578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.3465034578
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3447485515
Short name T1239
Test name
Test status
Simulation time 383275799 ps
CPU time 4.36 seconds
Started Aug 11 07:02:06 PM PDT 24
Finished Aug 11 07:02:10 PM PDT 24
Peak memory 245868 kb
Host smart-fc81160f-7df3-413d-af97-dbd3e17666c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447485515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.3447485515
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1382119508
Short name T1210
Test name
Test status
Simulation time 356014513 ps
CPU time 2.91 seconds
Started Aug 11 07:02:05 PM PDT 24
Finished Aug 11 07:02:08 PM PDT 24
Peak memory 247100 kb
Host smart-5a5d02a6-c315-437a-afb9-3404ef94720d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382119508 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.1382119508
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.3105010468
Short name T335
Test name
Test status
Simulation time 70382563 ps
CPU time 1.48 seconds
Started Aug 11 07:02:09 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 239660 kb
Host smart-c78794a8-bb46-49b0-addf-51dd80053af3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105010468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.3105010468
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2988737624
Short name T1268
Test name
Test status
Simulation time 41656482 ps
CPU time 1.53 seconds
Started Aug 11 07:02:07 PM PDT 24
Finished Aug 11 07:02:08 PM PDT 24
Peak memory 229948 kb
Host smart-56ae4955-2be9-4443-8c55-a5a38aec58bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988737624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2988737624
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.365894375
Short name T1257
Test name
Test status
Simulation time 59252851 ps
CPU time 2.92 seconds
Started Aug 11 07:02:14 PM PDT 24
Finished Aug 11 07:02:17 PM PDT 24
Peak memory 238848 kb
Host smart-aa721f36-541e-4414-8c2b-75ff87d81ebc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365894375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.365894375
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.2505659295
Short name T1206
Test name
Test status
Simulation time 1677145577 ps
CPU time 4.95 seconds
Started Aug 11 07:02:08 PM PDT 24
Finished Aug 11 07:02:13 PM PDT 24
Peak memory 247036 kb
Host smart-9d0b9f33-0317-4b7c-9861-b663073499c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505659295 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.2505659295
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1856930407
Short name T318
Test name
Test status
Simulation time 40935733 ps
CPU time 1.54 seconds
Started Aug 11 07:02:10 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 238908 kb
Host smart-601fc29c-b658-4b3b-84c0-ea7583a455ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856930407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.1856930407
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.529261925
Short name T1207
Test name
Test status
Simulation time 108510833 ps
CPU time 1.45 seconds
Started Aug 11 07:02:12 PM PDT 24
Finished Aug 11 07:02:14 PM PDT 24
Peak memory 229932 kb
Host smart-36fc4294-233c-4643-8392-664f9e7e50f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529261925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.529261925
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1748770117
Short name T325
Test name
Test status
Simulation time 44406430 ps
CPU time 1.91 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:13 PM PDT 24
Peak memory 241912 kb
Host smart-50c9038b-8133-4807-8703-e2732d2b8e41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748770117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.1748770117
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3205795315
Short name T1284
Test name
Test status
Simulation time 289925062 ps
CPU time 3.32 seconds
Started Aug 11 07:02:12 PM PDT 24
Finished Aug 11 07:02:16 PM PDT 24
Peak memory 238892 kb
Host smart-8dda2905-d538-4ded-bfc7-346798bd41b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205795315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3205795315
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1277966337
Short name T323
Test name
Test status
Simulation time 609049555 ps
CPU time 1.89 seconds
Started Aug 11 07:02:09 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 241000 kb
Host smart-8ee59a83-1031-447d-82a8-31ddd52a8f9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277966337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.1277966337
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3502175332
Short name T1229
Test name
Test status
Simulation time 154832102 ps
CPU time 1.52 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:13 PM PDT 24
Peak memory 230228 kb
Host smart-88d3e733-88aa-4e3f-a563-7048a5010e1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502175332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.3502175332
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1214252135
Short name T334
Test name
Test status
Simulation time 91184987 ps
CPU time 1.98 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:13 PM PDT 24
Peak memory 238820 kb
Host smart-909c49d3-1579-4706-9da0-06ddb971fa4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214252135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.1214252135
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2476377829
Short name T1238
Test name
Test status
Simulation time 101172071 ps
CPU time 3.19 seconds
Started Aug 11 07:02:09 PM PDT 24
Finished Aug 11 07:02:12 PM PDT 24
Peak memory 245896 kb
Host smart-6ca63c41-f29e-4829-bda9-ea452c39c672
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476377829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.2476377829
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3588966546
Short name T364
Test name
Test status
Simulation time 19050149258 ps
CPU time 39.02 seconds
Started Aug 11 07:02:16 PM PDT 24
Finished Aug 11 07:02:55 PM PDT 24
Peak memory 238988 kb
Host smart-7af463e0-0f3b-4c46-b018-41be81358010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588966546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.3588966546
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3342748605
Short name T1282
Test name
Test status
Simulation time 119268228 ps
CPU time 2.81 seconds
Started Aug 11 07:02:09 PM PDT 24
Finished Aug 11 07:02:12 PM PDT 24
Peak memory 247120 kb
Host smart-e8f54232-4a4d-4861-a73a-28c6f47c7ab7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342748605 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.3342748605
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.15760471
Short name T277
Test name
Test status
Simulation time 65258596 ps
CPU time 1.74 seconds
Started Aug 11 07:02:09 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 241200 kb
Host smart-5445f2e3-ca79-4770-a144-41d4c4796ef4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15760471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.15760471
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.60943802
Short name T1214
Test name
Test status
Simulation time 140999507 ps
CPU time 1.46 seconds
Started Aug 11 07:02:10 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 230632 kb
Host smart-10dbcaa5-b787-404d-8a33-7efac1a13568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60943802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.60943802
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.1284360791
Short name T1300
Test name
Test status
Simulation time 1440391442 ps
CPU time 4.56 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:16 PM PDT 24
Peak memory 238868 kb
Host smart-8c614d05-1847-49da-983e-797372212bd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284360791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.1284360791
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2980911044
Short name T1197
Test name
Test status
Simulation time 199046649 ps
CPU time 4.83 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:16 PM PDT 24
Peak memory 246032 kb
Host smart-8ccd3c7a-7480-407c-bbda-4855e6cd08f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980911044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.2980911044
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.684283692
Short name T371
Test name
Test status
Simulation time 19834605469 ps
CPU time 34.84 seconds
Started Aug 11 07:02:08 PM PDT 24
Finished Aug 11 07:02:43 PM PDT 24
Peak memory 238884 kb
Host smart-8ed7b213-cc0d-4bfe-8fbe-772b9a8a9403
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684283692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_in
tg_err.684283692
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.4074421816
Short name T1313
Test name
Test status
Simulation time 74897574 ps
CPU time 2.04 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:13 PM PDT 24
Peak memory 244308 kb
Host smart-5f30ba09-1435-4afb-a8fd-2fd58389036e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074421816 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.4074421816
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2129160333
Short name T320
Test name
Test status
Simulation time 76367690 ps
CPU time 1.77 seconds
Started Aug 11 07:02:09 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 241300 kb
Host smart-732e82f8-bdfa-4765-829b-d56fd2fb348f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129160333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.2129160333
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.1188202240
Short name T1296
Test name
Test status
Simulation time 73473431 ps
CPU time 1.51 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:13 PM PDT 24
Peak memory 230000 kb
Host smart-82edaed0-cf24-4f39-b9b7-de391e940fa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188202240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.1188202240
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2539191192
Short name T333
Test name
Test status
Simulation time 72347301 ps
CPU time 2.17 seconds
Started Aug 11 07:02:12 PM PDT 24
Finished Aug 11 07:02:14 PM PDT 24
Peak memory 238880 kb
Host smart-ad6a4de8-b9fd-4cc8-ac5f-3a535a07d2fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539191192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.2539191192
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2577520001
Short name T1254
Test name
Test status
Simulation time 72373001 ps
CPU time 4.72 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:16 PM PDT 24
Peak memory 246172 kb
Host smart-c7ddf1ce-d49b-4714-836d-95382a41467f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577520001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.2577520001
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3202599775
Short name T1215
Test name
Test status
Simulation time 70252117 ps
CPU time 2.32 seconds
Started Aug 11 07:02:10 PM PDT 24
Finished Aug 11 07:02:13 PM PDT 24
Peak memory 247156 kb
Host smart-d17ce366-6241-43d2-82d4-700f01b3096e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202599775 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.3202599775
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1374832961
Short name T316
Test name
Test status
Simulation time 159156135 ps
CPU time 1.82 seconds
Started Aug 11 07:02:10 PM PDT 24
Finished Aug 11 07:02:12 PM PDT 24
Peak memory 241220 kb
Host smart-623f21e5-f328-45f1-8438-bd11d0a3e066
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374832961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.1374832961
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1180811602
Short name T1222
Test name
Test status
Simulation time 141608831 ps
CPU time 1.45 seconds
Started Aug 11 07:02:09 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 230548 kb
Host smart-455f43a7-6be8-4443-aba1-a8b1914ff3e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180811602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.1180811602
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1116275775
Short name T328
Test name
Test status
Simulation time 55943016 ps
CPU time 2.44 seconds
Started Aug 11 07:02:12 PM PDT 24
Finished Aug 11 07:02:15 PM PDT 24
Peak memory 238792 kb
Host smart-5edcd675-6943-4026-a258-839bf7afe5be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116275775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.1116275775
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1191950878
Short name T1255
Test name
Test status
Simulation time 171306495 ps
CPU time 6.41 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:18 PM PDT 24
Peak memory 246300 kb
Host smart-92e2d43c-3cce-4626-9a1b-1f5985d4e02e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191950878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1191950878
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3872790060
Short name T1258
Test name
Test status
Simulation time 1567051405 ps
CPU time 4.55 seconds
Started Aug 11 07:02:16 PM PDT 24
Finished Aug 11 07:02:21 PM PDT 24
Peak memory 247156 kb
Host smart-cac637cb-38ec-4465-bb02-f2ec817c7ba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872790060 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.3872790060
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.2705264121
Short name T278
Test name
Test status
Simulation time 160538517 ps
CPU time 1.72 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:12 PM PDT 24
Peak memory 240320 kb
Host smart-71fa08b3-d1fb-465d-a8f6-56b0f1494f18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705264121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.2705264121
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.829957473
Short name T1305
Test name
Test status
Simulation time 77161461 ps
CPU time 1.45 seconds
Started Aug 11 07:02:12 PM PDT 24
Finished Aug 11 07:02:14 PM PDT 24
Peak memory 229956 kb
Host smart-0efdf8e9-6839-484e-92cf-92b88cbb7378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829957473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.829957473
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3439664604
Short name T326
Test name
Test status
Simulation time 203594032 ps
CPU time 2.99 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:14 PM PDT 24
Peak memory 238832 kb
Host smart-f337661a-daef-411c-bbc7-249c3401b0d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439664604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.3439664604
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.457375045
Short name T1195
Test name
Test status
Simulation time 203037669 ps
CPU time 3.39 seconds
Started Aug 11 07:02:08 PM PDT 24
Finished Aug 11 07:02:12 PM PDT 24
Peak memory 245716 kb
Host smart-d5124593-5dc0-4862-a8f2-aa01a97215ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457375045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.457375045
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2948925791
Short name T1212
Test name
Test status
Simulation time 115830136 ps
CPU time 2.18 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:13 PM PDT 24
Peak memory 244308 kb
Host smart-14b17778-0d32-4861-b030-17e78a41a6a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948925791 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.2948925791
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2184538397
Short name T330
Test name
Test status
Simulation time 38581278 ps
CPU time 1.54 seconds
Started Aug 11 07:02:08 PM PDT 24
Finished Aug 11 07:02:10 PM PDT 24
Peak memory 238840 kb
Host smart-d17d8bc0-5b47-4ba7-a607-ca871d9f8aca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184538397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.2184538397
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.591376138
Short name T1228
Test name
Test status
Simulation time 38388423 ps
CPU time 1.38 seconds
Started Aug 11 07:02:15 PM PDT 24
Finished Aug 11 07:02:17 PM PDT 24
Peak memory 229908 kb
Host smart-79a8068d-d8bf-44d2-aa80-2425dc8c3a1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591376138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.591376138
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1333613402
Short name T1310
Test name
Test status
Simulation time 66729325 ps
CPU time 2.15 seconds
Started Aug 11 07:02:12 PM PDT 24
Finished Aug 11 07:02:14 PM PDT 24
Peak memory 238824 kb
Host smart-8164c88e-57bf-436a-8d6f-a476d679cd3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333613402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.1333613402
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1219510756
Short name T1208
Test name
Test status
Simulation time 1437733778 ps
CPU time 3.82 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:15 PM PDT 24
Peak memory 246140 kb
Host smart-21b8186c-33dc-49e5-86b0-e5c66214db9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219510756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.1219510756
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3157708928
Short name T367
Test name
Test status
Simulation time 4010097419 ps
CPU time 21.43 seconds
Started Aug 11 07:02:10 PM PDT 24
Finished Aug 11 07:02:31 PM PDT 24
Peak memory 244444 kb
Host smart-3124a570-54c3-49a8-8081-c24adf66b849
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157708928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.3157708928
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.4291809464
Short name T1298
Test name
Test status
Simulation time 210098544 ps
CPU time 6.79 seconds
Started Aug 11 07:01:52 PM PDT 24
Finished Aug 11 07:01:59 PM PDT 24
Peak memory 238860 kb
Host smart-dabcc3e0-9029-4d68-90f1-77397cb98c61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291809464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.4291809464
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2724983639
Short name T1209
Test name
Test status
Simulation time 674319019 ps
CPU time 8.72 seconds
Started Aug 11 07:01:53 PM PDT 24
Finished Aug 11 07:02:02 PM PDT 24
Peak memory 238748 kb
Host smart-6daa7ad3-b2e0-41ce-aeba-cc0968c00e47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724983639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.2724983639
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1930021196
Short name T1294
Test name
Test status
Simulation time 91256979 ps
CPU time 2.28 seconds
Started Aug 11 07:01:53 PM PDT 24
Finished Aug 11 07:01:55 PM PDT 24
Peak memory 238904 kb
Host smart-31c28cc7-0f08-47d9-a4f2-59c5daa879ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930021196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.1930021196
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2441804154
Short name T1246
Test name
Test status
Simulation time 62518818 ps
CPU time 1.92 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:00 PM PDT 24
Peak memory 240960 kb
Host smart-13c78ac6-8ce6-42a5-abe3-db1e159e9348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441804154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.2441804154
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.4045609093
Short name T1314
Test name
Test status
Simulation time 38397891 ps
CPU time 1.5 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:01:59 PM PDT 24
Peak memory 229928 kb
Host smart-d84c77bc-6e9e-4245-bea0-518da5a323f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045609093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.4045609093
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1517046104
Short name T1219
Test name
Test status
Simulation time 50140551 ps
CPU time 1.4 seconds
Started Aug 11 07:01:53 PM PDT 24
Finished Aug 11 07:01:55 PM PDT 24
Peak memory 229640 kb
Host smart-77db4916-5872-41b1-8ebc-4e775dfb8803
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517046104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.1517046104
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1518798566
Short name T1231
Test name
Test status
Simulation time 126343718 ps
CPU time 1.45 seconds
Started Aug 11 07:01:53 PM PDT 24
Finished Aug 11 07:01:54 PM PDT 24
Peak memory 229636 kb
Host smart-ceae928f-5499-4681-9066-2e9c86f4c082
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518798566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.1518798566
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3813769961
Short name T1280
Test name
Test status
Simulation time 294983523 ps
CPU time 2.42 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:00 PM PDT 24
Peak memory 238772 kb
Host smart-3f98952d-4205-4c13-8f78-00d8591bbbc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813769961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.3813769961
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3820339482
Short name T1251
Test name
Test status
Simulation time 176640297 ps
CPU time 5.99 seconds
Started Aug 11 07:01:53 PM PDT 24
Finished Aug 11 07:01:59 PM PDT 24
Peak memory 246120 kb
Host smart-b25e0800-6f8a-49f6-b4c8-b5e89cd152c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820339482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3820339482
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2087626089
Short name T1241
Test name
Test status
Simulation time 741419149 ps
CPU time 10.72 seconds
Started Aug 11 07:01:55 PM PDT 24
Finished Aug 11 07:02:06 PM PDT 24
Peak memory 239064 kb
Host smart-1546a176-7be1-4719-8d6d-8769dd0aaec7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087626089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.2087626089
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.2021489629
Short name T1221
Test name
Test status
Simulation time 45233472 ps
CPU time 1.37 seconds
Started Aug 11 07:02:09 PM PDT 24
Finished Aug 11 07:02:10 PM PDT 24
Peak memory 229916 kb
Host smart-ef111369-f9c1-4751-9e5d-527fcb5629f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021489629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.2021489629
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2545534315
Short name T1288
Test name
Test status
Simulation time 91658360 ps
CPU time 1.51 seconds
Started Aug 11 07:02:11 PM PDT 24
Finished Aug 11 07:02:13 PM PDT 24
Peak memory 230812 kb
Host smart-e554b1f6-cb7e-46d7-865d-918967fd7d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545534315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2545534315
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2602092965
Short name T1311
Test name
Test status
Simulation time 152097132 ps
CPU time 1.56 seconds
Started Aug 11 07:02:10 PM PDT 24
Finished Aug 11 07:02:12 PM PDT 24
Peak memory 229992 kb
Host smart-6c397282-5873-4fd1-84c1-fd28b5e65b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602092965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.2602092965
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2506378574
Short name T1250
Test name
Test status
Simulation time 89595174 ps
CPU time 1.38 seconds
Started Aug 11 07:02:12 PM PDT 24
Finished Aug 11 07:02:14 PM PDT 24
Peak memory 229924 kb
Host smart-f1c9c81b-bb7e-4e23-acc7-e9b46066bb58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506378574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.2506378574
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.1852680655
Short name T1202
Test name
Test status
Simulation time 84948185 ps
CPU time 1.43 seconds
Started Aug 11 07:02:15 PM PDT 24
Finished Aug 11 07:02:17 PM PDT 24
Peak memory 229904 kb
Host smart-b68e6a92-7ffc-41d2-b37d-29642252402c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852680655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.1852680655
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1541458296
Short name T1200
Test name
Test status
Simulation time 562704875 ps
CPU time 1.42 seconds
Started Aug 11 07:02:15 PM PDT 24
Finished Aug 11 07:02:17 PM PDT 24
Peak memory 229940 kb
Host smart-61e5ea3b-e100-4b3a-b1db-b2b4b0216036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541458296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1541458296
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.2260842257
Short name T1253
Test name
Test status
Simulation time 75769242 ps
CPU time 1.4 seconds
Started Aug 11 07:02:13 PM PDT 24
Finished Aug 11 07:02:14 PM PDT 24
Peak memory 230608 kb
Host smart-c5626588-3b2c-470b-b555-424d35f110ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260842257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.2260842257
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1576087859
Short name T1309
Test name
Test status
Simulation time 76537960 ps
CPU time 1.62 seconds
Started Aug 11 07:02:15 PM PDT 24
Finished Aug 11 07:02:17 PM PDT 24
Peak memory 230656 kb
Host smart-5bd8f2f8-2166-4ad3-b455-b9b9456d38cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576087859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1576087859
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.337789585
Short name T1203
Test name
Test status
Simulation time 42593579 ps
CPU time 1.49 seconds
Started Aug 11 07:02:16 PM PDT 24
Finished Aug 11 07:02:18 PM PDT 24
Peak memory 230644 kb
Host smart-5836913e-267d-46fe-b2f3-c69a80a57662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337789585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.337789585
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1911979144
Short name T1317
Test name
Test status
Simulation time 151428508 ps
CPU time 1.53 seconds
Started Aug 11 07:02:13 PM PDT 24
Finished Aug 11 07:02:15 PM PDT 24
Peak memory 230256 kb
Host smart-30a6481c-2630-4eed-a60d-f22b4c79dcab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911979144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1911979144
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.607569338
Short name T1319
Test name
Test status
Simulation time 837445038 ps
CPU time 6.34 seconds
Started Aug 11 07:02:06 PM PDT 24
Finished Aug 11 07:02:13 PM PDT 24
Peak memory 238864 kb
Host smart-814a63c9-137f-4d36-a86b-542f66ccf13f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607569338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alias
ing.607569338
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2125369881
Short name T337
Test name
Test status
Simulation time 159258200 ps
CPU time 3.64 seconds
Started Aug 11 07:02:05 PM PDT 24
Finished Aug 11 07:02:09 PM PDT 24
Peak memory 230676 kb
Host smart-87ca94bc-18ca-43c4-a148-5f71705cd9b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125369881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.2125369881
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.971146853
Short name T1230
Test name
Test status
Simulation time 193149704 ps
CPU time 2.44 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:01 PM PDT 24
Peak memory 238828 kb
Host smart-3d707eeb-1132-40ee-b628-7128085a6ba4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971146853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_re
set.971146853
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.745742277
Short name T1201
Test name
Test status
Simulation time 124722348 ps
CPU time 2.13 seconds
Started Aug 11 07:01:59 PM PDT 24
Finished Aug 11 07:02:01 PM PDT 24
Peak memory 238896 kb
Host smart-f5ed118f-5054-4dc0-8f33-37422033d086
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745742277 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.745742277
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3383101157
Short name T1226
Test name
Test status
Simulation time 46946178 ps
CPU time 1.8 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:00 PM PDT 24
Peak memory 241032 kb
Host smart-26b25eaf-6391-429b-9fb6-d80f03952fc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383101157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.3383101157
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2539453689
Short name T1248
Test name
Test status
Simulation time 43548275 ps
CPU time 1.49 seconds
Started Aug 11 07:02:02 PM PDT 24
Finished Aug 11 07:02:04 PM PDT 24
Peak memory 230184 kb
Host smart-4dc5c406-f61b-4695-9537-4534ae20e9a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539453689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.2539453689
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2955985744
Short name T1240
Test name
Test status
Simulation time 40998364 ps
CPU time 1.44 seconds
Started Aug 11 07:02:02 PM PDT 24
Finished Aug 11 07:02:03 PM PDT 24
Peak memory 230448 kb
Host smart-5cdbc6e0-fa6d-4cf3-9287-dd02310c3f14
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955985744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.2955985744
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3258292510
Short name T1196
Test name
Test status
Simulation time 40420252 ps
CPU time 1.39 seconds
Started Aug 11 07:02:04 PM PDT 24
Finished Aug 11 07:02:06 PM PDT 24
Peak memory 230544 kb
Host smart-95eb1b10-0447-46be-b64c-8938eaba2c1f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258292510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.3258292510
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1155691055
Short name T1306
Test name
Test status
Simulation time 675091582 ps
CPU time 2.2 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:00 PM PDT 24
Peak memory 238784 kb
Host smart-e615f34c-fd35-49ae-95eb-1ee69e508e6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155691055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.1155691055
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1992910326
Short name T1242
Test name
Test status
Simulation time 709395896 ps
CPU time 6.65 seconds
Started Aug 11 07:01:56 PM PDT 24
Finished Aug 11 07:02:03 PM PDT 24
Peak memory 245992 kb
Host smart-cac6ec00-ff89-4244-aca5-cabfb81cbdd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992910326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1992910326
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2811927244
Short name T368
Test name
Test status
Simulation time 1271263944 ps
CPU time 17.07 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:15 PM PDT 24
Peak memory 244028 kb
Host smart-7a1a73df-e521-4a64-91ed-72b2c78951c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811927244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.2811927244
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1789094449
Short name T1198
Test name
Test status
Simulation time 103337206 ps
CPU time 1.49 seconds
Started Aug 11 07:02:15 PM PDT 24
Finished Aug 11 07:02:17 PM PDT 24
Peak memory 230164 kb
Host smart-d8093652-7eeb-402f-ae50-e2f898ab559d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789094449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1789094449
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.231540518
Short name T1225
Test name
Test status
Simulation time 539668207 ps
CPU time 1.35 seconds
Started Aug 11 07:02:23 PM PDT 24
Finished Aug 11 07:02:24 PM PDT 24
Peak memory 229948 kb
Host smart-fd3112de-b5af-4891-bdcb-7d86b093c42c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231540518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.231540518
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.3081505214
Short name T1245
Test name
Test status
Simulation time 43999102 ps
CPU time 1.51 seconds
Started Aug 11 07:02:16 PM PDT 24
Finished Aug 11 07:02:18 PM PDT 24
Peak memory 230540 kb
Host smart-07da8bcb-e1b9-4966-83e1-564a24c9aa99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081505214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.3081505214
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.467018444
Short name T1286
Test name
Test status
Simulation time 77625336 ps
CPU time 1.45 seconds
Started Aug 11 07:02:14 PM PDT 24
Finished Aug 11 07:02:15 PM PDT 24
Peak memory 230608 kb
Host smart-fccdcb84-1479-47c2-b366-5d4b43e4f55a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467018444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.467018444
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3541303611
Short name T1266
Test name
Test status
Simulation time 141148330 ps
CPU time 1.5 seconds
Started Aug 11 07:02:17 PM PDT 24
Finished Aug 11 07:02:18 PM PDT 24
Peak memory 230664 kb
Host smart-96a4d100-17f5-45b7-8319-5baef593675a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541303611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.3541303611
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.1688278323
Short name T1278
Test name
Test status
Simulation time 567209612 ps
CPU time 1.69 seconds
Started Aug 11 07:02:16 PM PDT 24
Finished Aug 11 07:02:18 PM PDT 24
Peak memory 229972 kb
Host smart-e80cbe3b-4d7b-4028-b7e5-1af3b2cd090d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688278323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.1688278323
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.2961588729
Short name T1292
Test name
Test status
Simulation time 75063576 ps
CPU time 1.49 seconds
Started Aug 11 07:02:15 PM PDT 24
Finished Aug 11 07:02:16 PM PDT 24
Peak memory 230608 kb
Host smart-32741eaf-8dc8-41e5-a238-474717fe4f68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961588729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.2961588729
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2337744078
Short name T1227
Test name
Test status
Simulation time 137406867 ps
CPU time 1.56 seconds
Started Aug 11 07:02:22 PM PDT 24
Finished Aug 11 07:02:24 PM PDT 24
Peak memory 229972 kb
Host smart-5ff07e8c-24c2-42e4-af18-ea5ee3a1e5bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337744078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.2337744078
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2636439436
Short name T1236
Test name
Test status
Simulation time 146717860 ps
CPU time 1.48 seconds
Started Aug 11 07:02:14 PM PDT 24
Finished Aug 11 07:02:16 PM PDT 24
Peak memory 230632 kb
Host smart-fad91464-7920-4663-ae64-fe4f0b0d2b52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636439436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2636439436
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2532392018
Short name T1218
Test name
Test status
Simulation time 40463719 ps
CPU time 1.42 seconds
Started Aug 11 07:02:21 PM PDT 24
Finished Aug 11 07:02:22 PM PDT 24
Peak memory 230664 kb
Host smart-f5a3a651-6748-48a3-a1a2-12864766d5cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532392018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2532392018
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.956940020
Short name T306
Test name
Test status
Simulation time 100173588 ps
CPU time 3.67 seconds
Started Aug 11 07:02:04 PM PDT 24
Finished Aug 11 07:02:08 PM PDT 24
Peak memory 238860 kb
Host smart-5356cd4e-d143-4b6c-86ef-bddb153bdb4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956940020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alias
ing.956940020
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2393267162
Short name T1291
Test name
Test status
Simulation time 1976963652 ps
CPU time 7.95 seconds
Started Aug 11 07:02:06 PM PDT 24
Finished Aug 11 07:02:14 PM PDT 24
Peak memory 239872 kb
Host smart-c7366ad7-a2dd-4fa2-abe9-a11c9204caa4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393267162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.2393267162
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1358241622
Short name T317
Test name
Test status
Simulation time 103653320 ps
CPU time 2.34 seconds
Started Aug 11 07:02:04 PM PDT 24
Finished Aug 11 07:02:07 PM PDT 24
Peak memory 238872 kb
Host smart-fca7a0b7-01b5-42e3-83ff-8698475a19fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358241622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.1358241622
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.1911943627
Short name T1205
Test name
Test status
Simulation time 1699801835 ps
CPU time 3.84 seconds
Started Aug 11 07:02:01 PM PDT 24
Finished Aug 11 07:02:05 PM PDT 24
Peak memory 238848 kb
Host smart-17cdf2b8-4752-43b5-bac6-fde4cf2767ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911943627 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.1911943627
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2908275915
Short name T319
Test name
Test status
Simulation time 58234090 ps
CPU time 1.54 seconds
Started Aug 11 07:01:57 PM PDT 24
Finished Aug 11 07:01:58 PM PDT 24
Peak memory 241244 kb
Host smart-ea5250c4-9af5-4906-b425-264ae683fc45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908275915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.2908275915
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.3304637882
Short name T1287
Test name
Test status
Simulation time 38996268 ps
CPU time 1.37 seconds
Started Aug 11 07:02:00 PM PDT 24
Finished Aug 11 07:02:01 PM PDT 24
Peak memory 230296 kb
Host smart-598fb2eb-6ecc-4f12-9695-aee35333460e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304637882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.3304637882
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2617121587
Short name T1232
Test name
Test status
Simulation time 506150105 ps
CPU time 1.94 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:00 PM PDT 24
Peak memory 230444 kb
Host smart-1c9af105-68f5-454c-a5c9-0809cab37c6c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617121587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.2617121587
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.398845264
Short name T1249
Test name
Test status
Simulation time 40327046 ps
CPU time 1.33 seconds
Started Aug 11 07:02:06 PM PDT 24
Finished Aug 11 07:02:08 PM PDT 24
Peak memory 229684 kb
Host smart-489dd5e7-bf52-4708-a3a0-3f7bc7a3513b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398845264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.
398845264
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2961341730
Short name T1243
Test name
Test status
Simulation time 104076474 ps
CPU time 2.69 seconds
Started Aug 11 07:02:00 PM PDT 24
Finished Aug 11 07:02:03 PM PDT 24
Peak memory 238780 kb
Host smart-3fca6b4a-8389-4578-b91d-607f738569e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961341730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.2961341730
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3695123708
Short name T1235
Test name
Test status
Simulation time 3333247679 ps
CPU time 8.01 seconds
Started Aug 11 07:02:03 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 246728 kb
Host smart-7832f93b-dc0d-4c67-bf03-4e9791cb5e1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695123708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3695123708
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2551326062
Short name T1308
Test name
Test status
Simulation time 4864013153 ps
CPU time 25.46 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:24 PM PDT 24
Peak memory 239140 kb
Host smart-a99c3b24-b6ae-4672-a710-c9788e9c594e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551326062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.2551326062
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.55124190
Short name T1307
Test name
Test status
Simulation time 147623816 ps
CPU time 1.5 seconds
Started Aug 11 07:02:16 PM PDT 24
Finished Aug 11 07:02:18 PM PDT 24
Peak memory 229992 kb
Host smart-864fac05-0189-4694-a60b-601d6404ebd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55124190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.55124190
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.778437342
Short name T1302
Test name
Test status
Simulation time 42970341 ps
CPU time 1.5 seconds
Started Aug 11 07:02:21 PM PDT 24
Finished Aug 11 07:02:22 PM PDT 24
Peak memory 230020 kb
Host smart-c7976997-fb38-443a-99a2-f9d85ee8797d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778437342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.778437342
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.4293846998
Short name T1237
Test name
Test status
Simulation time 134013873 ps
CPU time 1.48 seconds
Started Aug 11 07:02:19 PM PDT 24
Finished Aug 11 07:02:21 PM PDT 24
Peak memory 230676 kb
Host smart-906a631d-6118-4989-9cfa-8449ad15d15e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293846998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.4293846998
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1832392101
Short name T1252
Test name
Test status
Simulation time 573894458 ps
CPU time 1.56 seconds
Started Aug 11 07:02:21 PM PDT 24
Finished Aug 11 07:02:22 PM PDT 24
Peak memory 230192 kb
Host smart-6dee4ad2-9c3b-4742-af90-646f098af239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832392101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1832392101
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.4146629988
Short name T1281
Test name
Test status
Simulation time 155202249 ps
CPU time 1.4 seconds
Started Aug 11 07:02:16 PM PDT 24
Finished Aug 11 07:02:18 PM PDT 24
Peak memory 229820 kb
Host smart-05158d7b-8f67-419b-bc3d-8fb2c875b394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146629988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.4146629988
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.3470023150
Short name T1275
Test name
Test status
Simulation time 577049111 ps
CPU time 2.04 seconds
Started Aug 11 07:02:16 PM PDT 24
Finished Aug 11 07:02:19 PM PDT 24
Peak memory 229944 kb
Host smart-cff2b972-a114-413a-80ce-a5a9449ddc20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470023150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.3470023150
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.1860669028
Short name T1273
Test name
Test status
Simulation time 42105445 ps
CPU time 1.47 seconds
Started Aug 11 07:02:15 PM PDT 24
Finished Aug 11 07:02:16 PM PDT 24
Peak memory 229908 kb
Host smart-f25d7c17-73dd-41f5-8ece-79ad9b6036ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860669028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.1860669028
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.812286508
Short name T1233
Test name
Test status
Simulation time 76670168 ps
CPU time 1.49 seconds
Started Aug 11 07:02:14 PM PDT 24
Finished Aug 11 07:02:16 PM PDT 24
Peak memory 230588 kb
Host smart-1e315afa-daf4-4155-a541-2596416f4d0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812286508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.812286508
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.98871525
Short name T1272
Test name
Test status
Simulation time 37767615 ps
CPU time 1.4 seconds
Started Aug 11 07:02:22 PM PDT 24
Finished Aug 11 07:02:24 PM PDT 24
Peak memory 230644 kb
Host smart-3c56b725-3ed6-4834-8336-5390ad278ccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98871525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.98871525
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.1511100467
Short name T1274
Test name
Test status
Simulation time 47438069 ps
CPU time 1.46 seconds
Started Aug 11 07:02:24 PM PDT 24
Finished Aug 11 07:02:26 PM PDT 24
Peak memory 229988 kb
Host smart-5478ef95-0780-40d9-9586-3b0ff8b072f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511100467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.1511100467
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2453515565
Short name T1293
Test name
Test status
Simulation time 1690657515 ps
CPU time 3.98 seconds
Started Aug 11 07:01:57 PM PDT 24
Finished Aug 11 07:02:02 PM PDT 24
Peak memory 247104 kb
Host smart-124148b2-ab22-4a8e-9caa-69a1fe56eb9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453515565 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.2453515565
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.2066658601
Short name T329
Test name
Test status
Simulation time 168994564 ps
CPU time 1.81 seconds
Started Aug 11 07:02:02 PM PDT 24
Finished Aug 11 07:02:04 PM PDT 24
Peak memory 238852 kb
Host smart-6ce6221e-a537-4de8-b9c2-e02c76fb310d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066658601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.2066658601
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.2942562106
Short name T1220
Test name
Test status
Simulation time 525323571 ps
CPU time 1.51 seconds
Started Aug 11 07:02:06 PM PDT 24
Finished Aug 11 07:02:08 PM PDT 24
Peak memory 229940 kb
Host smart-a3ec1bc4-9215-4be2-8ebf-91914ce7b111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942562106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.2942562106
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3777822578
Short name T1289
Test name
Test status
Simulation time 151101488 ps
CPU time 2.47 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:00 PM PDT 24
Peak memory 238828 kb
Host smart-688e0a47-23ee-463e-8949-55ac3972b287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777822578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.3777822578
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2045121321
Short name T1283
Test name
Test status
Simulation time 134539121 ps
CPU time 5.35 seconds
Started Aug 11 07:01:57 PM PDT 24
Finished Aug 11 07:02:02 PM PDT 24
Peak memory 246168 kb
Host smart-bb20acd7-4e59-4ea1-80a0-c9b91136d79a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045121321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.2045121321
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3697034256
Short name T366
Test name
Test status
Simulation time 657911136 ps
CPU time 9.34 seconds
Started Aug 11 07:01:58 PM PDT 24
Finished Aug 11 07:02:07 PM PDT 24
Peak memory 238780 kb
Host smart-09887a65-5517-4ea7-b836-764467979a83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697034256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.3697034256
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3083101439
Short name T389
Test name
Test status
Simulation time 255986537 ps
CPU time 2.74 seconds
Started Aug 11 07:02:06 PM PDT 24
Finished Aug 11 07:02:09 PM PDT 24
Peak memory 247112 kb
Host smart-58e0921c-f044-451c-a820-cf1628ee2851
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083101439 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.3083101439
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.806280117
Short name T310
Test name
Test status
Simulation time 44840117 ps
CPU time 1.67 seconds
Started Aug 11 07:02:09 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 237756 kb
Host smart-3c9569dd-4bff-4069-9875-54c48cf6802e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806280117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.806280117
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2763758609
Short name T1301
Test name
Test status
Simulation time 73031216 ps
CPU time 1.44 seconds
Started Aug 11 07:02:10 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 229132 kb
Host smart-2bd6eafa-33a3-4a1b-8c2f-e4a0d9c04fbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763758609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2763758609
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.142684285
Short name T331
Test name
Test status
Simulation time 66023631 ps
CPU time 2.14 seconds
Started Aug 11 07:02:06 PM PDT 24
Finished Aug 11 07:02:08 PM PDT 24
Peak memory 238808 kb
Host smart-26e43f6a-5207-43fe-9077-6110066a1259
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142684285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ct
rl_same_csr_outstanding.142684285
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1212558120
Short name T1260
Test name
Test status
Simulation time 372880942 ps
CPU time 3.47 seconds
Started Aug 11 07:02:03 PM PDT 24
Finished Aug 11 07:02:07 PM PDT 24
Peak memory 245860 kb
Host smart-6e49ffc8-2f72-46f4-9c17-adbefa7b34b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212558120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.1212558120
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1330495893
Short name T1223
Test name
Test status
Simulation time 66222436 ps
CPU time 2.17 seconds
Started Aug 11 07:02:08 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 246044 kb
Host smart-3f0a0823-5b72-4a6e-b903-474dc5cc169b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330495893 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.1330495893
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.288376848
Short name T307
Test name
Test status
Simulation time 648862088 ps
CPU time 2.3 seconds
Started Aug 11 07:02:03 PM PDT 24
Finished Aug 11 07:02:06 PM PDT 24
Peak memory 238856 kb
Host smart-795001a4-c8d3-456c-965f-6bbd06e21b79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288376848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.288376848
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.2236344107
Short name T1261
Test name
Test status
Simulation time 39290710 ps
CPU time 1.41 seconds
Started Aug 11 07:02:10 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 229852 kb
Host smart-b408448c-161f-4525-aec9-61f927dffda8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236344107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.2236344107
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.4105426122
Short name T1312
Test name
Test status
Simulation time 46051039 ps
CPU time 1.98 seconds
Started Aug 11 07:02:06 PM PDT 24
Finished Aug 11 07:02:08 PM PDT 24
Peak memory 241848 kb
Host smart-086e41f8-bcaa-455c-8cf0-2b2fd4f48e9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105426122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.4105426122
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3230037727
Short name T1211
Test name
Test status
Simulation time 1224223315 ps
CPU time 6.39 seconds
Started Aug 11 07:02:09 PM PDT 24
Finished Aug 11 07:02:16 PM PDT 24
Peak memory 237816 kb
Host smart-b1e48e9d-9282-4b26-a3e8-fea2409f912b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230037727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3230037727
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1768355489
Short name T1303
Test name
Test status
Simulation time 2284758717 ps
CPU time 9.25 seconds
Started Aug 11 07:02:03 PM PDT 24
Finished Aug 11 07:02:12 PM PDT 24
Peak memory 243676 kb
Host smart-494ef0bd-ceef-47e0-9e83-1a89a1eee124
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768355489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.1768355489
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2440666449
Short name T1244
Test name
Test status
Simulation time 147037946 ps
CPU time 2.13 seconds
Started Aug 11 07:02:06 PM PDT 24
Finished Aug 11 07:02:08 PM PDT 24
Peak memory 238980 kb
Host smart-95954047-94b4-43cb-94d4-a80f430b2a77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440666449 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.2440666449
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3463416314
Short name T324
Test name
Test status
Simulation time 54884963 ps
CPU time 1.54 seconds
Started Aug 11 07:02:05 PM PDT 24
Finished Aug 11 07:02:06 PM PDT 24
Peak memory 240568 kb
Host smart-b0c617b4-80cd-456c-97b7-499d7a58b77f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463416314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.3463416314
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.354212049
Short name T1304
Test name
Test status
Simulation time 159240622 ps
CPU time 1.56 seconds
Started Aug 11 07:02:07 PM PDT 24
Finished Aug 11 07:02:09 PM PDT 24
Peak memory 229952 kb
Host smart-17482abc-2ea9-4017-b489-c20a70327d70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354212049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.354212049
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.4163712298
Short name T1318
Test name
Test status
Simulation time 77813656 ps
CPU time 1.93 seconds
Started Aug 11 07:02:09 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 237792 kb
Host smart-c4047e4d-08e2-46b0-8c39-2c5390844f07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163712298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.4163712298
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3767475363
Short name T1265
Test name
Test status
Simulation time 545564791 ps
CPU time 7.1 seconds
Started Aug 11 07:02:03 PM PDT 24
Finished Aug 11 07:02:11 PM PDT 24
Peak memory 246112 kb
Host smart-5dfa8c37-3b65-41b8-a3be-8c46b34fb51d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767475363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.3767475363
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2757960079
Short name T1295
Test name
Test status
Simulation time 2333979780 ps
CPU time 11.27 seconds
Started Aug 11 07:02:05 PM PDT 24
Finished Aug 11 07:02:16 PM PDT 24
Peak memory 238828 kb
Host smart-0797e6a9-2aba-4cd1-a4b1-dd76f78de297
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757960079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.2757960079
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1463816392
Short name T1316
Test name
Test status
Simulation time 206999269 ps
CPU time 3.79 seconds
Started Aug 11 07:02:08 PM PDT 24
Finished Aug 11 07:02:12 PM PDT 24
Peak memory 247060 kb
Host smart-127f39e6-07cc-4750-8b63-da6fd416336f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463816392 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.1463816392
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.467972620
Short name T1297
Test name
Test status
Simulation time 142864016 ps
CPU time 1.58 seconds
Started Aug 11 07:02:05 PM PDT 24
Finished Aug 11 07:02:07 PM PDT 24
Peak memory 241452 kb
Host smart-6efd70dd-ad19-4f1e-adf2-8a595d7e8565
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467972620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.467972620
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1293118247
Short name T1234
Test name
Test status
Simulation time 41653552 ps
CPU time 1.44 seconds
Started Aug 11 07:02:03 PM PDT 24
Finished Aug 11 07:02:05 PM PDT 24
Peak memory 229892 kb
Host smart-65b7e7d9-9e20-49ce-885f-3b82c6c99ba7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293118247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1293118247
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3779221433
Short name T332
Test name
Test status
Simulation time 163222659 ps
CPU time 2 seconds
Started Aug 11 07:02:05 PM PDT 24
Finished Aug 11 07:02:07 PM PDT 24
Peak memory 238708 kb
Host smart-0b5050dd-6713-4d98-9440-2d942abbcdc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779221433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.3779221433
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1841015945
Short name T1279
Test name
Test status
Simulation time 734798129 ps
CPU time 7.78 seconds
Started Aug 11 07:02:07 PM PDT 24
Finished Aug 11 07:02:15 PM PDT 24
Peak memory 246068 kb
Host smart-07f0324a-2143-43df-a52f-595b99ccdde1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841015945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.1841015945
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1087345025
Short name T274
Test name
Test status
Simulation time 1809618309 ps
CPU time 9.99 seconds
Started Aug 11 07:02:05 PM PDT 24
Finished Aug 11 07:02:15 PM PDT 24
Peak memory 243680 kb
Host smart-5efd7768-4ce5-45c0-b868-2c92e0469ca0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087345025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.1087345025
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.567937959
Short name T693
Test name
Test status
Simulation time 555603993 ps
CPU time 1.61 seconds
Started Aug 11 06:45:36 PM PDT 24
Finished Aug 11 06:45:37 PM PDT 24
Peak memory 240784 kb
Host smart-279cb076-4813-4c6d-b57a-4312259cd6b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567937959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.567937959
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.3458093412
Short name T480
Test name
Test status
Simulation time 797897659 ps
CPU time 5.11 seconds
Started Aug 11 06:45:26 PM PDT 24
Finished Aug 11 06:45:31 PM PDT 24
Peak memory 242500 kb
Host smart-549a60c4-87e2-4537-8689-a1f77cc29ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458093412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.3458093412
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.3820460401
Short name T778
Test name
Test status
Simulation time 699971091 ps
CPU time 13.13 seconds
Started Aug 11 06:45:24 PM PDT 24
Finished Aug 11 06:45:37 PM PDT 24
Peak memory 248552 kb
Host smart-965e0e1a-171c-43a7-ad1c-11cac1d88a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820460401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.3820460401
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.2831758245
Short name T1176
Test name
Test status
Simulation time 414099959 ps
CPU time 22.74 seconds
Started Aug 11 06:45:26 PM PDT 24
Finished Aug 11 06:45:49 PM PDT 24
Peak memory 241980 kb
Host smart-baecd018-0c9d-418e-b8a5-515ee52ffa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831758245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.2831758245
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.2899499102
Short name T1065
Test name
Test status
Simulation time 2416344622 ps
CPU time 20.01 seconds
Started Aug 11 06:45:25 PM PDT 24
Finished Aug 11 06:45:45 PM PDT 24
Peak memory 242344 kb
Host smart-8853652a-00a7-4615-8310-b99d7838a3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899499102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.2899499102
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.3745120824
Short name T465
Test name
Test status
Simulation time 3067949592 ps
CPU time 10.92 seconds
Started Aug 11 06:45:26 PM PDT 24
Finished Aug 11 06:45:37 PM PDT 24
Peak memory 240728 kb
Host smart-e9fc18c5-d796-4fd9-9f81-66b4074792d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745120824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.3745120824
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.4145030392
Short name T978
Test name
Test status
Simulation time 3766062274 ps
CPU time 25.66 seconds
Started Aug 11 06:45:28 PM PDT 24
Finished Aug 11 06:45:54 PM PDT 24
Peak memory 248676 kb
Host smart-48fbb4ff-95d4-41f6-82f0-15b3a77fe902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145030392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.4145030392
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.3351663678
Short name T1050
Test name
Test status
Simulation time 2194467037 ps
CPU time 7.32 seconds
Started Aug 11 06:45:24 PM PDT 24
Finished Aug 11 06:45:31 PM PDT 24
Peak memory 242400 kb
Host smart-3093e494-714d-4c16-b630-86069212e5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351663678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.3351663678
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.1169589732
Short name T1136
Test name
Test status
Simulation time 484587986 ps
CPU time 12.48 seconds
Started Aug 11 06:45:24 PM PDT 24
Finished Aug 11 06:45:37 PM PDT 24
Peak memory 247640 kb
Host smart-34105b36-f508-4a27-ad4d-cd8ec457cc76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1169589732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.1169589732
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.1500124822
Short name T447
Test name
Test status
Simulation time 1068095275 ps
CPU time 19.38 seconds
Started Aug 11 06:45:25 PM PDT 24
Finished Aug 11 06:45:44 PM PDT 24
Peak memory 241528 kb
Host smart-2d7688bd-abf5-4c54-87f4-6afddb8be78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500124822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1500124822
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.1341208354
Short name T777
Test name
Test status
Simulation time 223586019 ps
CPU time 6.63 seconds
Started Aug 11 06:45:20 PM PDT 24
Finished Aug 11 06:45:26 PM PDT 24
Peak memory 241892 kb
Host smart-1ec983fc-b7f3-41f3-9869-9cf7cac1d143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341208354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.1341208354
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.569813841
Short name T133
Test name
Test status
Simulation time 394480622803 ps
CPU time 732.64 seconds
Started Aug 11 06:45:35 PM PDT 24
Finished Aug 11 06:57:48 PM PDT 24
Peak memory 331108 kb
Host smart-ae1e4432-ebeb-492e-9596-fd1c5470931c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569813841 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.569813841
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.1909588249
Short name T971
Test name
Test status
Simulation time 7010758552 ps
CPU time 18.39 seconds
Started Aug 11 06:45:30 PM PDT 24
Finished Aug 11 06:45:48 PM PDT 24
Peak memory 242748 kb
Host smart-2e50a2b3-ae5a-4aae-9e76-881444e12e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909588249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.1909588249
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.971621641
Short name T851
Test name
Test status
Simulation time 921269683 ps
CPU time 15.87 seconds
Started Aug 11 06:45:38 PM PDT 24
Finished Aug 11 06:45:54 PM PDT 24
Peak memory 248636 kb
Host smart-bb88195f-3e34-4e6f-838b-7ff9f5253568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971621641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.971621641
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.4169302535
Short name T507
Test name
Test status
Simulation time 17771246339 ps
CPU time 42.28 seconds
Started Aug 11 06:45:43 PM PDT 24
Finished Aug 11 06:46:26 PM PDT 24
Peak memory 243264 kb
Host smart-fe52ca2c-741f-42b7-9ca8-467e2903d213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169302535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.4169302535
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.734371091
Short name T178
Test name
Test status
Simulation time 1077641994 ps
CPU time 15.76 seconds
Started Aug 11 06:45:38 PM PDT 24
Finished Aug 11 06:45:54 PM PDT 24
Peak memory 242100 kb
Host smart-047d518c-e842-435e-8e4e-32cabc6ab420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734371091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.734371091
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.194409750
Short name T781
Test name
Test status
Simulation time 93256451 ps
CPU time 2.59 seconds
Started Aug 11 06:45:40 PM PDT 24
Finished Aug 11 06:45:42 PM PDT 24
Peak memory 241992 kb
Host smart-7bb25fb3-e9dd-4812-9e23-d1ef3c9ab323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194409750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.194409750
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.4267447891
Short name T846
Test name
Test status
Simulation time 593776170 ps
CPU time 4.28 seconds
Started Aug 11 06:45:34 PM PDT 24
Finished Aug 11 06:45:38 PM PDT 24
Peak memory 242336 kb
Host smart-8877ab6c-ca0e-4d76-8e89-352c1bdbd2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267447891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.4267447891
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.3854985272
Short name T868
Test name
Test status
Simulation time 1913225647 ps
CPU time 22.31 seconds
Started Aug 11 06:45:47 PM PDT 24
Finished Aug 11 06:46:09 PM PDT 24
Peak memory 242792 kb
Host smart-7bba1866-8d87-4ddb-9906-44dfa30fb264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854985272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.3854985272
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.2764694760
Short name T1090
Test name
Test status
Simulation time 2331279723 ps
CPU time 15.59 seconds
Started Aug 11 06:45:42 PM PDT 24
Finished Aug 11 06:45:58 PM PDT 24
Peak memory 242308 kb
Host smart-fe9e8f18-ace9-46c8-b83f-db5014bee954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764694760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.2764694760
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.3263214918
Short name T690
Test name
Test status
Simulation time 80245995 ps
CPU time 2.43 seconds
Started Aug 11 06:45:36 PM PDT 24
Finished Aug 11 06:45:39 PM PDT 24
Peak memory 241964 kb
Host smart-16f5f27a-1391-426c-8c8e-74794f1d3fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263214918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.3263214918
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.946888777
Short name T88
Test name
Test status
Simulation time 10817036722 ps
CPU time 25.96 seconds
Started Aug 11 06:45:39 PM PDT 24
Finished Aug 11 06:46:05 PM PDT 24
Peak memory 248708 kb
Host smart-3dd63cae-9067-4279-a407-ee0f05faff42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946888777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.946888777
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.3724373716
Short name T880
Test name
Test status
Simulation time 2470674119 ps
CPU time 6.07 seconds
Started Aug 11 06:45:44 PM PDT 24
Finished Aug 11 06:45:50 PM PDT 24
Peak memory 242272 kb
Host smart-a77e8b94-93b2-45f3-9078-ab1470a92e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3724373716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3724373716
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.1742117518
Short name T238
Test name
Test status
Simulation time 165726088399 ps
CPU time 260.54 seconds
Started Aug 11 06:45:43 PM PDT 24
Finished Aug 11 06:50:04 PM PDT 24
Peak memory 271784 kb
Host smart-fda961e6-10a2-4b13-894a-c2313965ed5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742117518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.1742117518
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.1970943306
Short name T107
Test name
Test status
Simulation time 242186376 ps
CPU time 5 seconds
Started Aug 11 06:45:33 PM PDT 24
Finished Aug 11 06:45:38 PM PDT 24
Peak memory 241896 kb
Host smart-8913b737-4cd3-42b1-9fc6-54c2b7cf1e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970943306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.1970943306
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.2514790680
Short name T140
Test name
Test status
Simulation time 691520184239 ps
CPU time 1752.65 seconds
Started Aug 11 06:45:47 PM PDT 24
Finished Aug 11 07:15:00 PM PDT 24
Peak memory 328684 kb
Host smart-ee35fe59-793a-4812-9e8d-ff7ab72a9bf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514790680 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.2514790680
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.2316314418
Short name T859
Test name
Test status
Simulation time 1385936794 ps
CPU time 22.16 seconds
Started Aug 11 06:45:43 PM PDT 24
Finished Aug 11 06:46:05 PM PDT 24
Peak memory 242068 kb
Host smart-c2f8268a-f651-4331-add1-bad8b1294a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316314418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.2316314418
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.3036145679
Short name T613
Test name
Test status
Simulation time 58643707 ps
CPU time 1.9 seconds
Started Aug 11 06:46:59 PM PDT 24
Finished Aug 11 06:47:01 PM PDT 24
Peak memory 240464 kb
Host smart-253be8fa-a8dd-4b93-9c37-3b74c4c699f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036145679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.3036145679
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.3642683060
Short name T244
Test name
Test status
Simulation time 2619045650 ps
CPU time 40.61 seconds
Started Aug 11 06:46:53 PM PDT 24
Finished Aug 11 06:47:34 PM PDT 24
Peak memory 242604 kb
Host smart-03f890a4-ffcb-490d-8604-713238513965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642683060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.3642683060
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.2285666588
Short name T420
Test name
Test status
Simulation time 748738560 ps
CPU time 19.38 seconds
Started Aug 11 06:46:54 PM PDT 24
Finished Aug 11 06:47:13 PM PDT 24
Peak memory 242412 kb
Host smart-166821a0-f48e-4073-93b6-1eb481ad08ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285666588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.2285666588
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.390320561
Short name T915
Test name
Test status
Simulation time 11219620458 ps
CPU time 23.23 seconds
Started Aug 11 06:46:54 PM PDT 24
Finished Aug 11 06:47:17 PM PDT 24
Peak memory 243208 kb
Host smart-720bcc23-64b8-40bb-9823-c7fdb0f125cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390320561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.390320561
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.3778554835
Short name T984
Test name
Test status
Simulation time 150081816 ps
CPU time 3.9 seconds
Started Aug 11 06:46:53 PM PDT 24
Finished Aug 11 06:46:57 PM PDT 24
Peak memory 242188 kb
Host smart-cd399ed9-0d42-4ddb-b2cd-815db9263077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778554835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3778554835
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.2671963792
Short name T1188
Test name
Test status
Simulation time 25270899502 ps
CPU time 61.25 seconds
Started Aug 11 06:46:51 PM PDT 24
Finished Aug 11 06:47:52 PM PDT 24
Peak memory 256860 kb
Host smart-0cbdcf74-5c15-49fb-84ab-5f7609abbdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671963792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.2671963792
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.1510563638
Short name T611
Test name
Test status
Simulation time 12618853679 ps
CPU time 25.12 seconds
Started Aug 11 06:46:52 PM PDT 24
Finished Aug 11 06:47:17 PM PDT 24
Peak memory 242768 kb
Host smart-fcca793b-8230-4b14-9aaf-6959739bb7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510563638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.1510563638
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.4097194709
Short name T818
Test name
Test status
Simulation time 1044923309 ps
CPU time 10.57 seconds
Started Aug 11 06:46:52 PM PDT 24
Finished Aug 11 06:47:03 PM PDT 24
Peak memory 241876 kb
Host smart-026ce1d7-f3c8-4370-87a8-28646de1984d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097194709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.4097194709
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.1747880072
Short name T889
Test name
Test status
Simulation time 763833404 ps
CPU time 7.85 seconds
Started Aug 11 06:46:54 PM PDT 24
Finished Aug 11 06:47:01 PM PDT 24
Peak memory 241968 kb
Host smart-8e1bb13a-c0ce-4518-a19e-c86515a1a1b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747880072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.1747880072
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.1935253043
Short name T379
Test name
Test status
Simulation time 2429041219 ps
CPU time 7.7 seconds
Started Aug 11 06:46:57 PM PDT 24
Finished Aug 11 06:47:05 PM PDT 24
Peak memory 241892 kb
Host smart-292d6ee4-0c81-40a9-9068-e6a4c00f6785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935253043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.1935253043
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.3394261716
Short name T1067
Test name
Test status
Simulation time 340481947 ps
CPU time 7.88 seconds
Started Aug 11 06:46:52 PM PDT 24
Finished Aug 11 06:47:00 PM PDT 24
Peak memory 242112 kb
Host smart-cc8eaac6-336b-4ac8-b36a-33c7dce16332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394261716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.3394261716
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.2315072183
Short name T205
Test name
Test status
Simulation time 270080060 ps
CPU time 6.4 seconds
Started Aug 11 06:46:58 PM PDT 24
Finished Aug 11 06:47:05 PM PDT 24
Peak memory 242644 kb
Host smart-4cde944f-9d4a-4d4c-b7e6-4ecca0753018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315072183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.2315072183
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.1789955959
Short name T702
Test name
Test status
Simulation time 206555190 ps
CPU time 3.75 seconds
Started Aug 11 06:50:12 PM PDT 24
Finished Aug 11 06:50:16 PM PDT 24
Peak memory 242076 kb
Host smart-3fbff69e-42fa-4c58-a4d4-acb7ff5d0a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789955959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.1789955959
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.399422015
Short name T691
Test name
Test status
Simulation time 372833819 ps
CPU time 12.67 seconds
Started Aug 11 06:50:14 PM PDT 24
Finished Aug 11 06:50:27 PM PDT 24
Peak memory 241920 kb
Host smart-5bf57e57-3438-492d-8157-ea70d65bf551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399422015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.399422015
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.2583103870
Short name T973
Test name
Test status
Simulation time 222083150 ps
CPU time 4.27 seconds
Started Aug 11 06:50:12 PM PDT 24
Finished Aug 11 06:50:17 PM PDT 24
Peak memory 242348 kb
Host smart-e9c492d5-dc22-4dbd-8912-6a905a825b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583103870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.2583103870
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.4083350490
Short name T609
Test name
Test status
Simulation time 396924276 ps
CPU time 3.18 seconds
Started Aug 11 06:50:12 PM PDT 24
Finished Aug 11 06:50:16 PM PDT 24
Peak memory 241864 kb
Host smart-d1940e85-fb72-42a4-88f4-d94fc8947e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083350490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.4083350490
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.1047107188
Short name T262
Test name
Test status
Simulation time 902778659 ps
CPU time 17.23 seconds
Started Aug 11 06:50:12 PM PDT 24
Finished Aug 11 06:50:29 PM PDT 24
Peak memory 241720 kb
Host smart-2cf03a23-9abd-40db-b396-193809903814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047107188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.1047107188
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.3529199604
Short name T1080
Test name
Test status
Simulation time 124547064 ps
CPU time 4.27 seconds
Started Aug 11 06:50:19 PM PDT 24
Finished Aug 11 06:50:24 PM PDT 24
Peak memory 241960 kb
Host smart-7870fd04-f69f-4485-94d8-c6d13aa35184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529199604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.3529199604
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.424811201
Short name T658
Test name
Test status
Simulation time 641455494 ps
CPU time 5.29 seconds
Started Aug 11 06:50:15 PM PDT 24
Finished Aug 11 06:50:20 PM PDT 24
Peak memory 242372 kb
Host smart-0e353610-6106-4f10-b27d-9c60f867b9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424811201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.424811201
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.3808844658
Short name T191
Test name
Test status
Simulation time 244675994 ps
CPU time 4.03 seconds
Started Aug 11 06:50:12 PM PDT 24
Finished Aug 11 06:50:16 PM PDT 24
Peak memory 242200 kb
Host smart-e8d64634-d2f0-4271-978b-ee2f9e391127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808844658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.3808844658
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.4285316301
Short name T505
Test name
Test status
Simulation time 610756084 ps
CPU time 5.43 seconds
Started Aug 11 06:50:15 PM PDT 24
Finished Aug 11 06:50:21 PM PDT 24
Peak memory 242164 kb
Host smart-dd5b63f7-56aa-4d3a-84bc-5930db59307a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285316301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.4285316301
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.1951885778
Short name T267
Test name
Test status
Simulation time 2093702551 ps
CPU time 5.89 seconds
Started Aug 11 06:50:12 PM PDT 24
Finished Aug 11 06:50:19 PM PDT 24
Peak memory 242032 kb
Host smart-d95a9df3-cb19-4477-b0d3-0b5e26f068db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951885778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1951885778
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.4028395912
Short name T1147
Test name
Test status
Simulation time 98770412 ps
CPU time 3.47 seconds
Started Aug 11 06:50:11 PM PDT 24
Finished Aug 11 06:50:14 PM PDT 24
Peak memory 242032 kb
Host smart-d5d48db2-1d63-49cd-9eb4-a541c7709095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028395912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.4028395912
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.4260679540
Short name T196
Test name
Test status
Simulation time 365981555 ps
CPU time 4.07 seconds
Started Aug 11 06:50:20 PM PDT 24
Finished Aug 11 06:50:24 PM PDT 24
Peak memory 241948 kb
Host smart-eeeb9af6-11b8-437a-8965-bea7cfebe329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260679540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.4260679540
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.5433369
Short name T640
Test name
Test status
Simulation time 317007487 ps
CPU time 6.46 seconds
Started Aug 11 06:50:19 PM PDT 24
Finished Aug 11 06:50:26 PM PDT 24
Peak memory 241956 kb
Host smart-d7c9c398-674d-427e-856d-07a611e9569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5433369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.5433369
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.1432139245
Short name T845
Test name
Test status
Simulation time 422106650 ps
CPU time 3.25 seconds
Started Aug 11 06:50:11 PM PDT 24
Finished Aug 11 06:50:14 PM PDT 24
Peak memory 242140 kb
Host smart-fb4a55dc-9159-44d1-b16a-e5f416fa8c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432139245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.1432139245
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.670335688
Short name T1026
Test name
Test status
Simulation time 4170381981 ps
CPU time 27.64 seconds
Started Aug 11 06:50:12 PM PDT 24
Finished Aug 11 06:50:40 PM PDT 24
Peak memory 242040 kb
Host smart-71e339a7-a6ad-4c08-82c8-d4d3339c42dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670335688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.670335688
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.4291693959
Short name T1177
Test name
Test status
Simulation time 194309988 ps
CPU time 3.76 seconds
Started Aug 11 06:50:09 PM PDT 24
Finished Aug 11 06:50:13 PM PDT 24
Peak memory 242004 kb
Host smart-7525a616-f2aa-4832-90e4-3dfcb4afde01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291693959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.4291693959
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.2546804135
Short name T602
Test name
Test status
Simulation time 137523404 ps
CPU time 6.72 seconds
Started Aug 11 06:50:18 PM PDT 24
Finished Aug 11 06:50:25 PM PDT 24
Peak memory 242292 kb
Host smart-fbfa1d0b-361f-4c4d-a6d6-79f67c9273fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546804135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.2546804135
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.3057053713
Short name T811
Test name
Test status
Simulation time 1829903514 ps
CPU time 6.12 seconds
Started Aug 11 06:50:22 PM PDT 24
Finished Aug 11 06:50:28 PM PDT 24
Peak memory 242132 kb
Host smart-915c2b2b-9ab2-4671-8cdb-493a7a6e6ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057053713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.3057053713
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.535422644
Short name T177
Test name
Test status
Simulation time 128813840 ps
CPU time 5.29 seconds
Started Aug 11 06:50:18 PM PDT 24
Finished Aug 11 06:50:23 PM PDT 24
Peak memory 241904 kb
Host smart-00c604b7-ba12-41d8-819a-48b1b709fc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535422644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.535422644
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.3126403685
Short name T779
Test name
Test status
Simulation time 62321965 ps
CPU time 1.86 seconds
Started Aug 11 06:47:04 PM PDT 24
Finished Aug 11 06:47:06 PM PDT 24
Peak memory 240316 kb
Host smart-79fad010-35e7-40e8-8638-4a4001c80ad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126403685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.3126403685
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.1190123030
Short name T808
Test name
Test status
Simulation time 929596684 ps
CPU time 21.54 seconds
Started Aug 11 06:46:58 PM PDT 24
Finished Aug 11 06:47:19 PM PDT 24
Peak memory 243240 kb
Host smart-75fe064b-09ec-4383-9ea1-f7cc19de4f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190123030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.1190123030
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.435110170
Short name T1163
Test name
Test status
Simulation time 1112773333 ps
CPU time 31.26 seconds
Started Aug 11 06:46:58 PM PDT 24
Finished Aug 11 06:47:29 PM PDT 24
Peak memory 245260 kb
Host smart-a6d86d4d-a726-435b-9a27-ac274fa43f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435110170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.435110170
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.343187784
Short name T972
Test name
Test status
Simulation time 3698937224 ps
CPU time 38.68 seconds
Started Aug 11 06:46:58 PM PDT 24
Finished Aug 11 06:47:37 PM PDT 24
Peak memory 243204 kb
Host smart-dcada19a-692e-4bff-99ac-911bc90f446b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343187784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.343187784
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.1722137817
Short name T221
Test name
Test status
Simulation time 19585034895 ps
CPU time 48.06 seconds
Started Aug 11 06:47:02 PM PDT 24
Finished Aug 11 06:47:50 PM PDT 24
Peak memory 246468 kb
Host smart-854c451f-f395-4a6a-8957-649c6e52bb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722137817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.1722137817
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.982734097
Short name T866
Test name
Test status
Simulation time 13124921248 ps
CPU time 27.24 seconds
Started Aug 11 06:47:08 PM PDT 24
Finished Aug 11 06:47:36 PM PDT 24
Peak memory 243488 kb
Host smart-43fad107-ee44-46a9-b4bc-23789d834eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982734097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.982734097
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.1652088097
Short name T855
Test name
Test status
Simulation time 198896874 ps
CPU time 4.79 seconds
Started Aug 11 06:46:57 PM PDT 24
Finished Aug 11 06:47:02 PM PDT 24
Peak memory 241820 kb
Host smart-6d26e9e8-8216-4413-b50d-412803013a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652088097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.1652088097
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.977599928
Short name T826
Test name
Test status
Simulation time 174172872 ps
CPU time 5.02 seconds
Started Aug 11 06:46:58 PM PDT 24
Finished Aug 11 06:47:03 PM PDT 24
Peak memory 242056 kb
Host smart-192c1fd9-beb9-44bf-b0d0-f67dada11c44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=977599928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.977599928
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.4195013878
Short name T963
Test name
Test status
Simulation time 241806325 ps
CPU time 7.47 seconds
Started Aug 11 06:46:57 PM PDT 24
Finished Aug 11 06:47:05 PM PDT 24
Peak memory 242096 kb
Host smart-32c31c4e-cdb1-4c38-b281-6c384a9269a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195013878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.4195013878
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.1797390113
Short name T1183
Test name
Test status
Simulation time 51920471643 ps
CPU time 176.38 seconds
Started Aug 11 06:47:04 PM PDT 24
Finished Aug 11 06:50:00 PM PDT 24
Peak memory 257248 kb
Host smart-4833ef77-ff26-4372-a086-db799f5ae06d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797390113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.1797390113
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.4209337257
Short name T18
Test name
Test status
Simulation time 46283247173 ps
CPU time 325.27 seconds
Started Aug 11 06:47:05 PM PDT 24
Finished Aug 11 06:52:30 PM PDT 24
Peak memory 265204 kb
Host smart-e445c8b8-1a6d-43ed-a144-1118450ccb67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209337257 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.4209337257
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.129733308
Short name T1
Test name
Test status
Simulation time 152334626 ps
CPU time 5.1 seconds
Started Aug 11 06:47:03 PM PDT 24
Finished Aug 11 06:47:08 PM PDT 24
Peak memory 241932 kb
Host smart-d394fcd8-2b00-46e4-bb33-21c2c4633d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129733308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.129733308
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.2329630371
Short name T36
Test name
Test status
Simulation time 125157375 ps
CPU time 3.46 seconds
Started Aug 11 06:50:21 PM PDT 24
Finished Aug 11 06:50:25 PM PDT 24
Peak memory 242360 kb
Host smart-4a0d86c9-a59e-40cf-9863-23cd93211f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329630371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2329630371
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.1412883142
Short name T688
Test name
Test status
Simulation time 895859242 ps
CPU time 6.82 seconds
Started Aug 11 06:50:19 PM PDT 24
Finished Aug 11 06:50:26 PM PDT 24
Peak memory 241828 kb
Host smart-4865785a-0968-47e5-a007-6c24e4519a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412883142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.1412883142
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.1492874486
Short name T1054
Test name
Test status
Simulation time 148666738 ps
CPU time 5.21 seconds
Started Aug 11 06:50:19 PM PDT 24
Finished Aug 11 06:50:24 PM PDT 24
Peak memory 242456 kb
Host smart-b111d949-1b14-47df-b9ed-8b17a5038c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492874486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.1492874486
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.2312824008
Short name T738
Test name
Test status
Simulation time 261011301 ps
CPU time 11.43 seconds
Started Aug 11 06:50:16 PM PDT 24
Finished Aug 11 06:50:27 PM PDT 24
Peak memory 242028 kb
Host smart-5d62ecfa-ac19-444a-b932-483167540f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312824008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.2312824008
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.267835178
Short name T755
Test name
Test status
Simulation time 2778743954 ps
CPU time 7.24 seconds
Started Aug 11 06:50:16 PM PDT 24
Finished Aug 11 06:50:24 PM PDT 24
Peak memory 242484 kb
Host smart-65650337-a923-46ab-992d-994fe1bd6aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267835178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.267835178
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.2199702963
Short name T720
Test name
Test status
Simulation time 238675026 ps
CPU time 4.02 seconds
Started Aug 11 06:50:19 PM PDT 24
Finished Aug 11 06:50:23 PM PDT 24
Peak memory 242024 kb
Host smart-404c4318-e65f-4efe-8445-78cab99c2440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199702963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.2199702963
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.2613123352
Short name T986
Test name
Test status
Simulation time 324532133 ps
CPU time 4.85 seconds
Started Aug 11 06:50:18 PM PDT 24
Finished Aug 11 06:50:23 PM PDT 24
Peak memory 242224 kb
Host smart-4ae89a26-e063-45bc-b097-55e9ecdd5997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613123352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2613123352
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.3517144943
Short name T822
Test name
Test status
Simulation time 2499076234 ps
CPU time 9.1 seconds
Started Aug 11 06:50:18 PM PDT 24
Finished Aug 11 06:50:27 PM PDT 24
Peak memory 242088 kb
Host smart-1b8bc493-a193-453a-87b6-4911eaa4fe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517144943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.3517144943
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.2229863163
Short name T997
Test name
Test status
Simulation time 333395561 ps
CPU time 5.17 seconds
Started Aug 11 06:50:19 PM PDT 24
Finished Aug 11 06:50:24 PM PDT 24
Peak memory 241856 kb
Host smart-887ae402-39f2-41c2-90d8-9d10f257fa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229863163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.2229863163
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.529430027
Short name T556
Test name
Test status
Simulation time 258622373 ps
CPU time 3.7 seconds
Started Aug 11 06:50:16 PM PDT 24
Finished Aug 11 06:50:20 PM PDT 24
Peak memory 241952 kb
Host smart-b798772b-4c65-4bf4-aed9-4a8f6e9dff11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529430027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.529430027
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.2173838595
Short name T674
Test name
Test status
Simulation time 191394657 ps
CPU time 8.06 seconds
Started Aug 11 06:50:18 PM PDT 24
Finished Aug 11 06:50:26 PM PDT 24
Peak memory 242368 kb
Host smart-5d68a3c2-89ea-4276-921d-6e506cef5082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173838595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.2173838595
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.4182314824
Short name T442
Test name
Test status
Simulation time 271128513 ps
CPU time 3.53 seconds
Started Aug 11 06:50:17 PM PDT 24
Finished Aug 11 06:50:21 PM PDT 24
Peak memory 241956 kb
Host smart-d865e07f-6db8-4c33-bece-7096e2db8038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182314824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.4182314824
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.328215173
Short name T263
Test name
Test status
Simulation time 411192644 ps
CPU time 3.81 seconds
Started Aug 11 06:50:20 PM PDT 24
Finished Aug 11 06:50:24 PM PDT 24
Peak memory 242308 kb
Host smart-56b45cd6-b5e3-4e33-9f56-787fc07d51de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328215173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.328215173
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.2629085678
Short name T1039
Test name
Test status
Simulation time 1547953011 ps
CPU time 5.85 seconds
Started Aug 11 06:50:18 PM PDT 24
Finished Aug 11 06:50:24 PM PDT 24
Peak memory 242044 kb
Host smart-ebd3b806-c239-444d-bfe9-018a2ecc77c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629085678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.2629085678
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.3240203637
Short name T844
Test name
Test status
Simulation time 4925172828 ps
CPU time 22.76 seconds
Started Aug 11 06:50:24 PM PDT 24
Finished Aug 11 06:50:47 PM PDT 24
Peak memory 242304 kb
Host smart-455a7813-7cea-4a24-9c24-3c567622062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240203637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.3240203637
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.1105518500
Short name T87
Test name
Test status
Simulation time 104590613 ps
CPU time 3.64 seconds
Started Aug 11 06:50:24 PM PDT 24
Finished Aug 11 06:50:28 PM PDT 24
Peak memory 242304 kb
Host smart-4c6dd7c4-8fdf-4a2e-be1f-92fa357a54d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105518500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.1105518500
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.4174138275
Short name T1187
Test name
Test status
Simulation time 892938439 ps
CPU time 15.94 seconds
Started Aug 11 06:50:30 PM PDT 24
Finished Aug 11 06:50:46 PM PDT 24
Peak memory 242228 kb
Host smart-e82c3cc4-f81c-4a57-9857-cec352eb077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174138275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.4174138275
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.2918875701
Short name T879
Test name
Test status
Simulation time 170686658 ps
CPU time 2.3 seconds
Started Aug 11 06:47:06 PM PDT 24
Finished Aug 11 06:47:08 PM PDT 24
Peak memory 240528 kb
Host smart-c6719e45-3426-4033-b0f8-8c8826f12fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918875701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.2918875701
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.945048679
Short name T555
Test name
Test status
Simulation time 1240145847 ps
CPU time 29.51 seconds
Started Aug 11 06:47:03 PM PDT 24
Finished Aug 11 06:47:33 PM PDT 24
Peak memory 243188 kb
Host smart-b2d0be3e-e223-48e0-a79c-0932e032eb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945048679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.945048679
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.2240909985
Short name T179
Test name
Test status
Simulation time 286392072 ps
CPU time 4.79 seconds
Started Aug 11 06:47:05 PM PDT 24
Finished Aug 11 06:47:10 PM PDT 24
Peak memory 242332 kb
Host smart-db7141b4-06d7-42f8-a95d-8dedebd6f73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240909985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.2240909985
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.4143021319
Short name T1128
Test name
Test status
Simulation time 432211195 ps
CPU time 3.18 seconds
Started Aug 11 06:47:05 PM PDT 24
Finished Aug 11 06:47:08 PM PDT 24
Peak memory 242308 kb
Host smart-1156f4bb-5830-4b25-add6-c995f75ef89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143021319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.4143021319
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.2585071307
Short name T1018
Test name
Test status
Simulation time 643023001 ps
CPU time 11.66 seconds
Started Aug 11 06:47:03 PM PDT 24
Finished Aug 11 06:47:15 PM PDT 24
Peak memory 242060 kb
Host smart-e80e6f0b-c283-455f-830d-b3313285de6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585071307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.2585071307
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.3758418011
Short name T1015
Test name
Test status
Simulation time 4409648262 ps
CPU time 14.62 seconds
Started Aug 11 06:47:03 PM PDT 24
Finished Aug 11 06:47:17 PM PDT 24
Peak memory 242364 kb
Host smart-9c38d8db-cb4a-4c88-885b-db996f9f7038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758418011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.3758418011
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.2643511180
Short name T410
Test name
Test status
Simulation time 454915500 ps
CPU time 4.01 seconds
Started Aug 11 06:47:05 PM PDT 24
Finished Aug 11 06:47:09 PM PDT 24
Peak memory 241992 kb
Host smart-0a7cf17c-9bdc-4f48-9fba-9d03e6b48feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643511180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.2643511180
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.3203922278
Short name T1073
Test name
Test status
Simulation time 652433345 ps
CPU time 18.5 seconds
Started Aug 11 06:47:08 PM PDT 24
Finished Aug 11 06:47:27 PM PDT 24
Peak memory 242088 kb
Host smart-43052d5f-74d0-43eb-8b8b-e91a7b0ece47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203922278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.3203922278
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.2597820095
Short name T1030
Test name
Test status
Simulation time 120228657 ps
CPU time 3.93 seconds
Started Aug 11 06:47:08 PM PDT 24
Finished Aug 11 06:47:12 PM PDT 24
Peak memory 242108 kb
Host smart-afce655e-7c8c-4e84-9c86-ef5394243cf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597820095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2597820095
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.2449508586
Short name T665
Test name
Test status
Simulation time 213670757 ps
CPU time 6.01 seconds
Started Aug 11 06:47:03 PM PDT 24
Finished Aug 11 06:47:09 PM PDT 24
Peak memory 241968 kb
Host smart-370adbc1-19ba-4cb5-9408-98b9f07dffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449508586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2449508586
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.2004824610
Short name T709
Test name
Test status
Simulation time 9566586975 ps
CPU time 59.82 seconds
Started Aug 11 06:47:08 PM PDT 24
Finished Aug 11 06:48:08 PM PDT 24
Peak memory 256916 kb
Host smart-d2108f9d-bb3f-432f-99e6-0721260dc921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004824610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.2004824610
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.605110061
Short name T608
Test name
Test status
Simulation time 123765029964 ps
CPU time 874.26 seconds
Started Aug 11 06:47:09 PM PDT 24
Finished Aug 11 07:01:43 PM PDT 24
Peak memory 295076 kb
Host smart-ab2696b8-9f75-41b6-ac80-2cdc8c7d5007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605110061 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.605110061
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.685284922
Short name T939
Test name
Test status
Simulation time 7056804196 ps
CPU time 20.8 seconds
Started Aug 11 06:47:09 PM PDT 24
Finished Aug 11 06:47:30 PM PDT 24
Peak memory 242872 kb
Host smart-88da27f2-2cfd-47f9-9460-54cbf9de1344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685284922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.685284922
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.4098191582
Short name T907
Test name
Test status
Simulation time 204828098 ps
CPU time 3.26 seconds
Started Aug 11 06:50:25 PM PDT 24
Finished Aug 11 06:50:28 PM PDT 24
Peak memory 242112 kb
Host smart-3c3684ba-d808-426f-96e7-53f0f7fc3dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098191582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.4098191582
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.399105893
Short name T1097
Test name
Test status
Simulation time 221469071 ps
CPU time 4.81 seconds
Started Aug 11 06:50:23 PM PDT 24
Finished Aug 11 06:50:28 PM PDT 24
Peak memory 242004 kb
Host smart-605cb242-449d-47ec-adff-7f61fa961bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399105893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.399105893
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.847838298
Short name T176
Test name
Test status
Simulation time 3229553988 ps
CPU time 10.52 seconds
Started Aug 11 06:50:30 PM PDT 24
Finished Aug 11 06:50:41 PM PDT 24
Peak memory 242296 kb
Host smart-0566c733-1c0d-43fc-8df5-e931b58ed7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847838298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.847838298
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.3797263668
Short name T713
Test name
Test status
Simulation time 140957858 ps
CPU time 4.22 seconds
Started Aug 11 06:50:24 PM PDT 24
Finished Aug 11 06:50:29 PM PDT 24
Peak memory 242008 kb
Host smart-627fc942-837d-404d-ac95-0ac656afefe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797263668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.3797263668
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.2676933929
Short name T716
Test name
Test status
Simulation time 694476748 ps
CPU time 5.62 seconds
Started Aug 11 06:50:27 PM PDT 24
Finished Aug 11 06:50:32 PM PDT 24
Peak memory 242032 kb
Host smart-fd899e03-c605-4628-9dba-5a5490866d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676933929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.2676933929
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.2487472155
Short name T896
Test name
Test status
Simulation time 136372407 ps
CPU time 3.19 seconds
Started Aug 11 06:50:24 PM PDT 24
Finished Aug 11 06:50:27 PM PDT 24
Peak memory 242000 kb
Host smart-dc173a3d-218c-49a7-8a0a-e30dd9765587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487472155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.2487472155
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.3535181559
Short name T392
Test name
Test status
Simulation time 1278342723 ps
CPU time 15.48 seconds
Started Aug 11 06:50:24 PM PDT 24
Finished Aug 11 06:50:40 PM PDT 24
Peak memory 242268 kb
Host smart-ec48a42c-7f6b-4861-92bc-14ba31c58778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535181559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.3535181559
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.1709745003
Short name T796
Test name
Test status
Simulation time 221122688 ps
CPU time 3.45 seconds
Started Aug 11 06:50:23 PM PDT 24
Finished Aug 11 06:50:26 PM PDT 24
Peak memory 242192 kb
Host smart-043e970c-efd5-4935-b645-f3391529bd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709745003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.1709745003
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.3145270583
Short name T273
Test name
Test status
Simulation time 246456554 ps
CPU time 7.05 seconds
Started Aug 11 06:50:25 PM PDT 24
Finished Aug 11 06:50:32 PM PDT 24
Peak memory 242024 kb
Host smart-23fef23e-a0cf-4b31-a721-d0f859320d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145270583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.3145270583
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.4123081919
Short name T672
Test name
Test status
Simulation time 264865255 ps
CPU time 7.07 seconds
Started Aug 11 06:50:30 PM PDT 24
Finished Aug 11 06:50:37 PM PDT 24
Peak memory 241784 kb
Host smart-68479772-6475-44d8-8def-19feab8f6213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123081919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.4123081919
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.594213892
Short name T1149
Test name
Test status
Simulation time 355383245 ps
CPU time 2.95 seconds
Started Aug 11 06:50:22 PM PDT 24
Finished Aug 11 06:50:25 PM PDT 24
Peak memory 242136 kb
Host smart-12722674-e29e-45ab-b4fb-fbd8f7b02972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594213892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.594213892
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.87540932
Short name T629
Test name
Test status
Simulation time 325750136 ps
CPU time 9.93 seconds
Started Aug 11 06:50:22 PM PDT 24
Finished Aug 11 06:50:32 PM PDT 24
Peak memory 241828 kb
Host smart-1f33a09b-94ad-4cef-b353-6e8cd8d5d85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87540932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.87540932
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.299506029
Short name T1077
Test name
Test status
Simulation time 164941585 ps
CPU time 3.08 seconds
Started Aug 11 06:50:23 PM PDT 24
Finished Aug 11 06:50:26 PM PDT 24
Peak memory 242224 kb
Host smart-1f055bed-c11c-4404-b292-6c180e1dbead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299506029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.299506029
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.743586278
Short name T792
Test name
Test status
Simulation time 1685246673 ps
CPU time 18.61 seconds
Started Aug 11 06:50:26 PM PDT 24
Finished Aug 11 06:50:45 PM PDT 24
Peak memory 241860 kb
Host smart-079cd98e-9730-402c-aed3-801bfcfc0204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743586278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.743586278
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.2149790013
Short name T1059
Test name
Test status
Simulation time 236497174 ps
CPU time 5.09 seconds
Started Aug 11 06:50:23 PM PDT 24
Finished Aug 11 06:50:28 PM PDT 24
Peak memory 242408 kb
Host smart-23a344a8-dea9-4612-b9de-d713ec180779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149790013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.2149790013
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.2391586524
Short name T439
Test name
Test status
Simulation time 431158779 ps
CPU time 11.71 seconds
Started Aug 11 06:50:21 PM PDT 24
Finished Aug 11 06:50:33 PM PDT 24
Peak memory 241916 kb
Host smart-699947b8-c9ee-4d7b-8a2b-1b4b5c79c3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391586524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.2391586524
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.1741558873
Short name T599
Test name
Test status
Simulation time 109015591 ps
CPU time 3.76 seconds
Started Aug 11 06:50:23 PM PDT 24
Finished Aug 11 06:50:27 PM PDT 24
Peak memory 242212 kb
Host smart-d060e0ca-d221-4af6-b6d3-2de5346fece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741558873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.1741558873
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.2656998977
Short name T271
Test name
Test status
Simulation time 256678801 ps
CPU time 6.62 seconds
Started Aug 11 06:50:24 PM PDT 24
Finished Aug 11 06:50:31 PM PDT 24
Peak memory 241864 kb
Host smart-05815ab1-7ec2-47dc-b882-2d91635bf05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656998977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2656998977
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.1480766230
Short name T853
Test name
Test status
Simulation time 64121690 ps
CPU time 1.8 seconds
Started Aug 11 06:47:14 PM PDT 24
Finished Aug 11 06:47:16 PM PDT 24
Peak memory 240520 kb
Host smart-9fb688f6-5d32-41d8-9cf2-67e62aeddd59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480766230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1480766230
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.2572432984
Short name T1001
Test name
Test status
Simulation time 496444405 ps
CPU time 11.28 seconds
Started Aug 11 06:47:09 PM PDT 24
Finished Aug 11 06:47:21 PM PDT 24
Peak memory 242412 kb
Host smart-f7cf67ef-557c-476d-b1ec-c563b24f3b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572432984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.2572432984
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.452861187
Short name T427
Test name
Test status
Simulation time 1670175436 ps
CPU time 22.64 seconds
Started Aug 11 06:47:09 PM PDT 24
Finished Aug 11 06:47:32 PM PDT 24
Peak memory 242004 kb
Host smart-f03bfc32-551c-4152-b1a9-86318dd63627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452861187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.452861187
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.2032839111
Short name T542
Test name
Test status
Simulation time 1229038197 ps
CPU time 11.33 seconds
Started Aug 11 06:47:10 PM PDT 24
Finished Aug 11 06:47:22 PM PDT 24
Peak memory 242256 kb
Host smart-258dcba7-a1d5-46fb-86c8-1ea7c3f8dfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032839111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.2032839111
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.2689796752
Short name T1056
Test name
Test status
Simulation time 129304683 ps
CPU time 4.62 seconds
Started Aug 11 06:47:09 PM PDT 24
Finished Aug 11 06:47:14 PM PDT 24
Peak memory 241984 kb
Host smart-bd43909a-92d5-419b-ba85-93adabfab949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689796752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.2689796752
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.2165952766
Short name T871
Test name
Test status
Simulation time 202804012 ps
CPU time 8.2 seconds
Started Aug 11 06:47:09 PM PDT 24
Finished Aug 11 06:47:17 PM PDT 24
Peak memory 242412 kb
Host smart-ab243d1a-5063-439d-ac75-4c253108a7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165952766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.2165952766
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.2440785536
Short name T1095
Test name
Test status
Simulation time 763130787 ps
CPU time 15 seconds
Started Aug 11 06:47:07 PM PDT 24
Finished Aug 11 06:47:22 PM PDT 24
Peak memory 242392 kb
Host smart-5fef4608-129d-47ab-a63f-a07feb60d80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440785536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.2440785536
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.1964049344
Short name T146
Test name
Test status
Simulation time 549075024 ps
CPU time 3.87 seconds
Started Aug 11 06:47:10 PM PDT 24
Finished Aug 11 06:47:14 PM PDT 24
Peak memory 241956 kb
Host smart-4777d9c0-d4ae-456e-a711-76a79eec9e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964049344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1964049344
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.2356145168
Short name T401
Test name
Test status
Simulation time 583424450 ps
CPU time 17.35 seconds
Started Aug 11 06:47:09 PM PDT 24
Finished Aug 11 06:47:27 PM PDT 24
Peak memory 242100 kb
Host smart-691abcc9-70ed-4f11-87ee-bab10eee4d3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2356145168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.2356145168
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.41715122
Short name T380
Test name
Test status
Simulation time 171702468 ps
CPU time 5.6 seconds
Started Aug 11 06:47:09 PM PDT 24
Finished Aug 11 06:47:15 PM PDT 24
Peak memory 242224 kb
Host smart-68a81b8d-e3cf-4014-81aa-90666dba43d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41715122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.41715122
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.554776810
Short name T628
Test name
Test status
Simulation time 348059067 ps
CPU time 7.08 seconds
Started Aug 11 06:47:09 PM PDT 24
Finished Aug 11 06:47:16 PM PDT 24
Peak memory 241960 kb
Host smart-d4bcdd5e-2631-4176-a496-a8d59cec0562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554776810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.554776810
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.3402255504
Short name T558
Test name
Test status
Simulation time 411388252632 ps
CPU time 922.52 seconds
Started Aug 11 06:47:16 PM PDT 24
Finished Aug 11 07:02:39 PM PDT 24
Peak memory 321924 kb
Host smart-71752a3b-da64-4b56-9c4e-4dc9658b4542
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402255504 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.3402255504
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.15518586
Short name T937
Test name
Test status
Simulation time 558750050 ps
CPU time 9.43 seconds
Started Aug 11 06:47:09 PM PDT 24
Finished Aug 11 06:47:18 PM PDT 24
Peak memory 242204 kb
Host smart-fd24116a-232b-4eac-810f-e2f7730ad43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15518586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.15518586
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.85963971
Short name T114
Test name
Test status
Simulation time 203610677 ps
CPU time 2.9 seconds
Started Aug 11 06:50:25 PM PDT 24
Finished Aug 11 06:50:28 PM PDT 24
Peak memory 242156 kb
Host smart-0492652b-edbc-49ba-aca3-45014199e2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85963971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.85963971
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.3456613452
Short name T249
Test name
Test status
Simulation time 4651442156 ps
CPU time 30.05 seconds
Started Aug 11 06:50:22 PM PDT 24
Finished Aug 11 06:50:53 PM PDT 24
Peak memory 242416 kb
Host smart-77808e64-9eab-4efc-bcb2-d286bfd0b273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456613452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3456613452
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.2569200579
Short name T710
Test name
Test status
Simulation time 1265898058 ps
CPU time 16.51 seconds
Started Aug 11 06:50:23 PM PDT 24
Finished Aug 11 06:50:40 PM PDT 24
Peak memory 241972 kb
Host smart-d9f1c15e-276b-48f1-82b5-ea6d39b07cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569200579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.2569200579
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.1366049380
Short name T52
Test name
Test status
Simulation time 261967619 ps
CPU time 4.15 seconds
Started Aug 11 06:50:24 PM PDT 24
Finished Aug 11 06:50:28 PM PDT 24
Peak memory 242172 kb
Host smart-91bb51a1-74af-401a-a74c-ba9d37837cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366049380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.1366049380
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.2313112713
Short name T1047
Test name
Test status
Simulation time 745037689 ps
CPU time 12.87 seconds
Started Aug 11 06:50:26 PM PDT 24
Finished Aug 11 06:50:39 PM PDT 24
Peak memory 241852 kb
Host smart-59fecf4f-3d56-407d-a11f-feb8b9cb44c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313112713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.2313112713
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.934058877
Short name T610
Test name
Test status
Simulation time 290132247 ps
CPU time 4.31 seconds
Started Aug 11 06:50:30 PM PDT 24
Finished Aug 11 06:50:35 PM PDT 24
Peak memory 242392 kb
Host smart-0468c6fa-67e9-4caa-920b-bc491e4bb78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934058877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.934058877
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.3377114389
Short name T776
Test name
Test status
Simulation time 8102981868 ps
CPU time 17.86 seconds
Started Aug 11 06:50:23 PM PDT 24
Finished Aug 11 06:50:41 PM PDT 24
Peak memory 242096 kb
Host smart-3b768148-e804-4803-a524-7151aa0df3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377114389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.3377114389
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.949749078
Short name T1061
Test name
Test status
Simulation time 2217284622 ps
CPU time 5.28 seconds
Started Aug 11 06:50:31 PM PDT 24
Finished Aug 11 06:50:36 PM PDT 24
Peak memory 242320 kb
Host smart-ceebed73-8025-4140-b1b4-08c069d76127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949749078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.949749078
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.2275937151
Short name T1135
Test name
Test status
Simulation time 759368403 ps
CPU time 13.21 seconds
Started Aug 11 06:50:31 PM PDT 24
Finished Aug 11 06:50:44 PM PDT 24
Peak memory 242364 kb
Host smart-4843baf9-d7c4-4ebf-b845-5c06cb9a1d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275937151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2275937151
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.2811750218
Short name T502
Test name
Test status
Simulation time 646770017 ps
CPU time 4.49 seconds
Started Aug 11 06:50:35 PM PDT 24
Finished Aug 11 06:50:40 PM PDT 24
Peak memory 242296 kb
Host smart-664e30da-b821-4116-8360-13a4a81a1ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811750218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.2811750218
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.1238495245
Short name T1121
Test name
Test status
Simulation time 139996949 ps
CPU time 3.74 seconds
Started Aug 11 06:50:31 PM PDT 24
Finished Aug 11 06:50:35 PM PDT 24
Peak memory 241940 kb
Host smart-694589fe-3557-4acd-bdfa-095873fab7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238495245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.1238495245
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.881347138
Short name T990
Test name
Test status
Simulation time 540578119 ps
CPU time 5.86 seconds
Started Aug 11 06:50:40 PM PDT 24
Finished Aug 11 06:50:46 PM PDT 24
Peak memory 241968 kb
Host smart-4c15bd36-b137-48da-af25-aec30ba560fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881347138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.881347138
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.1633415419
Short name T182
Test name
Test status
Simulation time 934556851 ps
CPU time 6.88 seconds
Started Aug 11 06:50:30 PM PDT 24
Finished Aug 11 06:50:37 PM PDT 24
Peak memory 241820 kb
Host smart-fdb9f641-19cc-4074-b44a-4fac89f1a89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633415419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1633415419
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.655598411
Short name T668
Test name
Test status
Simulation time 1852615909 ps
CPU time 5.76 seconds
Started Aug 11 06:50:40 PM PDT 24
Finished Aug 11 06:50:45 PM PDT 24
Peak memory 242148 kb
Host smart-a48b75a0-ddfe-4c3e-84dd-d03c1bd7372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655598411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.655598411
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.1835977808
Short name T949
Test name
Test status
Simulation time 1447196965 ps
CPU time 16.16 seconds
Started Aug 11 06:50:31 PM PDT 24
Finished Aug 11 06:50:47 PM PDT 24
Peak memory 241888 kb
Host smart-abee0f9e-78aa-44a8-b5e3-454063cc9c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835977808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.1835977808
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2966108404
Short name T722
Test name
Test status
Simulation time 281322375 ps
CPU time 3.21 seconds
Started Aug 11 06:50:28 PM PDT 24
Finished Aug 11 06:50:32 PM PDT 24
Peak memory 242112 kb
Host smart-85f5a24c-1cc3-40f0-822b-6aa1c009bfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966108404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2966108404
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.772281412
Short name T551
Test name
Test status
Simulation time 467914988 ps
CPU time 8.58 seconds
Started Aug 11 06:50:28 PM PDT 24
Finished Aug 11 06:50:37 PM PDT 24
Peak memory 242312 kb
Host smart-1da5622c-f869-4fea-b2e5-684bcfea91e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772281412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.772281412
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.3246538458
Short name T825
Test name
Test status
Simulation time 741007099 ps
CPU time 2.01 seconds
Started Aug 11 06:47:19 PM PDT 24
Finished Aug 11 06:47:21 PM PDT 24
Peak memory 240724 kb
Host smart-a7f4e695-2d56-4809-bf31-10519fc2ccf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246538458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.3246538458
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.4065525922
Short name T158
Test name
Test status
Simulation time 326272405 ps
CPU time 9.5 seconds
Started Aug 11 06:47:13 PM PDT 24
Finished Aug 11 06:47:22 PM PDT 24
Peak memory 241808 kb
Host smart-f1a585fc-b836-4322-bda5-bcea38ebdf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065525922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.4065525922
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.1080081011
Short name T869
Test name
Test status
Simulation time 2286694825 ps
CPU time 5.22 seconds
Started Aug 11 06:47:12 PM PDT 24
Finished Aug 11 06:47:17 PM PDT 24
Peak memory 242316 kb
Host smart-3f638d95-93a9-4a22-8519-07260185f0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080081011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.1080081011
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.741564120
Short name T71
Test name
Test status
Simulation time 211081234 ps
CPU time 4.17 seconds
Started Aug 11 06:47:13 PM PDT 24
Finished Aug 11 06:47:18 PM PDT 24
Peak memory 242120 kb
Host smart-678073c4-8764-47af-ad44-857f01a0b6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741564120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.741564120
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.2677309747
Short name T207
Test name
Test status
Simulation time 4543760744 ps
CPU time 41.47 seconds
Started Aug 11 06:47:13 PM PDT 24
Finished Aug 11 06:47:54 PM PDT 24
Peak memory 248668 kb
Host smart-4fe45feb-2790-4dd6-ae06-2f1a91a3c93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677309747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.2677309747
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.2538968225
Short name T803
Test name
Test status
Simulation time 1957664059 ps
CPU time 27.99 seconds
Started Aug 11 06:47:14 PM PDT 24
Finished Aug 11 06:47:42 PM PDT 24
Peak memory 248604 kb
Host smart-0085ea53-2efd-439b-bc7c-f72d779da202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538968225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.2538968225
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.3224845802
Short name T623
Test name
Test status
Simulation time 652665606 ps
CPU time 9.63 seconds
Started Aug 11 06:47:16 PM PDT 24
Finished Aug 11 06:47:25 PM PDT 24
Peak memory 242284 kb
Host smart-584fcf84-ae4a-4db4-974f-792af4ee3edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224845802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.3224845802
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.2977819645
Short name T960
Test name
Test status
Simulation time 640024481 ps
CPU time 21.03 seconds
Started Aug 11 06:47:14 PM PDT 24
Finished Aug 11 06:47:35 PM PDT 24
Peak memory 242000 kb
Host smart-bbd08d02-aff9-49e8-89dd-7e541cd577e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977819645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.2977819645
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.143043574
Short name T377
Test name
Test status
Simulation time 989215227 ps
CPU time 8.56 seconds
Started Aug 11 06:47:15 PM PDT 24
Finished Aug 11 06:47:23 PM PDT 24
Peak memory 242316 kb
Host smart-cbbe1e7d-fa25-4c7f-a382-3e0f728543cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=143043574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.143043574
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.217798104
Short name T578
Test name
Test status
Simulation time 702671659 ps
CPU time 5.11 seconds
Started Aug 11 06:47:16 PM PDT 24
Finished Aug 11 06:47:21 PM PDT 24
Peak memory 242020 kb
Host smart-4bf4bc6b-b02a-4797-98f6-9b8dc9740e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217798104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.217798104
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.1623045039
Short name T356
Test name
Test status
Simulation time 64345629329 ps
CPU time 1023.46 seconds
Started Aug 11 06:47:19 PM PDT 24
Finished Aug 11 07:04:23 PM PDT 24
Peak memory 378796 kb
Host smart-790c77ba-71bc-400a-8d5b-ba31edb45252
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623045039 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.1623045039
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.1363203226
Short name T435
Test name
Test status
Simulation time 123620345 ps
CPU time 3.91 seconds
Started Aug 11 06:50:30 PM PDT 24
Finished Aug 11 06:50:34 PM PDT 24
Peak memory 242044 kb
Host smart-8568f5bc-1028-4403-a526-1edc27e3a8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363203226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.1363203226
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.171345526
Short name T494
Test name
Test status
Simulation time 1650910820 ps
CPU time 5.35 seconds
Started Aug 11 06:50:30 PM PDT 24
Finished Aug 11 06:50:36 PM PDT 24
Peak memory 242312 kb
Host smart-a99161e8-22f1-4d41-8632-df044969cf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171345526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.171345526
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.3199384799
Short name T1148
Test name
Test status
Simulation time 242438472 ps
CPU time 3.48 seconds
Started Aug 11 06:50:30 PM PDT 24
Finished Aug 11 06:50:33 PM PDT 24
Peak memory 242212 kb
Host smart-dda1899a-fc78-43e4-9e81-f269d1497a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199384799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3199384799
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.1614315395
Short name T251
Test name
Test status
Simulation time 566693838 ps
CPU time 6.92 seconds
Started Aug 11 06:50:40 PM PDT 24
Finished Aug 11 06:50:47 PM PDT 24
Peak memory 241776 kb
Host smart-d3a53f3d-3b64-4271-924f-189c1c2f02e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614315395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.1614315395
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.2832205645
Short name T163
Test name
Test status
Simulation time 130797815 ps
CPU time 3.5 seconds
Started Aug 11 06:50:30 PM PDT 24
Finished Aug 11 06:50:34 PM PDT 24
Peak memory 242396 kb
Host smart-469d7b65-d831-4d8c-9c9b-969682b0a2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832205645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.2832205645
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.4155347785
Short name T687
Test name
Test status
Simulation time 335907573 ps
CPU time 3.8 seconds
Started Aug 11 06:50:40 PM PDT 24
Finished Aug 11 06:50:44 PM PDT 24
Peak memory 242288 kb
Host smart-221f49ec-5f31-41b4-9eb9-3c068bf5c90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155347785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.4155347785
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.3447843133
Short name T192
Test name
Test status
Simulation time 1429741078 ps
CPU time 3.56 seconds
Started Aug 11 06:50:35 PM PDT 24
Finished Aug 11 06:50:39 PM PDT 24
Peak memory 242044 kb
Host smart-966bb913-23be-4917-8dc7-3f481dc98ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447843133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.3447843133
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.2102322083
Short name T857
Test name
Test status
Simulation time 661719179 ps
CPU time 8.62 seconds
Started Aug 11 06:50:40 PM PDT 24
Finished Aug 11 06:50:49 PM PDT 24
Peak memory 242224 kb
Host smart-961da81c-a9bd-4526-ad9e-d33c70d8f4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102322083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.2102322083
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.925536557
Short name T190
Test name
Test status
Simulation time 250653982 ps
CPU time 3.73 seconds
Started Aug 11 06:50:31 PM PDT 24
Finished Aug 11 06:50:35 PM PDT 24
Peak memory 242260 kb
Host smart-ae7b5213-f871-4bc4-a89b-cb610b88b4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925536557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.925536557
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.1181186676
Short name T466
Test name
Test status
Simulation time 1350928687 ps
CPU time 28.9 seconds
Started Aug 11 06:50:31 PM PDT 24
Finished Aug 11 06:51:00 PM PDT 24
Peak memory 242308 kb
Host smart-f2f354a1-96c1-4aeb-8c7a-ca90746b6f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181186676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.1181186676
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.2036695630
Short name T806
Test name
Test status
Simulation time 326988964 ps
CPU time 4.09 seconds
Started Aug 11 06:50:28 PM PDT 24
Finished Aug 11 06:50:32 PM PDT 24
Peak memory 242288 kb
Host smart-d8dff4fb-32e7-44d0-b3d9-8e0aff940984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036695630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2036695630
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.463693118
Short name T482
Test name
Test status
Simulation time 1635203476 ps
CPU time 6.98 seconds
Started Aug 11 06:50:26 PM PDT 24
Finished Aug 11 06:50:33 PM PDT 24
Peak memory 241872 kb
Host smart-e8278de9-73df-4a84-a276-2c3a647dfcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463693118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.463693118
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.2028269573
Short name T479
Test name
Test status
Simulation time 1766041294 ps
CPU time 6.04 seconds
Started Aug 11 06:50:40 PM PDT 24
Finished Aug 11 06:50:46 PM PDT 24
Peak memory 242248 kb
Host smart-bae0f41e-a39d-4cef-bfc9-7b342b98b1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028269573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.2028269573
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.1152451413
Short name T126
Test name
Test status
Simulation time 1230671203 ps
CPU time 16.37 seconds
Started Aug 11 06:50:29 PM PDT 24
Finished Aug 11 06:50:46 PM PDT 24
Peak memory 242024 kb
Host smart-1f837fa6-b787-4d3e-90b0-dfa6ce81e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152451413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.1152451413
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.1503792799
Short name T714
Test name
Test status
Simulation time 558423823 ps
CPU time 3.79 seconds
Started Aug 11 06:50:40 PM PDT 24
Finished Aug 11 06:50:44 PM PDT 24
Peak memory 242388 kb
Host smart-39da646f-e40d-4a17-a9df-c1bdb8e6b07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503792799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.1503792799
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.3558093223
Short name T393
Test name
Test status
Simulation time 522000010 ps
CPU time 6.84 seconds
Started Aug 11 06:50:32 PM PDT 24
Finished Aug 11 06:50:39 PM PDT 24
Peak memory 242196 kb
Host smart-03f3bb95-5715-435c-8320-38f5d1833daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558093223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.3558093223
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.867109464
Short name T42
Test name
Test status
Simulation time 290624939 ps
CPU time 4.57 seconds
Started Aug 11 06:50:30 PM PDT 24
Finished Aug 11 06:50:34 PM PDT 24
Peak memory 241856 kb
Host smart-c5358a19-9a77-4431-9956-548f93d39468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867109464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.867109464
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.2006664531
Short name T849
Test name
Test status
Simulation time 102898766 ps
CPU time 3.95 seconds
Started Aug 11 06:50:29 PM PDT 24
Finished Aug 11 06:50:33 PM PDT 24
Peak memory 242260 kb
Host smart-48dbe0cc-6c62-48fb-9b03-a85a81f02796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006664531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.2006664531
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.2495309134
Short name T415
Test name
Test status
Simulation time 65359288 ps
CPU time 1.79 seconds
Started Aug 11 06:47:23 PM PDT 24
Finished Aug 11 06:47:25 PM PDT 24
Peak memory 240544 kb
Host smart-7eb33143-4eb6-419f-9ec7-b42923ca51bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495309134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.2495309134
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.1786831597
Short name T117
Test name
Test status
Simulation time 818659754 ps
CPU time 17.39 seconds
Started Aug 11 06:47:23 PM PDT 24
Finished Aug 11 06:47:41 PM PDT 24
Peak memory 248560 kb
Host smart-9cedfbbb-585e-42d4-ba52-c5a8e31f8124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786831597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1786831597
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.2941645152
Short name T455
Test name
Test status
Simulation time 1505784433 ps
CPU time 20.11 seconds
Started Aug 11 06:47:19 PM PDT 24
Finished Aug 11 06:47:39 PM PDT 24
Peak memory 241980 kb
Host smart-b9ff184a-0937-493e-8a04-b91e5b06ff61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941645152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.2941645152
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.1096748234
Short name T591
Test name
Test status
Simulation time 3141520727 ps
CPU time 16.01 seconds
Started Aug 11 06:47:18 PM PDT 24
Finished Aug 11 06:47:34 PM PDT 24
Peak memory 242360 kb
Host smart-71644430-2058-4394-aa68-ebd33d6c7a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096748234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.1096748234
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.3596367332
Short name T965
Test name
Test status
Simulation time 1690161618 ps
CPU time 4.45 seconds
Started Aug 11 06:47:21 PM PDT 24
Finished Aug 11 06:47:26 PM PDT 24
Peak memory 242316 kb
Host smart-11f7c937-f107-419d-8ce4-3fd169a312e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596367332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.3596367332
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.3218337687
Short name T840
Test name
Test status
Simulation time 4600718059 ps
CPU time 20.2 seconds
Started Aug 11 06:47:22 PM PDT 24
Finished Aug 11 06:47:43 PM PDT 24
Peak memory 248752 kb
Host smart-b6d8f78b-f6ec-4b9d-b116-b6cad84cafeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218337687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.3218337687
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.768600050
Short name T775
Test name
Test status
Simulation time 7135517551 ps
CPU time 23.12 seconds
Started Aug 11 06:47:24 PM PDT 24
Finished Aug 11 06:47:48 PM PDT 24
Peak memory 242832 kb
Host smart-4ca9d617-a5b6-483f-aa0f-712aaa7c10d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768600050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.768600050
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.282776906
Short name T902
Test name
Test status
Simulation time 2938718208 ps
CPU time 7.71 seconds
Started Aug 11 06:47:22 PM PDT 24
Finished Aug 11 06:47:29 PM PDT 24
Peak memory 242020 kb
Host smart-92642ce8-2e17-4a05-b5ef-d19250a4708d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282776906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.282776906
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.2000615350
Short name T977
Test name
Test status
Simulation time 1034452085 ps
CPU time 16.44 seconds
Started Aug 11 06:47:20 PM PDT 24
Finished Aug 11 06:47:37 PM PDT 24
Peak memory 242104 kb
Host smart-2d569176-42eb-42c5-8423-52f58ef02d42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2000615350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.2000615350
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.2145884020
Short name T782
Test name
Test status
Simulation time 306887858 ps
CPU time 9.71 seconds
Started Aug 11 06:47:24 PM PDT 24
Finished Aug 11 06:47:34 PM PDT 24
Peak memory 248576 kb
Host smart-9d55634e-1708-4c53-8fcf-05264db4ad37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145884020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.2145884020
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.1007719888
Short name T562
Test name
Test status
Simulation time 2145993693 ps
CPU time 7.09 seconds
Started Aug 11 06:47:20 PM PDT 24
Finished Aug 11 06:47:27 PM PDT 24
Peak memory 241892 kb
Host smart-a958959d-c552-4a21-b963-99a9980ba3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007719888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.1007719888
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.2451470800
Short name T1042
Test name
Test status
Simulation time 4724597291 ps
CPU time 32.59 seconds
Started Aug 11 06:47:24 PM PDT 24
Finished Aug 11 06:47:57 PM PDT 24
Peak memory 244476 kb
Host smart-409a391d-6fc9-4e5b-b28e-eec717cf8575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451470800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.2451470800
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.86891942
Short name T534
Test name
Test status
Simulation time 674271109 ps
CPU time 9.4 seconds
Started Aug 11 06:47:24 PM PDT 24
Finished Aug 11 06:47:33 PM PDT 24
Peak memory 242088 kb
Host smart-599c7a43-94a0-4e94-82e2-905d933e1990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86891942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.86891942
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.3929076063
Short name T923
Test name
Test status
Simulation time 143405390 ps
CPU time 4.3 seconds
Started Aug 11 06:50:36 PM PDT 24
Finished Aug 11 06:50:41 PM PDT 24
Peak memory 242416 kb
Host smart-4ad05e29-e519-463e-abd2-789787cc9d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929076063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.3929076063
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.1621907485
Short name T574
Test name
Test status
Simulation time 237831289 ps
CPU time 5.96 seconds
Started Aug 11 06:50:36 PM PDT 24
Finished Aug 11 06:50:42 PM PDT 24
Peak memory 241944 kb
Host smart-2f920583-67d8-466b-970e-c493caba7903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621907485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.1621907485
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.2548334754
Short name T734
Test name
Test status
Simulation time 277805699 ps
CPU time 3.57 seconds
Started Aug 11 06:50:41 PM PDT 24
Finished Aug 11 06:50:44 PM PDT 24
Peak memory 242140 kb
Host smart-bca306c7-4ac5-47b9-891a-2c7530bf5c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548334754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.2548334754
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.2517025854
Short name T810
Test name
Test status
Simulation time 162956215 ps
CPU time 7.55 seconds
Started Aug 11 06:50:35 PM PDT 24
Finished Aug 11 06:50:43 PM PDT 24
Peak memory 242000 kb
Host smart-71edbcb5-7354-4703-937d-4e674fd2ca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517025854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.2517025854
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.1395293082
Short name T964
Test name
Test status
Simulation time 138003211 ps
CPU time 3.8 seconds
Started Aug 11 06:50:40 PM PDT 24
Finished Aug 11 06:50:44 PM PDT 24
Peak memory 242344 kb
Host smart-e380df35-560b-4a09-b130-889aa6c8698d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395293082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.1395293082
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.662366069
Short name T248
Test name
Test status
Simulation time 171739489 ps
CPU time 4.19 seconds
Started Aug 11 06:50:35 PM PDT 24
Finished Aug 11 06:50:40 PM PDT 24
Peak memory 247316 kb
Host smart-4d692a5b-c276-423e-b03c-8798e9b42941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662366069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.662366069
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.3883467363
Short name T166
Test name
Test status
Simulation time 158562031 ps
CPU time 4.26 seconds
Started Aug 11 06:50:36 PM PDT 24
Finished Aug 11 06:50:41 PM PDT 24
Peak memory 241988 kb
Host smart-fe576544-ab4e-4f56-8309-0f8046fda80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883467363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.3883467363
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.1011938915
Short name T802
Test name
Test status
Simulation time 8248960194 ps
CPU time 17.56 seconds
Started Aug 11 06:50:36 PM PDT 24
Finished Aug 11 06:50:54 PM PDT 24
Peak memory 242072 kb
Host smart-8e1ff70a-1b4d-4b22-b13a-7eeb97fd3b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011938915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.1011938915
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.3064917390
Short name T24
Test name
Test status
Simulation time 1891749963 ps
CPU time 5.58 seconds
Started Aug 11 06:50:36 PM PDT 24
Finished Aug 11 06:50:42 PM PDT 24
Peak memory 242048 kb
Host smart-e8867b1d-a1d3-44ba-9e44-70009c91d14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064917390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.3064917390
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.103677174
Short name T1072
Test name
Test status
Simulation time 449842612 ps
CPU time 3.96 seconds
Started Aug 11 06:50:40 PM PDT 24
Finished Aug 11 06:50:45 PM PDT 24
Peak memory 241892 kb
Host smart-c4345fbb-7373-42e8-bae3-b49f55a62ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103677174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.103677174
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.2882855749
Short name T33
Test name
Test status
Simulation time 246484529 ps
CPU time 4.36 seconds
Started Aug 11 06:50:37 PM PDT 24
Finished Aug 11 06:50:41 PM PDT 24
Peak memory 242136 kb
Host smart-c9eaad49-32e0-4596-aea6-e84d2a8c69a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882855749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2882855749
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.3630516081
Short name T749
Test name
Test status
Simulation time 421052923 ps
CPU time 8.76 seconds
Started Aug 11 06:50:36 PM PDT 24
Finished Aug 11 06:50:45 PM PDT 24
Peak memory 242040 kb
Host smart-1e75ca20-5fc1-48a9-b8d7-20178e62a6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630516081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3630516081
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.3561176476
Short name T462
Test name
Test status
Simulation time 220445525 ps
CPU time 4.57 seconds
Started Aug 11 06:50:35 PM PDT 24
Finished Aug 11 06:50:39 PM PDT 24
Peak memory 242008 kb
Host smart-4b21769b-e6b7-4948-9b0c-14dd4859fae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561176476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3561176476
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.4169928981
Short name T724
Test name
Test status
Simulation time 669684533 ps
CPU time 11.03 seconds
Started Aug 11 06:50:37 PM PDT 24
Finished Aug 11 06:50:48 PM PDT 24
Peak memory 242288 kb
Host smart-6a5c152e-09dc-4a84-9eae-584da3cc2b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169928981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.4169928981
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.3531249825
Short name T1035
Test name
Test status
Simulation time 134096302 ps
CPU time 5 seconds
Started Aug 11 06:50:34 PM PDT 24
Finished Aug 11 06:50:39 PM PDT 24
Peak memory 242260 kb
Host smart-acccf2a6-7ad2-437b-bbb7-792e9766d789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531249825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.3531249825
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.3046300761
Short name T1007
Test name
Test status
Simulation time 3891022520 ps
CPU time 20.11 seconds
Started Aug 11 06:50:34 PM PDT 24
Finished Aug 11 06:50:54 PM PDT 24
Peak memory 242088 kb
Host smart-d5093ce5-4bae-46e9-a051-dc4fdb30947b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046300761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.3046300761
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.2848179400
Short name T31
Test name
Test status
Simulation time 358475587 ps
CPU time 4.02 seconds
Started Aug 11 06:50:34 PM PDT 24
Finished Aug 11 06:50:38 PM PDT 24
Peak memory 242060 kb
Host smart-4f3cd304-738d-4271-9faf-cea6bd323fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848179400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.2848179400
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.448020158
Short name T566
Test name
Test status
Simulation time 347133354 ps
CPU time 7.66 seconds
Started Aug 11 06:50:39 PM PDT 24
Finished Aug 11 06:50:47 PM PDT 24
Peak memory 242260 kb
Host smart-c070d1ef-eff0-4f34-9ee7-48bd4d543841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448020158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.448020158
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.2141818708
Short name T761
Test name
Test status
Simulation time 262697216 ps
CPU time 4.73 seconds
Started Aug 11 06:50:40 PM PDT 24
Finished Aug 11 06:50:45 PM PDT 24
Peak memory 242168 kb
Host smart-149ac5c2-610d-4e3c-965e-5640485c0bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141818708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2141818708
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.1518483035
Short name T352
Test name
Test status
Simulation time 205842250 ps
CPU time 4.79 seconds
Started Aug 11 06:50:42 PM PDT 24
Finished Aug 11 06:50:47 PM PDT 24
Peak memory 242136 kb
Host smart-85db05a6-07a0-4563-a406-22edd5848ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518483035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1518483035
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.195681600
Short name T895
Test name
Test status
Simulation time 132957914 ps
CPU time 2.36 seconds
Started Aug 11 06:47:36 PM PDT 24
Finished Aug 11 06:47:38 PM PDT 24
Peak memory 240500 kb
Host smart-374ee836-ef5e-4a3d-8129-fe033d02488f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195681600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.195681600
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.2827699276
Short name T893
Test name
Test status
Simulation time 163618307 ps
CPU time 4.22 seconds
Started Aug 11 06:47:28 PM PDT 24
Finished Aug 11 06:47:32 PM PDT 24
Peak memory 248192 kb
Host smart-117363ea-2758-4b56-9be2-162e724557eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827699276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.2827699276
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.3395617038
Short name T362
Test name
Test status
Simulation time 14935428888 ps
CPU time 32.64 seconds
Started Aug 11 06:47:27 PM PDT 24
Finished Aug 11 06:48:00 PM PDT 24
Peak memory 245020 kb
Host smart-922f7182-38d3-4b9e-99ea-badd8e9752ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395617038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.3395617038
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.2865417774
Short name T1115
Test name
Test status
Simulation time 579060582 ps
CPU time 8.36 seconds
Started Aug 11 06:47:24 PM PDT 24
Finished Aug 11 06:47:32 PM PDT 24
Peak memory 242064 kb
Host smart-7951b076-26bb-4f25-8e23-bfa49221cd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865417774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.2865417774
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.1053233584
Short name T56
Test name
Test status
Simulation time 2485461529 ps
CPU time 6.98 seconds
Started Aug 11 06:47:24 PM PDT 24
Finished Aug 11 06:47:32 PM PDT 24
Peak memory 242068 kb
Host smart-2b7d172a-c67f-495d-96ac-580bf6c836f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053233584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.1053233584
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.2754934962
Short name T477
Test name
Test status
Simulation time 307266509 ps
CPU time 6.56 seconds
Started Aug 11 06:47:27 PM PDT 24
Finished Aug 11 06:47:34 PM PDT 24
Peak memory 243052 kb
Host smart-e23edb6e-8018-4d74-8a6d-d48fcb4d8d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754934962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.2754934962
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.2425887499
Short name T727
Test name
Test status
Simulation time 6012387856 ps
CPU time 32.16 seconds
Started Aug 11 06:47:28 PM PDT 24
Finished Aug 11 06:48:01 PM PDT 24
Peak memory 242136 kb
Host smart-1b1fe952-9821-4a74-b514-e6f14c40204d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425887499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2425887499
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.2411064441
Short name T1111
Test name
Test status
Simulation time 13833355128 ps
CPU time 27.38 seconds
Started Aug 11 06:47:27 PM PDT 24
Finished Aug 11 06:47:55 PM PDT 24
Peak memory 241936 kb
Host smart-715a8982-295d-4020-ac46-51cb6785e436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411064441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.2411064441
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.968316824
Short name T877
Test name
Test status
Simulation time 2357361121 ps
CPU time 27.03 seconds
Started Aug 11 06:47:23 PM PDT 24
Finished Aug 11 06:47:50 PM PDT 24
Peak memory 242024 kb
Host smart-d5969b90-752d-455d-b274-3015ea3eac28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968316824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.968316824
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.1215734171
Short name T385
Test name
Test status
Simulation time 307215102 ps
CPU time 5.67 seconds
Started Aug 11 06:47:28 PM PDT 24
Finished Aug 11 06:47:34 PM PDT 24
Peak memory 248684 kb
Host smart-ace83760-1c7c-48af-866f-fe16bdecd770
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1215734171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.1215734171
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.2636725159
Short name T873
Test name
Test status
Simulation time 229511675 ps
CPU time 3.94 seconds
Started Aug 11 06:47:24 PM PDT 24
Finished Aug 11 06:47:28 PM PDT 24
Peak memory 242088 kb
Host smart-16aea7fa-33a2-4a01-afc5-87d64c26f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636725159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2636725159
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.2695092442
Short name T785
Test name
Test status
Simulation time 68479440006 ps
CPU time 110.64 seconds
Started Aug 11 06:47:35 PM PDT 24
Finished Aug 11 06:49:26 PM PDT 24
Peak memory 257104 kb
Host smart-1fdda15e-fe09-499f-bdf6-14c898e2b6c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695092442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.2695092442
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.817037085
Short name T794
Test name
Test status
Simulation time 2722210954 ps
CPU time 11.68 seconds
Started Aug 11 06:47:35 PM PDT 24
Finished Aug 11 06:47:47 PM PDT 24
Peak memory 241988 kb
Host smart-790b37b9-1c6a-4574-b3bf-a2a7494f8c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817037085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.817037085
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.3605454493
Short name T199
Test name
Test status
Simulation time 431513182 ps
CPU time 4.63 seconds
Started Aug 11 06:50:40 PM PDT 24
Finished Aug 11 06:50:45 PM PDT 24
Peak memory 242328 kb
Host smart-3035057b-4ce1-459d-bf22-99ea3b9e6b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605454493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3605454493
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.612976617
Short name T730
Test name
Test status
Simulation time 2487720937 ps
CPU time 4.73 seconds
Started Aug 11 06:50:35 PM PDT 24
Finished Aug 11 06:50:40 PM PDT 24
Peak memory 242328 kb
Host smart-5d012ff1-4255-4040-b705-ba60a8936001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612976617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.612976617
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.665276936
Short name T338
Test name
Test status
Simulation time 794287928 ps
CPU time 5.71 seconds
Started Aug 11 06:50:36 PM PDT 24
Finished Aug 11 06:50:42 PM PDT 24
Peak memory 241776 kb
Host smart-ec1a78f4-cb7a-4c27-8f56-556cdd47a222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665276936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.665276936
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.2100722970
Short name T539
Test name
Test status
Simulation time 478411519 ps
CPU time 4.51 seconds
Started Aug 11 06:50:43 PM PDT 24
Finished Aug 11 06:50:48 PM PDT 24
Peak memory 242196 kb
Host smart-08aed658-ccc9-41c5-be86-6fa69d62d405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100722970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.2100722970
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.3952464287
Short name T1082
Test name
Test status
Simulation time 206368174 ps
CPU time 4.64 seconds
Started Aug 11 06:50:44 PM PDT 24
Finished Aug 11 06:50:48 PM PDT 24
Peak memory 242056 kb
Host smart-286ab19e-9e0c-4d99-ab2c-1f1cce4e3cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952464287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.3952464287
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.14891780
Short name T339
Test name
Test status
Simulation time 645461526 ps
CPU time 6.36 seconds
Started Aug 11 06:50:42 PM PDT 24
Finished Aug 11 06:50:48 PM PDT 24
Peak memory 248564 kb
Host smart-9e85ab78-236c-4295-9241-6c9491adb4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14891780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.14891780
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.3917632436
Short name T595
Test name
Test status
Simulation time 513254766 ps
CPU time 4.32 seconds
Started Aug 11 06:50:45 PM PDT 24
Finished Aug 11 06:50:49 PM PDT 24
Peak memory 242124 kb
Host smart-4c6d3cea-29b5-494f-b538-6fbb035d56c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917632436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.3917632436
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.3127996965
Short name T645
Test name
Test status
Simulation time 3698474035 ps
CPU time 29.29 seconds
Started Aug 11 06:50:44 PM PDT 24
Finished Aug 11 06:51:13 PM PDT 24
Peak memory 242480 kb
Host smart-3e4be198-5eb4-482d-9a3c-f7dbbcfac48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127996965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.3127996965
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.682831989
Short name T1036
Test name
Test status
Simulation time 440101810 ps
CPU time 4.67 seconds
Started Aug 11 06:50:43 PM PDT 24
Finished Aug 11 06:50:48 PM PDT 24
Peak memory 241932 kb
Host smart-4157a97b-bbd2-482d-b373-8a17f7feb907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682831989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.682831989
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.1343424610
Short name T351
Test name
Test status
Simulation time 2679359377 ps
CPU time 6.81 seconds
Started Aug 11 06:50:41 PM PDT 24
Finished Aug 11 06:50:48 PM PDT 24
Peak memory 242016 kb
Host smart-3b5c0c01-5751-4e4a-85e8-f71a62a65310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343424610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.1343424610
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.3190876099
Short name T49
Test name
Test status
Simulation time 266034726 ps
CPU time 5.32 seconds
Started Aug 11 06:50:43 PM PDT 24
Finished Aug 11 06:50:48 PM PDT 24
Peak memory 242464 kb
Host smart-7351623e-385a-40a7-90af-2c0ec6ff62ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190876099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.3190876099
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.837080513
Short name T232
Test name
Test status
Simulation time 591754352 ps
CPU time 3.98 seconds
Started Aug 11 06:50:43 PM PDT 24
Finished Aug 11 06:50:47 PM PDT 24
Peak memory 242224 kb
Host smart-69621804-bf39-44e2-b4ed-d0bb25787641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837080513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.837080513
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.2663674188
Short name T349
Test name
Test status
Simulation time 969775900 ps
CPU time 16.04 seconds
Started Aug 11 06:50:43 PM PDT 24
Finished Aug 11 06:50:59 PM PDT 24
Peak memory 242444 kb
Host smart-a96c86c8-320d-445b-b109-275e26bb4d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663674188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.2663674188
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.826877289
Short name T313
Test name
Test status
Simulation time 276748161 ps
CPU time 4.24 seconds
Started Aug 11 06:50:43 PM PDT 24
Finished Aug 11 06:50:47 PM PDT 24
Peak memory 241912 kb
Host smart-5f4876f1-74de-4ce5-93a2-63323f867f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826877289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.826877289
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.27253791
Short name T643
Test name
Test status
Simulation time 1446217517 ps
CPU time 20.08 seconds
Started Aug 11 06:50:41 PM PDT 24
Finished Aug 11 06:51:02 PM PDT 24
Peak memory 242076 kb
Host smart-1f6f9238-c398-423a-9dc1-fa434ad5f46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27253791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.27253791
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.127728209
Short name T663
Test name
Test status
Simulation time 108043630 ps
CPU time 4.29 seconds
Started Aug 11 06:50:41 PM PDT 24
Finished Aug 11 06:50:45 PM PDT 24
Peak memory 241912 kb
Host smart-b30abc50-b71e-457e-b6dc-cd813e15d746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127728209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.127728209
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.743821590
Short name T991
Test name
Test status
Simulation time 2185861440 ps
CPU time 17.92 seconds
Started Aug 11 06:50:44 PM PDT 24
Finished Aug 11 06:51:02 PM PDT 24
Peak memory 242260 kb
Host smart-b2e82783-6377-46a4-903f-8cb2fbd7ba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743821590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.743821590
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.4133042998
Short name T347
Test name
Test status
Simulation time 170536037 ps
CPU time 1.63 seconds
Started Aug 11 06:47:33 PM PDT 24
Finished Aug 11 06:47:34 PM PDT 24
Peak memory 240756 kb
Host smart-b3c8b616-4ced-4dce-ba62-6fc512ceba2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133042998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.4133042998
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.281017486
Short name T46
Test name
Test status
Simulation time 1663695494 ps
CPU time 36.69 seconds
Started Aug 11 06:47:33 PM PDT 24
Finished Aug 11 06:48:10 PM PDT 24
Peak memory 248704 kb
Host smart-2750a49f-ce6a-45c9-a531-9a6c29bac5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281017486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.281017486
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.1371468663
Short name T227
Test name
Test status
Simulation time 674301246 ps
CPU time 19.83 seconds
Started Aug 11 06:47:33 PM PDT 24
Finished Aug 11 06:47:53 PM PDT 24
Peak memory 241980 kb
Host smart-6e16d7f1-773c-40e3-844f-7e7c9c919b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371468663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.1371468663
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.621482354
Short name T200
Test name
Test status
Simulation time 1861579062 ps
CPU time 22.92 seconds
Started Aug 11 06:47:35 PM PDT 24
Finished Aug 11 06:47:58 PM PDT 24
Peak memory 242468 kb
Host smart-514b54bd-3552-4e88-85a6-84ca8c1c46f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621482354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.621482354
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.300800973
Short name T298
Test name
Test status
Simulation time 273791587 ps
CPU time 3.55 seconds
Started Aug 11 06:47:36 PM PDT 24
Finished Aug 11 06:47:39 PM PDT 24
Peak memory 242148 kb
Host smart-17a0c830-76e0-4cda-b859-cc7521370928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300800973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.300800973
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.578959991
Short name T756
Test name
Test status
Simulation time 7581704565 ps
CPU time 72.53 seconds
Started Aug 11 06:47:32 PM PDT 24
Finished Aug 11 06:48:45 PM PDT 24
Peak memory 248168 kb
Host smart-6ee58f74-b386-438b-a453-9a64942c3e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578959991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.578959991
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.3384023849
Short name T1046
Test name
Test status
Simulation time 9840988435 ps
CPU time 31.75 seconds
Started Aug 11 06:47:33 PM PDT 24
Finished Aug 11 06:48:05 PM PDT 24
Peak memory 243132 kb
Host smart-c3de769d-3150-4aa3-bd5c-e02eabcac9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384023849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.3384023849
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.3010592356
Short name T598
Test name
Test status
Simulation time 574239017 ps
CPU time 9.85 seconds
Started Aug 11 06:47:33 PM PDT 24
Finished Aug 11 06:47:42 PM PDT 24
Peak memory 241848 kb
Host smart-c15cb319-d80a-42e6-a51f-24ea81550ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010592356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3010592356
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.3457172390
Short name T203
Test name
Test status
Simulation time 893700847 ps
CPU time 20.63 seconds
Started Aug 11 06:47:35 PM PDT 24
Finished Aug 11 06:47:56 PM PDT 24
Peak memory 242144 kb
Host smart-6e2c36e2-ed69-42b2-8fd7-612fb33adafe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457172390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.3457172390
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.1182725493
Short name T219
Test name
Test status
Simulation time 209431883 ps
CPU time 8.57 seconds
Started Aug 11 06:47:34 PM PDT 24
Finished Aug 11 06:47:43 PM PDT 24
Peak memory 241820 kb
Host smart-ed13829d-5e9b-4d6d-9a73-bd17ed7126c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182725493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.1182725493
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.3938165309
Short name T774
Test name
Test status
Simulation time 1280718954 ps
CPU time 12.93 seconds
Started Aug 11 06:47:28 PM PDT 24
Finished Aug 11 06:47:42 PM PDT 24
Peak memory 242268 kb
Host smart-ef176cfa-8a97-4fc7-8946-69f8c452f1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938165309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.3938165309
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.2145538039
Short name T632
Test name
Test status
Simulation time 11099106514 ps
CPU time 76.53 seconds
Started Aug 11 06:47:35 PM PDT 24
Finished Aug 11 06:48:52 PM PDT 24
Peak memory 258504 kb
Host smart-c98434c6-41e6-4c95-978e-e047d2695d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145538039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.2145538039
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.1402358740
Short name T293
Test name
Test status
Simulation time 80889846377 ps
CPU time 887.21 seconds
Started Aug 11 06:47:33 PM PDT 24
Finished Aug 11 07:02:20 PM PDT 24
Peak memory 297912 kb
Host smart-045e2c98-4ea9-4862-83de-ac56be89f307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402358740 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.1402358740
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.1026759612
Short name T741
Test name
Test status
Simulation time 255937096 ps
CPU time 8.72 seconds
Started Aug 11 06:47:33 PM PDT 24
Finished Aug 11 06:47:42 PM PDT 24
Peak memory 242340 kb
Host smart-d1a0f27d-70d4-407b-9a1e-b432baf584b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026759612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.1026759612
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.3348078070
Short name T1060
Test name
Test status
Simulation time 2345637366 ps
CPU time 6.55 seconds
Started Aug 11 06:50:40 PM PDT 24
Finished Aug 11 06:50:47 PM PDT 24
Peak memory 242072 kb
Host smart-9952b711-7af9-46f3-a498-7ae1185f8454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348078070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.3348078070
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.1659066345
Short name T1141
Test name
Test status
Simulation time 1859929939 ps
CPU time 7.68 seconds
Started Aug 11 06:50:41 PM PDT 24
Finished Aug 11 06:50:49 PM PDT 24
Peak memory 241968 kb
Host smart-f4400312-8091-4e49-875c-8851a5800a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659066345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.1659066345
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.147276928
Short name T167
Test name
Test status
Simulation time 404012938 ps
CPU time 4.43 seconds
Started Aug 11 06:50:42 PM PDT 24
Finished Aug 11 06:50:47 PM PDT 24
Peak memory 242204 kb
Host smart-2894068a-9706-49ca-85c8-62e1ca262b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147276928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.147276928
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.3489593220
Short name T725
Test name
Test status
Simulation time 5399082028 ps
CPU time 10.1 seconds
Started Aug 11 06:50:41 PM PDT 24
Finished Aug 11 06:50:51 PM PDT 24
Peak memory 242368 kb
Host smart-28fbc077-ec40-4fe9-9f17-7451d104fa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489593220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.3489593220
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.2336697123
Short name T980
Test name
Test status
Simulation time 145880622 ps
CPU time 3.29 seconds
Started Aug 11 06:50:40 PM PDT 24
Finished Aug 11 06:50:44 PM PDT 24
Peak memory 242260 kb
Host smart-088b42c4-8848-40e8-9d66-665cfb72739d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336697123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.2336697123
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.3961698413
Short name T391
Test name
Test status
Simulation time 675953691 ps
CPU time 14.88 seconds
Started Aug 11 06:50:44 PM PDT 24
Finished Aug 11 06:50:58 PM PDT 24
Peak memory 242200 kb
Host smart-1a98d8c8-7d16-4f5f-9da6-598c1c71350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961698413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.3961698413
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.243570514
Short name T50
Test name
Test status
Simulation time 184877643 ps
CPU time 4.75 seconds
Started Aug 11 06:50:43 PM PDT 24
Finished Aug 11 06:50:48 PM PDT 24
Peak memory 242004 kb
Host smart-5c7e421b-b4e6-4d27-87a5-15fd50f43abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243570514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.243570514
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.353213386
Short name T549
Test name
Test status
Simulation time 176780137 ps
CPU time 3.35 seconds
Started Aug 11 06:50:43 PM PDT 24
Finished Aug 11 06:50:47 PM PDT 24
Peak memory 242308 kb
Host smart-33d38810-40ba-47e5-9aa2-038f02c4594f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353213386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.353213386
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.4114686447
Short name T1013
Test name
Test status
Simulation time 285300873 ps
CPU time 4.58 seconds
Started Aug 11 06:50:42 PM PDT 24
Finished Aug 11 06:50:47 PM PDT 24
Peak memory 242376 kb
Host smart-1f236b10-30d7-409f-a1bb-dfd3a5f5e382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114686447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.4114686447
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.519579850
Short name T1032
Test name
Test status
Simulation time 392917906 ps
CPU time 5.13 seconds
Started Aug 11 06:50:42 PM PDT 24
Finished Aug 11 06:50:47 PM PDT 24
Peak memory 242280 kb
Host smart-4c7a1185-14f5-4afa-989c-a25cdb8e040b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519579850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.519579850
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.2676916999
Short name T242
Test name
Test status
Simulation time 101413773 ps
CPU time 3.1 seconds
Started Aug 11 06:50:42 PM PDT 24
Finished Aug 11 06:50:45 PM PDT 24
Peak memory 242456 kb
Host smart-690eaf63-cd06-4a5a-8f6a-d93de328a024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676916999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.2676916999
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.3112337587
Short name T999
Test name
Test status
Simulation time 2028878473 ps
CPU time 24.87 seconds
Started Aug 11 06:50:41 PM PDT 24
Finished Aug 11 06:51:06 PM PDT 24
Peak memory 241652 kb
Host smart-5c902490-3395-4ca1-a1e1-e2192d01ec3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112337587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.3112337587
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.394161876
Short name T1129
Test name
Test status
Simulation time 198758873 ps
CPU time 3.66 seconds
Started Aug 11 06:50:43 PM PDT 24
Finished Aug 11 06:50:46 PM PDT 24
Peak memory 242400 kb
Host smart-bc3bd27b-ba60-45e3-84e0-ff99a6421009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394161876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.394161876
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.334193494
Short name T1132
Test name
Test status
Simulation time 167079444 ps
CPU time 4.44 seconds
Started Aug 11 06:50:43 PM PDT 24
Finished Aug 11 06:50:48 PM PDT 24
Peak memory 241924 kb
Host smart-a645537c-96f6-4e07-b0da-d2ffd41cffe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334193494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.334193494
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.981528240
Short name T1025
Test name
Test status
Simulation time 433232960 ps
CPU time 5.55 seconds
Started Aug 11 06:50:43 PM PDT 24
Finished Aug 11 06:50:49 PM PDT 24
Peak memory 242372 kb
Host smart-8fcd0c8a-8e3f-4420-9c79-0d2049a8e080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981528240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.981528240
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.500831128
Short name T652
Test name
Test status
Simulation time 176089018 ps
CPU time 2.63 seconds
Started Aug 11 06:50:44 PM PDT 24
Finished Aug 11 06:50:46 PM PDT 24
Peak memory 242120 kb
Host smart-dba29782-4e96-4f32-8084-9fd3714a25f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500831128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.500831128
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.1566243432
Short name T70
Test name
Test status
Simulation time 224585977 ps
CPU time 4.19 seconds
Started Aug 11 06:50:43 PM PDT 24
Finished Aug 11 06:50:47 PM PDT 24
Peak memory 242424 kb
Host smart-9dfbd8f1-56d3-4797-b59e-715c61c96d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566243432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.1566243432
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.1277690741
Short name T890
Test name
Test status
Simulation time 797005136 ps
CPU time 16.55 seconds
Started Aug 11 06:50:55 PM PDT 24
Finished Aug 11 06:51:11 PM PDT 24
Peak memory 241992 kb
Host smart-a86820ad-cd44-4b9f-adaf-964aa1f15c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277690741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.1277690741
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.1603697027
Short name T1150
Test name
Test status
Simulation time 108642080 ps
CPU time 3.84 seconds
Started Aug 11 06:50:48 PM PDT 24
Finished Aug 11 06:50:52 PM PDT 24
Peak memory 241960 kb
Host smart-0985d4bf-4373-4df9-8396-6891297adca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603697027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.1603697027
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.887332328
Short name T173
Test name
Test status
Simulation time 130153821 ps
CPU time 5.37 seconds
Started Aug 11 06:50:51 PM PDT 24
Finished Aug 11 06:50:57 PM PDT 24
Peak memory 241932 kb
Host smart-e09f38cd-94b0-4955-b5c4-0cad47318460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887332328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.887332328
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.1436287914
Short name T596
Test name
Test status
Simulation time 46487793 ps
CPU time 1.59 seconds
Started Aug 11 06:47:39 PM PDT 24
Finished Aug 11 06:47:41 PM PDT 24
Peak memory 240596 kb
Host smart-728e134f-2d88-499c-8fc1-d83a43946d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436287914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.1436287914
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.2203439956
Short name T580
Test name
Test status
Simulation time 1130081258 ps
CPU time 21.03 seconds
Started Aug 11 06:47:38 PM PDT 24
Finished Aug 11 06:47:59 PM PDT 24
Peak memory 242436 kb
Host smart-cb653fb4-01f4-498c-a043-f7712cc71789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203439956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.2203439956
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.3314254970
Short name T952
Test name
Test status
Simulation time 433242049 ps
CPU time 14.07 seconds
Started Aug 11 06:47:36 PM PDT 24
Finished Aug 11 06:47:51 PM PDT 24
Peak memory 242348 kb
Host smart-b0191202-b85b-4146-a074-b0eea7dd923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314254970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.3314254970
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.83875664
Short name T1034
Test name
Test status
Simulation time 2164023701 ps
CPU time 23.18 seconds
Started Aug 11 06:47:44 PM PDT 24
Finished Aug 11 06:48:07 PM PDT 24
Peak memory 242288 kb
Host smart-9c24735c-70bd-4cab-8075-9cd9e45d06d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83875664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.83875664
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.2312756961
Short name T839
Test name
Test status
Simulation time 500787972 ps
CPU time 3.59 seconds
Started Aug 11 06:47:44 PM PDT 24
Finished Aug 11 06:47:47 PM PDT 24
Peak memory 242064 kb
Host smart-88feee09-3773-48ee-aa61-102b9a2d2aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312756961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2312756961
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.4264352574
Short name T213
Test name
Test status
Simulation time 1104687678 ps
CPU time 16.97 seconds
Started Aug 11 06:47:42 PM PDT 24
Finished Aug 11 06:47:59 PM PDT 24
Peak memory 243828 kb
Host smart-679ce954-596c-40ff-b51b-2f95acd8686f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264352574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.4264352574
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.1373119139
Short name T864
Test name
Test status
Simulation time 6850839033 ps
CPU time 49.64 seconds
Started Aug 11 06:47:40 PM PDT 24
Finished Aug 11 06:48:30 PM PDT 24
Peak memory 243428 kb
Host smart-b9c1d213-ede3-438e-ae3a-8a888e3b71d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373119139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.1373119139
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.3322604456
Short name T1155
Test name
Test status
Simulation time 580263140 ps
CPU time 4.73 seconds
Started Aug 11 06:47:38 PM PDT 24
Finished Aug 11 06:47:43 PM PDT 24
Peak memory 241956 kb
Host smart-21d86699-47cf-4262-911a-50ce1685a042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322604456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.3322604456
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.319102286
Short name T1078
Test name
Test status
Simulation time 4702263923 ps
CPU time 14.24 seconds
Started Aug 11 06:47:39 PM PDT 24
Finished Aug 11 06:47:54 PM PDT 24
Peak memory 242176 kb
Host smart-a45f705a-b26c-4938-bd32-31a9ba0f6160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=319102286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.319102286
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.1010699184
Short name T417
Test name
Test status
Simulation time 150528823 ps
CPU time 5.2 seconds
Started Aug 11 06:47:39 PM PDT 24
Finished Aug 11 06:47:44 PM PDT 24
Peak memory 242080 kb
Host smart-08aed374-9fdf-4ce0-9e89-55fe3b12d94e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010699184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1010699184
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.2110325607
Short name T109
Test name
Test status
Simulation time 930540466 ps
CPU time 6.18 seconds
Started Aug 11 06:47:33 PM PDT 24
Finished Aug 11 06:47:40 PM PDT 24
Peak memory 242164 kb
Host smart-f1e36ce1-122e-466e-ab36-edb5d2e3b55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110325607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.2110325607
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.3796282353
Short name T270
Test name
Test status
Simulation time 5302352714 ps
CPU time 79 seconds
Started Aug 11 06:47:44 PM PDT 24
Finished Aug 11 06:49:03 PM PDT 24
Peak memory 245388 kb
Host smart-ddfbbe02-5675-4c15-af07-d9f69cbbda67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796282353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.3796282353
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.3215369966
Short name T510
Test name
Test status
Simulation time 3156399598 ps
CPU time 23.54 seconds
Started Aug 11 06:47:39 PM PDT 24
Finished Aug 11 06:48:03 PM PDT 24
Peak memory 248712 kb
Host smart-8c4327c0-cba1-4dd2-933b-3eab4a538451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215369966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.3215369966
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.2481392303
Short name T852
Test name
Test status
Simulation time 226383260 ps
CPU time 2.99 seconds
Started Aug 11 06:50:49 PM PDT 24
Finished Aug 11 06:50:52 PM PDT 24
Peak memory 242296 kb
Host smart-9b79670b-580e-4fd4-9cfd-6c181403d103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481392303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.2481392303
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.4207761956
Short name T481
Test name
Test status
Simulation time 2870823798 ps
CPU time 5.17 seconds
Started Aug 11 06:50:49 PM PDT 24
Finished Aug 11 06:50:54 PM PDT 24
Peak memory 242336 kb
Host smart-0b7d9fdf-0e1b-4345-97ab-7f9b58538dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207761956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.4207761956
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.2401022625
Short name T486
Test name
Test status
Simulation time 1757023482 ps
CPU time 5.07 seconds
Started Aug 11 06:50:51 PM PDT 24
Finished Aug 11 06:50:56 PM PDT 24
Peak memory 242064 kb
Host smart-827e1b74-d1d4-4dd6-80fb-7df939341023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401022625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.2401022625
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.1285182834
Short name T437
Test name
Test status
Simulation time 189029856 ps
CPU time 4.41 seconds
Started Aug 11 06:50:49 PM PDT 24
Finished Aug 11 06:50:53 PM PDT 24
Peak memory 241904 kb
Host smart-c66e9f64-373b-45a6-8574-c01517206a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285182834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.1285182834
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.2497457243
Short name T685
Test name
Test status
Simulation time 182997924 ps
CPU time 3.29 seconds
Started Aug 11 06:50:51 PM PDT 24
Finished Aug 11 06:50:54 PM PDT 24
Peak memory 242156 kb
Host smart-5ed465f2-cc65-4140-b2e5-c9b7e5f9a728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497457243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.2497457243
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.3729564753
Short name T1181
Test name
Test status
Simulation time 126234612 ps
CPU time 4.61 seconds
Started Aug 11 06:50:54 PM PDT 24
Finished Aug 11 06:50:59 PM PDT 24
Peak memory 242132 kb
Host smart-2451838a-5369-4ef2-bba5-eb82041ed299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729564753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.3729564753
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.511854890
Short name T832
Test name
Test status
Simulation time 148641800 ps
CPU time 4.1 seconds
Started Aug 11 06:50:49 PM PDT 24
Finished Aug 11 06:50:53 PM PDT 24
Peak memory 242204 kb
Host smart-79a64cc1-b91c-4f4c-98a1-cc88888caf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511854890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.511854890
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.3996505133
Short name T736
Test name
Test status
Simulation time 140086998 ps
CPU time 6.66 seconds
Started Aug 11 06:50:48 PM PDT 24
Finished Aug 11 06:50:55 PM PDT 24
Peak memory 242444 kb
Host smart-1591f884-b038-4847-84e4-1af26b9ce9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996505133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.3996505133
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.3302902685
Short name T110
Test name
Test status
Simulation time 135876159 ps
CPU time 3.71 seconds
Started Aug 11 06:50:47 PM PDT 24
Finished Aug 11 06:50:51 PM PDT 24
Peak memory 242372 kb
Host smart-eb3361fd-d15c-40b2-842b-427578571d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302902685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.3302902685
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.3551001252
Short name T1023
Test name
Test status
Simulation time 2251126935 ps
CPU time 17.1 seconds
Started Aug 11 06:50:49 PM PDT 24
Finished Aug 11 06:51:06 PM PDT 24
Peak memory 242036 kb
Host smart-32f85aa6-b2f1-4a0f-8c69-7bff8bf92a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551001252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.3551001252
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.4023438457
Short name T10
Test name
Test status
Simulation time 1896986316 ps
CPU time 6.05 seconds
Started Aug 11 06:50:47 PM PDT 24
Finished Aug 11 06:50:53 PM PDT 24
Peak memory 242128 kb
Host smart-cfc6e7eb-7402-4862-a0d1-c2003e0bda69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023438457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.4023438457
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.3134744794
Short name T1098
Test name
Test status
Simulation time 345612969 ps
CPU time 3.95 seconds
Started Aug 11 06:50:48 PM PDT 24
Finished Aug 11 06:50:52 PM PDT 24
Peak memory 242132 kb
Host smart-84954b74-545c-48b6-9d3a-ae0304dafc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134744794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.3134744794
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.3474904431
Short name T250
Test name
Test status
Simulation time 267701162 ps
CPU time 11.73 seconds
Started Aug 11 06:50:55 PM PDT 24
Finished Aug 11 06:51:07 PM PDT 24
Peak memory 241992 kb
Host smart-fdf6da06-3283-4835-beaf-551837959b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474904431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.3474904431
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.388890052
Short name T57
Test name
Test status
Simulation time 227677160 ps
CPU time 4.17 seconds
Started Aug 11 06:50:50 PM PDT 24
Finished Aug 11 06:50:54 PM PDT 24
Peak memory 241944 kb
Host smart-4730303f-7c27-49e3-b156-68ab8e5be817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388890052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.388890052
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.1982785564
Short name T948
Test name
Test status
Simulation time 1068848555 ps
CPU time 27.56 seconds
Started Aug 11 06:50:48 PM PDT 24
Finished Aug 11 06:51:16 PM PDT 24
Peak memory 242040 kb
Host smart-cb788cc9-a757-4ec0-9093-cfa5bb4cee8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982785564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.1982785564
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.1074074190
Short name T78
Test name
Test status
Simulation time 316716106 ps
CPU time 4.7 seconds
Started Aug 11 06:50:50 PM PDT 24
Finished Aug 11 06:50:55 PM PDT 24
Peak memory 241956 kb
Host smart-3f2c9d79-ae11-41fe-bbd8-9c357a136bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074074190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.1074074190
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.4202650802
Short name T1120
Test name
Test status
Simulation time 672501569 ps
CPU time 18.83 seconds
Started Aug 11 06:50:51 PM PDT 24
Finished Aug 11 06:51:10 PM PDT 24
Peak memory 241972 kb
Host smart-64bac835-19d7-41cf-ba03-9afe8a9930aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202650802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.4202650802
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.1574867163
Short name T474
Test name
Test status
Simulation time 2091189159 ps
CPU time 5.08 seconds
Started Aug 11 06:50:49 PM PDT 24
Finished Aug 11 06:50:54 PM PDT 24
Peak memory 242168 kb
Host smart-195c2f65-dff8-4bd1-913b-963db0471cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574867163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.1574867163
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.3541411230
Short name T149
Test name
Test status
Simulation time 10463953286 ps
CPU time 20.89 seconds
Started Aug 11 06:50:50 PM PDT 24
Finished Aug 11 06:51:10 PM PDT 24
Peak memory 242356 kb
Host smart-81d78ed9-beda-4130-929d-2a7d68cac754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541411230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.3541411230
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.2821821205
Short name T441
Test name
Test status
Simulation time 131433561 ps
CPU time 1.68 seconds
Started Aug 11 06:47:45 PM PDT 24
Finished Aug 11 06:47:46 PM PDT 24
Peak memory 240520 kb
Host smart-189c3c65-4883-4266-a2c8-59c7cc173e53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821821205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.2821821205
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.560223330
Short name T945
Test name
Test status
Simulation time 331181288 ps
CPU time 5.58 seconds
Started Aug 11 06:47:38 PM PDT 24
Finished Aug 11 06:47:44 PM PDT 24
Peak memory 248532 kb
Host smart-1c40719b-b227-4c0d-bbe5-5d7a70eafd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560223330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.560223330
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.2977390571
Short name T862
Test name
Test status
Simulation time 3866114505 ps
CPU time 33.99 seconds
Started Aug 11 06:47:39 PM PDT 24
Finished Aug 11 06:48:13 PM PDT 24
Peak memory 246404 kb
Host smart-ec02ca27-40ee-4181-bc95-5434a5d96210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977390571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.2977390571
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.1705062095
Short name T514
Test name
Test status
Simulation time 1096430638 ps
CPU time 11.03 seconds
Started Aug 11 06:47:44 PM PDT 24
Finished Aug 11 06:47:55 PM PDT 24
Peak memory 242292 kb
Host smart-38d9fd4e-3c38-4ad9-99d9-6a4242cdfeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705062095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.1705062095
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.2236975161
Short name T1045
Test name
Test status
Simulation time 1997164027 ps
CPU time 6.97 seconds
Started Aug 11 06:47:37 PM PDT 24
Finished Aug 11 06:47:44 PM PDT 24
Peak memory 242280 kb
Host smart-c8abf31e-aa38-40ee-8ee1-dd8e00486453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236975161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.2236975161
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.1077579142
Short name T154
Test name
Test status
Simulation time 2000440737 ps
CPU time 23.28 seconds
Started Aug 11 06:47:44 PM PDT 24
Finished Aug 11 06:48:07 PM PDT 24
Peak memory 248396 kb
Host smart-a04f6975-2130-4f4b-83aa-97f186609f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077579142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.1077579142
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.2671377850
Short name T424
Test name
Test status
Simulation time 614311870 ps
CPU time 5.64 seconds
Started Aug 11 06:47:44 PM PDT 24
Finished Aug 11 06:47:50 PM PDT 24
Peak memory 248616 kb
Host smart-90923357-12fd-46e0-9f0f-5fbc28902d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671377850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.2671377850
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.437955427
Short name T603
Test name
Test status
Simulation time 578982084 ps
CPU time 6.75 seconds
Started Aug 11 06:47:40 PM PDT 24
Finished Aug 11 06:47:47 PM PDT 24
Peak memory 242040 kb
Host smart-28079b3a-5a58-4ee0-8824-7475d9ad4035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437955427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.437955427
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.4123293991
Short name T1081
Test name
Test status
Simulation time 580406832 ps
CPU time 10.48 seconds
Started Aug 11 06:47:38 PM PDT 24
Finished Aug 11 06:47:49 PM PDT 24
Peak memory 248512 kb
Host smart-7177a272-c005-4602-8bdc-7b36c16ad9c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123293991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.4123293991
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.1891410612
Short name T1027
Test name
Test status
Simulation time 485314071 ps
CPU time 8.36 seconds
Started Aug 11 06:47:45 PM PDT 24
Finished Aug 11 06:47:54 PM PDT 24
Peak memory 241968 kb
Host smart-24c3b1f1-5ea5-48a7-b404-9c2006f98346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1891410612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.1891410612
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.3806857917
Short name T416
Test name
Test status
Simulation time 946552379 ps
CPU time 5.72 seconds
Started Aug 11 06:47:40 PM PDT 24
Finished Aug 11 06:47:46 PM PDT 24
Peak memory 242228 kb
Host smart-5901f81b-34ba-489d-8ebf-5a86c51926cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806857917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.3806857917
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.390178985
Short name T348
Test name
Test status
Simulation time 16745524944 ps
CPU time 36.33 seconds
Started Aug 11 06:47:55 PM PDT 24
Finished Aug 11 06:48:32 PM PDT 24
Peak memory 242952 kb
Host smart-ab6fea67-2e51-49fc-a715-ea9c485fdd08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390178985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.
390178985
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.1022204867
Short name T19
Test name
Test status
Simulation time 18707711251 ps
CPU time 442.27 seconds
Started Aug 11 06:47:44 PM PDT 24
Finished Aug 11 06:55:07 PM PDT 24
Peak memory 274956 kb
Host smart-c71fe4a0-64f7-4a4b-8fc5-f2e2362e8ffe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022204867 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.1022204867
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.2763474766
Short name T661
Test name
Test status
Simulation time 3095707524 ps
CPU time 29.04 seconds
Started Aug 11 06:47:44 PM PDT 24
Finished Aug 11 06:48:13 PM PDT 24
Peak memory 241904 kb
Host smart-bd8e1ec3-dee9-4577-a11d-968854d7fc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763474766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.2763474766
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.53738453
Short name T421
Test name
Test status
Simulation time 1905733667 ps
CPU time 6.82 seconds
Started Aug 11 06:50:48 PM PDT 24
Finished Aug 11 06:50:55 PM PDT 24
Peak memory 242244 kb
Host smart-27249b75-e82d-4dd2-aa3a-2862011a5bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53738453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.53738453
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.2915669381
Short name T1180
Test name
Test status
Simulation time 149755956 ps
CPU time 5.45 seconds
Started Aug 11 06:50:47 PM PDT 24
Finished Aug 11 06:50:52 PM PDT 24
Peak memory 242368 kb
Host smart-0c2a6d7d-9d3f-46b1-8a74-bbe04b57c463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915669381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.2915669381
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.3210016552
Short name T812
Test name
Test status
Simulation time 632248353 ps
CPU time 5.04 seconds
Started Aug 11 06:50:49 PM PDT 24
Finished Aug 11 06:50:54 PM PDT 24
Peak memory 242152 kb
Host smart-e58e8964-740a-451e-a380-f23caeb2f8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210016552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.3210016552
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.2160643990
Short name T653
Test name
Test status
Simulation time 172508208 ps
CPU time 8.47 seconds
Started Aug 11 06:50:48 PM PDT 24
Finished Aug 11 06:50:57 PM PDT 24
Peak memory 242040 kb
Host smart-d05f6148-d668-44f3-aa2e-590fddf52700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160643990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2160643990
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.3475937374
Short name T764
Test name
Test status
Simulation time 2317443518 ps
CPU time 4.68 seconds
Started Aug 11 06:50:50 PM PDT 24
Finished Aug 11 06:50:55 PM PDT 24
Peak memory 242240 kb
Host smart-3ecc4b1a-67d8-42b6-b565-b23ada261a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475937374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.3475937374
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.2479138310
Short name T799
Test name
Test status
Simulation time 416927947 ps
CPU time 5.75 seconds
Started Aug 11 06:50:52 PM PDT 24
Finished Aug 11 06:50:58 PM PDT 24
Peak memory 241980 kb
Host smart-541224b6-4514-44fb-b26c-e6ddd4192ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479138310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.2479138310
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.1631220150
Short name T425
Test name
Test status
Simulation time 245059932 ps
CPU time 4.5 seconds
Started Aug 11 06:50:51 PM PDT 24
Finished Aug 11 06:50:56 PM PDT 24
Peak memory 241948 kb
Host smart-6536e168-98b4-4cc2-8eaa-3ccedd2ca227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631220150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1631220150
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.868791812
Short name T934
Test name
Test status
Simulation time 466414380 ps
CPU time 7.68 seconds
Started Aug 11 06:50:55 PM PDT 24
Finished Aug 11 06:51:03 PM PDT 24
Peak memory 247600 kb
Host smart-ee5bf742-df42-4bae-802b-03aa185c6490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868791812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.868791812
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.2534918757
Short name T1101
Test name
Test status
Simulation time 170151042 ps
CPU time 5.81 seconds
Started Aug 11 06:50:53 PM PDT 24
Finished Aug 11 06:50:59 PM PDT 24
Peak memory 242204 kb
Host smart-5e4ff665-ecb6-4428-ad31-28af28bfbc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534918757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.2534918757
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.2697263154
Short name T1109
Test name
Test status
Simulation time 7819351453 ps
CPU time 17.87 seconds
Started Aug 11 06:50:52 PM PDT 24
Finished Aug 11 06:51:10 PM PDT 24
Peak memory 242060 kb
Host smart-9aa6079e-ac04-4b6c-8aba-96b8e18ea90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697263154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.2697263154
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.3821818312
Short name T974
Test name
Test status
Simulation time 292328364 ps
CPU time 3.62 seconds
Started Aug 11 06:50:54 PM PDT 24
Finished Aug 11 06:50:57 PM PDT 24
Peak memory 241816 kb
Host smart-d0b4e511-0a08-4bb8-817d-77edc9a1d4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821818312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.3821818312
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.2069670506
Short name T1006
Test name
Test status
Simulation time 461083180 ps
CPU time 10.7 seconds
Started Aug 11 06:50:50 PM PDT 24
Finished Aug 11 06:51:01 PM PDT 24
Peak memory 241816 kb
Host smart-b40f0d09-90ea-4592-a299-f5444f35879a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069670506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.2069670506
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.1494770182
Short name T1153
Test name
Test status
Simulation time 497713855 ps
CPU time 3.92 seconds
Started Aug 11 06:50:51 PM PDT 24
Finished Aug 11 06:50:55 PM PDT 24
Peak memory 242108 kb
Host smart-c3519876-2a2f-4e03-ba10-33af426fb46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494770182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.1494770182
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.1757170607
Short name T414
Test name
Test status
Simulation time 255079981 ps
CPU time 4.02 seconds
Started Aug 11 06:50:52 PM PDT 24
Finished Aug 11 06:50:56 PM PDT 24
Peak memory 242348 kb
Host smart-0119b9b1-b626-40e2-ae4e-6114f27e0181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757170607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.1757170607
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.1538664454
Short name T1166
Test name
Test status
Simulation time 107364703 ps
CPU time 3.89 seconds
Started Aug 11 06:50:52 PM PDT 24
Finished Aug 11 06:50:56 PM PDT 24
Peak memory 242212 kb
Host smart-a94e2192-5fac-4d2f-b2ee-b2a698f8ca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538664454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.1538664454
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.1927477629
Short name T627
Test name
Test status
Simulation time 286161323 ps
CPU time 8.32 seconds
Started Aug 11 06:50:52 PM PDT 24
Finished Aug 11 06:51:00 PM PDT 24
Peak memory 242288 kb
Host smart-b47023cb-051c-4c30-9998-a58037945c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927477629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1927477629
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.3535032769
Short name T1123
Test name
Test status
Simulation time 137103952 ps
CPU time 3.78 seconds
Started Aug 11 06:50:55 PM PDT 24
Finished Aug 11 06:50:59 PM PDT 24
Peak memory 242208 kb
Host smart-7256f518-49ac-4a1d-8b74-8cf2fccc8c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535032769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.3535032769
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.391937284
Short name T677
Test name
Test status
Simulation time 255841902 ps
CPU time 11.17 seconds
Started Aug 11 06:50:52 PM PDT 24
Finished Aug 11 06:51:04 PM PDT 24
Peak memory 241756 kb
Host smart-d299e8b7-3799-4d7e-afd7-de9325a979c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391937284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.391937284
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.469918137
Short name T1168
Test name
Test status
Simulation time 251384041 ps
CPU time 3.43 seconds
Started Aug 11 06:50:55 PM PDT 24
Finished Aug 11 06:50:59 PM PDT 24
Peak memory 242272 kb
Host smart-f3ee4f17-e5f4-4c87-8217-e216c0007eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469918137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.469918137
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.1165585420
Short name T252
Test name
Test status
Simulation time 1545439510 ps
CPU time 12.35 seconds
Started Aug 11 06:50:51 PM PDT 24
Finished Aug 11 06:51:04 PM PDT 24
Peak memory 242312 kb
Host smart-90d4c8f7-d13c-4b00-9623-086705c4948e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165585420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1165585420
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.4231736074
Short name T906
Test name
Test status
Simulation time 831549246 ps
CPU time 2.47 seconds
Started Aug 11 06:45:57 PM PDT 24
Finished Aug 11 06:45:59 PM PDT 24
Peak memory 240400 kb
Host smart-ac3a7602-1cc3-48e8-a5fa-278c3b1b8059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231736074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.4231736074
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.3146112133
Short name T1108
Test name
Test status
Simulation time 962124784 ps
CPU time 26.12 seconds
Started Aug 11 06:45:48 PM PDT 24
Finished Aug 11 06:46:14 PM PDT 24
Peak memory 248684 kb
Host smart-521f8127-e77a-47df-b494-995143ac0387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146112133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.3146112133
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.2941291898
Short name T76
Test name
Test status
Simulation time 3954191183 ps
CPU time 22.47 seconds
Started Aug 11 06:45:53 PM PDT 24
Finished Aug 11 06:46:16 PM PDT 24
Peak memory 246352 kb
Host smart-a22759a6-dd36-40d0-8d3e-3453913c122c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941291898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.2941291898
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.3180854596
Short name T429
Test name
Test status
Simulation time 3723661433 ps
CPU time 36.79 seconds
Started Aug 11 06:45:53 PM PDT 24
Finished Aug 11 06:46:30 PM PDT 24
Peak memory 245104 kb
Host smart-9195bba8-110c-4d20-a986-293dd5dadc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180854596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.3180854596
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.2025323703
Short name T1125
Test name
Test status
Simulation time 5684730335 ps
CPU time 38.03 seconds
Started Aug 11 06:45:52 PM PDT 24
Finished Aug 11 06:46:30 PM PDT 24
Peak memory 242152 kb
Host smart-cd1f5d29-3769-4154-bce5-98139ddc740e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025323703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.2025323703
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.1729879856
Short name T53
Test name
Test status
Simulation time 109125552 ps
CPU time 4.07 seconds
Started Aug 11 06:45:47 PM PDT 24
Finished Aug 11 06:45:51 PM PDT 24
Peak memory 242288 kb
Host smart-c0981f71-7231-4270-a0e7-439901ebb867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729879856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.1729879856
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.2876529255
Short name T492
Test name
Test status
Simulation time 5511815688 ps
CPU time 39.24 seconds
Started Aug 11 06:45:56 PM PDT 24
Finished Aug 11 06:46:35 PM PDT 24
Peak memory 256944 kb
Host smart-82a0bd18-b361-4ecb-9ca3-5d0ea741e941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876529255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.2876529255
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.1576907717
Short name T523
Test name
Test status
Simulation time 13758948122 ps
CPU time 38.95 seconds
Started Aug 11 06:45:55 PM PDT 24
Finished Aug 11 06:46:34 PM PDT 24
Peak memory 242860 kb
Host smart-b560a1d7-3243-4534-9a15-684db4fd1d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576907717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.1576907717
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.2812884626
Short name T995
Test name
Test status
Simulation time 163336698 ps
CPU time 4.24 seconds
Started Aug 11 06:45:52 PM PDT 24
Finished Aug 11 06:45:57 PM PDT 24
Peak memory 241908 kb
Host smart-ac22acbd-8e7f-45c1-a010-70ea58a6f3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812884626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2812884626
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.818416902
Short name T752
Test name
Test status
Simulation time 198899614 ps
CPU time 4.8 seconds
Started Aug 11 06:45:54 PM PDT 24
Finished Aug 11 06:45:59 PM PDT 24
Peak memory 248324 kb
Host smart-9281515a-4b48-4ede-bd72-9dc2509db317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=818416902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.818416902
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.3673626540
Short name T1106
Test name
Test status
Simulation time 293066731 ps
CPU time 4.67 seconds
Started Aug 11 06:46:00 PM PDT 24
Finished Aug 11 06:46:05 PM PDT 24
Peak memory 242104 kb
Host smart-d44a89c9-4d2c-4244-8661-584f77dadabe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673626540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.3673626540
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.2977032609
Short name T20
Test name
Test status
Simulation time 14840482197 ps
CPU time 183.21 seconds
Started Aug 11 06:46:00 PM PDT 24
Finished Aug 11 06:49:03 PM PDT 24
Peak memory 266092 kb
Host smart-5636452b-2606-494a-aebc-7c78754567eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977032609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2977032609
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.4146058215
Short name T904
Test name
Test status
Simulation time 328048096 ps
CPU time 7.38 seconds
Started Aug 11 06:45:49 PM PDT 24
Finished Aug 11 06:45:57 PM PDT 24
Peak memory 242324 kb
Host smart-d96781cb-efb9-4002-acd4-46e090b8ee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146058215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.4146058215
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.3089454934
Short name T122
Test name
Test status
Simulation time 5336640745 ps
CPU time 99.48 seconds
Started Aug 11 06:45:56 PM PDT 24
Finished Aug 11 06:47:35 PM PDT 24
Peak memory 246352 kb
Host smart-12406f7c-53a9-405b-a57b-2d6d8c17dbad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089454934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
3089454934
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.2560309559
Short name T17
Test name
Test status
Simulation time 351982545511 ps
CPU time 1078.79 seconds
Started Aug 11 06:45:56 PM PDT 24
Finished Aug 11 07:03:55 PM PDT 24
Peak memory 359056 kb
Host smart-3bd15df9-b14a-424a-81a8-28b1df62546d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560309559 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.2560309559
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.2874571170
Short name T1063
Test name
Test status
Simulation time 104707349 ps
CPU time 4.13 seconds
Started Aug 11 06:45:57 PM PDT 24
Finished Aug 11 06:46:01 PM PDT 24
Peak memory 242160 kb
Host smart-badd8633-36e0-4357-ac6b-41d9fead6beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874571170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.2874571170
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.32038319
Short name T584
Test name
Test status
Simulation time 185613651 ps
CPU time 1.58 seconds
Started Aug 11 06:47:49 PM PDT 24
Finished Aug 11 06:47:50 PM PDT 24
Peak memory 240516 kb
Host smart-532bd82b-80fa-4a24-b82a-bf3c2c46cc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32038319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.32038319
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.2194828365
Short name T1043
Test name
Test status
Simulation time 2824462451 ps
CPU time 18.55 seconds
Started Aug 11 06:47:45 PM PDT 24
Finished Aug 11 06:48:04 PM PDT 24
Peak memory 242004 kb
Host smart-406f06f1-7e5f-4f84-8c56-0a617f975ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194828365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.2194828365
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.1565732216
Short name T1040
Test name
Test status
Simulation time 1548467860 ps
CPU time 30.5 seconds
Started Aug 11 06:47:43 PM PDT 24
Finished Aug 11 06:48:13 PM PDT 24
Peak memory 242216 kb
Host smart-10b489da-86ac-452b-8b65-d7df9ee9b50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565732216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.1565732216
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.2723542186
Short name T753
Test name
Test status
Simulation time 355647577 ps
CPU time 3.84 seconds
Started Aug 11 06:47:45 PM PDT 24
Finished Aug 11 06:47:49 PM PDT 24
Peak memory 242192 kb
Host smart-ae30f5bd-6726-46a7-a0ff-419229df6c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723542186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2723542186
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.1012053184
Short name T767
Test name
Test status
Simulation time 135650807 ps
CPU time 4.11 seconds
Started Aug 11 06:47:44 PM PDT 24
Finished Aug 11 06:47:48 PM PDT 24
Peak memory 242172 kb
Host smart-3fa0abdc-3a3c-49ff-a7da-a063b3d399f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012053184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.1012053184
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.3838230162
Short name T571
Test name
Test status
Simulation time 1124281140 ps
CPU time 22.84 seconds
Started Aug 11 06:47:45 PM PDT 24
Finished Aug 11 06:48:08 PM PDT 24
Peak memory 242296 kb
Host smart-085aed29-7443-4652-a6e3-3879a322c642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838230162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.3838230162
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.1456136083
Short name T681
Test name
Test status
Simulation time 447362872 ps
CPU time 13.27 seconds
Started Aug 11 06:47:46 PM PDT 24
Finished Aug 11 06:47:59 PM PDT 24
Peak memory 241888 kb
Host smart-8e2ec4f8-6168-4ebf-a5ba-eb98b509f4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456136083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.1456136083
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.3416321242
Short name T637
Test name
Test status
Simulation time 2704148788 ps
CPU time 22.5 seconds
Started Aug 11 06:47:45 PM PDT 24
Finished Aug 11 06:48:08 PM PDT 24
Peak memory 241988 kb
Host smart-c18515fe-460a-4da6-9098-e7c99b0210ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3416321242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.3416321242
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.3531293409
Short name T1114
Test name
Test status
Simulation time 2299964771 ps
CPU time 6.52 seconds
Started Aug 11 06:47:47 PM PDT 24
Finished Aug 11 06:47:54 PM PDT 24
Peak memory 241972 kb
Host smart-07d68a68-a0f8-4d55-a3d8-fc505a1bd402
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531293409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.3531293409
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.1885229088
Short name T841
Test name
Test status
Simulation time 317767814 ps
CPU time 6.71 seconds
Started Aug 11 06:47:44 PM PDT 24
Finished Aug 11 06:47:51 PM PDT 24
Peak memory 242372 kb
Host smart-be1d498c-4987-4940-b6bd-4388a7b90917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885229088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.1885229088
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.587992562
Short name T1122
Test name
Test status
Simulation time 11506165450 ps
CPU time 180.06 seconds
Started Aug 11 06:47:49 PM PDT 24
Finished Aug 11 06:50:49 PM PDT 24
Peak memory 257856 kb
Host smart-c38772de-ea76-48eb-b6dc-195e64167945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587992562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.
587992562
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.3261349629
Short name T89
Test name
Test status
Simulation time 90452148593 ps
CPU time 897.88 seconds
Started Aug 11 06:47:51 PM PDT 24
Finished Aug 11 07:02:49 PM PDT 24
Peak memory 294040 kb
Host smart-9e5f153c-268f-40f6-93d9-268329f46375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261349629 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.3261349629
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.1973814127
Short name T967
Test name
Test status
Simulation time 1338157334 ps
CPU time 27.27 seconds
Started Aug 11 06:47:48 PM PDT 24
Finished Aug 11 06:48:16 PM PDT 24
Peak memory 242160 kb
Host smart-26cc0254-d15d-43ab-979a-906a318cc230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973814127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.1973814127
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.4033694363
Short name T170
Test name
Test status
Simulation time 136948805 ps
CPU time 4.1 seconds
Started Aug 11 06:50:54 PM PDT 24
Finished Aug 11 06:50:58 PM PDT 24
Peak memory 242008 kb
Host smart-8bbbf93a-e701-44a5-a11f-4d1f38bfa4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033694363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.4033694363
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.2670508877
Short name T210
Test name
Test status
Simulation time 272795431 ps
CPU time 4.26 seconds
Started Aug 11 06:50:52 PM PDT 24
Finished Aug 11 06:50:57 PM PDT 24
Peak memory 242080 kb
Host smart-35f6f7f2-177f-4b20-9058-e4856f2904df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670508877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.2670508877
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.3068587169
Short name T918
Test name
Test status
Simulation time 334830672 ps
CPU time 4.06 seconds
Started Aug 11 06:50:52 PM PDT 24
Finished Aug 11 06:50:56 PM PDT 24
Peak memory 241884 kb
Host smart-e3bec90e-b23d-41e1-ad1e-5950f7049fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068587169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.3068587169
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.4072290091
Short name T579
Test name
Test status
Simulation time 517526749 ps
CPU time 4.75 seconds
Started Aug 11 06:50:52 PM PDT 24
Finished Aug 11 06:50:57 PM PDT 24
Peak memory 242264 kb
Host smart-9b35a838-c468-4c38-bfc5-bba6470f2584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072290091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.4072290091
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.852961135
Short name T231
Test name
Test status
Simulation time 338408187 ps
CPU time 4.02 seconds
Started Aug 11 06:50:52 PM PDT 24
Finished Aug 11 06:50:57 PM PDT 24
Peak memory 242008 kb
Host smart-659bf210-43b3-4cba-94f2-73e8e59056e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852961135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.852961135
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.1572482414
Short name T183
Test name
Test status
Simulation time 2414303614 ps
CPU time 6.76 seconds
Started Aug 11 06:50:52 PM PDT 24
Finished Aug 11 06:50:59 PM PDT 24
Peak memory 242072 kb
Host smart-cdccdb49-674c-4845-be70-04f647b84176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572482414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.1572482414
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.1374534274
Short name T1069
Test name
Test status
Simulation time 541731807 ps
CPU time 3.68 seconds
Started Aug 11 06:50:59 PM PDT 24
Finished Aug 11 06:51:03 PM PDT 24
Peak memory 242164 kb
Host smart-891c6289-7ac8-4b16-b924-e3ffd5c1870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374534274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.1374534274
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.837735515
Short name T148
Test name
Test status
Simulation time 481957594 ps
CPU time 3.97 seconds
Started Aug 11 06:50:59 PM PDT 24
Finished Aug 11 06:51:03 PM PDT 24
Peak memory 242204 kb
Host smart-af54649a-7c37-4c21-8662-cb3f58701426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837735515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.837735515
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.2932465696
Short name T111
Test name
Test status
Simulation time 2469369930 ps
CPU time 5.61 seconds
Started Aug 11 06:51:03 PM PDT 24
Finished Aug 11 06:51:09 PM PDT 24
Peak memory 242036 kb
Host smart-2077e62b-04ac-422b-9438-b4d98ef325c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932465696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.2932465696
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.1513725830
Short name T485
Test name
Test status
Simulation time 171190735 ps
CPU time 2.86 seconds
Started Aug 11 06:50:58 PM PDT 24
Finished Aug 11 06:51:01 PM PDT 24
Peak memory 242412 kb
Host smart-a821953c-aa76-4f2c-9bf4-608923117e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513725830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.1513725830
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.1031538949
Short name T436
Test name
Test status
Simulation time 214870778 ps
CPU time 2.11 seconds
Started Aug 11 06:47:50 PM PDT 24
Finished Aug 11 06:47:52 PM PDT 24
Peak memory 240820 kb
Host smart-daee0a27-a89f-4d75-9399-0df00a570f6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031538949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.1031538949
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.2314663408
Short name T966
Test name
Test status
Simulation time 5339796348 ps
CPU time 23.25 seconds
Started Aug 11 06:47:50 PM PDT 24
Finished Aug 11 06:48:13 PM PDT 24
Peak memory 248604 kb
Host smart-81aa4230-ff44-43ec-96de-248e61351ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314663408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.2314663408
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.3873372581
Short name T735
Test name
Test status
Simulation time 9862391864 ps
CPU time 25.13 seconds
Started Aug 11 06:47:49 PM PDT 24
Finished Aug 11 06:48:14 PM PDT 24
Peak memory 242016 kb
Host smart-b861aa14-6129-4971-9e21-5ab329f73abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873372581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3873372581
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.1819938100
Short name T927
Test name
Test status
Simulation time 487552016 ps
CPU time 14.39 seconds
Started Aug 11 06:47:53 PM PDT 24
Finished Aug 11 06:48:08 PM PDT 24
Peak memory 242284 kb
Host smart-5d284154-0278-4993-8dc7-998706c561e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819938100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1819938100
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.1414782286
Short name T660
Test name
Test status
Simulation time 177426880 ps
CPU time 3.94 seconds
Started Aug 11 06:47:48 PM PDT 24
Finished Aug 11 06:47:52 PM PDT 24
Peak memory 242220 kb
Host smart-2bcdf445-a9cb-4f44-84d1-306967fd5c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414782286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.1414782286
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.2330264849
Short name T544
Test name
Test status
Simulation time 5565636451 ps
CPU time 38.32 seconds
Started Aug 11 06:47:48 PM PDT 24
Finished Aug 11 06:48:26 PM PDT 24
Peak memory 249840 kb
Host smart-b919a1a0-1664-4346-a7ac-b08c15f6a79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330264849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.2330264849
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.1939166894
Short name T588
Test name
Test status
Simulation time 823643483 ps
CPU time 17.23 seconds
Started Aug 11 06:47:52 PM PDT 24
Finished Aug 11 06:48:10 PM PDT 24
Peak memory 242124 kb
Host smart-10117f3e-32fe-43e9-a54e-e21b6ddd8565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939166894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.1939166894
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.1334425684
Short name T622
Test name
Test status
Simulation time 238618026 ps
CPU time 7.02 seconds
Started Aug 11 06:47:47 PM PDT 24
Finished Aug 11 06:47:55 PM PDT 24
Peak memory 241844 kb
Host smart-2825b517-0579-47db-a473-46b575c223d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334425684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.1334425684
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.993474143
Short name T1053
Test name
Test status
Simulation time 858817581 ps
CPU time 12.71 seconds
Started Aug 11 06:47:48 PM PDT 24
Finished Aug 11 06:48:01 PM PDT 24
Peak memory 242360 kb
Host smart-e987f21c-90d0-4301-8ca8-9aa68646823a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=993474143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.993474143
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.243759135
Short name T878
Test name
Test status
Simulation time 1906977069 ps
CPU time 4.93 seconds
Started Aug 11 06:47:51 PM PDT 24
Finished Aug 11 06:47:56 PM PDT 24
Peak memory 242324 kb
Host smart-6d857a6b-651a-4e3e-b8b0-588a784ec405
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=243759135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.243759135
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.3550293752
Short name T1014
Test name
Test status
Simulation time 386191618 ps
CPU time 2.95 seconds
Started Aug 11 06:47:50 PM PDT 24
Finished Aug 11 06:47:53 PM PDT 24
Peak memory 241832 kb
Host smart-f80ecfa2-cf4d-4c07-ae64-90f3ba8f6488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550293752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.3550293752
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.2024458113
Short name T1011
Test name
Test status
Simulation time 912954507 ps
CPU time 5.91 seconds
Started Aug 11 06:47:47 PM PDT 24
Finished Aug 11 06:47:53 PM PDT 24
Peak memory 241788 kb
Host smart-dba39ee9-6b42-4f04-a6c0-01242a159c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024458113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.2024458113
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.2054896843
Short name T340
Test name
Test status
Simulation time 358772717342 ps
CPU time 2372.08 seconds
Started Aug 11 06:47:52 PM PDT 24
Finished Aug 11 07:27:24 PM PDT 24
Peak memory 289748 kb
Host smart-8782d9f6-800e-45ee-80e4-9e7562006ef1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054896843 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.2054896843
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.3213603863
Short name T883
Test name
Test status
Simulation time 1339900698 ps
CPU time 11.42 seconds
Started Aug 11 06:47:49 PM PDT 24
Finished Aug 11 06:48:00 PM PDT 24
Peak memory 241932 kb
Host smart-3f287c43-19cf-4106-8766-e58dd603d9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213603863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.3213603863
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.1743389413
Short name T912
Test name
Test status
Simulation time 366999524 ps
CPU time 4.23 seconds
Started Aug 11 06:51:03 PM PDT 24
Finished Aug 11 06:51:07 PM PDT 24
Peak memory 242104 kb
Host smart-7b6d557d-dd3f-4a7b-bb10-f8b1490ef658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743389413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.1743389413
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.3437052113
Short name T820
Test name
Test status
Simulation time 230909061 ps
CPU time 4.43 seconds
Started Aug 11 06:51:00 PM PDT 24
Finished Aug 11 06:51:04 PM PDT 24
Peak memory 242204 kb
Host smart-bd04c63a-1cf0-48cb-956b-13d573703b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437052113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.3437052113
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.4263188763
Short name T241
Test name
Test status
Simulation time 175455273 ps
CPU time 3.14 seconds
Started Aug 11 06:51:03 PM PDT 24
Finished Aug 11 06:51:06 PM PDT 24
Peak memory 242248 kb
Host smart-13c46d36-e7b9-4482-be35-e77c3f79a846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263188763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.4263188763
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.2690142420
Short name T733
Test name
Test status
Simulation time 308624989 ps
CPU time 3.64 seconds
Started Aug 11 06:50:59 PM PDT 24
Finished Aug 11 06:51:03 PM PDT 24
Peak memory 242420 kb
Host smart-44dd24b8-82ae-488c-9fb3-6046b2923cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690142420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.2690142420
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.249203305
Short name T815
Test name
Test status
Simulation time 2396206977 ps
CPU time 6.01 seconds
Started Aug 11 06:50:58 PM PDT 24
Finished Aug 11 06:51:04 PM PDT 24
Peak memory 241988 kb
Host smart-c52018c5-1de0-4108-9ef8-a13f574e23f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249203305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.249203305
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.4203631265
Short name T1179
Test name
Test status
Simulation time 126708579 ps
CPU time 3.5 seconds
Started Aug 11 06:51:03 PM PDT 24
Finished Aug 11 06:51:07 PM PDT 24
Peak memory 242192 kb
Host smart-dcbeb9b2-98fe-4a20-9f43-b811fba9acde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203631265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.4203631265
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.3786255915
Short name T229
Test name
Test status
Simulation time 126076578 ps
CPU time 4.2 seconds
Started Aug 11 06:50:59 PM PDT 24
Finished Aug 11 06:51:04 PM PDT 24
Peak memory 242220 kb
Host smart-add025cc-4d22-4b0a-91c9-fd419d54e214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786255915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3786255915
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.2221563229
Short name T528
Test name
Test status
Simulation time 103425305 ps
CPU time 3.75 seconds
Started Aug 11 06:51:00 PM PDT 24
Finished Aug 11 06:51:04 PM PDT 24
Peak memory 242016 kb
Host smart-88c2d82e-f988-4364-afb4-3a5515a72800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221563229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2221563229
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.2399357183
Short name T460
Test name
Test status
Simulation time 92728314 ps
CPU time 1.76 seconds
Started Aug 11 06:47:58 PM PDT 24
Finished Aug 11 06:47:59 PM PDT 24
Peak memory 240520 kb
Host smart-609832c6-35d1-4e3a-8519-953ffc533188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399357183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.2399357183
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.1097835961
Short name T215
Test name
Test status
Simulation time 190075226 ps
CPU time 3.28 seconds
Started Aug 11 06:47:53 PM PDT 24
Finished Aug 11 06:47:57 PM PDT 24
Peak memory 241976 kb
Host smart-83506422-9aca-460f-a10d-186c3c80dca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097835961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.1097835961
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.755336736
Short name T930
Test name
Test status
Simulation time 3102712168 ps
CPU time 39.7 seconds
Started Aug 11 06:47:56 PM PDT 24
Finished Aug 11 06:48:35 PM PDT 24
Peak memory 249196 kb
Host smart-aa24bf8d-fa24-4fab-b400-58d03f27f829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755336736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.755336736
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.3121725225
Short name T933
Test name
Test status
Simulation time 4822339480 ps
CPU time 17.58 seconds
Started Aug 11 06:47:55 PM PDT 24
Finished Aug 11 06:48:13 PM PDT 24
Peak memory 242008 kb
Host smart-259d1abc-86f5-413d-afa5-55894c644f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121725225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.3121725225
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.3243225145
Short name T723
Test name
Test status
Simulation time 166458211 ps
CPU time 4.39 seconds
Started Aug 11 06:47:54 PM PDT 24
Finished Aug 11 06:47:59 PM PDT 24
Peak memory 242184 kb
Host smart-9669a65b-1e35-427c-b993-efc5071a4d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243225145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3243225145
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.2864875450
Short name T651
Test name
Test status
Simulation time 1009224515 ps
CPU time 19.69 seconds
Started Aug 11 06:47:54 PM PDT 24
Finished Aug 11 06:48:14 PM PDT 24
Peak memory 248556 kb
Host smart-117e4e3f-edbe-4dcf-a124-5b1f099d683a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864875450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2864875450
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.4072779061
Short name T606
Test name
Test status
Simulation time 1121938951 ps
CPU time 14.1 seconds
Started Aug 11 06:47:54 PM PDT 24
Finished Aug 11 06:48:08 PM PDT 24
Peak memory 242156 kb
Host smart-afcfbf20-b2ce-49c0-a02c-315591916eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072779061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.4072779061
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.146633480
Short name T311
Test name
Test status
Simulation time 256199932 ps
CPU time 5.36 seconds
Started Aug 11 06:47:54 PM PDT 24
Finished Aug 11 06:48:00 PM PDT 24
Peak memory 241756 kb
Host smart-c10e76eb-2c61-45f8-9e76-b2ba3428358f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146633480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.146633480
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.1664758644
Short name T1074
Test name
Test status
Simulation time 2761964029 ps
CPU time 24.34 seconds
Started Aug 11 06:47:55 PM PDT 24
Finished Aug 11 06:48:19 PM PDT 24
Peak memory 242056 kb
Host smart-98e82418-66d5-496e-8f0e-7a498484a1ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1664758644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.1664758644
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.1562423000
Short name T790
Test name
Test status
Simulation time 249235694 ps
CPU time 4.25 seconds
Started Aug 11 06:47:55 PM PDT 24
Finished Aug 11 06:48:00 PM PDT 24
Peak memory 241960 kb
Host smart-206bc2ab-8640-4a92-9461-a2ad1fd945ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1562423000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1562423000
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.3633775299
Short name T538
Test name
Test status
Simulation time 130998574 ps
CPU time 4.81 seconds
Started Aug 11 06:47:54 PM PDT 24
Finished Aug 11 06:47:59 PM PDT 24
Peak memory 242044 kb
Host smart-77f5aed9-6807-492c-97e4-dc0c496fd778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633775299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.3633775299
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.2843646220
Short name T909
Test name
Test status
Simulation time 33873154254 ps
CPU time 370.18 seconds
Started Aug 11 06:47:54 PM PDT 24
Finished Aug 11 06:54:05 PM PDT 24
Peak memory 248692 kb
Host smart-1898ce26-46af-4cd1-b1ab-db3817f9cb9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843646220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.2843646220
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.3291948205
Short name T962
Test name
Test status
Simulation time 279653104 ps
CPU time 4.55 seconds
Started Aug 11 06:47:55 PM PDT 24
Finished Aug 11 06:47:59 PM PDT 24
Peak memory 241928 kb
Host smart-c7bd7301-65b9-41c6-ab65-d0ef233f4689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291948205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.3291948205
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.2300123399
Short name T897
Test name
Test status
Simulation time 136344498 ps
CPU time 3.21 seconds
Started Aug 11 06:51:02 PM PDT 24
Finished Aug 11 06:51:06 PM PDT 24
Peak memory 242324 kb
Host smart-516bca57-f836-46c8-8c4a-84bfbcb67b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300123399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2300123399
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.3416980829
Short name T211
Test name
Test status
Simulation time 1598579247 ps
CPU time 5.81 seconds
Started Aug 11 06:51:00 PM PDT 24
Finished Aug 11 06:51:06 PM PDT 24
Peak memory 242132 kb
Host smart-d2874354-e797-45c0-9354-32ac5bf1cbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416980829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3416980829
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.248486997
Short name T516
Test name
Test status
Simulation time 217124590 ps
CPU time 4.91 seconds
Started Aug 11 06:51:00 PM PDT 24
Finished Aug 11 06:51:05 PM PDT 24
Peak memory 242064 kb
Host smart-0ce3e447-57b7-4bd5-9b05-59cf7020ca73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248486997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.248486997
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.305919253
Short name T1070
Test name
Test status
Simulation time 280863439 ps
CPU time 4.08 seconds
Started Aug 11 06:51:00 PM PDT 24
Finished Aug 11 06:51:04 PM PDT 24
Peak memory 242164 kb
Host smart-076cb982-2c97-46d1-b167-7687f58efeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305919253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.305919253
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.2784518413
Short name T917
Test name
Test status
Simulation time 1400106639 ps
CPU time 3.48 seconds
Started Aug 11 06:50:59 PM PDT 24
Finished Aug 11 06:51:02 PM PDT 24
Peak memory 241848 kb
Host smart-1fffbb3a-23dc-494e-8f4c-bd57e89caba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784518413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2784518413
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.1128524714
Short name T445
Test name
Test status
Simulation time 658235124 ps
CPU time 4.08 seconds
Started Aug 11 06:50:59 PM PDT 24
Finished Aug 11 06:51:03 PM PDT 24
Peak memory 242348 kb
Host smart-2df7a966-9904-4745-a067-d1624291626f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128524714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.1128524714
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.4153016523
Short name T47
Test name
Test status
Simulation time 126426332 ps
CPU time 4.87 seconds
Started Aug 11 06:50:58 PM PDT 24
Finished Aug 11 06:51:03 PM PDT 24
Peak memory 242000 kb
Host smart-10f47fa0-1d94-40c5-a20a-965d19c84b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153016523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.4153016523
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.2201712036
Short name T1169
Test name
Test status
Simulation time 91789624 ps
CPU time 3.32 seconds
Started Aug 11 06:51:01 PM PDT 24
Finished Aug 11 06:51:04 PM PDT 24
Peak memory 242068 kb
Host smart-fe9b4c59-7245-4030-81d2-43b4bfc8fdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201712036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.2201712036
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.3123722157
Short name T209
Test name
Test status
Simulation time 393372719 ps
CPU time 4.18 seconds
Started Aug 11 06:50:59 PM PDT 24
Finished Aug 11 06:51:04 PM PDT 24
Peak memory 242192 kb
Host smart-8a0ac9ff-f8d7-4463-a1f6-35ea8e82669f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123722157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.3123722157
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.3190521557
Short name T946
Test name
Test status
Simulation time 226672452 ps
CPU time 2.05 seconds
Started Aug 11 06:48:01 PM PDT 24
Finished Aug 11 06:48:03 PM PDT 24
Peak memory 240528 kb
Host smart-0e8b1e51-710d-454c-b9a3-8a936b5fec24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190521557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.3190521557
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.1881580084
Short name T858
Test name
Test status
Simulation time 450832081 ps
CPU time 4.84 seconds
Started Aug 11 06:47:59 PM PDT 24
Finished Aug 11 06:48:04 PM PDT 24
Peak memory 248560 kb
Host smart-f74fcf3c-75eb-44e8-80c6-52e6d636f990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881580084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.1881580084
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.1141964957
Short name T819
Test name
Test status
Simulation time 989083159 ps
CPU time 21.4 seconds
Started Aug 11 06:48:00 PM PDT 24
Finished Aug 11 06:48:21 PM PDT 24
Peak memory 242384 kb
Host smart-33031f4e-ccc4-41c8-9192-79837d690c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141964957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1141964957
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.3902292095
Short name T236
Test name
Test status
Simulation time 686336872 ps
CPU time 19.79 seconds
Started Aug 11 06:47:58 PM PDT 24
Finished Aug 11 06:48:18 PM PDT 24
Peak memory 242324 kb
Host smart-9cf91f75-158f-41ec-9e00-82bcf972e1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902292095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.3902292095
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.1294844256
Short name T171
Test name
Test status
Simulation time 3145373953 ps
CPU time 17.47 seconds
Started Aug 11 06:48:01 PM PDT 24
Finished Aug 11 06:48:19 PM PDT 24
Peak memory 242996 kb
Host smart-89a090b9-2479-4fb5-8821-f9e7ed1ac0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294844256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.1294844256
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.576338237
Short name T577
Test name
Test status
Simulation time 291763893 ps
CPU time 7.33 seconds
Started Aug 11 06:47:59 PM PDT 24
Finished Aug 11 06:48:06 PM PDT 24
Peak memory 242004 kb
Host smart-0df5ae7c-4901-413e-b641-e1ab8ad5afc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576338237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.576338237
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.1616658896
Short name T600
Test name
Test status
Simulation time 966540474 ps
CPU time 24.64 seconds
Started Aug 11 06:47:58 PM PDT 24
Finished Aug 11 06:48:23 PM PDT 24
Peak memory 242028 kb
Host smart-a5532a5c-a8ba-4c4e-80e6-0c0f02ff0330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616658896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.1616658896
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.2954208504
Short name T856
Test name
Test status
Simulation time 1822951444 ps
CPU time 16 seconds
Started Aug 11 06:48:01 PM PDT 24
Finished Aug 11 06:48:17 PM PDT 24
Peak memory 242340 kb
Host smart-8722ec4c-dd4a-43c8-9cfa-030b77c9d7a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2954208504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.2954208504
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.730343338
Short name T228
Test name
Test status
Simulation time 1221065598 ps
CPU time 12.42 seconds
Started Aug 11 06:47:59 PM PDT 24
Finished Aug 11 06:48:12 PM PDT 24
Peak memory 241952 kb
Host smart-ea4a6537-aeee-4782-8d15-ddd7d7fdb807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=730343338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.730343338
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.1433656247
Short name T413
Test name
Test status
Simulation time 247159090 ps
CPU time 7.96 seconds
Started Aug 11 06:47:56 PM PDT 24
Finished Aug 11 06:48:04 PM PDT 24
Peak memory 242124 kb
Host smart-54a48beb-0016-4031-bafc-0f3da448e203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433656247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.1433656247
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.3089492193
Short name T843
Test name
Test status
Simulation time 9943803247 ps
CPU time 68.21 seconds
Started Aug 11 06:48:02 PM PDT 24
Finished Aug 11 06:49:10 PM PDT 24
Peak memory 244396 kb
Host smart-3edd6634-229d-4cd5-9a25-ad49b343ad4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089492193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.3089492193
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.1494513006
Short name T5
Test name
Test status
Simulation time 1959891671 ps
CPU time 30.49 seconds
Started Aug 11 06:48:01 PM PDT 24
Finished Aug 11 06:48:32 PM PDT 24
Peak memory 242416 kb
Host smart-79ce17c5-f1cb-4935-baed-f1ecdea29e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494513006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.1494513006
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.2441663700
Short name T1140
Test name
Test status
Simulation time 139654666 ps
CPU time 3.52 seconds
Started Aug 11 06:51:04 PM PDT 24
Finished Aug 11 06:51:08 PM PDT 24
Peak memory 242276 kb
Host smart-65746488-8d1a-4e73-b5bd-152b220f77e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441663700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.2441663700
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.3162346436
Short name T1193
Test name
Test status
Simulation time 161272811 ps
CPU time 4.09 seconds
Started Aug 11 06:51:04 PM PDT 24
Finished Aug 11 06:51:08 PM PDT 24
Peak memory 242232 kb
Host smart-fe865427-493d-4f3a-b216-07a3a6ed277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162346436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3162346436
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.4146906559
Short name T422
Test name
Test status
Simulation time 476320337 ps
CPU time 4.43 seconds
Started Aug 11 06:51:04 PM PDT 24
Finished Aug 11 06:51:08 PM PDT 24
Peak memory 242468 kb
Host smart-3dd9ad25-578b-4529-8603-8520b99c9d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146906559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.4146906559
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.1147738090
Short name T905
Test name
Test status
Simulation time 128279889 ps
CPU time 3.6 seconds
Started Aug 11 06:51:02 PM PDT 24
Finished Aug 11 06:51:06 PM PDT 24
Peak memory 242352 kb
Host smart-212b8bb6-ad86-4067-ad86-0b356d2fe0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147738090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.1147738090
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.3208723894
Short name T1068
Test name
Test status
Simulation time 152364739 ps
CPU time 4.06 seconds
Started Aug 11 06:51:07 PM PDT 24
Finished Aug 11 06:51:11 PM PDT 24
Peak memory 242204 kb
Host smart-365fd722-87cd-42db-9b74-1e84c28cadf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208723894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3208723894
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.2120488500
Short name T975
Test name
Test status
Simulation time 211389820 ps
CPU time 3.73 seconds
Started Aug 11 06:51:04 PM PDT 24
Finished Aug 11 06:51:08 PM PDT 24
Peak memory 242188 kb
Host smart-a4366c90-17f6-4094-aa92-cb135f63374c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120488500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.2120488500
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.2219455288
Short name T86
Test name
Test status
Simulation time 280577519 ps
CPU time 4.7 seconds
Started Aug 11 06:51:07 PM PDT 24
Finished Aug 11 06:51:11 PM PDT 24
Peak memory 242064 kb
Host smart-94480305-90be-46fa-8810-2d36d0ebb0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219455288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2219455288
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.36126044
Short name T576
Test name
Test status
Simulation time 192793870 ps
CPU time 5.11 seconds
Started Aug 11 06:51:03 PM PDT 24
Finished Aug 11 06:51:08 PM PDT 24
Peak memory 242156 kb
Host smart-28952ad0-42e2-4e01-be71-401e65056994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36126044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.36126044
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.2505981958
Short name T1022
Test name
Test status
Simulation time 1835938999 ps
CPU time 5.62 seconds
Started Aug 11 06:51:03 PM PDT 24
Finished Aug 11 06:51:09 PM PDT 24
Peak memory 242040 kb
Host smart-d45110a6-2a39-4ae3-a0e1-729a13336c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505981958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.2505981958
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.4090783411
Short name T220
Test name
Test status
Simulation time 116763565 ps
CPU time 3.83 seconds
Started Aug 11 06:51:06 PM PDT 24
Finished Aug 11 06:51:10 PM PDT 24
Peak memory 241940 kb
Host smart-a7221db5-f6b5-47c8-9727-90db9674cebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090783411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.4090783411
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.3039529497
Short name T1144
Test name
Test status
Simulation time 48138529 ps
CPU time 1.6 seconds
Started Aug 11 06:48:07 PM PDT 24
Finished Aug 11 06:48:08 PM PDT 24
Peak memory 240600 kb
Host smart-2cf6b5c2-ca8d-4826-9c3e-9eeb7b9acb66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039529497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.3039529497
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.3422317993
Short name T245
Test name
Test status
Simulation time 1126233310 ps
CPU time 20.93 seconds
Started Aug 11 06:48:00 PM PDT 24
Finished Aug 11 06:48:21 PM PDT 24
Peak memory 248648 kb
Host smart-48f6aa0b-1898-4f7e-bae4-23dd5281a98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422317993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.3422317993
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.2557556353
Short name T754
Test name
Test status
Simulation time 910406485 ps
CPU time 24.66 seconds
Started Aug 11 06:48:04 PM PDT 24
Finished Aug 11 06:48:29 PM PDT 24
Peak memory 241908 kb
Host smart-6d9ece1b-bb50-4882-9a80-0dea7f72ba86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557556353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.2557556353
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.3411274075
Short name T312
Test name
Test status
Simulation time 2795760200 ps
CPU time 15.15 seconds
Started Aug 11 06:47:58 PM PDT 24
Finished Aug 11 06:48:14 PM PDT 24
Peak memory 248656 kb
Host smart-05570d06-3f46-421c-b71c-0614d8a06a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411274075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.3411274075
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.499239484
Short name T618
Test name
Test status
Simulation time 180956433 ps
CPU time 4.03 seconds
Started Aug 11 06:48:02 PM PDT 24
Finished Aug 11 06:48:06 PM PDT 24
Peak memory 242200 kb
Host smart-7e1f28ba-78f7-4fd7-a50a-0c3b9dd778fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499239484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.499239484
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.2166008122
Short name T208
Test name
Test status
Simulation time 1278946575 ps
CPU time 9.97 seconds
Started Aug 11 06:47:59 PM PDT 24
Finished Aug 11 06:48:09 PM PDT 24
Peak memory 242064 kb
Host smart-33504436-eeeb-4430-ba5e-c33c18a1682a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166008122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.2166008122
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.327929223
Short name T836
Test name
Test status
Simulation time 423086024 ps
CPU time 9.11 seconds
Started Aug 11 06:48:01 PM PDT 24
Finished Aug 11 06:48:10 PM PDT 24
Peak memory 242296 kb
Host smart-b130c1f4-03e3-4b9d-bf1e-80fb37566cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327929223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.327929223
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.977803558
Short name T1016
Test name
Test status
Simulation time 275913817 ps
CPU time 8.9 seconds
Started Aug 11 06:48:01 PM PDT 24
Finished Aug 11 06:48:10 PM PDT 24
Peak memory 241948 kb
Host smart-af1c5505-47b0-4d7f-ac51-5b2bedbcfa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977803558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.977803558
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.1981208946
Short name T440
Test name
Test status
Simulation time 1159454804 ps
CPU time 11.62 seconds
Started Aug 11 06:48:01 PM PDT 24
Finished Aug 11 06:48:13 PM PDT 24
Peak memory 242012 kb
Host smart-bf4f6358-0062-4320-a1bb-575fd65bc0d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1981208946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.1981208946
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.3475564986
Short name T226
Test name
Test status
Simulation time 469327161 ps
CPU time 5.73 seconds
Started Aug 11 06:48:06 PM PDT 24
Finished Aug 11 06:48:12 PM PDT 24
Peak memory 241912 kb
Host smart-b0faa479-0bff-431c-b7c3-8acb927a5a19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3475564986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.3475564986
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.3293363723
Short name T463
Test name
Test status
Simulation time 1005411805 ps
CPU time 6.29 seconds
Started Aug 11 06:47:58 PM PDT 24
Finished Aug 11 06:48:04 PM PDT 24
Peak memory 241948 kb
Host smart-ce836292-d0a9-4bc4-a9dd-20a491a5b48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293363723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.3293363723
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.2049062161
Short name T360
Test name
Test status
Simulation time 2418763563 ps
CPU time 69.97 seconds
Started Aug 11 06:48:08 PM PDT 24
Finished Aug 11 06:49:18 PM PDT 24
Peak memory 241636 kb
Host smart-10f2d046-6fab-4e49-b4ed-d0f7425d9ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049062161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.2049062161
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.2054451167
Short name T1102
Test name
Test status
Simulation time 10953630781 ps
CPU time 26.07 seconds
Started Aug 11 06:48:08 PM PDT 24
Finished Aug 11 06:48:34 PM PDT 24
Peak memory 242000 kb
Host smart-a104b4a4-c66e-442e-b2e1-e1e2861bfe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054451167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.2054451167
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.8175998
Short name T1117
Test name
Test status
Simulation time 282074925 ps
CPU time 3.86 seconds
Started Aug 11 06:51:05 PM PDT 24
Finished Aug 11 06:51:09 PM PDT 24
Peak memory 242456 kb
Host smart-1dd26abf-53b5-4a76-9645-3f47261fc465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8175998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.8175998
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.3001284196
Short name T74
Test name
Test status
Simulation time 211085789 ps
CPU time 4.11 seconds
Started Aug 11 06:51:06 PM PDT 24
Finished Aug 11 06:51:11 PM PDT 24
Peak memory 242304 kb
Host smart-f1bb0adc-bbf0-4b1c-bab4-8adacb2fa2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001284196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.3001284196
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.2450465441
Short name T223
Test name
Test status
Simulation time 576551993 ps
CPU time 4.39 seconds
Started Aug 11 06:51:04 PM PDT 24
Finished Aug 11 06:51:09 PM PDT 24
Peak memory 241924 kb
Host smart-b813b219-a6ab-4b37-a5d1-d0f6405e9ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450465441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.2450465441
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.3647115187
Short name T985
Test name
Test status
Simulation time 167694061 ps
CPU time 4.78 seconds
Started Aug 11 06:51:07 PM PDT 24
Finished Aug 11 06:51:12 PM PDT 24
Peak memory 241824 kb
Host smart-f419fbd9-7da0-4a2c-a033-9d6a4d8774a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647115187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.3647115187
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.667952721
Short name T490
Test name
Test status
Simulation time 157193581 ps
CPU time 4.64 seconds
Started Aug 11 06:51:03 PM PDT 24
Finished Aug 11 06:51:07 PM PDT 24
Peak memory 242184 kb
Host smart-97cc71d0-2b6a-4f1f-b6b7-b7512013de71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667952721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.667952721
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.3047818552
Short name T950
Test name
Test status
Simulation time 469004659 ps
CPU time 4.04 seconds
Started Aug 11 06:51:07 PM PDT 24
Finished Aug 11 06:51:11 PM PDT 24
Peak memory 242020 kb
Host smart-cfd71c4f-4d63-4873-aebc-33c24dabf82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047818552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.3047818552
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.1919276278
Short name T874
Test name
Test status
Simulation time 491394369 ps
CPU time 3.43 seconds
Started Aug 11 06:51:05 PM PDT 24
Finished Aug 11 06:51:09 PM PDT 24
Peak memory 242204 kb
Host smart-683bbd84-341a-4f5f-8c1f-ee6bda4157e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919276278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1919276278
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.1417313615
Short name T619
Test name
Test status
Simulation time 159332304 ps
CPU time 4.3 seconds
Started Aug 11 06:51:06 PM PDT 24
Finished Aug 11 06:51:10 PM PDT 24
Peak memory 242020 kb
Host smart-f74b2e03-cc9f-4122-aae8-8074b760abc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417313615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.1417313615
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.3095096117
Short name T1003
Test name
Test status
Simulation time 161559116 ps
CPU time 4.54 seconds
Started Aug 11 06:51:05 PM PDT 24
Finished Aug 11 06:51:10 PM PDT 24
Peak memory 242044 kb
Host smart-97792ed8-c935-41db-958d-b293f0a1259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095096117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3095096117
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.3597850884
Short name T454
Test name
Test status
Simulation time 260171251 ps
CPU time 3.13 seconds
Started Aug 11 06:48:13 PM PDT 24
Finished Aug 11 06:48:16 PM PDT 24
Peak memory 240832 kb
Host smart-0996240d-d7a2-4078-8d28-f9547f00c1b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597850884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.3597850884
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.2081500790
Short name T891
Test name
Test status
Simulation time 1705298255 ps
CPU time 23.71 seconds
Started Aug 11 06:48:07 PM PDT 24
Finished Aug 11 06:48:30 PM PDT 24
Peak memory 248540 kb
Host smart-e96978f0-e204-4b3a-b864-07bcdad26642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081500790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.2081500790
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.1376303789
Short name T1189
Test name
Test status
Simulation time 2444675280 ps
CPU time 20.19 seconds
Started Aug 11 06:48:08 PM PDT 24
Finished Aug 11 06:48:29 PM PDT 24
Peak memory 242488 kb
Host smart-374eca06-d17e-4686-a22d-0b3bc6a93063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376303789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.1376303789
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.3535253765
Short name T617
Test name
Test status
Simulation time 1075025462 ps
CPU time 17.39 seconds
Started Aug 11 06:48:06 PM PDT 24
Finished Aug 11 06:48:24 PM PDT 24
Peak memory 242180 kb
Host smart-0a68b9fa-7690-464c-ad61-a17468039f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535253765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.3535253765
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.1654307295
Short name T187
Test name
Test status
Simulation time 126592241 ps
CPU time 3.22 seconds
Started Aug 11 06:48:06 PM PDT 24
Finished Aug 11 06:48:10 PM PDT 24
Peak memory 242324 kb
Host smart-926679ce-4475-4fd6-9330-b7a762ba0250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654307295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1654307295
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.3185162117
Short name T863
Test name
Test status
Simulation time 867347265 ps
CPU time 5.12 seconds
Started Aug 11 06:48:05 PM PDT 24
Finished Aug 11 06:48:10 PM PDT 24
Peak memory 242260 kb
Host smart-e5bab8b7-e4ae-494b-afa2-5569040f9d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185162117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.3185162117
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.1760037860
Short name T488
Test name
Test status
Simulation time 1610175913 ps
CPU time 17.72 seconds
Started Aug 11 06:48:09 PM PDT 24
Finished Aug 11 06:48:27 PM PDT 24
Peak memory 248560 kb
Host smart-353fb126-4328-4f91-84da-7e2618d5458a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760037860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.1760037860
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.2855301842
Short name T614
Test name
Test status
Simulation time 356296883 ps
CPU time 9.46 seconds
Started Aug 11 06:48:06 PM PDT 24
Finished Aug 11 06:48:16 PM PDT 24
Peak memory 241984 kb
Host smart-574603dc-785d-41cd-bc10-6ba2e92953e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855301842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2855301842
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.555569382
Short name T936
Test name
Test status
Simulation time 9191491765 ps
CPU time 21.58 seconds
Started Aug 11 06:48:07 PM PDT 24
Finished Aug 11 06:48:29 PM PDT 24
Peak memory 242004 kb
Host smart-949af3d2-cd22-49b6-b863-b79d8c8d97f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=555569382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.555569382
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.3205444796
Short name T378
Test name
Test status
Simulation time 181761458 ps
CPU time 3.62 seconds
Started Aug 11 06:48:09 PM PDT 24
Finished Aug 11 06:48:13 PM PDT 24
Peak memory 241848 kb
Host smart-1c2da261-0ab5-48c2-8f68-208c283638c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205444796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.3205444796
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.4155122777
Short name T1009
Test name
Test status
Simulation time 518129233 ps
CPU time 5.19 seconds
Started Aug 11 06:48:07 PM PDT 24
Finished Aug 11 06:48:12 PM PDT 24
Peak memory 242312 kb
Host smart-d7ade395-8247-4876-aabe-a9981dcd623d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155122777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.4155122777
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.1628821448
Short name T1145
Test name
Test status
Simulation time 21320902184 ps
CPU time 166.33 seconds
Started Aug 11 06:48:11 PM PDT 24
Finished Aug 11 06:50:57 PM PDT 24
Peak memory 248688 kb
Host smart-3e01bbcf-0e3c-496e-a04b-3b4255eb57b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628821448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.1628821448
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.3211705738
Short name T994
Test name
Test status
Simulation time 221530933 ps
CPU time 3.85 seconds
Started Aug 11 06:48:14 PM PDT 24
Finished Aug 11 06:48:18 PM PDT 24
Peak memory 241916 kb
Host smart-222ac40b-f890-4c2e-b7fd-96c58cce6941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211705738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.3211705738
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.2841332066
Short name T616
Test name
Test status
Simulation time 450856874 ps
CPU time 3.41 seconds
Started Aug 11 06:51:04 PM PDT 24
Finished Aug 11 06:51:07 PM PDT 24
Peak memory 242080 kb
Host smart-286183ac-d169-414e-897f-220e9baf5ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841332066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.2841332066
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.2940398505
Short name T992
Test name
Test status
Simulation time 2208478178 ps
CPU time 5.66 seconds
Started Aug 11 06:51:03 PM PDT 24
Finished Aug 11 06:51:09 PM PDT 24
Peak memory 242076 kb
Host smart-9e77180a-b30b-45b8-88ae-23103b603799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940398505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.2940398505
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.1523052624
Short name T1167
Test name
Test status
Simulation time 91456248 ps
CPU time 3.05 seconds
Started Aug 11 06:51:05 PM PDT 24
Finished Aug 11 06:51:08 PM PDT 24
Peak memory 242152 kb
Host smart-c8e77fe6-d610-4302-82c0-b61b3a0705ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523052624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.1523052624
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.934664094
Short name T1021
Test name
Test status
Simulation time 545303729 ps
CPU time 3.9 seconds
Started Aug 11 06:51:02 PM PDT 24
Finished Aug 11 06:51:06 PM PDT 24
Peak memory 241900 kb
Host smart-c4248dc6-6926-4194-8524-a826f0c49e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934664094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.934664094
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.3050609335
Short name T412
Test name
Test status
Simulation time 609629103 ps
CPU time 4.63 seconds
Started Aug 11 06:51:07 PM PDT 24
Finished Aug 11 06:51:12 PM PDT 24
Peak memory 242312 kb
Host smart-743d405c-ae01-42f8-9fd3-1b6e981d890b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050609335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.3050609335
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.2575737159
Short name T885
Test name
Test status
Simulation time 173498083 ps
CPU time 4.73 seconds
Started Aug 11 06:51:07 PM PDT 24
Finished Aug 11 06:51:12 PM PDT 24
Peak memory 242192 kb
Host smart-99a6c2ce-123f-43c6-a121-f41d8628171c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575737159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.2575737159
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.2397444321
Short name T256
Test name
Test status
Simulation time 217108916 ps
CPU time 3.63 seconds
Started Aug 11 06:51:05 PM PDT 24
Finished Aug 11 06:51:08 PM PDT 24
Peak memory 242384 kb
Host smart-40f91fed-7d65-485d-a936-dee7d0089c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397444321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.2397444321
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.2214535349
Short name T786
Test name
Test status
Simulation time 120401859 ps
CPU time 4.27 seconds
Started Aug 11 06:51:05 PM PDT 24
Finished Aug 11 06:51:10 PM PDT 24
Peak memory 242036 kb
Host smart-f507ed02-4f29-409e-b116-5ce977ab9a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214535349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2214535349
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.1314294476
Short name T214
Test name
Test status
Simulation time 140472942 ps
CPU time 3.92 seconds
Started Aug 11 06:51:04 PM PDT 24
Finished Aug 11 06:51:08 PM PDT 24
Peak memory 242284 kb
Host smart-6ef50e76-aaec-4728-a65e-8d4d66a8df35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314294476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.1314294476
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.2489879007
Short name T188
Test name
Test status
Simulation time 1777621485 ps
CPU time 3.6 seconds
Started Aug 11 06:51:07 PM PDT 24
Finished Aug 11 06:51:10 PM PDT 24
Peak memory 242016 kb
Host smart-687c8669-166e-491b-ad6d-0bb539a16f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489879007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2489879007
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.1689029119
Short name T1085
Test name
Test status
Simulation time 152988022 ps
CPU time 1.75 seconds
Started Aug 11 06:48:12 PM PDT 24
Finished Aug 11 06:48:14 PM PDT 24
Peak memory 240424 kb
Host smart-5b903afd-0c54-4b24-9eae-58a2c850575c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689029119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.1689029119
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.473728175
Short name T766
Test name
Test status
Simulation time 868534810 ps
CPU time 16.35 seconds
Started Aug 11 06:48:13 PM PDT 24
Finished Aug 11 06:48:29 PM PDT 24
Peak memory 242012 kb
Host smart-43c533a0-31dd-49ba-8ea9-bda627a72da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473728175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.473728175
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.1166684233
Short name T626
Test name
Test status
Simulation time 743932735 ps
CPU time 20.35 seconds
Started Aug 11 06:48:11 PM PDT 24
Finished Aug 11 06:48:32 PM PDT 24
Peak memory 242428 kb
Host smart-ca968c7d-00ca-4ea4-b293-35baa46f7a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166684233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.1166684233
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.4103321573
Short name T1091
Test name
Test status
Simulation time 545103990 ps
CPU time 16.24 seconds
Started Aug 11 06:48:13 PM PDT 24
Finished Aug 11 06:48:30 PM PDT 24
Peak memory 248700 kb
Host smart-708ea47a-a9cb-47e5-9751-ea7e557307fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103321573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.4103321573
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.1990903278
Short name T648
Test name
Test status
Simulation time 138287813 ps
CPU time 3.89 seconds
Started Aug 11 06:48:14 PM PDT 24
Finished Aug 11 06:48:18 PM PDT 24
Peak memory 242220 kb
Host smart-a8b36c63-fceb-4372-abb7-cf46ec7ba695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990903278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.1990903278
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.2538072337
Short name T699
Test name
Test status
Simulation time 22095797985 ps
CPU time 40.57 seconds
Started Aug 11 06:48:11 PM PDT 24
Finished Aug 11 06:48:52 PM PDT 24
Peak memory 256904 kb
Host smart-6b6fa43d-44f4-4f0a-81d5-921edb97978d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538072337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.2538072337
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.3020256210
Short name T217
Test name
Test status
Simulation time 355745859 ps
CPU time 6.4 seconds
Started Aug 11 06:48:12 PM PDT 24
Finished Aug 11 06:48:19 PM PDT 24
Peak memory 242124 kb
Host smart-85e6ceb4-782b-4014-a9ff-d034fdd2f113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020256210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.3020256210
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.2252027878
Short name T1174
Test name
Test status
Simulation time 3546924055 ps
CPU time 28.02 seconds
Started Aug 11 06:48:14 PM PDT 24
Finished Aug 11 06:48:42 PM PDT 24
Peak memory 241944 kb
Host smart-0396b444-e3ce-4160-9db1-d0a805e05480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252027878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.2252027878
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.720434388
Short name T989
Test name
Test status
Simulation time 466522720 ps
CPU time 4.83 seconds
Started Aug 11 06:48:11 PM PDT 24
Finished Aug 11 06:48:16 PM PDT 24
Peak memory 247656 kb
Host smart-7a0aef94-ea34-45ec-b5cc-9b9bacaa47d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=720434388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.720434388
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.257093779
Short name T100
Test name
Test status
Simulation time 220161879 ps
CPU time 3.84 seconds
Started Aug 11 06:48:11 PM PDT 24
Finished Aug 11 06:48:15 PM PDT 24
Peak memory 241948 kb
Host smart-44835ec8-a537-429c-a742-49b4fb3582bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257093779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.257093779
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.2483001924
Short name T634
Test name
Test status
Simulation time 5942515448 ps
CPU time 16.74 seconds
Started Aug 11 06:48:13 PM PDT 24
Finished Aug 11 06:48:29 PM PDT 24
Peak memory 241952 kb
Host smart-2ba3d9d7-93e4-4003-a81a-edcc81e3f803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483001924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.2483001924
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.1481294257
Short name T336
Test name
Test status
Simulation time 530252327926 ps
CPU time 1537.58 seconds
Started Aug 11 06:48:11 PM PDT 24
Finished Aug 11 07:13:49 PM PDT 24
Peak memory 451720 kb
Host smart-9fa95260-022d-4351-8b6a-70dda7bb9bec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481294257 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.1481294257
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.1944262045
Short name T96
Test name
Test status
Simulation time 1201518302 ps
CPU time 14.77 seconds
Started Aug 11 06:48:13 PM PDT 24
Finished Aug 11 06:48:28 PM PDT 24
Peak memory 242424 kb
Host smart-a62c8bba-a73d-41a0-8810-1fbdea6fa5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944262045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.1944262045
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.1281548399
Short name T721
Test name
Test status
Simulation time 196142303 ps
CPU time 5.05 seconds
Started Aug 11 06:51:03 PM PDT 24
Finished Aug 11 06:51:08 PM PDT 24
Peak memory 242148 kb
Host smart-3a22ca46-c1ad-4cf5-a9c9-8ff7489eb3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281548399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.1281548399
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.2155690745
Short name T1142
Test name
Test status
Simulation time 131721756 ps
CPU time 3.53 seconds
Started Aug 11 06:51:06 PM PDT 24
Finished Aug 11 06:51:09 PM PDT 24
Peak memory 241960 kb
Host smart-95fa7f2e-7eff-4c32-a207-38880a81128c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155690745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.2155690745
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.4121337844
Short name T1110
Test name
Test status
Simulation time 592941765 ps
CPU time 4.5 seconds
Started Aug 11 06:51:06 PM PDT 24
Finished Aug 11 06:51:10 PM PDT 24
Peak memory 241924 kb
Host smart-497d5461-e8c8-4528-8c92-9a4090650e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121337844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.4121337844
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.319322387
Short name T575
Test name
Test status
Simulation time 95470002 ps
CPU time 3.69 seconds
Started Aug 11 06:51:07 PM PDT 24
Finished Aug 11 06:51:11 PM PDT 24
Peak memory 242092 kb
Host smart-249e1205-16bc-40d5-aad6-cc3c3113916d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319322387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.319322387
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.2183868224
Short name T592
Test name
Test status
Simulation time 1426918552 ps
CPU time 5.51 seconds
Started Aug 11 06:51:04 PM PDT 24
Finished Aug 11 06:51:09 PM PDT 24
Peak memory 241996 kb
Host smart-ee65482f-2907-4b96-a1f0-a841bdf59071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183868224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2183868224
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.312980419
Short name T453
Test name
Test status
Simulation time 529066690 ps
CPU time 4.1 seconds
Started Aug 11 06:51:09 PM PDT 24
Finished Aug 11 06:51:14 PM PDT 24
Peak memory 242416 kb
Host smart-f1874b66-9142-4cfd-b34d-f2fa3b3b4d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312980419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.312980419
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.2311976538
Short name T1116
Test name
Test status
Simulation time 341842792 ps
CPU time 3.34 seconds
Started Aug 11 06:51:13 PM PDT 24
Finished Aug 11 06:51:16 PM PDT 24
Peak memory 242180 kb
Host smart-f165462f-e885-4917-9f45-5f98f8911777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311976538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.2311976538
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.2980867880
Short name T61
Test name
Test status
Simulation time 110488067 ps
CPU time 4.26 seconds
Started Aug 11 06:51:12 PM PDT 24
Finished Aug 11 06:51:17 PM PDT 24
Peak memory 242280 kb
Host smart-711ae9a7-8419-469e-85e4-b3a0e7eb2fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980867880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.2980867880
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.159672787
Short name T301
Test name
Test status
Simulation time 592908545 ps
CPU time 4.09 seconds
Started Aug 11 06:51:11 PM PDT 24
Finished Aug 11 06:51:15 PM PDT 24
Peak memory 242384 kb
Host smart-22034bd6-5f80-4114-816b-7b827c8563a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159672787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.159672787
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.858714853
Short name T1152
Test name
Test status
Simulation time 186580165 ps
CPU time 3.37 seconds
Started Aug 11 06:51:11 PM PDT 24
Finished Aug 11 06:51:15 PM PDT 24
Peak memory 242272 kb
Host smart-a3c05ba8-0e5c-4224-a99c-7523af79111c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858714853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.858714853
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.4292618536
Short name T837
Test name
Test status
Simulation time 54743224 ps
CPU time 1.75 seconds
Started Aug 11 06:48:20 PM PDT 24
Finished Aug 11 06:48:22 PM PDT 24
Peak memory 240492 kb
Host smart-58c2a9da-1e6b-456d-95df-e84635e0ad28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292618536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.4292618536
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.3473892957
Short name T529
Test name
Test status
Simulation time 5157744888 ps
CPU time 26.25 seconds
Started Aug 11 06:48:17 PM PDT 24
Finished Aug 11 06:48:44 PM PDT 24
Peak memory 242160 kb
Host smart-6838a0dd-971c-4442-9dab-6cf395b13f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473892957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.3473892957
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.2774725956
Short name T13
Test name
Test status
Simulation time 219489168 ps
CPU time 5.62 seconds
Started Aug 11 06:48:18 PM PDT 24
Finished Aug 11 06:48:23 PM PDT 24
Peak memory 241992 kb
Host smart-d809b4aa-b528-4953-9f22-fe160bf67426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774725956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.2774725956
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.3346936768
Short name T1124
Test name
Test status
Simulation time 241527982 ps
CPU time 3.96 seconds
Started Aug 11 06:48:16 PM PDT 24
Finished Aug 11 06:48:21 PM PDT 24
Peak memory 242164 kb
Host smart-9d44540f-0cf7-4216-982e-2f9b35e780f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346936768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3346936768
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.1895974859
Short name T153
Test name
Test status
Simulation time 883136609 ps
CPU time 12.38 seconds
Started Aug 11 06:48:18 PM PDT 24
Finished Aug 11 06:48:31 PM PDT 24
Peak memory 242072 kb
Host smart-30401688-0a44-4bdf-82e8-083bf4aa3195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895974859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.1895974859
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.4105378372
Short name T202
Test name
Test status
Simulation time 3385633236 ps
CPU time 22.96 seconds
Started Aug 11 06:48:18 PM PDT 24
Finished Aug 11 06:48:41 PM PDT 24
Peak memory 248680 kb
Host smart-08e460ee-473e-4008-8cb6-6578441fe61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105378372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.4105378372
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.1978839954
Short name T633
Test name
Test status
Simulation time 173727349 ps
CPU time 4.62 seconds
Started Aug 11 06:48:18 PM PDT 24
Finished Aug 11 06:48:23 PM PDT 24
Peak memory 241920 kb
Host smart-6eb0c169-d3b5-47bd-aba6-8f212a2af974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978839954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.1978839954
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.2135593370
Short name T649
Test name
Test status
Simulation time 473856601 ps
CPU time 13.82 seconds
Started Aug 11 06:48:17 PM PDT 24
Finished Aug 11 06:48:31 PM PDT 24
Peak memory 242356 kb
Host smart-94526426-054d-43c1-af78-c54c22436ad5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2135593370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2135593370
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.3902106366
Short name T935
Test name
Test status
Simulation time 454450605 ps
CPU time 8.42 seconds
Started Aug 11 06:48:19 PM PDT 24
Finished Aug 11 06:48:28 PM PDT 24
Peak memory 241856 kb
Host smart-68bc7e74-89c4-4aef-aa72-798e53752957
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3902106366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.3902106366
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.161732136
Short name T922
Test name
Test status
Simulation time 289786952 ps
CPU time 6.32 seconds
Started Aug 11 06:48:13 PM PDT 24
Finished Aug 11 06:48:20 PM PDT 24
Peak memory 242332 kb
Host smart-cc04eb3e-5df2-4f50-9c8b-917dd66e197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161732136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.161732136
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.887167901
Short name T1164
Test name
Test status
Simulation time 385660139624 ps
CPU time 951.36 seconds
Started Aug 11 06:48:28 PM PDT 24
Finished Aug 11 07:04:19 PM PDT 24
Peak memory 379176 kb
Host smart-bc6a5555-e46e-41c9-b184-9132d0bdc27d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887167901 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.887167901
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.1715989529
Short name T737
Test name
Test status
Simulation time 2611829253 ps
CPU time 15.47 seconds
Started Aug 11 06:48:18 PM PDT 24
Finished Aug 11 06:48:33 PM PDT 24
Peak memory 242160 kb
Host smart-7a865fe3-301e-4211-863c-c3bee8ca2639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715989529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.1715989529
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.2427906028
Short name T834
Test name
Test status
Simulation time 2513735732 ps
CPU time 6.03 seconds
Started Aug 11 06:51:12 PM PDT 24
Finished Aug 11 06:51:18 PM PDT 24
Peak memory 242176 kb
Host smart-06abcbb5-06db-4e69-bf0c-e378af107306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427906028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2427906028
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.2238076986
Short name T666
Test name
Test status
Simulation time 170843764 ps
CPU time 3.68 seconds
Started Aug 11 06:51:12 PM PDT 24
Finished Aug 11 06:51:16 PM PDT 24
Peak memory 242268 kb
Host smart-b846adaa-249a-4d5c-b83a-d2ad94f1ab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238076986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.2238076986
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.4120021611
Short name T1044
Test name
Test status
Simulation time 385562652 ps
CPU time 3.78 seconds
Started Aug 11 06:51:10 PM PDT 24
Finished Aug 11 06:51:14 PM PDT 24
Peak memory 242484 kb
Host smart-31551dab-344c-43c0-9592-95c2c9179575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120021611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.4120021611
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.1893775325
Short name T942
Test name
Test status
Simulation time 210667650 ps
CPU time 3.4 seconds
Started Aug 11 06:51:13 PM PDT 24
Finished Aug 11 06:51:16 PM PDT 24
Peak memory 242172 kb
Host smart-a6d364b8-055f-4340-9237-a15371195697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893775325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.1893775325
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.1599779914
Short name T1049
Test name
Test status
Simulation time 3172401096 ps
CPU time 4.97 seconds
Started Aug 11 06:51:11 PM PDT 24
Finished Aug 11 06:51:16 PM PDT 24
Peak memory 241976 kb
Host smart-ec90ab8a-7b24-4994-af05-fbf749167941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599779914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.1599779914
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.4119290468
Short name T655
Test name
Test status
Simulation time 112358140 ps
CPU time 4.31 seconds
Started Aug 11 06:51:11 PM PDT 24
Finished Aug 11 06:51:15 PM PDT 24
Peak memory 242112 kb
Host smart-4a37f516-db2e-466a-9a2f-0d4313adf44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119290468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.4119290468
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.3188935806
Short name T1173
Test name
Test status
Simulation time 668460744 ps
CPU time 4.71 seconds
Started Aug 11 06:51:14 PM PDT 24
Finished Aug 11 06:51:19 PM PDT 24
Peak memory 241984 kb
Host smart-b81fef49-86ac-4378-8059-dbe32c532ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188935806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3188935806
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.3180234886
Short name T1075
Test name
Test status
Simulation time 120969511 ps
CPU time 2.93 seconds
Started Aug 11 06:51:12 PM PDT 24
Finished Aug 11 06:51:15 PM PDT 24
Peak memory 242440 kb
Host smart-a3df0abb-41de-4eb7-b7d3-762dee255b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180234886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.3180234886
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.3719518305
Short name T726
Test name
Test status
Simulation time 2906597169 ps
CPU time 4.55 seconds
Started Aug 11 06:51:11 PM PDT 24
Finished Aug 11 06:51:16 PM PDT 24
Peak memory 242312 kb
Host smart-6fc3f673-362a-4f3a-ae8f-3bf63349b399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719518305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3719518305
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.1399702483
Short name T169
Test name
Test status
Simulation time 107681720 ps
CPU time 3.09 seconds
Started Aug 11 06:51:10 PM PDT 24
Finished Aug 11 06:51:13 PM PDT 24
Peak memory 242380 kb
Host smart-8621a16f-6922-4a06-b675-07ca84f6a172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399702483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.1399702483
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.2217151790
Short name T568
Test name
Test status
Simulation time 988339667 ps
CPU time 3.04 seconds
Started Aug 11 06:48:25 PM PDT 24
Finished Aug 11 06:48:28 PM PDT 24
Peak memory 240536 kb
Host smart-4c140921-f53b-4a59-831d-5d8a957bf14c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217151790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.2217151790
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.1043800502
Short name T925
Test name
Test status
Simulation time 2790524787 ps
CPU time 27.2 seconds
Started Aug 11 06:48:28 PM PDT 24
Finished Aug 11 06:48:55 PM PDT 24
Peak memory 242180 kb
Host smart-cc117ddf-28ba-4480-aad1-2ed5241abe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043800502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.1043800502
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.3281540965
Short name T157
Test name
Test status
Simulation time 4652081429 ps
CPU time 25.7 seconds
Started Aug 11 06:48:18 PM PDT 24
Finished Aug 11 06:48:44 PM PDT 24
Peak memory 242432 kb
Host smart-da2b1daa-745b-41eb-b037-ed91c3719b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281540965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.3281540965
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.3870884780
Short name T928
Test name
Test status
Simulation time 2197336017 ps
CPU time 6.65 seconds
Started Aug 11 06:48:20 PM PDT 24
Finished Aug 11 06:48:26 PM PDT 24
Peak memory 242560 kb
Host smart-b08e52af-31fa-43af-880b-13f9084714bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870884780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.3870884780
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.1597619318
Short name T77
Test name
Test status
Simulation time 130843326 ps
CPU time 3.78 seconds
Started Aug 11 06:48:20 PM PDT 24
Finished Aug 11 06:48:24 PM PDT 24
Peak memory 241976 kb
Host smart-c3cfa571-ce85-4ae2-ba65-d1619221053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597619318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.1597619318
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.1982632376
Short name T1127
Test name
Test status
Simulation time 3448237618 ps
CPU time 8.43 seconds
Started Aug 11 06:48:18 PM PDT 24
Finished Aug 11 06:48:26 PM PDT 24
Peak memory 242096 kb
Host smart-40a57a42-f3aa-4cca-97dc-a5b3dff3a7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982632376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.1982632376
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.3222150615
Short name T201
Test name
Test status
Simulation time 641783931 ps
CPU time 15.03 seconds
Started Aug 11 06:48:18 PM PDT 24
Finished Aug 11 06:48:33 PM PDT 24
Peak memory 242068 kb
Host smart-c0394811-d6bf-4682-9e4d-0d50ab98dbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222150615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.3222150615
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.776259640
Short name T553
Test name
Test status
Simulation time 397325570 ps
CPU time 5.75 seconds
Started Aug 11 06:48:27 PM PDT 24
Finished Aug 11 06:48:33 PM PDT 24
Peak memory 241956 kb
Host smart-6b1970c0-2720-4aff-af78-1dd18a778d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776259640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.776259640
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.2407990820
Short name T224
Test name
Test status
Simulation time 1475542182 ps
CPU time 20.13 seconds
Started Aug 11 06:48:20 PM PDT 24
Finished Aug 11 06:48:40 PM PDT 24
Peak memory 242104 kb
Host smart-90e16ea4-b3a5-4044-bd8e-5569c5de62b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407990820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.2407990820
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.3528631949
Short name T1192
Test name
Test status
Simulation time 140601218 ps
CPU time 5.47 seconds
Started Aug 11 06:48:29 PM PDT 24
Finished Aug 11 06:48:34 PM PDT 24
Peak memory 242208 kb
Host smart-d132962d-df34-4b0d-8266-3178c736eb0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528631949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.3528631949
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.1192226780
Short name T268
Test name
Test status
Simulation time 589063074 ps
CPU time 9.4 seconds
Started Aug 11 06:48:28 PM PDT 24
Finished Aug 11 06:48:37 PM PDT 24
Peak memory 241976 kb
Host smart-a4b8d2d3-7ab3-4e1a-8291-72aec1e4e4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192226780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1192226780
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.2176246792
Short name T97
Test name
Test status
Simulation time 6696252777 ps
CPU time 38.39 seconds
Started Aug 11 06:48:25 PM PDT 24
Finished Aug 11 06:49:03 PM PDT 24
Peak memory 243296 kb
Host smart-964b3581-510e-4d59-9de4-890e25a461be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176246792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.2176246792
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.4120195339
Short name T397
Test name
Test status
Simulation time 2524014228 ps
CPU time 21.3 seconds
Started Aug 11 06:48:29 PM PDT 24
Finished Aug 11 06:48:51 PM PDT 24
Peak memory 242088 kb
Host smart-dfe2b8d9-4a67-48c4-98fa-656bfcfe0ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120195339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.4120195339
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.3887343080
Short name T495
Test name
Test status
Simulation time 300118690 ps
CPU time 5.35 seconds
Started Aug 11 06:51:08 PM PDT 24
Finished Aug 11 06:51:14 PM PDT 24
Peak memory 242280 kb
Host smart-ce392b6a-9044-4f3f-a353-28efb240a937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887343080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3887343080
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.2858982259
Short name T25
Test name
Test status
Simulation time 132959691 ps
CPU time 3.67 seconds
Started Aug 11 06:51:11 PM PDT 24
Finished Aug 11 06:51:15 PM PDT 24
Peak memory 242096 kb
Host smart-76448973-ea3c-44f3-8612-ec60e696eb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858982259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.2858982259
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.1940192242
Short name T449
Test name
Test status
Simulation time 542354947 ps
CPU time 4.21 seconds
Started Aug 11 06:51:10 PM PDT 24
Finished Aug 11 06:51:14 PM PDT 24
Peak memory 242128 kb
Host smart-e54b9c67-d857-41be-bb92-e65c17c71031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940192242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.1940192242
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.3613692893
Short name T561
Test name
Test status
Simulation time 194813925 ps
CPU time 2.89 seconds
Started Aug 11 06:51:12 PM PDT 24
Finished Aug 11 06:51:15 PM PDT 24
Peak memory 242164 kb
Host smart-ae3bf724-66d5-4fbd-9ffb-d4f4e66dfb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613692893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.3613692893
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.1064843698
Short name T62
Test name
Test status
Simulation time 150288108 ps
CPU time 3.99 seconds
Started Aug 11 06:51:11 PM PDT 24
Finished Aug 11 06:51:15 PM PDT 24
Peak memory 242128 kb
Host smart-5c78398e-eb90-4050-a020-8ba54f58fa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064843698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.1064843698
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.3064756990
Short name T164
Test name
Test status
Simulation time 391779889 ps
CPU time 3.51 seconds
Started Aug 11 06:51:12 PM PDT 24
Finished Aug 11 06:51:15 PM PDT 24
Peak memory 242396 kb
Host smart-0fa27327-1ffa-4785-b290-4dd3c2bad080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064756990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.3064756990
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.2442411876
Short name T732
Test name
Test status
Simulation time 546332318 ps
CPU time 3.82 seconds
Started Aug 11 06:51:15 PM PDT 24
Finished Aug 11 06:51:19 PM PDT 24
Peak memory 242064 kb
Host smart-04974195-bfd4-4f81-8e71-f0b3d7a15c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442411876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.2442411876
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.1900998477
Short name T814
Test name
Test status
Simulation time 298526758 ps
CPU time 3.65 seconds
Started Aug 11 06:51:16 PM PDT 24
Finished Aug 11 06:51:20 PM PDT 24
Peak memory 242144 kb
Host smart-df6675cb-8c03-4087-9649-fecf030867fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900998477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.1900998477
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.1882431759
Short name T908
Test name
Test status
Simulation time 114900750 ps
CPU time 1.75 seconds
Started Aug 11 06:48:26 PM PDT 24
Finished Aug 11 06:48:27 PM PDT 24
Peak memory 240804 kb
Host smart-443fa923-6af0-404a-a184-35ee65cca761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882431759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.1882431759
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.3391451641
Short name T683
Test name
Test status
Simulation time 796319125 ps
CPU time 10.94 seconds
Started Aug 11 06:48:23 PM PDT 24
Finished Aug 11 06:48:34 PM PDT 24
Peak memory 242356 kb
Host smart-8ee1b895-6552-4499-94a1-6793d8012634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391451641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3391451641
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.2323906093
Short name T1143
Test name
Test status
Simulation time 9601506562 ps
CPU time 42.83 seconds
Started Aug 11 06:48:24 PM PDT 24
Finished Aug 11 06:49:07 PM PDT 24
Peak memory 243476 kb
Host smart-0d6fecde-2bd2-43e0-880b-d61c9b0ebea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323906093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.2323906093
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.526922282
Short name T432
Test name
Test status
Simulation time 118136493 ps
CPU time 4.59 seconds
Started Aug 11 06:48:29 PM PDT 24
Finished Aug 11 06:48:34 PM PDT 24
Peak memory 242016 kb
Host smart-9b5339ef-dbb3-4715-bae5-6d0b5caa1dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526922282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.526922282
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.1354937851
Short name T1118
Test name
Test status
Simulation time 3514450326 ps
CPU time 35.31 seconds
Started Aug 11 06:48:24 PM PDT 24
Finished Aug 11 06:49:00 PM PDT 24
Peak memory 256812 kb
Host smart-6fde4e1a-8d46-4a57-9daf-468d4c77181b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354937851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.1354937851
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.2209538682
Short name T297
Test name
Test status
Simulation time 1260500963 ps
CPU time 26.05 seconds
Started Aug 11 06:48:24 PM PDT 24
Finished Aug 11 06:48:50 PM PDT 24
Peak memory 248700 kb
Host smart-daffb65d-f79e-4f9f-b4c9-842fb4a4bdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209538682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.2209538682
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.2904305804
Short name T1086
Test name
Test status
Simulation time 204833082 ps
CPU time 4.15 seconds
Started Aug 11 06:48:22 PM PDT 24
Finished Aug 11 06:48:26 PM PDT 24
Peak memory 242308 kb
Host smart-af50279d-e0ea-4373-9467-d6b43237a0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904305804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.2904305804
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.90534374
Short name T533
Test name
Test status
Simulation time 1346137200 ps
CPU time 9.94 seconds
Started Aug 11 06:48:23 PM PDT 24
Finished Aug 11 06:48:33 PM PDT 24
Peak memory 248660 kb
Host smart-9784a386-5f86-4c8f-a927-36b859e05f99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90534374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.90534374
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.2663091674
Short name T2
Test name
Test status
Simulation time 270149265 ps
CPU time 4.28 seconds
Started Aug 11 06:48:25 PM PDT 24
Finished Aug 11 06:48:30 PM PDT 24
Peak memory 242264 kb
Host smart-3265bbae-7dde-40fa-98b4-ff7035038ae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663091674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.2663091674
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.1737471993
Short name T451
Test name
Test status
Simulation time 2562513879 ps
CPU time 5.36 seconds
Started Aug 11 06:48:23 PM PDT 24
Finished Aug 11 06:48:28 PM PDT 24
Peak memory 242044 kb
Host smart-8e50ede8-999b-4293-8cb1-d8047f6ca319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737471993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1737471993
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.1109414422
Short name T363
Test name
Test status
Simulation time 8898601565 ps
CPU time 118.8 seconds
Started Aug 11 06:48:26 PM PDT 24
Finished Aug 11 06:50:25 PM PDT 24
Peak memory 248736 kb
Host smart-9ec034e2-ff8a-423d-9ffa-49a67230b5c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109414422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.1109414422
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.1765762145
Short name T484
Test name
Test status
Simulation time 83825609504 ps
CPU time 1162.27 seconds
Started Aug 11 06:48:25 PM PDT 24
Finished Aug 11 07:07:48 PM PDT 24
Peak memory 470220 kb
Host smart-b03d8361-20ac-4288-9b86-e1efd86bfe35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765762145 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.1765762145
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.1433750753
Short name T204
Test name
Test status
Simulation time 777594061 ps
CPU time 14.56 seconds
Started Aug 11 06:48:25 PM PDT 24
Finished Aug 11 06:48:40 PM PDT 24
Peak memory 242040 kb
Host smart-cc396a44-d78d-4286-bf71-1e4fcbaca4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433750753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.1433750753
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.1692599832
Short name T750
Test name
Test status
Simulation time 187733567 ps
CPU time 3.19 seconds
Started Aug 11 06:51:16 PM PDT 24
Finished Aug 11 06:51:19 PM PDT 24
Peak memory 242032 kb
Host smart-7689b92e-f32e-494f-a3a9-960ccfbda39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692599832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.1692599832
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.735280619
Short name T43
Test name
Test status
Simulation time 218706003 ps
CPU time 3.97 seconds
Started Aug 11 06:51:16 PM PDT 24
Finished Aug 11 06:51:20 PM PDT 24
Peak memory 242208 kb
Host smart-ae2237b9-92c9-487d-b2af-2fb2aacfe2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735280619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.735280619
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.3624152736
Short name T769
Test name
Test status
Simulation time 2491918179 ps
CPU time 5.7 seconds
Started Aug 11 06:51:16 PM PDT 24
Finished Aug 11 06:51:22 PM PDT 24
Peak memory 242056 kb
Host smart-a5512a54-62bb-4bc8-91d6-d4ba926613f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624152736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.3624152736
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.469425581
Short name T522
Test name
Test status
Simulation time 2343856970 ps
CPU time 4.02 seconds
Started Aug 11 06:51:16 PM PDT 24
Finished Aug 11 06:51:20 PM PDT 24
Peak memory 242284 kb
Host smart-dd6aabc8-5108-4535-8bda-345b28cfe49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469425581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.469425581
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.3071250254
Short name T686
Test name
Test status
Simulation time 193804218 ps
CPU time 3.89 seconds
Started Aug 11 06:51:16 PM PDT 24
Finished Aug 11 06:51:20 PM PDT 24
Peak memory 242028 kb
Host smart-aa3e2848-338a-418b-9b7f-9f2d1a7265f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071250254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.3071250254
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.4085426047
Short name T892
Test name
Test status
Simulation time 1521781714 ps
CPU time 5 seconds
Started Aug 11 06:51:21 PM PDT 24
Finished Aug 11 06:51:26 PM PDT 24
Peak memory 242012 kb
Host smart-de732132-09a3-459a-b53a-b39120c2dd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085426047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.4085426047
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.2220208887
Short name T996
Test name
Test status
Simulation time 183891293 ps
CPU time 3.28 seconds
Started Aug 11 06:51:18 PM PDT 24
Finished Aug 11 06:51:22 PM PDT 24
Peak memory 242372 kb
Host smart-e9de54d2-189f-477a-a8c5-bbdaf8b7c7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220208887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.2220208887
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.3877528688
Short name T798
Test name
Test status
Simulation time 204380068 ps
CPU time 4.01 seconds
Started Aug 11 06:51:18 PM PDT 24
Finished Aug 11 06:51:22 PM PDT 24
Peak memory 242112 kb
Host smart-abe48a49-8840-4b95-be4f-117951b69175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877528688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.3877528688
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.200702450
Short name T1033
Test name
Test status
Simulation time 501430593 ps
CPU time 3.56 seconds
Started Aug 11 06:51:16 PM PDT 24
Finished Aug 11 06:51:20 PM PDT 24
Peak memory 242324 kb
Host smart-b5642328-0bde-45ba-9b66-14b1bcfe2638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200702450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.200702450
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.1150179723
Short name T503
Test name
Test status
Simulation time 137455964 ps
CPU time 3.67 seconds
Started Aug 11 06:51:15 PM PDT 24
Finished Aug 11 06:51:19 PM PDT 24
Peak memory 242004 kb
Host smart-83b3c2c9-7d2d-4592-be88-ad9d99409388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150179723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.1150179723
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.1990987422
Short name T955
Test name
Test status
Simulation time 768675665 ps
CPU time 1.58 seconds
Started Aug 11 06:46:06 PM PDT 24
Finished Aug 11 06:46:08 PM PDT 24
Peak memory 240676 kb
Host smart-9b74d43f-7eaa-457f-b367-cc4d3df0b6d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990987422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1990987422
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.2914631177
Short name T402
Test name
Test status
Simulation time 398117228 ps
CPU time 7.59 seconds
Started Aug 11 06:46:02 PM PDT 24
Finished Aug 11 06:46:09 PM PDT 24
Peak memory 242064 kb
Host smart-49a23d7a-9ab0-4c58-85db-4182320e1c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914631177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.2914631177
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.3387696148
Short name T468
Test name
Test status
Simulation time 3919761433 ps
CPU time 38.25 seconds
Started Aug 11 06:46:01 PM PDT 24
Finished Aug 11 06:46:40 PM PDT 24
Peak memory 243852 kb
Host smart-b9bb915f-a67d-4cf1-87a0-73ce784f4fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387696148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.3387696148
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.241373742
Short name T969
Test name
Test status
Simulation time 878229970 ps
CPU time 19.13 seconds
Started Aug 11 06:46:03 PM PDT 24
Finished Aug 11 06:46:22 PM PDT 24
Peak memory 242116 kb
Host smart-338eb2a7-5769-48e4-8d77-67d68d3435c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241373742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.241373742
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.2515647905
Short name T189
Test name
Test status
Simulation time 267110085 ps
CPU time 4.31 seconds
Started Aug 11 06:46:02 PM PDT 24
Finished Aug 11 06:46:06 PM PDT 24
Peak memory 242232 kb
Host smart-df2d2a25-c793-404b-b735-44601d069273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515647905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.2515647905
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.1809240936
Short name T979
Test name
Test status
Simulation time 240551276 ps
CPU time 8.74 seconds
Started Aug 11 06:46:01 PM PDT 24
Finished Aug 11 06:46:10 PM PDT 24
Peak memory 242476 kb
Host smart-642a78dc-3c78-4047-ba63-dd2c09c407d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809240936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1809240936
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.1487872031
Short name T961
Test name
Test status
Simulation time 540126853 ps
CPU time 12.79 seconds
Started Aug 11 06:46:03 PM PDT 24
Finished Aug 11 06:46:16 PM PDT 24
Peak memory 242164 kb
Host smart-36b64c58-039d-4efe-b9f5-bdf3e6e378a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487872031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.1487872031
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.3269679392
Short name T586
Test name
Test status
Simulation time 2372274628 ps
CPU time 20.06 seconds
Started Aug 11 06:46:03 PM PDT 24
Finished Aug 11 06:46:23 PM PDT 24
Peak memory 242472 kb
Host smart-8e6067c0-3b7a-4782-b459-af99e894f451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3269679392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.3269679392
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.3252728243
Short name T22
Test name
Test status
Simulation time 10599045454 ps
CPU time 165.31 seconds
Started Aug 11 06:46:06 PM PDT 24
Finished Aug 11 06:48:51 PM PDT 24
Peak memory 268060 kb
Host smart-3dc605bc-1f21-4aee-b1fa-1a082a3b1072
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252728243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.3252728243
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.1549120656
Short name T582
Test name
Test status
Simulation time 506192409 ps
CPU time 7.55 seconds
Started Aug 11 06:46:00 PM PDT 24
Finished Aug 11 06:46:08 PM PDT 24
Peak memory 242392 kb
Host smart-d433a57a-9798-4a49-8f93-79d7a17a9cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549120656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.1549120656
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.1937168833
Short name T344
Test name
Test status
Simulation time 421838384071 ps
CPU time 3399.08 seconds
Started Aug 11 06:46:06 PM PDT 24
Finished Aug 11 07:42:45 PM PDT 24
Peak memory 314620 kb
Host smart-780bf657-9945-4b65-aec2-ff99020a7edc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937168833 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.1937168833
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.1709300672
Short name T1041
Test name
Test status
Simulation time 972563804 ps
CPU time 16.05 seconds
Started Aug 11 06:46:06 PM PDT 24
Finished Aug 11 06:46:22 PM PDT 24
Peak memory 248556 kb
Host smart-4c8b1216-e619-48b5-a22c-5b1c67ba43a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709300672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.1709300672
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.4277743519
Short name T234
Test name
Test status
Simulation time 755582748 ps
CPU time 2.74 seconds
Started Aug 11 06:48:28 PM PDT 24
Finished Aug 11 06:48:31 PM PDT 24
Peak memory 240740 kb
Host smart-ed775900-1402-460d-aa85-ab6d66cfc72d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277743519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.4277743519
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.963011967
Short name T717
Test name
Test status
Simulation time 4898928895 ps
CPU time 31.01 seconds
Started Aug 11 06:48:31 PM PDT 24
Finished Aug 11 06:49:02 PM PDT 24
Peak memory 242116 kb
Host smart-17f5dae4-f0d7-441b-bdc4-4f8c90364713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963011967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.963011967
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.847489759
Short name T1146
Test name
Test status
Simulation time 676261318 ps
CPU time 19.69 seconds
Started Aug 11 06:48:30 PM PDT 24
Finished Aug 11 06:48:50 PM PDT 24
Peak memory 242024 kb
Host smart-19d2c587-bfb6-4133-984f-9187b9094fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847489759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.847489759
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.1741309446
Short name T1094
Test name
Test status
Simulation time 163943314 ps
CPU time 4.36 seconds
Started Aug 11 06:48:26 PM PDT 24
Finished Aug 11 06:48:30 PM PDT 24
Peak memory 242140 kb
Host smart-64691aea-f739-476a-ba98-2d44323a562f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741309446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1741309446
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.285557982
Short name T517
Test name
Test status
Simulation time 13330339647 ps
CPU time 19.7 seconds
Started Aug 11 06:48:30 PM PDT 24
Finished Aug 11 06:48:50 PM PDT 24
Peak memory 248676 kb
Host smart-9829835c-1bf9-41ef-b304-3b4cb1287b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285557982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.285557982
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.3747093265
Short name T612
Test name
Test status
Simulation time 3013401466 ps
CPU time 5.67 seconds
Started Aug 11 06:48:28 PM PDT 24
Finished Aug 11 06:48:34 PM PDT 24
Peak memory 241980 kb
Host smart-976ad7ec-d648-480b-ac74-83847e022fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747093265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.3747093265
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.619693064
Short name T1172
Test name
Test status
Simulation time 978816890 ps
CPU time 9.73 seconds
Started Aug 11 06:48:31 PM PDT 24
Finished Aug 11 06:48:41 PM PDT 24
Peak memory 241996 kb
Host smart-637aaa24-0584-4e7e-b3ee-30ef06a0c32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619693064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.619693064
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.2152596784
Short name T395
Test name
Test status
Simulation time 774811480 ps
CPU time 11.63 seconds
Started Aug 11 06:48:30 PM PDT 24
Finished Aug 11 06:48:42 PM PDT 24
Peak memory 248592 kb
Host smart-dc1a3501-6136-4d06-ab88-91699523342e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2152596784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.2152596784
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.672270617
Short name T483
Test name
Test status
Simulation time 663445871 ps
CPU time 6.91 seconds
Started Aug 11 06:48:32 PM PDT 24
Finished Aug 11 06:48:39 PM PDT 24
Peak memory 242332 kb
Host smart-f5f8961f-8a26-4fd6-aa46-1ae0ea27dd64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=672270617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.672270617
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.148499821
Short name T1083
Test name
Test status
Simulation time 1014939895 ps
CPU time 10.94 seconds
Started Aug 11 06:48:25 PM PDT 24
Finished Aug 11 06:48:36 PM PDT 24
Peak memory 248564 kb
Host smart-6a18e8ac-79be-4d92-b06b-1075aad7334e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148499821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.148499821
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.773237420
Short name T636
Test name
Test status
Simulation time 1212056970 ps
CPU time 32.42 seconds
Started Aug 11 06:48:29 PM PDT 24
Finished Aug 11 06:49:02 PM PDT 24
Peak memory 243184 kb
Host smart-ed136cc5-774f-4c41-a473-f4fe3b9d755c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773237420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.
773237420
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.293529155
Short name T772
Test name
Test status
Simulation time 422748396231 ps
CPU time 2101.05 seconds
Started Aug 11 06:48:27 PM PDT 24
Finished Aug 11 07:23:29 PM PDT 24
Peak memory 362948 kb
Host smart-10ee4648-ac87-4c38-bbb4-cb84212481d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293529155 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.293529155
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.2167961811
Short name T444
Test name
Test status
Simulation time 453204473 ps
CPU time 10.72 seconds
Started Aug 11 06:48:31 PM PDT 24
Finished Aug 11 06:48:41 PM PDT 24
Peak memory 242128 kb
Host smart-00d36990-287f-4229-b0f0-426d13f22f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167961811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.2167961811
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.1108783103
Short name T565
Test name
Test status
Simulation time 77049917 ps
CPU time 1.57 seconds
Started Aug 11 06:48:30 PM PDT 24
Finished Aug 11 06:48:32 PM PDT 24
Peak memory 240364 kb
Host smart-5485e61e-f75a-4abf-a397-d883c13da3c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108783103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.1108783103
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.1194349813
Short name T638
Test name
Test status
Simulation time 1164568545 ps
CPU time 11.23 seconds
Started Aug 11 06:48:30 PM PDT 24
Finished Aug 11 06:48:41 PM PDT 24
Peak memory 242228 kb
Host smart-51ac40bf-178b-4af3-b993-fc1d958b89fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194349813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.1194349813
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.444926881
Short name T1012
Test name
Test status
Simulation time 2531571856 ps
CPU time 19.22 seconds
Started Aug 11 06:48:30 PM PDT 24
Finished Aug 11 06:48:50 PM PDT 24
Peak memory 242388 kb
Host smart-3d614de2-fb03-478e-ba75-67da1d92158d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444926881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.444926881
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.2824148484
Short name T976
Test name
Test status
Simulation time 185373956 ps
CPU time 5.51 seconds
Started Aug 11 06:48:31 PM PDT 24
Finished Aug 11 06:48:36 PM PDT 24
Peak memory 242104 kb
Host smart-faf14adb-8882-4aea-b4cf-47af115aea21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824148484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.2824148484
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.3522837914
Short name T48
Test name
Test status
Simulation time 315529961 ps
CPU time 4.83 seconds
Started Aug 11 06:48:29 PM PDT 24
Finished Aug 11 06:48:34 PM PDT 24
Peak memory 242032 kb
Host smart-1bac6f1a-66f1-4e57-bf62-f9abe5ccd1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522837914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.3522837914
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.3064341380
Short name T430
Test name
Test status
Simulation time 327994947 ps
CPU time 6.89 seconds
Started Aug 11 06:48:29 PM PDT 24
Finished Aug 11 06:48:36 PM PDT 24
Peak memory 242172 kb
Host smart-5f087586-93f6-404d-a69c-ce3ab62ddddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064341380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.3064341380
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.1766952380
Short name T801
Test name
Test status
Simulation time 2818830732 ps
CPU time 41.05 seconds
Started Aug 11 06:48:30 PM PDT 24
Finished Aug 11 06:49:11 PM PDT 24
Peak memory 242336 kb
Host smart-a7d97977-3f95-4c6c-a96c-311a1fc8a83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766952380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.1766952380
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.2277205241
Short name T284
Test name
Test status
Simulation time 390090523 ps
CPU time 4.71 seconds
Started Aug 11 06:48:29 PM PDT 24
Finished Aug 11 06:48:34 PM PDT 24
Peak memory 242176 kb
Host smart-306e305f-5c4d-4aab-b11b-797493331b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277205241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.2277205241
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.1926925730
Short name T748
Test name
Test status
Simulation time 1780229596 ps
CPU time 27.35 seconds
Started Aug 11 06:48:34 PM PDT 24
Finished Aug 11 06:49:01 PM PDT 24
Peak memory 241912 kb
Host smart-a7b76d5d-82b8-4eeb-a471-3897e7daa3e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1926925730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.1926925730
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.3793113876
Short name T546
Test name
Test status
Simulation time 108260319 ps
CPU time 3.38 seconds
Started Aug 11 06:48:29 PM PDT 24
Finished Aug 11 06:48:32 PM PDT 24
Peak memory 241972 kb
Host smart-a4575d75-1811-4da8-8d57-dd76bf133d76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3793113876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.3793113876
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.2565254661
Short name T744
Test name
Test status
Simulation time 584903993 ps
CPU time 7.73 seconds
Started Aug 11 06:48:28 PM PDT 24
Finished Aug 11 06:48:36 PM PDT 24
Peak memory 248620 kb
Host smart-2a4aaa09-0eb5-4bc5-bc66-333ebb106392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565254661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.2565254661
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.3429674182
Short name T988
Test name
Test status
Simulation time 211951988392 ps
CPU time 1602.07 seconds
Started Aug 11 06:48:28 PM PDT 24
Finished Aug 11 07:15:11 PM PDT 24
Peak memory 582068 kb
Host smart-b46ed22c-457b-4cb3-a725-980c67ca2e60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429674182 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.3429674182
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.3933715081
Short name T403
Test name
Test status
Simulation time 6315699991 ps
CPU time 38.7 seconds
Started Aug 11 06:48:31 PM PDT 24
Finished Aug 11 06:49:10 PM PDT 24
Peak memory 242104 kb
Host smart-e8fe715b-a4dd-4c0b-a25d-f1903808d466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933715081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.3933715081
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.2973154756
Short name T1019
Test name
Test status
Simulation time 198650497 ps
CPU time 2.35 seconds
Started Aug 11 06:48:34 PM PDT 24
Finished Aug 11 06:48:37 PM PDT 24
Peak memory 240780 kb
Host smart-c6ba0dfa-b139-47a7-9b3b-c45157777eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973154756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.2973154756
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.205113350
Short name T1160
Test name
Test status
Simulation time 384033779 ps
CPU time 8.79 seconds
Started Aug 11 06:48:38 PM PDT 24
Finished Aug 11 06:48:47 PM PDT 24
Peak memory 242116 kb
Host smart-324f90aa-1c13-436c-b098-a14eb6e20294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205113350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.205113350
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.2992554274
Short name T457
Test name
Test status
Simulation time 3394189385 ps
CPU time 36.61 seconds
Started Aug 11 06:48:36 PM PDT 24
Finished Aug 11 06:49:13 PM PDT 24
Peak memory 242912 kb
Host smart-14eb6e60-92d8-4f24-bbfa-6f94c70ae892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992554274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.2992554274
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.2091291479
Short name T569
Test name
Test status
Simulation time 15709937531 ps
CPU time 69.05 seconds
Started Aug 11 06:48:38 PM PDT 24
Finished Aug 11 06:49:47 PM PDT 24
Peak memory 248644 kb
Host smart-e712bdb7-04bb-4adf-823a-252e7a4e96b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091291479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.2091291479
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.85479949
Short name T299
Test name
Test status
Simulation time 329789941 ps
CPU time 4.44 seconds
Started Aug 11 06:48:31 PM PDT 24
Finished Aug 11 06:48:35 PM PDT 24
Peak memory 241932 kb
Host smart-6f964876-917a-466f-bd4d-9080e6952768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85479949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.85479949
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.2528402914
Short name T670
Test name
Test status
Simulation time 7564458221 ps
CPU time 73.4 seconds
Started Aug 11 06:48:37 PM PDT 24
Finished Aug 11 06:49:51 PM PDT 24
Peak memory 248684 kb
Host smart-dfa6b8a2-c1d1-44a9-898a-0576db566626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528402914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.2528402914
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.882585527
Short name T1131
Test name
Test status
Simulation time 10400173326 ps
CPU time 27.48 seconds
Started Aug 11 06:48:36 PM PDT 24
Finished Aug 11 06:49:03 PM PDT 24
Peak memory 242192 kb
Host smart-af455317-ba3d-4722-aa38-89fe8a24638e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882585527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.882585527
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.1533110292
Short name T1138
Test name
Test status
Simulation time 12970118428 ps
CPU time 31.21 seconds
Started Aug 11 06:48:35 PM PDT 24
Finished Aug 11 06:49:06 PM PDT 24
Peak memory 242336 kb
Host smart-be4d081a-fd45-4e13-bb5e-0054004a90e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533110292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.1533110292
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.34379831
Short name T475
Test name
Test status
Simulation time 2810438401 ps
CPU time 21.36 seconds
Started Aug 11 06:48:29 PM PDT 24
Finished Aug 11 06:48:50 PM PDT 24
Peak memory 248632 kb
Host smart-b73eda97-603a-4d12-ade4-cce6d66e17d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34379831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.34379831
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.1052188302
Short name T1137
Test name
Test status
Simulation time 147114029 ps
CPU time 4.64 seconds
Started Aug 11 06:48:36 PM PDT 24
Finished Aug 11 06:48:41 PM PDT 24
Peak memory 241952 kb
Host smart-03955cf3-e817-473e-8b38-03769d8501ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052188302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1052188302
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.3089924011
Short name T521
Test name
Test status
Simulation time 47766728547 ps
CPU time 315.65 seconds
Started Aug 11 06:48:39 PM PDT 24
Finished Aug 11 06:53:54 PM PDT 24
Peak memory 261540 kb
Host smart-b9cfe434-625c-4adc-bbb4-be758a6eac69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089924011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.3089924011
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.3296516600
Short name T296
Test name
Test status
Simulation time 39784159263 ps
CPU time 408.81 seconds
Started Aug 11 06:48:35 PM PDT 24
Finished Aug 11 06:55:24 PM PDT 24
Peak memory 256980 kb
Host smart-7f979316-976a-4a2b-90b3-7f37331fd5f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296516600 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.3296516600
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.3261805129
Short name T498
Test name
Test status
Simulation time 421644319 ps
CPU time 8.06 seconds
Started Aug 11 06:48:35 PM PDT 24
Finished Aug 11 06:48:43 PM PDT 24
Peak memory 241852 kb
Host smart-3cadd6ef-2800-44a1-86f5-271a95648ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261805129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.3261805129
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.3178615426
Short name T1185
Test name
Test status
Simulation time 121128842 ps
CPU time 2.22 seconds
Started Aug 11 06:48:41 PM PDT 24
Finished Aug 11 06:48:44 PM PDT 24
Peak memory 240532 kb
Host smart-e049e89d-1f0d-4dd6-b0f4-60e2caace5e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178615426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3178615426
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.2107466282
Short name T1119
Test name
Test status
Simulation time 384323648 ps
CPU time 7.54 seconds
Started Aug 11 06:48:37 PM PDT 24
Finished Aug 11 06:48:44 PM PDT 24
Peak memory 242436 kb
Host smart-01a7d7ea-4305-4914-ab2c-c7b96bf3f800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107466282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2107466282
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.2678844545
Short name T783
Test name
Test status
Simulation time 3583426722 ps
CPU time 24.07 seconds
Started Aug 11 06:48:36 PM PDT 24
Finished Aug 11 06:49:00 PM PDT 24
Peak memory 242412 kb
Host smart-e8b52dab-2ded-486d-8a16-76d2eae24088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678844545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.2678844545
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.3787753241
Short name T400
Test name
Test status
Simulation time 9505524631 ps
CPU time 29.35 seconds
Started Aug 11 06:48:38 PM PDT 24
Finished Aug 11 06:49:07 PM PDT 24
Peak memory 242716 kb
Host smart-030b7da9-a852-46c0-bddb-9abee04a0bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787753241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3787753241
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.115185389
Short name T695
Test name
Test status
Simulation time 113414590 ps
CPU time 3.95 seconds
Started Aug 11 06:48:37 PM PDT 24
Finished Aug 11 06:48:41 PM PDT 24
Peak memory 242248 kb
Host smart-59c8af5e-f9f5-4f66-8618-5d9090ab88b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115185389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.115185389
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.1072333181
Short name T1126
Test name
Test status
Simulation time 3569603957 ps
CPU time 44.63 seconds
Started Aug 11 06:48:38 PM PDT 24
Finished Aug 11 06:49:23 PM PDT 24
Peak memory 246332 kb
Host smart-262aa6f0-07c6-43a1-b4d8-efd0822ac976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072333181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.1072333181
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.2969664988
Short name T404
Test name
Test status
Simulation time 2258785859 ps
CPU time 24.43 seconds
Started Aug 11 06:48:38 PM PDT 24
Finished Aug 11 06:49:02 PM PDT 24
Peak memory 242116 kb
Host smart-6f72a9f6-3e8b-4041-8165-1d1d1d93f7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969664988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2969664988
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.64595994
Short name T541
Test name
Test status
Simulation time 165674856 ps
CPU time 2.53 seconds
Started Aug 11 06:48:35 PM PDT 24
Finished Aug 11 06:48:38 PM PDT 24
Peak memory 242080 kb
Host smart-f1fac865-af8f-40ee-b621-d1098e03a8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64595994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.64595994
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.3904976952
Short name T446
Test name
Test status
Simulation time 2343272888 ps
CPU time 19.24 seconds
Started Aug 11 06:48:38 PM PDT 24
Finished Aug 11 06:48:57 PM PDT 24
Peak memory 242220 kb
Host smart-5649bb5b-2f06-4fa8-9ef7-25729eed6fe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3904976952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.3904976952
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.81312666
Short name T828
Test name
Test status
Simulation time 144357492 ps
CPU time 4.77 seconds
Started Aug 11 06:48:36 PM PDT 24
Finished Aug 11 06:48:41 PM PDT 24
Peak memory 242332 kb
Host smart-ebd803a0-6f5d-4273-88da-c9df16472920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81312666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.81312666
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.2056522064
Short name T524
Test name
Test status
Simulation time 2913250867 ps
CPU time 4.52 seconds
Started Aug 11 06:48:35 PM PDT 24
Finished Aug 11 06:48:40 PM PDT 24
Peak memory 242384 kb
Host smart-548c05f2-0f41-4e13-85de-24522538e324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056522064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2056522064
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.3654090903
Short name T1079
Test name
Test status
Simulation time 2094221724 ps
CPU time 40.8 seconds
Started Aug 11 06:48:41 PM PDT 24
Finished Aug 11 06:49:22 PM PDT 24
Peak memory 244892 kb
Host smart-e985bab2-ac67-4252-b266-62e5ec8da63b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654090903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.3654090903
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.3241396085
Short name T290
Test name
Test status
Simulation time 222273425242 ps
CPU time 1013.27 seconds
Started Aug 11 06:48:42 PM PDT 24
Finished Aug 11 07:05:35 PM PDT 24
Peak memory 307424 kb
Host smart-effb76ce-c39e-44a0-9ebe-472d25670a42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241396085 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.3241396085
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.3795744952
Short name T452
Test name
Test status
Simulation time 32100669314 ps
CPU time 63.39 seconds
Started Aug 11 06:48:35 PM PDT 24
Finished Aug 11 06:49:38 PM PDT 24
Peak memory 243324 kb
Host smart-72ecbf93-a66e-4590-b321-6feb0b5513f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795744952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.3795744952
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.131176244
Short name T944
Test name
Test status
Simulation time 42078656 ps
CPU time 1.52 seconds
Started Aug 11 06:48:41 PM PDT 24
Finished Aug 11 06:48:42 PM PDT 24
Peak memory 240856 kb
Host smart-3dbb1c19-8fdc-45cf-b9d4-3e57ca654f4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131176244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.131176244
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.2657772997
Short name T40
Test name
Test status
Simulation time 2958598568 ps
CPU time 14.14 seconds
Started Aug 11 06:48:41 PM PDT 24
Finished Aug 11 06:48:55 PM PDT 24
Peak memory 242288 kb
Host smart-5ffcedbb-6ea2-45d5-a408-3fda02d8b330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657772997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.2657772997
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.3506494357
Short name T458
Test name
Test status
Simulation time 1450294694 ps
CPU time 40.77 seconds
Started Aug 11 06:48:41 PM PDT 24
Finished Aug 11 06:49:22 PM PDT 24
Peak memory 252636 kb
Host smart-fe932b7b-db32-419f-8207-9b5831434763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506494357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.3506494357
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.2510176656
Short name T765
Test name
Test status
Simulation time 4463550801 ps
CPU time 27.98 seconds
Started Aug 11 06:48:42 PM PDT 24
Finished Aug 11 06:49:10 PM PDT 24
Peak memory 241944 kb
Host smart-0f2f0e59-25a7-4f4b-8649-b5c451667dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510176656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.2510176656
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.3712831917
Short name T780
Test name
Test status
Simulation time 589714141 ps
CPU time 4.48 seconds
Started Aug 11 06:48:41 PM PDT 24
Finished Aug 11 06:48:46 PM PDT 24
Peak memory 242224 kb
Host smart-85d82187-dc06-4b4a-89eb-9318d90a91b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712831917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.3712831917
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.2323961989
Short name T708
Test name
Test status
Simulation time 501173512 ps
CPU time 11.82 seconds
Started Aug 11 06:48:40 PM PDT 24
Finished Aug 11 06:48:52 PM PDT 24
Peak memory 248612 kb
Host smart-426acddb-cacd-45fa-bbb4-45e0210f4cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323961989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.2323961989
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.1985105673
Short name T729
Test name
Test status
Simulation time 1074870136 ps
CPU time 12.83 seconds
Started Aug 11 06:48:41 PM PDT 24
Finished Aug 11 06:48:53 PM PDT 24
Peak memory 242128 kb
Host smart-7e51fe89-3bc9-47f0-900a-ab828a717585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985105673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.1985105673
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.1670524318
Short name T1057
Test name
Test status
Simulation time 117090004 ps
CPU time 5.34 seconds
Started Aug 11 06:48:39 PM PDT 24
Finished Aug 11 06:48:45 PM PDT 24
Peak memory 241976 kb
Host smart-ce4c7135-6435-4169-8252-52c054a3d004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670524318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.1670524318
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.1128263022
Short name T919
Test name
Test status
Simulation time 841173278 ps
CPU time 7.14 seconds
Started Aug 11 06:48:41 PM PDT 24
Finished Aug 11 06:48:49 PM PDT 24
Peak memory 241928 kb
Host smart-a6cdb0bf-5c16-4cb3-8e49-825338b32c9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1128263022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.1128263022
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.2771557338
Short name T381
Test name
Test status
Simulation time 894758853 ps
CPU time 6.81 seconds
Started Aug 11 06:48:41 PM PDT 24
Finished Aug 11 06:48:48 PM PDT 24
Peak memory 241944 kb
Host smart-7d3d187d-8223-4146-abdb-d6ab5971205e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771557338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2771557338
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.421998839
Short name T715
Test name
Test status
Simulation time 2720822982 ps
CPU time 6.33 seconds
Started Aug 11 06:48:40 PM PDT 24
Finished Aug 11 06:48:46 PM PDT 24
Peak memory 242316 kb
Host smart-d9f0628a-7093-4576-b31d-09f724acf2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421998839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.421998839
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.2275069437
Short name T1170
Test name
Test status
Simulation time 11661114873 ps
CPU time 147.35 seconds
Started Aug 11 06:48:40 PM PDT 24
Finished Aug 11 06:51:08 PM PDT 24
Peak memory 249696 kb
Host smart-db862f5f-e0ae-4d7b-93ec-94a80b69b82d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275069437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.2275069437
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.3139682474
Short name T620
Test name
Test status
Simulation time 591184436 ps
CPU time 8.76 seconds
Started Aug 11 06:48:40 PM PDT 24
Finished Aug 11 06:48:49 PM PDT 24
Peak memory 242508 kb
Host smart-379c0472-8185-4681-8a87-96a72d47cfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139682474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.3139682474
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.4079337909
Short name T662
Test name
Test status
Simulation time 102901507 ps
CPU time 1.8 seconds
Started Aug 11 06:48:45 PM PDT 24
Finished Aug 11 06:48:47 PM PDT 24
Peak memory 240816 kb
Host smart-d8085e04-b51d-4f70-aae5-e0226d7791d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079337909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.4079337909
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.4268761580
Short name T701
Test name
Test status
Simulation time 1160973869 ps
CPU time 16.68 seconds
Started Aug 11 06:48:46 PM PDT 24
Finished Aug 11 06:49:03 PM PDT 24
Peak memory 243056 kb
Host smart-a78c2681-7185-4fb7-a0eb-e1e90cce6cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268761580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.4268761580
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.1524648986
Short name T594
Test name
Test status
Simulation time 3036313606 ps
CPU time 22.31 seconds
Started Aug 11 06:48:49 PM PDT 24
Finished Aug 11 06:49:11 PM PDT 24
Peak memory 242356 kb
Host smart-85dc1918-40ff-4b0b-be19-49f0cd5a02ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524648986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.1524648986
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.468957909
Short name T604
Test name
Test status
Simulation time 1785562188 ps
CPU time 24.59 seconds
Started Aug 11 06:48:42 PM PDT 24
Finished Aug 11 06:49:07 PM PDT 24
Peak memory 242644 kb
Host smart-66a80a53-0d71-4419-b0a9-945ef4c655c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468957909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.468957909
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.73670049
Short name T1154
Test name
Test status
Simulation time 205650034 ps
CPU time 3.8 seconds
Started Aug 11 06:48:40 PM PDT 24
Finished Aug 11 06:48:44 PM PDT 24
Peak memory 242052 kb
Host smart-1179c051-46c8-4230-8e42-2dc7b501de79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73670049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.73670049
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.834352441
Short name T487
Test name
Test status
Simulation time 1870593806 ps
CPU time 4.13 seconds
Started Aug 11 06:48:50 PM PDT 24
Finished Aug 11 06:48:54 PM PDT 24
Peak memory 242276 kb
Host smart-194af0cd-f17e-49ad-81ff-1b2b42836de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834352441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.834352441
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.1138136606
Short name T536
Test name
Test status
Simulation time 2995040524 ps
CPU time 11.05 seconds
Started Aug 11 06:48:52 PM PDT 24
Finished Aug 11 06:49:03 PM PDT 24
Peak memory 242160 kb
Host smart-df9503e1-4529-48bf-8f6a-09b8c2712f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138136606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1138136606
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.2242008008
Short name T1171
Test name
Test status
Simulation time 1535581650 ps
CPU time 23.79 seconds
Started Aug 11 06:48:41 PM PDT 24
Finished Aug 11 06:49:05 PM PDT 24
Peak memory 242256 kb
Host smart-46889911-a379-40c1-bfb4-d203013237be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242008008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.2242008008
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.1279943673
Short name T739
Test name
Test status
Simulation time 467555969 ps
CPU time 8.29 seconds
Started Aug 11 06:48:40 PM PDT 24
Finished Aug 11 06:48:49 PM PDT 24
Peak memory 248640 kb
Host smart-9ce7c834-20c6-48b2-b123-4903413e5231
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279943673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.1279943673
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.3727260971
Short name T848
Test name
Test status
Simulation time 729132736 ps
CPU time 10.37 seconds
Started Aug 11 06:48:47 PM PDT 24
Finished Aug 11 06:48:57 PM PDT 24
Peak memory 242200 kb
Host smart-07bd20ef-cede-497c-ae9f-960354acb16d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3727260971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.3727260971
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.3498633952
Short name T1004
Test name
Test status
Simulation time 322180119 ps
CPU time 9.37 seconds
Started Aug 11 06:48:42 PM PDT 24
Finished Aug 11 06:48:51 PM PDT 24
Peak memory 242108 kb
Host smart-06d6061c-00b5-4d78-9a6e-413eb8b8a337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498633952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.3498633952
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.1462937160
Short name T1048
Test name
Test status
Simulation time 10482735573 ps
CPU time 96.2 seconds
Started Aug 11 06:48:51 PM PDT 24
Finished Aug 11 06:50:27 PM PDT 24
Peak memory 246128 kb
Host smart-5b8a33e3-58d3-4eb2-88bb-9fd18ef2d6bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462937160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.1462937160
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.97231587
Short name T291
Test name
Test status
Simulation time 125506201462 ps
CPU time 2014.06 seconds
Started Aug 11 06:48:45 PM PDT 24
Finished Aug 11 07:22:19 PM PDT 24
Peak memory 382636 kb
Host smart-0955dbf8-5a6b-42ee-9a75-be9ef90e4c28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97231587 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.97231587
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.3031776899
Short name T504
Test name
Test status
Simulation time 2497846763 ps
CPU time 6.28 seconds
Started Aug 11 06:48:46 PM PDT 24
Finished Aug 11 06:48:53 PM PDT 24
Peak memory 242064 kb
Host smart-d49801bf-6322-4e43-9424-71dad2736c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031776899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.3031776899
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.2953224855
Short name T831
Test name
Test status
Simulation time 668540437 ps
CPU time 1.69 seconds
Started Aug 11 06:48:49 PM PDT 24
Finished Aug 11 06:48:51 PM PDT 24
Peak memory 240396 kb
Host smart-570ffbe8-5d3e-48ae-b262-917a24f83c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953224855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.2953224855
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.3505621518
Short name T300
Test name
Test status
Simulation time 1459726243 ps
CPU time 10.05 seconds
Started Aug 11 06:48:49 PM PDT 24
Finished Aug 11 06:48:59 PM PDT 24
Peak memory 248496 kb
Host smart-9fc5160f-9f73-470c-9d2a-28b45546f2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505621518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.3505621518
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.3741476915
Short name T357
Test name
Test status
Simulation time 647243197 ps
CPU time 17.19 seconds
Started Aug 11 06:48:47 PM PDT 24
Finished Aug 11 06:49:05 PM PDT 24
Peak memory 242276 kb
Host smart-29e1d151-a975-4eb7-b85b-9904d1f4a6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741476915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.3741476915
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.184457729
Short name T692
Test name
Test status
Simulation time 1652669087 ps
CPU time 15.72 seconds
Started Aug 11 06:48:46 PM PDT 24
Finished Aug 11 06:49:02 PM PDT 24
Peak memory 248692 kb
Host smart-1a6a94fc-0692-48ea-b085-bccecb505304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184457729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.184457729
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.3812280012
Short name T583
Test name
Test status
Simulation time 255423766 ps
CPU time 3.91 seconds
Started Aug 11 06:48:48 PM PDT 24
Finished Aug 11 06:48:52 PM PDT 24
Peak memory 242432 kb
Host smart-19b2b6b7-03bc-4cb4-a162-06c408f12dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812280012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3812280012
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.3361106269
Short name T156
Test name
Test status
Simulation time 2865115741 ps
CPU time 26.65 seconds
Started Aug 11 06:48:45 PM PDT 24
Finished Aug 11 06:49:12 PM PDT 24
Peak memory 242432 kb
Host smart-1064837c-63f9-47e5-b2a2-89f3c12b3610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361106269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.3361106269
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.260666764
Short name T520
Test name
Test status
Simulation time 30524634320 ps
CPU time 42.32 seconds
Started Aug 11 06:48:46 PM PDT 24
Finished Aug 11 06:49:28 PM PDT 24
Peak memory 242184 kb
Host smart-5ffb4345-666f-4a21-8268-f6ad8435aef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260666764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.260666764
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.144799394
Short name T216
Test name
Test status
Simulation time 1930356337 ps
CPU time 17.25 seconds
Started Aug 11 06:48:46 PM PDT 24
Finished Aug 11 06:49:04 PM PDT 24
Peak memory 242404 kb
Host smart-081effcc-68f0-4826-b928-a4ebdb2c78ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144799394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.144799394
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.3781460735
Short name T540
Test name
Test status
Simulation time 4137098571 ps
CPU time 10.03 seconds
Started Aug 11 06:48:49 PM PDT 24
Finished Aug 11 06:48:59 PM PDT 24
Peak memory 242500 kb
Host smart-bc284139-7508-4867-8ff6-e4029f81d354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781460735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.3781460735
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.2964127580
Short name T374
Test name
Test status
Simulation time 313339287 ps
CPU time 10.18 seconds
Started Aug 11 06:48:49 PM PDT 24
Finished Aug 11 06:48:59 PM PDT 24
Peak memory 242180 kb
Host smart-3471e5d9-fdee-4ae3-aa66-fb051c0456c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2964127580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.2964127580
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.3061821168
Short name T585
Test name
Test status
Simulation time 2534125994 ps
CPU time 6.01 seconds
Started Aug 11 06:48:49 PM PDT 24
Finished Aug 11 06:48:55 PM PDT 24
Peak memory 242064 kb
Host smart-953deb1a-4130-456a-a3a3-89808586d73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061821168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3061821168
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.2837637580
Short name T398
Test name
Test status
Simulation time 12948484557 ps
CPU time 102.29 seconds
Started Aug 11 06:48:49 PM PDT 24
Finished Aug 11 06:50:31 PM PDT 24
Peak memory 245820 kb
Host smart-41feb755-5e0b-4b49-9d7e-cc6c9618255a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837637580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.2837637580
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.2535351901
Short name T508
Test name
Test status
Simulation time 1053880100 ps
CPU time 14.54 seconds
Started Aug 11 06:48:47 PM PDT 24
Finished Aug 11 06:49:01 PM PDT 24
Peak memory 242028 kb
Host smart-a4b1bc34-2a56-473e-823e-800038d76a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535351901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.2535351901
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.2450467088
Short name T1158
Test name
Test status
Simulation time 62040448 ps
CPU time 1.89 seconds
Started Aug 11 06:48:56 PM PDT 24
Finished Aug 11 06:48:58 PM PDT 24
Peak memory 240460 kb
Host smart-c5560a78-ba48-411a-b0a9-8b80077b84fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450467088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2450467088
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.1597718309
Short name T39
Test name
Test status
Simulation time 6520640702 ps
CPU time 18.07 seconds
Started Aug 11 06:48:50 PM PDT 24
Finished Aug 11 06:49:09 PM PDT 24
Peak memory 243112 kb
Host smart-02c729ac-e8aa-4fa7-a1c8-d5d9ef9419ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597718309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.1597718309
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.3253907235
Short name T428
Test name
Test status
Simulation time 1184993952 ps
CPU time 12.12 seconds
Started Aug 11 06:48:51 PM PDT 24
Finished Aug 11 06:49:03 PM PDT 24
Peak memory 242312 kb
Host smart-1756aeb8-62e6-49ab-9efc-b23ef29d0bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253907235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.3253907235
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.2179278533
Short name T894
Test name
Test status
Simulation time 2171956691 ps
CPU time 24.88 seconds
Started Aug 11 06:48:52 PM PDT 24
Finished Aug 11 06:49:17 PM PDT 24
Peak memory 242528 kb
Host smart-4e8a261a-2a5d-4bcb-905d-5e5c456a5640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179278533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.2179278533
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.2210442791
Short name T426
Test name
Test status
Simulation time 291092479 ps
CPU time 3.72 seconds
Started Aug 11 06:48:51 PM PDT 24
Finished Aug 11 06:48:55 PM PDT 24
Peak memory 242244 kb
Host smart-1df6276b-0d5d-4cb8-81c8-e14908fd9750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210442791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2210442791
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.3947681637
Short name T106
Test name
Test status
Simulation time 632954888 ps
CPU time 14.08 seconds
Started Aug 11 06:48:52 PM PDT 24
Finished Aug 11 06:49:06 PM PDT 24
Peak memory 242252 kb
Host smart-2ee4fdcb-cab6-44d3-8ed7-c5fcf6af1db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947681637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.3947681637
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.2971668645
Short name T630
Test name
Test status
Simulation time 1699417225 ps
CPU time 21.27 seconds
Started Aug 11 06:48:55 PM PDT 24
Finished Aug 11 06:49:16 PM PDT 24
Peak memory 243048 kb
Host smart-b193ee22-52f2-48eb-9bc1-35b748f6926b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971668645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.2971668645
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.4022979830
Short name T718
Test name
Test status
Simulation time 695252010 ps
CPU time 18.4 seconds
Started Aug 11 06:48:51 PM PDT 24
Finished Aug 11 06:49:09 PM PDT 24
Peak memory 241996 kb
Host smart-91be2006-458b-4018-91f3-319829710305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022979830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.4022979830
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.728624846
Short name T921
Test name
Test status
Simulation time 666905286 ps
CPU time 10.72 seconds
Started Aug 11 06:48:52 PM PDT 24
Finished Aug 11 06:49:03 PM PDT 24
Peak memory 242024 kb
Host smart-27e2da7b-86be-4a5c-bb32-2168620b1716
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=728624846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.728624846
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.1226850333
Short name T646
Test name
Test status
Simulation time 142706846 ps
CPU time 5.46 seconds
Started Aug 11 06:48:51 PM PDT 24
Finished Aug 11 06:48:56 PM PDT 24
Peak memory 242232 kb
Host smart-d714bd1e-d7be-4d9b-9248-015d5a05f5fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226850333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.1226850333
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.2160511531
Short name T1005
Test name
Test status
Simulation time 601887736 ps
CPU time 7.79 seconds
Started Aug 11 06:48:53 PM PDT 24
Finished Aug 11 06:49:01 PM PDT 24
Peak memory 242032 kb
Host smart-a9cef76b-7742-457d-add2-89d9b5d178f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160511531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.2160511531
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.4217489015
Short name T789
Test name
Test status
Simulation time 23247839090 ps
CPU time 711.07 seconds
Started Aug 11 06:48:51 PM PDT 24
Finished Aug 11 07:00:43 PM PDT 24
Peak memory 284812 kb
Host smart-b56ce929-8290-4b2f-af09-97fbfd326e4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217489015 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.4217489015
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.3740912525
Short name T1029
Test name
Test status
Simulation time 13415656484 ps
CPU time 25.53 seconds
Started Aug 11 06:48:51 PM PDT 24
Finished Aug 11 06:49:17 PM PDT 24
Peak memory 242964 kb
Host smart-08d486c3-b988-4015-b80e-f64a7feba438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740912525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.3740912525
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.4126036279
Short name T641
Test name
Test status
Simulation time 136230512 ps
CPU time 1.75 seconds
Started Aug 11 06:48:56 PM PDT 24
Finished Aug 11 06:48:58 PM PDT 24
Peak memory 240928 kb
Host smart-993ebb4d-cfa9-4162-a0ed-6c3da5f97999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126036279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.4126036279
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.2670038336
Short name T124
Test name
Test status
Simulation time 2731907650 ps
CPU time 13.71 seconds
Started Aug 11 06:48:53 PM PDT 24
Finished Aug 11 06:49:07 PM PDT 24
Peak memory 242052 kb
Host smart-aa2c9a92-d32c-4d2e-a581-4f8b4aa847b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670038336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.2670038336
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.2786233278
Short name T625
Test name
Test status
Simulation time 4854032305 ps
CPU time 20.4 seconds
Started Aug 11 06:48:51 PM PDT 24
Finished Aug 11 06:49:11 PM PDT 24
Peak memory 242480 kb
Host smart-88e81fb4-f9e2-4271-8389-d4e8a4511a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786233278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.2786233278
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.333529932
Short name T898
Test name
Test status
Simulation time 3179742223 ps
CPU time 31.01 seconds
Started Aug 11 06:48:52 PM PDT 24
Finished Aug 11 06:49:23 PM PDT 24
Peak memory 248836 kb
Host smart-425ed719-9fd4-4520-bd7e-eebeabc40791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333529932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.333529932
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.316307712
Short name T791
Test name
Test status
Simulation time 199467836 ps
CPU time 2.99 seconds
Started Aug 11 06:48:51 PM PDT 24
Finished Aug 11 06:48:54 PM PDT 24
Peak memory 242372 kb
Host smart-35d4c858-d53a-46cb-8431-8143bb1eb3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316307712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.316307712
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.933715595
Short name T1084
Test name
Test status
Simulation time 987006253 ps
CPU time 32.91 seconds
Started Aug 11 06:48:50 PM PDT 24
Finished Aug 11 06:49:24 PM PDT 24
Peak memory 244652 kb
Host smart-e9a842ab-5f72-4381-b941-045041614478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933715595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.933715595
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.39116844
Short name T467
Test name
Test status
Simulation time 698728430 ps
CPU time 16.1 seconds
Started Aug 11 06:48:56 PM PDT 24
Finished Aug 11 06:49:12 PM PDT 24
Peak memory 241932 kb
Host smart-68a02f0a-eef6-45ca-a4ba-6485bd664eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39116844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.39116844
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.2104562902
Short name T530
Test name
Test status
Simulation time 413382198 ps
CPU time 5.43 seconds
Started Aug 11 06:48:54 PM PDT 24
Finished Aug 11 06:48:59 PM PDT 24
Peak memory 247424 kb
Host smart-97884758-48c9-4ea0-a172-1fe387119529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104562902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2104562902
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.99799618
Short name T94
Test name
Test status
Simulation time 11542875177 ps
CPU time 30.23 seconds
Started Aug 11 06:48:51 PM PDT 24
Finished Aug 11 06:49:21 PM PDT 24
Peak memory 242004 kb
Host smart-68551552-188e-4b1b-860a-30b3a0668fcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99799618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.99799618
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.3788028626
Short name T376
Test name
Test status
Simulation time 240559051 ps
CPU time 4.53 seconds
Started Aug 11 06:48:59 PM PDT 24
Finished Aug 11 06:49:04 PM PDT 24
Peak memory 241908 kb
Host smart-d5babf3b-9628-4f3c-b08d-d5e2ac7d7d70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3788028626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3788028626
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.1369805037
Short name T461
Test name
Test status
Simulation time 424264105 ps
CPU time 12.33 seconds
Started Aug 11 06:48:56 PM PDT 24
Finished Aug 11 06:49:09 PM PDT 24
Peak memory 241952 kb
Host smart-2a88120a-53c4-4237-a6db-01763d4471c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369805037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1369805037
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.2162054905
Short name T359
Test name
Test status
Simulation time 1278626779970 ps
CPU time 2857.82 seconds
Started Aug 11 06:48:56 PM PDT 24
Finished Aug 11 07:36:34 PM PDT 24
Peak memory 623908 kb
Host smart-c95b0faf-7f67-48fd-ac95-87e8e44afae8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162054905 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.2162054905
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.2615683538
Short name T519
Test name
Test status
Simulation time 2372298048 ps
CPU time 22.43 seconds
Started Aug 11 06:48:58 PM PDT 24
Finished Aug 11 06:49:21 PM PDT 24
Peak memory 248660 kb
Host smart-b0727d38-7a97-41f2-87fb-ed152fadecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615683538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.2615683538
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.1756287702
Short name T554
Test name
Test status
Simulation time 60537324 ps
CPU time 1.8 seconds
Started Aug 11 06:49:09 PM PDT 24
Finished Aug 11 06:49:11 PM PDT 24
Peak memory 240576 kb
Host smart-4010caa1-dbd6-4a76-aada-fb0c749e4e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756287702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.1756287702
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.3957621243
Short name T75
Test name
Test status
Simulation time 732144700 ps
CPU time 12.17 seconds
Started Aug 11 06:48:56 PM PDT 24
Finished Aug 11 06:49:09 PM PDT 24
Peak memory 242088 kb
Host smart-f7644f3a-49ae-409e-af5c-a6f12e0b3c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957621243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.3957621243
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.2425246169
Short name T515
Test name
Test status
Simulation time 1197454417 ps
CPU time 37.03 seconds
Started Aug 11 06:48:57 PM PDT 24
Finished Aug 11 06:49:35 PM PDT 24
Peak memory 249084 kb
Host smart-16d46546-d3e9-496f-997a-1cbb7bd74208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425246169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.2425246169
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.1192619129
Short name T910
Test name
Test status
Simulation time 24590559452 ps
CPU time 43.68 seconds
Started Aug 11 06:48:55 PM PDT 24
Finished Aug 11 06:49:39 PM PDT 24
Peak memory 243212 kb
Host smart-4425a181-2cfc-43f3-a67e-5af29e252a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192619129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.1192619129
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.4003619555
Short name T947
Test name
Test status
Simulation time 327960966 ps
CPU time 3.68 seconds
Started Aug 11 06:48:56 PM PDT 24
Finished Aug 11 06:49:00 PM PDT 24
Peak memory 242056 kb
Host smart-104cce55-b33e-4c93-aa21-f23b279ba8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003619555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.4003619555
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.1142297217
Short name T1089
Test name
Test status
Simulation time 847941018 ps
CPU time 22.44 seconds
Started Aug 11 06:48:55 PM PDT 24
Finished Aug 11 06:49:18 PM PDT 24
Peak memory 242016 kb
Host smart-c0b8a3f7-5598-44e1-a3d4-55e382cc81d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142297217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.1142297217
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.4255974200
Short name T823
Test name
Test status
Simulation time 4704413870 ps
CPU time 29.89 seconds
Started Aug 11 06:48:56 PM PDT 24
Finished Aug 11 06:49:26 PM PDT 24
Peak memory 248684 kb
Host smart-b67b8446-2554-48d6-a647-5115f7f0a4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255974200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.4255974200
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.145116234
Short name T644
Test name
Test status
Simulation time 232645281 ps
CPU time 5.12 seconds
Started Aug 11 06:48:57 PM PDT 24
Finished Aug 11 06:49:02 PM PDT 24
Peak memory 242360 kb
Host smart-bcef1043-c7f0-4368-8f7d-7330ae6a8f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145116234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.145116234
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.1034594816
Short name T531
Test name
Test status
Simulation time 1617115124 ps
CPU time 21.84 seconds
Started Aug 11 06:48:56 PM PDT 24
Finished Aug 11 06:49:18 PM PDT 24
Peak memory 242176 kb
Host smart-d09a4cf6-43e4-428d-999a-cdad97fb9c14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034594816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1034594816
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.3294349591
Short name T372
Test name
Test status
Simulation time 331586559 ps
CPU time 6.84 seconds
Started Aug 11 06:49:03 PM PDT 24
Finished Aug 11 06:49:10 PM PDT 24
Peak memory 242016 kb
Host smart-0aaef371-304e-45db-983b-8098f9df16ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3294349591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.3294349591
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.4081025233
Short name T656
Test name
Test status
Simulation time 377878513 ps
CPU time 6.57 seconds
Started Aug 11 06:48:56 PM PDT 24
Finished Aug 11 06:49:03 PM PDT 24
Peak memory 241964 kb
Host smart-ea12ee10-ea19-4288-857b-446b624a456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081025233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.4081025233
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.2696146132
Short name T1191
Test name
Test status
Simulation time 11973925719 ps
CPU time 85.08 seconds
Started Aug 11 06:49:00 PM PDT 24
Finished Aug 11 06:50:25 PM PDT 24
Peak memory 246376 kb
Host smart-daab47ea-67bf-4afc-9dbb-af2c5bdc213a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696146132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.2696146132
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.2141797407
Short name T957
Test name
Test status
Simulation time 1991159315 ps
CPU time 30.29 seconds
Started Aug 11 06:49:03 PM PDT 24
Finished Aug 11 06:49:33 PM PDT 24
Peak memory 248604 kb
Host smart-c2e90de1-17f3-4e8b-bc58-5d2577df28d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141797407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.2141797407
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.3596100406
Short name T6
Test name
Test status
Simulation time 320700083 ps
CPU time 2.11 seconds
Started Aug 11 06:46:15 PM PDT 24
Finished Aug 11 06:46:17 PM PDT 24
Peak memory 240688 kb
Host smart-d56cbd51-d12f-4486-b983-67cc8909629e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596100406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.3596100406
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.4074526865
Short name T1010
Test name
Test status
Simulation time 26781808151 ps
CPU time 45.39 seconds
Started Aug 11 06:46:14 PM PDT 24
Finished Aug 11 06:46:59 PM PDT 24
Peak memory 242748 kb
Host smart-a3aaf4f7-b818-4b4f-8883-febd989896f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074526865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.4074526865
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.336568053
Short name T28
Test name
Test status
Simulation time 745048273 ps
CPU time 18.78 seconds
Started Aug 11 06:46:10 PM PDT 24
Finished Aug 11 06:46:29 PM PDT 24
Peak memory 242232 kb
Host smart-f407f1ba-598d-4e1b-8d22-d135b0d8d578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336568053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.336568053
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.3903929669
Short name T647
Test name
Test status
Simulation time 567673055 ps
CPU time 13.88 seconds
Started Aug 11 06:46:14 PM PDT 24
Finished Aug 11 06:46:28 PM PDT 24
Peak memory 241968 kb
Host smart-42f72533-ab68-472e-aedf-687f6cf0ae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903929669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.3903929669
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.246944059
Short name T731
Test name
Test status
Simulation time 2073710028 ps
CPU time 21.86 seconds
Started Aug 11 06:46:13 PM PDT 24
Finished Aug 11 06:46:35 PM PDT 24
Peak memory 242676 kb
Host smart-18f6f1d7-157f-40a2-997d-7d2d0bca837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246944059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.246944059
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.68045852
Short name T671
Test name
Test status
Simulation time 278665264 ps
CPU time 3.89 seconds
Started Aug 11 06:46:06 PM PDT 24
Finished Aug 11 06:46:10 PM PDT 24
Peak memory 242316 kb
Host smart-c259da1e-dc4d-43cc-a07f-b5145e589488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68045852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.68045852
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.3709289111
Short name T959
Test name
Test status
Simulation time 1118003303 ps
CPU time 12.89 seconds
Started Aug 11 06:46:10 PM PDT 24
Finished Aug 11 06:46:23 PM PDT 24
Peak memory 241948 kb
Host smart-c8ae25b8-2b37-45ca-be74-754d0a3536bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709289111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3709289111
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.2419849554
Short name T434
Test name
Test status
Simulation time 189665520 ps
CPU time 6.34 seconds
Started Aug 11 06:46:14 PM PDT 24
Finished Aug 11 06:46:21 PM PDT 24
Peak memory 242220 kb
Host smart-78324fdf-f9a7-4dd7-80c2-b580a2bdace6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419849554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.2419849554
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.404666210
Short name T92
Test name
Test status
Simulation time 1758338025 ps
CPU time 18.62 seconds
Started Aug 11 06:46:14 PM PDT 24
Finished Aug 11 06:46:32 PM PDT 24
Peak memory 241952 kb
Host smart-d6f5fa65-6dc0-4f08-b215-a804ff22eb51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=404666210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.404666210
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.1981319210
Short name T409
Test name
Test status
Simulation time 864428626 ps
CPU time 5.39 seconds
Started Aug 11 06:46:11 PM PDT 24
Finished Aug 11 06:46:17 PM PDT 24
Peak memory 242188 kb
Host smart-2b092f88-220b-45bb-8cef-2275a6ad6780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1981319210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1981319210
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.2253961865
Short name T218
Test name
Test status
Simulation time 226773941 ps
CPU time 6.28 seconds
Started Aug 11 06:46:07 PM PDT 24
Finished Aug 11 06:46:13 PM PDT 24
Peak memory 241984 kb
Host smart-d31e52f6-ba6b-4422-bc14-9e664e28a593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253961865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.2253961865
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.1731926727
Short name T1002
Test name
Test status
Simulation time 33730862469 ps
CPU time 98.17 seconds
Started Aug 11 06:46:13 PM PDT 24
Finished Aug 11 06:47:51 PM PDT 24
Peak memory 245804 kb
Host smart-347bb860-10a0-47b9-b53b-6ec0febbd74f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731926727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
1731926727
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.167452859
Short name T141
Test name
Test status
Simulation time 27307309433 ps
CPU time 726.02 seconds
Started Aug 11 06:46:13 PM PDT 24
Finished Aug 11 06:58:19 PM PDT 24
Peak memory 256976 kb
Host smart-cfe58685-6a26-4272-bc10-5c2602931fa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167452859 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.167452859
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.3144732602
Short name T833
Test name
Test status
Simulation time 13290720054 ps
CPU time 22.76 seconds
Started Aug 11 06:46:09 PM PDT 24
Finished Aug 11 06:46:32 PM PDT 24
Peak memory 242580 kb
Host smart-8b8d45c0-7bcb-4512-8a96-4f02bc6dfff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144732602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.3144732602
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.3070949026
Short name T525
Test name
Test status
Simulation time 56653395 ps
CPU time 1.84 seconds
Started Aug 11 06:49:06 PM PDT 24
Finished Aug 11 06:49:08 PM PDT 24
Peak memory 240516 kb
Host smart-7390e689-6ae7-4337-97e8-f5478d6fe5d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070949026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.3070949026
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.2054406536
Short name T45
Test name
Test status
Simulation time 518311413 ps
CPU time 6.09 seconds
Started Aug 11 06:49:02 PM PDT 24
Finished Aug 11 06:49:08 PM PDT 24
Peak memory 248688 kb
Host smart-29519a25-7428-4b65-8c3c-d440ccf63fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054406536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.2054406536
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.4077100026
Short name T346
Test name
Test status
Simulation time 504092740 ps
CPU time 14.86 seconds
Started Aug 11 06:49:03 PM PDT 24
Finished Aug 11 06:49:18 PM PDT 24
Peak memory 242024 kb
Host smart-79cce72f-e7c9-4099-90c6-c6dfaf6cfd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077100026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.4077100026
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.1189142339
Short name T247
Test name
Test status
Simulation time 2785194522 ps
CPU time 23.9 seconds
Started Aug 11 06:49:04 PM PDT 24
Finished Aug 11 06:49:28 PM PDT 24
Peak memory 242236 kb
Host smart-84dd67de-7495-4b0f-9911-49a67f1f8738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189142339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.1189142339
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.379841164
Short name T589
Test name
Test status
Simulation time 15591674444 ps
CPU time 22.95 seconds
Started Aug 11 06:49:01 PM PDT 24
Finished Aug 11 06:49:24 PM PDT 24
Peak memory 244564 kb
Host smart-41c7e826-c351-407c-a6b9-38334a493e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379841164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.379841164
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.3894752608
Short name T535
Test name
Test status
Simulation time 6092916023 ps
CPU time 17.2 seconds
Started Aug 11 06:49:02 PM PDT 24
Finished Aug 11 06:49:19 PM PDT 24
Peak memory 248712 kb
Host smart-1e6678c3-46ed-499c-93a4-d3f930ca3901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894752608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.3894752608
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.802190524
Short name T11
Test name
Test status
Simulation time 4482100747 ps
CPU time 8.86 seconds
Started Aug 11 06:49:03 PM PDT 24
Finished Aug 11 06:49:12 PM PDT 24
Peak memory 242352 kb
Host smart-678ac6f5-2dd8-4495-94ca-317c80a02d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802190524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.802190524
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.2086640243
Short name T38
Test name
Test status
Simulation time 1556341291 ps
CPU time 16.76 seconds
Started Aug 11 06:49:04 PM PDT 24
Finished Aug 11 06:49:21 PM PDT 24
Peak memory 242504 kb
Host smart-b4d9213d-d331-488e-a58b-f8ba314b14b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2086640243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.2086640243
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.1242570533
Short name T679
Test name
Test status
Simulation time 142402188 ps
CPU time 4.37 seconds
Started Aug 11 06:49:04 PM PDT 24
Finished Aug 11 06:49:08 PM PDT 24
Peak memory 241972 kb
Host smart-7c1aea89-fbe9-40b0-9e45-e59bdb315277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1242570533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.1242570533
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.842369764
Short name T886
Test name
Test status
Simulation time 678027115 ps
CPU time 8.83 seconds
Started Aug 11 06:49:02 PM PDT 24
Finished Aug 11 06:49:11 PM PDT 24
Peak memory 241916 kb
Host smart-17802410-64ca-4021-ab14-4c9d9020f6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842369764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.842369764
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.2508121784
Short name T929
Test name
Test status
Simulation time 5886356417 ps
CPU time 50.45 seconds
Started Aug 11 06:49:08 PM PDT 24
Finished Aug 11 06:49:58 PM PDT 24
Peak memory 249636 kb
Host smart-b8a0ec1f-15ff-491d-a2ca-cfb8c861d285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508121784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.2508121784
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.3426992013
Short name T773
Test name
Test status
Simulation time 1780751456 ps
CPU time 31.9 seconds
Started Aug 11 06:49:01 PM PDT 24
Finished Aug 11 06:49:33 PM PDT 24
Peak memory 242324 kb
Host smart-030975b0-3c12-4d7a-ad6e-c8662a6dc44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426992013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.3426992013
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.778322756
Short name T787
Test name
Test status
Simulation time 84328241 ps
CPU time 2.04 seconds
Started Aug 11 06:49:10 PM PDT 24
Finished Aug 11 06:49:12 PM PDT 24
Peak memory 240556 kb
Host smart-b0cc9ec7-fbc7-4e3f-99dc-262baaf9f724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778322756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.778322756
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.4254852960
Short name T27
Test name
Test status
Simulation time 2115641322 ps
CPU time 28.17 seconds
Started Aug 11 06:49:08 PM PDT 24
Finished Aug 11 06:49:36 PM PDT 24
Peak memory 242296 kb
Host smart-26860b37-4ad0-4fc7-b866-6238f2eddc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254852960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.4254852960
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.978644820
Short name T537
Test name
Test status
Simulation time 859264069 ps
CPU time 13.12 seconds
Started Aug 11 06:49:08 PM PDT 24
Finished Aug 11 06:49:21 PM PDT 24
Peak memory 242400 kb
Host smart-045e0afa-51f6-4197-881b-66d6bfb526ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978644820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.978644820
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.2542765716
Short name T953
Test name
Test status
Simulation time 4189756678 ps
CPU time 9.78 seconds
Started Aug 11 06:49:08 PM PDT 24
Finished Aug 11 06:49:18 PM PDT 24
Peak memory 242104 kb
Host smart-e2933d7f-74d1-42c7-a1af-521cfcde0862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542765716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.2542765716
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.813095034
Short name T745
Test name
Test status
Simulation time 165913811 ps
CPU time 4.27 seconds
Started Aug 11 06:49:12 PM PDT 24
Finished Aug 11 06:49:16 PM PDT 24
Peak memory 242216 kb
Host smart-73d58dd4-6181-40d6-bc67-19dd157254c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813095034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.813095034
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.593965568
Short name T747
Test name
Test status
Simulation time 4686036274 ps
CPU time 54.02 seconds
Started Aug 11 06:49:08 PM PDT 24
Finished Aug 11 06:50:02 PM PDT 24
Peak memory 248684 kb
Host smart-f4145067-8283-483f-85a4-d57c127c100b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593965568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.593965568
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.1150004186
Short name T470
Test name
Test status
Simulation time 1830855019 ps
CPU time 22.64 seconds
Started Aug 11 06:49:10 PM PDT 24
Finished Aug 11 06:49:33 PM PDT 24
Peak memory 242364 kb
Host smart-2f6d80dd-76b7-45b8-bad6-a7a873c19842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150004186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1150004186
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.2448768250
Short name T809
Test name
Test status
Simulation time 9589285485 ps
CPU time 21.29 seconds
Started Aug 11 06:49:07 PM PDT 24
Finished Aug 11 06:49:28 PM PDT 24
Peak memory 242472 kb
Host smart-c090a302-05a1-4429-a541-e6619e4b2c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448768250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.2448768250
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.359795216
Short name T501
Test name
Test status
Simulation time 548703463 ps
CPU time 9.11 seconds
Started Aug 11 06:49:07 PM PDT 24
Finished Aug 11 06:49:17 PM PDT 24
Peak memory 242132 kb
Host smart-208e2411-e184-440b-9be5-144af5477f02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359795216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.359795216
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.2654226097
Short name T970
Test name
Test status
Simulation time 726756786 ps
CPU time 6.77 seconds
Started Aug 11 06:49:13 PM PDT 24
Finished Aug 11 06:49:20 PM PDT 24
Peak memory 241872 kb
Host smart-6c842658-a4cc-4bab-a8d9-5c38879fd40f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654226097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.2654226097
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.383081075
Short name T450
Test name
Test status
Simulation time 926375370 ps
CPU time 9.5 seconds
Started Aug 11 06:49:10 PM PDT 24
Finished Aug 11 06:49:20 PM PDT 24
Peak memory 241928 kb
Host smart-3b9af79b-15e4-4969-9764-dc0b1d76182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383081075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.383081075
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.2011126653
Short name T1112
Test name
Test status
Simulation time 6291135426 ps
CPU time 138.07 seconds
Started Aug 11 06:49:09 PM PDT 24
Finished Aug 11 06:51:27 PM PDT 24
Peak memory 245852 kb
Host smart-2b5e0b98-ff91-467d-a656-31bc2b94a5e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011126653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.2011126653
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.2744398614
Short name T911
Test name
Test status
Simulation time 2845234200 ps
CPU time 23.57 seconds
Started Aug 11 06:49:10 PM PDT 24
Finished Aug 11 06:49:33 PM PDT 24
Peak memory 242160 kb
Host smart-c92c2de3-d1cb-4c9e-b6f3-4632cda912e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744398614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.2744398614
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.2776274865
Short name T233
Test name
Test status
Simulation time 174826028 ps
CPU time 2.16 seconds
Started Aug 11 06:49:08 PM PDT 24
Finished Aug 11 06:49:11 PM PDT 24
Peak memory 240596 kb
Host smart-4f00f3a9-543d-4730-946b-a8270ab8e804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776274865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.2776274865
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.136068029
Short name T407
Test name
Test status
Simulation time 684116346 ps
CPU time 5.53 seconds
Started Aug 11 06:49:10 PM PDT 24
Finished Aug 11 06:49:16 PM PDT 24
Peak memory 248420 kb
Host smart-e45d555f-c3fa-4238-bcd8-edb0a27535f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136068029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.136068029
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.2099320290
Short name T557
Test name
Test status
Simulation time 940790961 ps
CPU time 12.85 seconds
Started Aug 11 06:49:06 PM PDT 24
Finished Aug 11 06:49:20 PM PDT 24
Peak memory 241956 kb
Host smart-dcea39b6-2ae4-4f29-a304-ef79e7ee95eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099320290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.2099320290
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.2888538518
Short name T913
Test name
Test status
Simulation time 930767159 ps
CPU time 10.81 seconds
Started Aug 11 06:49:06 PM PDT 24
Finished Aug 11 06:49:17 PM PDT 24
Peak memory 248564 kb
Host smart-c2bbec76-3561-46ec-a8fc-30646b2a6db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888538518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.2888538518
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.2276632229
Short name T816
Test name
Test status
Simulation time 212628104 ps
CPU time 4.48 seconds
Started Aug 11 06:49:10 PM PDT 24
Finished Aug 11 06:49:15 PM PDT 24
Peak memory 242436 kb
Host smart-0403b30b-8ed5-45ad-bd78-39186b732b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276632229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.2276632229
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.1451438400
Short name T743
Test name
Test status
Simulation time 3773137882 ps
CPU time 33.83 seconds
Started Aug 11 06:49:10 PM PDT 24
Finished Aug 11 06:49:44 PM PDT 24
Peak memory 242580 kb
Host smart-254e80d5-483b-4e76-82a0-e59fe960e725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451438400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1451438400
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.1972335134
Short name T552
Test name
Test status
Simulation time 1695509463 ps
CPU time 35.43 seconds
Started Aug 11 06:49:13 PM PDT 24
Finished Aug 11 06:49:49 PM PDT 24
Peak memory 242280 kb
Host smart-6a80056e-d90f-4f20-a12a-3ecbda9d9670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972335134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.1972335134
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.168425732
Short name T572
Test name
Test status
Simulation time 199671133 ps
CPU time 5.5 seconds
Started Aug 11 06:49:08 PM PDT 24
Finished Aug 11 06:49:14 PM PDT 24
Peak memory 241872 kb
Host smart-a2f72dac-1b3e-4a33-8f66-d286f04e2fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168425732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.168425732
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.3562706323
Short name T926
Test name
Test status
Simulation time 3144673500 ps
CPU time 27.71 seconds
Started Aug 11 06:49:07 PM PDT 24
Finished Aug 11 06:49:35 PM PDT 24
Peak memory 248728 kb
Host smart-02f6660b-0bfe-4966-8aa1-e8a347679ea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3562706323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.3562706323
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.2379764261
Short name T383
Test name
Test status
Simulation time 3964933891 ps
CPU time 7.92 seconds
Started Aug 11 06:49:13 PM PDT 24
Finished Aug 11 06:49:21 PM PDT 24
Peak memory 242320 kb
Host smart-c8db0a32-0461-4d13-abfd-9a6934409f3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2379764261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.2379764261
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.554033698
Short name T104
Test name
Test status
Simulation time 254443063 ps
CPU time 5.64 seconds
Started Aug 11 06:49:13 PM PDT 24
Finished Aug 11 06:49:19 PM PDT 24
Peak memory 241956 kb
Host smart-8d924a78-c051-4503-bd53-a0391aff896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554033698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.554033698
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.3616014492
Short name T657
Test name
Test status
Simulation time 101550038053 ps
CPU time 1407.37 seconds
Started Aug 11 06:49:09 PM PDT 24
Finished Aug 11 07:12:36 PM PDT 24
Peak memory 363268 kb
Host smart-39c4af2d-53ac-4f9a-bc66-45acfeb58cd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616014492 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.3616014492
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.164598466
Short name T559
Test name
Test status
Simulation time 610316293 ps
CPU time 10.02 seconds
Started Aug 11 06:49:10 PM PDT 24
Finished Aug 11 06:49:20 PM PDT 24
Peak memory 242064 kb
Host smart-12bce82a-d80f-498d-84b0-7672aebd5e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164598466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.164598466
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.3999780018
Short name T940
Test name
Test status
Simulation time 692233009 ps
CPU time 2.02 seconds
Started Aug 11 06:49:14 PM PDT 24
Finished Aug 11 06:49:16 PM PDT 24
Peak memory 240472 kb
Host smart-9d1e2b93-f437-44b3-8c1f-5dd899d4e98b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999780018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.3999780018
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.2422165491
Short name T358
Test name
Test status
Simulation time 1535162464 ps
CPU time 21.96 seconds
Started Aug 11 06:49:14 PM PDT 24
Finished Aug 11 06:49:36 PM PDT 24
Peak memory 242416 kb
Host smart-7d59883b-b774-4d19-9538-5d73ac022fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422165491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.2422165491
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.2535748880
Short name T464
Test name
Test status
Simulation time 146321801 ps
CPU time 3.35 seconds
Started Aug 11 06:49:12 PM PDT 24
Finished Aug 11 06:49:16 PM PDT 24
Peak memory 241800 kb
Host smart-7a9e630e-77f5-49f3-bcae-948f6820c12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535748880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.2535748880
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.2312181756
Short name T884
Test name
Test status
Simulation time 147233631 ps
CPU time 3.8 seconds
Started Aug 11 06:49:14 PM PDT 24
Finished Aug 11 06:49:18 PM PDT 24
Peak memory 242332 kb
Host smart-1752f8ba-d5b6-4c92-9e8f-56ba6dcfc4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312181756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.2312181756
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.2482418204
Short name T903
Test name
Test status
Simulation time 2715275166 ps
CPU time 29.44 seconds
Started Aug 11 06:49:14 PM PDT 24
Finished Aug 11 06:49:43 PM PDT 24
Peak memory 244668 kb
Host smart-28712a5c-f69b-4524-b8b1-0c9f745d47bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482418204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.2482418204
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.1922641453
Short name T105
Test name
Test status
Simulation time 1230692125 ps
CPU time 23.03 seconds
Started Aug 11 06:49:14 PM PDT 24
Finished Aug 11 06:49:37 PM PDT 24
Peak memory 242316 kb
Host smart-01b43b34-abc7-4033-ad35-c5c45b621ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922641453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.1922641453
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.2098840506
Short name T1096
Test name
Test status
Simulation time 119252612 ps
CPU time 4.22 seconds
Started Aug 11 06:49:12 PM PDT 24
Finished Aug 11 06:49:17 PM PDT 24
Peak memory 242356 kb
Host smart-34d7ea27-b7cb-481b-9e5d-89154f4def99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098840506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.2098840506
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.3442289978
Short name T93
Test name
Test status
Simulation time 1423640980 ps
CPU time 23.82 seconds
Started Aug 11 06:49:12 PM PDT 24
Finished Aug 11 06:49:36 PM PDT 24
Peak memory 242120 kb
Host smart-3c88de2f-1e36-4729-bd19-641d9431175b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3442289978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.3442289978
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.2137400743
Short name T388
Test name
Test status
Simulation time 414235261 ps
CPU time 5.73 seconds
Started Aug 11 06:49:13 PM PDT 24
Finished Aug 11 06:49:19 PM PDT 24
Peak memory 241820 kb
Host smart-224c9236-e756-4de1-b338-28ec528c4bcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137400743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.2137400743
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.3581428350
Short name T350
Test name
Test status
Simulation time 367828158 ps
CPU time 5.08 seconds
Started Aug 11 06:49:12 PM PDT 24
Finished Aug 11 06:49:17 PM PDT 24
Peak memory 242012 kb
Host smart-d6031d7b-6944-49d8-9db3-3fedd87623f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581428350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.3581428350
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.3151061013
Short name T1159
Test name
Test status
Simulation time 20651938420 ps
CPU time 156.94 seconds
Started Aug 11 06:49:12 PM PDT 24
Finished Aug 11 06:51:49 PM PDT 24
Peak memory 265172 kb
Host smart-d8a61f58-2780-4a44-8fc9-8189fe7d31d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151061013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.3151061013
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.2937720015
Short name T1052
Test name
Test status
Simulation time 74120395481 ps
CPU time 682.48 seconds
Started Aug 11 06:49:13 PM PDT 24
Finished Aug 11 07:00:35 PM PDT 24
Peak memory 272892 kb
Host smart-15711d74-e803-467c-a9c1-badc0d925c7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937720015 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.2937720015
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.2952640670
Short name T303
Test name
Test status
Simulation time 765291876 ps
CPU time 11.25 seconds
Started Aug 11 06:49:14 PM PDT 24
Finished Aug 11 06:49:25 PM PDT 24
Peak memory 242060 kb
Host smart-be1bd048-771b-4f6b-95ef-76ab3353de9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952640670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.2952640670
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.2317715289
Short name T1099
Test name
Test status
Simulation time 141799351 ps
CPU time 1.9 seconds
Started Aug 11 06:49:19 PM PDT 24
Finished Aug 11 06:49:21 PM PDT 24
Peak memory 240392 kb
Host smart-bdc74cc4-7566-42ad-9707-d862cefc81e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317715289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.2317715289
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.2881439075
Short name T123
Test name
Test status
Simulation time 2418888617 ps
CPU time 16.3 seconds
Started Aug 11 06:49:18 PM PDT 24
Finished Aug 11 06:49:35 PM PDT 24
Peak memory 248612 kb
Host smart-d7d57ab8-892f-4b15-9bff-909da301d0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881439075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.2881439075
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.683460544
Short name T1186
Test name
Test status
Simulation time 1865862578 ps
CPU time 31.37 seconds
Started Aug 11 06:49:16 PM PDT 24
Finished Aug 11 06:49:48 PM PDT 24
Peak memory 243800 kb
Host smart-ae071976-efca-4232-b903-6104aa711023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683460544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.683460544
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.2567948426
Short name T1066
Test name
Test status
Simulation time 598106623 ps
CPU time 6.1 seconds
Started Aug 11 06:49:15 PM PDT 24
Finished Aug 11 06:49:21 PM PDT 24
Peak memory 241996 kb
Host smart-392bc483-8d5f-425f-9151-3d8b73e984c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567948426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2567948426
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.1188792942
Short name T1161
Test name
Test status
Simulation time 300566849 ps
CPU time 4.09 seconds
Started Aug 11 06:49:14 PM PDT 24
Finished Aug 11 06:49:18 PM PDT 24
Peak memory 242188 kb
Host smart-f7d32dba-fa91-4bc5-9dcc-435d31a2862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188792942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.1188792942
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.3902050834
Short name T85
Test name
Test status
Simulation time 1483470784 ps
CPU time 15.83 seconds
Started Aug 11 06:49:18 PM PDT 24
Finished Aug 11 06:49:33 PM PDT 24
Peak memory 243708 kb
Host smart-b6d10378-918f-4e89-a3e7-e604b996b2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902050834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.3902050834
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.1704215779
Short name T998
Test name
Test status
Simulation time 2971235631 ps
CPU time 17.35 seconds
Started Aug 11 06:49:18 PM PDT 24
Finished Aug 11 06:49:36 PM PDT 24
Peak memory 248612 kb
Host smart-919253d1-f498-426a-b278-d9f0dc95f01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704215779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.1704215779
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.3284094488
Short name T431
Test name
Test status
Simulation time 139441088 ps
CPU time 3.79 seconds
Started Aug 11 06:49:13 PM PDT 24
Finished Aug 11 06:49:17 PM PDT 24
Peak memory 241920 kb
Host smart-ef0e4d36-6db8-429a-b843-494ccf17c454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284094488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.3284094488
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.2727477173
Short name T689
Test name
Test status
Simulation time 1199941369 ps
CPU time 20.99 seconds
Started Aug 11 06:49:12 PM PDT 24
Finished Aug 11 06:49:33 PM PDT 24
Peak memory 241972 kb
Host smart-5965612a-f61f-45df-bf45-227da575a95e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727477173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.2727477173
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.1213615754
Short name T1076
Test name
Test status
Simulation time 1971819057 ps
CPU time 6.68 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:49:38 PM PDT 24
Peak memory 242296 kb
Host smart-4c5b975a-2632-4fa4-8c76-3222ef029db3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1213615754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.1213615754
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.619093991
Short name T1162
Test name
Test status
Simulation time 173287577 ps
CPU time 4.85 seconds
Started Aug 11 06:49:14 PM PDT 24
Finished Aug 11 06:49:19 PM PDT 24
Peak memory 241916 kb
Host smart-826fec19-833f-4016-a67d-e045a41de338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619093991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.619093991
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2600823863
Short name T1134
Test name
Test status
Simulation time 67336361010 ps
CPU time 649.09 seconds
Started Aug 11 06:49:20 PM PDT 24
Finished Aug 11 07:00:09 PM PDT 24
Peak memory 256980 kb
Host smart-e1996ce7-2c7e-4f8f-a60d-cef53a91a626
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600823863 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.2600823863
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.326204380
Short name T405
Test name
Test status
Simulation time 1375167632 ps
CPU time 17.12 seconds
Started Aug 11 06:49:30 PM PDT 24
Finished Aug 11 06:49:47 PM PDT 24
Peak memory 242008 kb
Host smart-b0f69605-6c29-4d7f-8692-c254d597de8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326204380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.326204380
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.1296397310
Short name T497
Test name
Test status
Simulation time 100843202 ps
CPU time 1.76 seconds
Started Aug 11 06:49:20 PM PDT 24
Finished Aug 11 06:49:22 PM PDT 24
Peak memory 240584 kb
Host smart-7f7beb45-73ce-4be7-99f5-764a68dc8f50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296397310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.1296397310
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.2386978785
Short name T1184
Test name
Test status
Simulation time 904433673 ps
CPU time 26.12 seconds
Started Aug 11 06:49:21 PM PDT 24
Finished Aug 11 06:49:47 PM PDT 24
Peak memory 241988 kb
Host smart-7b564240-36f2-4d9c-8ec0-85563b198ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386978785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.2386978785
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.3147876008
Short name T607
Test name
Test status
Simulation time 1771289641 ps
CPU time 12.41 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:49:44 PM PDT 24
Peak memory 242036 kb
Host smart-7df659dd-3ba9-4bfd-ac6b-d3f660e24577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147876008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.3147876008
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.2642797961
Short name T79
Test name
Test status
Simulation time 157369760 ps
CPU time 4.26 seconds
Started Aug 11 06:49:30 PM PDT 24
Finished Aug 11 06:49:35 PM PDT 24
Peak memory 242384 kb
Host smart-01f47931-9474-4f54-95fc-88e228106ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642797961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.2642797961
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.1168071602
Short name T1092
Test name
Test status
Simulation time 4758548433 ps
CPU time 11.33 seconds
Started Aug 11 06:49:19 PM PDT 24
Finished Aug 11 06:49:30 PM PDT 24
Peak memory 243224 kb
Host smart-fd2c6483-f583-4360-8a28-c413ab41534c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168071602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.1168071602
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.732019801
Short name T768
Test name
Test status
Simulation time 2679599397 ps
CPU time 39.12 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:50:11 PM PDT 24
Peak memory 242516 kb
Host smart-7665a353-78b7-4ab4-8bad-54ee31472b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732019801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.732019801
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.1188778483
Short name T639
Test name
Test status
Simulation time 537756288 ps
CPU time 6.33 seconds
Started Aug 11 06:49:21 PM PDT 24
Finished Aug 11 06:49:27 PM PDT 24
Peak memory 241980 kb
Host smart-5ee23fde-3dcf-4966-a3ca-c5a02aa58810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188778483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.1188778483
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.621492010
Short name T396
Test name
Test status
Simulation time 1453825712 ps
CPU time 11.51 seconds
Started Aug 11 06:49:17 PM PDT 24
Finished Aug 11 06:49:29 PM PDT 24
Peak memory 248632 kb
Host smart-5dc21653-6721-4f15-8778-2e42c3bb8dc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621492010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.621492010
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.1268311538
Short name T180
Test name
Test status
Simulation time 622733989 ps
CPU time 11.14 seconds
Started Aug 11 06:49:19 PM PDT 24
Finished Aug 11 06:49:31 PM PDT 24
Peak memory 241976 kb
Host smart-0e02b382-e22c-4086-9c8e-f87979be9395
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268311538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.1268311538
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.120651515
Short name T867
Test name
Test status
Simulation time 1165052308 ps
CPU time 7.22 seconds
Started Aug 11 06:49:18 PM PDT 24
Finished Aug 11 06:49:26 PM PDT 24
Peak memory 248440 kb
Host smart-332b8bb9-2d65-4856-9305-eb9667f29ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120651515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.120651515
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.429323047
Short name T14
Test name
Test status
Simulation time 264570970853 ps
CPU time 3008.84 seconds
Started Aug 11 06:49:20 PM PDT 24
Finished Aug 11 07:39:29 PM PDT 24
Peak memory 330028 kb
Host smart-1ff7037a-93ef-4db9-ab20-fdc8ed7e6969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429323047 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.429323047
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.92850494
Short name T476
Test name
Test status
Simulation time 1560379733 ps
CPU time 19.72 seconds
Started Aug 11 06:49:30 PM PDT 24
Finished Aug 11 06:49:50 PM PDT 24
Peak memory 242016 kb
Host smart-42db8365-44d2-4fce-9365-84fe34ffc0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92850494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.92850494
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.3811531787
Short name T302
Test name
Test status
Simulation time 352073021 ps
CPU time 2.34 seconds
Started Aug 11 06:49:27 PM PDT 24
Finished Aug 11 06:49:29 PM PDT 24
Peak memory 240492 kb
Host smart-f2476cc3-bd22-4846-8b37-bdba8c965a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811531787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.3811531787
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.2537526076
Short name T669
Test name
Test status
Simulation time 812490490 ps
CPU time 18.39 seconds
Started Aug 11 06:49:25 PM PDT 24
Finished Aug 11 06:49:44 PM PDT 24
Peak memory 248596 kb
Host smart-3f2f40d6-94be-4186-ac4d-b3c33857fae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537526076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2537526076
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.3896074443
Short name T675
Test name
Test status
Simulation time 5825074773 ps
CPU time 48.93 seconds
Started Aug 11 06:49:25 PM PDT 24
Finished Aug 11 06:50:14 PM PDT 24
Peak memory 255336 kb
Host smart-7b12279d-f26d-41fe-8b0a-82df3de2a740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896074443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.3896074443
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.1705521913
Short name T850
Test name
Test status
Simulation time 1555947268 ps
CPU time 10.81 seconds
Started Aug 11 06:49:24 PM PDT 24
Finished Aug 11 06:49:35 PM PDT 24
Peak memory 241876 kb
Host smart-fbccf6af-af4c-4257-a8be-337d29702b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705521913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.1705521913
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.4060860516
Short name T493
Test name
Test status
Simulation time 1836908293 ps
CPU time 18.98 seconds
Started Aug 11 06:49:25 PM PDT 24
Finished Aug 11 06:49:44 PM PDT 24
Peak memory 242580 kb
Host smart-30fa10f5-a4b8-46bb-946b-053d5c9b0e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060860516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.4060860516
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.2269579087
Short name T881
Test name
Test status
Simulation time 645363621 ps
CPU time 5.43 seconds
Started Aug 11 06:49:27 PM PDT 24
Finished Aug 11 06:49:32 PM PDT 24
Peak memory 241840 kb
Host smart-bd145aa0-b9b1-40e3-94a9-ab1fbd7cf909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269579087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.2269579087
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.1062887860
Short name T206
Test name
Test status
Simulation time 368467052 ps
CPU time 11.69 seconds
Started Aug 11 06:49:25 PM PDT 24
Finished Aug 11 06:49:37 PM PDT 24
Peak memory 241880 kb
Host smart-5c350fb6-f782-42db-909e-47f0a3ad2258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062887860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1062887860
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.90134108
Short name T1190
Test name
Test status
Simulation time 641477401 ps
CPU time 20.03 seconds
Started Aug 11 06:49:24 PM PDT 24
Finished Aug 11 06:49:45 PM PDT 24
Peak memory 242152 kb
Host smart-ba0fda7b-03fb-4688-a800-0cb8a4aea194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90134108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.90134108
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.1207811433
Short name T797
Test name
Test status
Simulation time 658614901 ps
CPU time 7.29 seconds
Started Aug 11 06:49:25 PM PDT 24
Finished Aug 11 06:49:33 PM PDT 24
Peak memory 248688 kb
Host smart-83031269-e55c-4a65-b8e1-ca195dc7097c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207811433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.1207811433
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.3048359066
Short name T411
Test name
Test status
Simulation time 521680160 ps
CPU time 5.83 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:49:37 PM PDT 24
Peak memory 242192 kb
Host smart-b8f34019-62b4-4e99-b7da-b5e73b99cdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048359066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3048359066
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.3458653072
Short name T84
Test name
Test status
Simulation time 7993607098 ps
CPU time 62.79 seconds
Started Aug 11 06:49:25 PM PDT 24
Finished Aug 11 06:50:28 PM PDT 24
Peak memory 244300 kb
Host smart-ab715011-76c5-459a-995e-bb3803b2eef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458653072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.3458653072
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.3827369728
Short name T16
Test name
Test status
Simulation time 410099582578 ps
CPU time 933.24 seconds
Started Aug 11 06:49:25 PM PDT 24
Finished Aug 11 07:04:59 PM PDT 24
Peak memory 373720 kb
Host smart-9a96c97a-2fa0-4fd6-8bd9-b92770a5cb6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827369728 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.3827369728
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.3662229755
Short name T804
Test name
Test status
Simulation time 3870240182 ps
CPU time 22.28 seconds
Started Aug 11 06:49:25 PM PDT 24
Finished Aug 11 06:49:48 PM PDT 24
Peak memory 242616 kb
Host smart-029c35e8-9a59-43c8-b6a4-3fbb40fbbe66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662229755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.3662229755
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.3682743896
Short name T697
Test name
Test status
Simulation time 50292162 ps
CPU time 1.7 seconds
Started Aug 11 06:49:29 PM PDT 24
Finished Aug 11 06:49:31 PM PDT 24
Peak memory 240580 kb
Host smart-f59d101f-f0d0-4c07-9946-858ce294e4cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682743896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.3682743896
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.11943808
Short name T55
Test name
Test status
Simulation time 9933202556 ps
CPU time 44.38 seconds
Started Aug 11 06:49:24 PM PDT 24
Finished Aug 11 06:50:09 PM PDT 24
Peak memory 245000 kb
Host smart-fe75cadf-efc5-4b7f-960b-6cffc0ad00ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11943808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.11943808
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.2074880799
Short name T1157
Test name
Test status
Simulation time 927485786 ps
CPU time 29.49 seconds
Started Aug 11 06:49:25 PM PDT 24
Finished Aug 11 06:49:55 PM PDT 24
Peak memory 242360 kb
Host smart-f2105550-3852-43bf-85c6-2d1358fac904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074880799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.2074880799
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.1817450066
Short name T678
Test name
Test status
Simulation time 699419643 ps
CPU time 19.18 seconds
Started Aug 11 06:49:27 PM PDT 24
Finished Aug 11 06:49:46 PM PDT 24
Peak memory 241928 kb
Host smart-131698a0-23be-45f9-891a-253cd3f7457f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817450066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.1817450066
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.2834368846
Short name T824
Test name
Test status
Simulation time 142452010 ps
CPU time 4.16 seconds
Started Aug 11 06:49:24 PM PDT 24
Finished Aug 11 06:49:28 PM PDT 24
Peak memory 242016 kb
Host smart-6ffa004a-5621-42d8-b07b-dd7fe5ab32d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834368846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.2834368846
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.1183335460
Short name T159
Test name
Test status
Simulation time 1988518943 ps
CPU time 42.48 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:50:13 PM PDT 24
Peak memory 255352 kb
Host smart-1da297c9-9917-498f-9b69-2abafb7aae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183335460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.1183335460
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.2005824751
Short name T981
Test name
Test status
Simulation time 1738809211 ps
CPU time 21.28 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:49:52 PM PDT 24
Peak memory 248632 kb
Host smart-caed9931-27e0-4150-879a-c870e341a3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005824751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2005824751
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.3338545311
Short name T654
Test name
Test status
Simulation time 585266309 ps
CPU time 19.22 seconds
Started Aug 11 06:49:26 PM PDT 24
Finished Aug 11 06:49:45 PM PDT 24
Peak memory 242560 kb
Host smart-bb5140c9-f76a-4d05-85ba-2d54a19e019f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3338545311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.3338545311
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.1582488423
Short name T315
Test name
Test status
Simulation time 3540517614 ps
CPU time 8.3 seconds
Started Aug 11 06:49:33 PM PDT 24
Finished Aug 11 06:49:41 PM PDT 24
Peak memory 242000 kb
Host smart-1754b2be-516f-4083-b5fc-aec29cf6effb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1582488423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.1582488423
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.3222174044
Short name T642
Test name
Test status
Simulation time 1031090267 ps
CPU time 10.51 seconds
Started Aug 11 06:49:26 PM PDT 24
Finished Aug 11 06:49:36 PM PDT 24
Peak memory 242356 kb
Host smart-cc03b862-a927-412d-8c7c-58cde6dd0400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222174044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3222174044
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.994092761
Short name T1017
Test name
Test status
Simulation time 26450853950 ps
CPU time 317.63 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:54:49 PM PDT 24
Peak memory 268040 kb
Host smart-a617bb9b-4ee4-409c-91b1-6a1985a2ca2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994092761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.
994092761
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.3124677982
Short name T145
Test name
Test status
Simulation time 61747028903 ps
CPU time 611.52 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:59:43 PM PDT 24
Peak memory 279580 kb
Host smart-f39dbcd8-7035-4745-9760-956473e17c72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124677982 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.3124677982
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.614477606
Short name T511
Test name
Test status
Simulation time 903800443 ps
CPU time 10.06 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:49:41 PM PDT 24
Peak memory 241964 kb
Host smart-bf4e7a24-55ce-4deb-aa8f-6aeeaccd0abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614477606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.614477606
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.367983941
Short name T958
Test name
Test status
Simulation time 198025715 ps
CPU time 1.77 seconds
Started Aug 11 06:49:30 PM PDT 24
Finished Aug 11 06:49:32 PM PDT 24
Peak memory 240664 kb
Host smart-10378072-430d-4b61-831a-da726ec3a022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367983941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.367983941
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.1384870806
Short name T113
Test name
Test status
Simulation time 271336549 ps
CPU time 7.76 seconds
Started Aug 11 06:49:32 PM PDT 24
Finished Aug 11 06:49:40 PM PDT 24
Peak memory 248544 kb
Host smart-64d9a23c-fff1-41a9-9721-554a3c219ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384870806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.1384870806
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.494746253
Short name T1182
Test name
Test status
Simulation time 14453863259 ps
CPU time 38.2 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:50:09 PM PDT 24
Peak memory 245132 kb
Host smart-c35e61e8-b9e2-40d0-8643-4719b5600167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494746253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.494746253
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.1351596066
Short name T916
Test name
Test status
Simulation time 1680248887 ps
CPU time 23.23 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:49:55 PM PDT 24
Peak memory 242020 kb
Host smart-cb688707-2c41-4006-8891-ad50fd69f6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351596066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.1351596066
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.1625918962
Short name T712
Test name
Test status
Simulation time 140139823 ps
CPU time 3.7 seconds
Started Aug 11 06:49:33 PM PDT 24
Finished Aug 11 06:49:36 PM PDT 24
Peak memory 242468 kb
Host smart-2767e543-76f1-4204-a549-239eff98d72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625918962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.1625918962
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.1295809932
Short name T1139
Test name
Test status
Simulation time 534517529 ps
CPU time 13.7 seconds
Started Aug 11 06:49:29 PM PDT 24
Finished Aug 11 06:49:43 PM PDT 24
Peak memory 242096 kb
Host smart-542472f3-a37c-44f0-853f-f77412ff2ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295809932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.1295809932
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.1567179015
Short name T696
Test name
Test status
Simulation time 714030302 ps
CPU time 14.71 seconds
Started Aug 11 06:49:32 PM PDT 24
Finished Aug 11 06:49:47 PM PDT 24
Peak memory 242420 kb
Host smart-99fe9d8c-d7de-4840-98bf-7c47e9c48f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567179015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.1567179015
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.1103170711
Short name T813
Test name
Test status
Simulation time 206042759 ps
CPU time 6.96 seconds
Started Aug 11 06:49:30 PM PDT 24
Finished Aug 11 06:49:37 PM PDT 24
Peak memory 241864 kb
Host smart-c063e42b-7846-425f-9153-5ca400623408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103170711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.1103170711
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.2371336906
Short name T680
Test name
Test status
Simulation time 2781123198 ps
CPU time 23.54 seconds
Started Aug 11 06:49:32 PM PDT 24
Finished Aug 11 06:49:56 PM PDT 24
Peak memory 248732 kb
Host smart-a6bfd4e1-8f48-4054-b817-02656f5ad209
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371336906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.2371336906
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.1823358656
Short name T573
Test name
Test status
Simulation time 298646337 ps
CPU time 4.56 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:49:35 PM PDT 24
Peak memory 241948 kb
Host smart-029c2662-2a7e-46e2-b96e-53f0fb388688
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823358656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.1823358656
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.3262397458
Short name T564
Test name
Test status
Simulation time 410933107 ps
CPU time 11.29 seconds
Started Aug 11 06:49:30 PM PDT 24
Finished Aug 11 06:49:42 PM PDT 24
Peak memory 242020 kb
Host smart-625eed37-a5ed-44a2-a2df-58cc2c712585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262397458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.3262397458
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.2438958253
Short name T760
Test name
Test status
Simulation time 208039845369 ps
CPU time 1386.55 seconds
Started Aug 11 06:49:30 PM PDT 24
Finished Aug 11 07:12:37 PM PDT 24
Peak memory 306864 kb
Host smart-f150fe79-9020-453e-9922-6c4d799ae89b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438958253 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.2438958253
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.1848479798
Short name T987
Test name
Test status
Simulation time 579302435 ps
CPU time 13.98 seconds
Started Aug 11 06:49:30 PM PDT 24
Finished Aug 11 06:49:45 PM PDT 24
Peak memory 242288 kb
Host smart-0f231ec4-433d-4b3b-9bbc-929ff4099908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848479798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1848479798
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.3656651401
Short name T1051
Test name
Test status
Simulation time 89553743 ps
CPU time 1.58 seconds
Started Aug 11 06:49:35 PM PDT 24
Finished Aug 11 06:49:37 PM PDT 24
Peak memory 240720 kb
Host smart-2e5aa525-9fc8-45aa-bd7d-2aa3273fcc15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656651401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.3656651401
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.2103865921
Short name T127
Test name
Test status
Simulation time 5015624186 ps
CPU time 39.41 seconds
Started Aug 11 06:49:37 PM PDT 24
Finished Aug 11 06:50:17 PM PDT 24
Peak memory 248620 kb
Host smart-9d4a210d-55e2-4c50-8414-b0f94942a1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103865921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.2103865921
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.3364896930
Short name T175
Test name
Test status
Simulation time 1219796476 ps
CPU time 19.85 seconds
Started Aug 11 06:49:37 PM PDT 24
Finished Aug 11 06:49:57 PM PDT 24
Peak memory 241900 kb
Host smart-9b9f0c48-8ef2-4b92-bc4f-d8d02a90f504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364896930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.3364896930
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.3662887226
Short name T763
Test name
Test status
Simulation time 545269583 ps
CPU time 12.96 seconds
Started Aug 11 06:49:37 PM PDT 24
Finished Aug 11 06:49:50 PM PDT 24
Peak memory 242412 kb
Host smart-aa48fe6c-28e0-446d-9c85-5bf2fbfda27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662887226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.3662887226
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.3938197648
Short name T195
Test name
Test status
Simulation time 460818909 ps
CPU time 3.83 seconds
Started Aug 11 06:49:39 PM PDT 24
Finished Aug 11 06:49:43 PM PDT 24
Peak memory 242276 kb
Host smart-90e6e640-aa70-4488-969b-25506766d115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938197648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.3938197648
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.1926198392
Short name T932
Test name
Test status
Simulation time 1327255269 ps
CPU time 26.52 seconds
Started Aug 11 06:49:37 PM PDT 24
Finished Aug 11 06:50:04 PM PDT 24
Peak memory 244248 kb
Host smart-e0f08519-739a-41b5-bc08-66c067b70753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926198392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.1926198392
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.1823007514
Short name T394
Test name
Test status
Simulation time 1463276110 ps
CPU time 18.97 seconds
Started Aug 11 06:49:38 PM PDT 24
Finished Aug 11 06:49:57 PM PDT 24
Peak memory 242252 kb
Host smart-553fc99f-edfd-4617-bce5-7262e236e8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823007514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.1823007514
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.3140230426
Short name T872
Test name
Test status
Simulation time 934114979 ps
CPU time 13.65 seconds
Started Aug 11 06:49:36 PM PDT 24
Finished Aug 11 06:49:50 PM PDT 24
Peak memory 242264 kb
Host smart-63f8cf5a-3c39-492b-ad90-6d9307a679a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140230426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3140230426
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.686947334
Short name T707
Test name
Test status
Simulation time 1002018294 ps
CPU time 25.98 seconds
Started Aug 11 06:49:37 PM PDT 24
Finished Aug 11 06:50:03 PM PDT 24
Peak memory 241924 kb
Host smart-3e2c52f2-78b4-4467-84f2-bccde8844009
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=686947334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.686947334
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.3040828905
Short name T700
Test name
Test status
Simulation time 735333759 ps
CPU time 6.29 seconds
Started Aug 11 06:49:36 PM PDT 24
Finished Aug 11 06:49:43 PM PDT 24
Peak memory 242068 kb
Host smart-165c0a53-6198-45a3-bf25-eea197bf15f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040828905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.3040828905
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.3835660226
Short name T90
Test name
Test status
Simulation time 2751101029 ps
CPU time 8.07 seconds
Started Aug 11 06:49:31 PM PDT 24
Finished Aug 11 06:49:39 PM PDT 24
Peak memory 242060 kb
Host smart-d81476a0-8d61-4b64-b1a6-773e106ca282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835660226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.3835660226
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.855811453
Short name T1000
Test name
Test status
Simulation time 6106072905 ps
CPU time 50.77 seconds
Started Aug 11 06:49:36 PM PDT 24
Finished Aug 11 06:50:27 PM PDT 24
Peak memory 241628 kb
Host smart-31810f3c-be52-45d3-b91b-913fa6565f15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855811453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.
855811453
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.1572077955
Short name T757
Test name
Test status
Simulation time 951431395 ps
CPU time 16.04 seconds
Started Aug 11 06:49:36 PM PDT 24
Finished Aug 11 06:49:52 PM PDT 24
Peak memory 242360 kb
Host smart-eb69255b-5df5-4cff-bf5a-fcedf3c185b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572077955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.1572077955
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.1552893680
Short name T956
Test name
Test status
Simulation time 94797581 ps
CPU time 1.52 seconds
Started Aug 11 06:46:24 PM PDT 24
Finished Aug 11 06:46:26 PM PDT 24
Peak memory 240664 kb
Host smart-e48f4a14-c7e4-4d8c-b825-519a540466b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552893680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.1552893680
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.2702680984
Short name T260
Test name
Test status
Simulation time 1477049156 ps
CPU time 23.38 seconds
Started Aug 11 06:46:22 PM PDT 24
Finished Aug 11 06:46:46 PM PDT 24
Peak memory 248688 kb
Host smart-1d4919a7-b6b6-48e0-9278-260ead1fba41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702680984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.2702680984
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.924204369
Short name T448
Test name
Test status
Simulation time 9836006093 ps
CPU time 65.04 seconds
Started Aug 11 06:46:20 PM PDT 24
Finished Aug 11 06:47:25 PM PDT 24
Peak memory 242920 kb
Host smart-23ac341a-49fe-4d2b-a4ec-3ab66d939bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924204369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.924204369
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.2247147931
Short name T130
Test name
Test status
Simulation time 12666772759 ps
CPU time 30.52 seconds
Started Aug 11 06:46:18 PM PDT 24
Finished Aug 11 06:46:49 PM PDT 24
Peak memory 242112 kb
Host smart-831a8327-0703-4c3e-b937-1cafe2a286bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247147931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.2247147931
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.3419693706
Short name T805
Test name
Test status
Simulation time 3559084828 ps
CPU time 40.13 seconds
Started Aug 11 06:46:21 PM PDT 24
Finished Aug 11 06:47:01 PM PDT 24
Peak memory 242480 kb
Host smart-1a36e620-f7b1-4853-bcb6-b1099dc3cb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419693706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.3419693706
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.2568720456
Short name T771
Test name
Test status
Simulation time 613431367 ps
CPU time 5.06 seconds
Started Aug 11 06:46:15 PM PDT 24
Finished Aug 11 06:46:20 PM PDT 24
Peak memory 242420 kb
Host smart-85927ee0-e200-4f84-bb78-8ca8099cb272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568720456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.2568720456
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.3548370240
Short name T1028
Test name
Test status
Simulation time 292833944 ps
CPU time 8.84 seconds
Started Aug 11 06:46:20 PM PDT 24
Finished Aug 11 06:46:29 PM PDT 24
Peak memory 242192 kb
Host smart-40cc0407-f1e1-48e6-84a9-e43686cee8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548370240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.3548370240
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.3775276443
Short name T98
Test name
Test status
Simulation time 1653696097 ps
CPU time 19.56 seconds
Started Aug 11 06:46:20 PM PDT 24
Finished Aug 11 06:46:40 PM PDT 24
Peak memory 242100 kb
Host smart-81bc6b38-1596-4006-850f-0543d7aa7461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775276443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3775276443
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.1682980776
Short name T829
Test name
Test status
Simulation time 797932896 ps
CPU time 11.43 seconds
Started Aug 11 06:46:19 PM PDT 24
Finished Aug 11 06:46:30 PM PDT 24
Peak memory 242088 kb
Host smart-ebee6514-6f12-4505-b3ca-d945f66c7154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682980776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.1682980776
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.2626822049
Short name T513
Test name
Test status
Simulation time 1041846792 ps
CPU time 6.28 seconds
Started Aug 11 06:46:20 PM PDT 24
Finished Aug 11 06:46:27 PM PDT 24
Peak memory 242252 kb
Host smart-d5fa38e3-d9cc-4a99-b956-897073c17ed5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2626822049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.2626822049
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.1705805717
Short name T793
Test name
Test status
Simulation time 437822422 ps
CPU time 3.71 seconds
Started Aug 11 06:46:22 PM PDT 24
Finished Aug 11 06:46:26 PM PDT 24
Peak memory 248368 kb
Host smart-071f91da-49a1-4bc5-8cad-5275d0eef329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705805717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.1705805717
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.2926216761
Short name T601
Test name
Test status
Simulation time 710964737 ps
CPU time 9.1 seconds
Started Aug 11 06:46:15 PM PDT 24
Finished Aug 11 06:46:24 PM PDT 24
Peak memory 242344 kb
Host smart-83ff8953-680b-40e9-9352-85487a7cb7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926216761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.2926216761
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.3618334503
Short name T728
Test name
Test status
Simulation time 297466086 ps
CPU time 11.97 seconds
Started Aug 11 06:46:26 PM PDT 24
Finished Aug 11 06:46:38 PM PDT 24
Peak memory 242752 kb
Host smart-8ae98af2-c410-42db-921b-c2bf22e4aee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618334503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
3618334503
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.3273980042
Short name T292
Test name
Test status
Simulation time 215797491050 ps
CPU time 1377.38 seconds
Started Aug 11 06:46:26 PM PDT 24
Finished Aug 11 07:09:23 PM PDT 24
Peak memory 347112 kb
Host smart-339314f0-e2ef-4bbb-8e85-20a389d2844b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273980042 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.3273980042
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.616300274
Short name T1020
Test name
Test status
Simulation time 4602433406 ps
CPU time 38.8 seconds
Started Aug 11 06:46:26 PM PDT 24
Finished Aug 11 06:47:05 PM PDT 24
Peak memory 242160 kb
Host smart-c64f54c3-c8e9-42c6-a952-28562e9af10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616300274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.616300274
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.1352360134
Short name T197
Test name
Test status
Simulation time 543088040 ps
CPU time 3.68 seconds
Started Aug 11 06:49:37 PM PDT 24
Finished Aug 11 06:49:41 PM PDT 24
Peak memory 241896 kb
Host smart-0a31ea7c-7224-4d21-8d41-31958cb5e3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352360134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.1352360134
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.1024953209
Short name T272
Test name
Test status
Simulation time 344434033 ps
CPU time 6.58 seconds
Started Aug 11 06:49:35 PM PDT 24
Finished Aug 11 06:49:41 PM PDT 24
Peak memory 242244 kb
Host smart-15388e3a-7ac6-4c15-b744-071ee3d0abb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024953209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.1024953209
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.4009328474
Short name T139
Test name
Test status
Simulation time 52396551592 ps
CPU time 1393.34 seconds
Started Aug 11 06:49:39 PM PDT 24
Finished Aug 11 07:12:53 PM PDT 24
Peak memory 273412 kb
Host smart-a2fa8d39-872d-4254-84eb-2cc74457587c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009328474 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.4009328474
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.1278274599
Short name T112
Test name
Test status
Simulation time 467997185 ps
CPU time 4.05 seconds
Started Aug 11 06:49:38 PM PDT 24
Finished Aug 11 06:49:42 PM PDT 24
Peak memory 242280 kb
Host smart-ebffe117-6357-4c26-a8fe-26c487cfd48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278274599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.1278274599
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.1487288919
Short name T835
Test name
Test status
Simulation time 282821729 ps
CPU time 3.81 seconds
Started Aug 11 06:49:37 PM PDT 24
Finished Aug 11 06:49:41 PM PDT 24
Peak memory 241864 kb
Host smart-5b602604-2814-480d-b6b4-1cca02bc9c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487288919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.1487288919
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.805363558
Short name T1062
Test name
Test status
Simulation time 180958868899 ps
CPU time 4162.53 seconds
Started Aug 11 06:49:37 PM PDT 24
Finished Aug 11 07:59:00 PM PDT 24
Peak memory 957692 kb
Host smart-692e0aa5-c69b-4952-b855-e056b26688ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805363558 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.805363558
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.1564529896
Short name T1037
Test name
Test status
Simulation time 167926293 ps
CPU time 4.38 seconds
Started Aug 11 06:49:37 PM PDT 24
Finished Aug 11 06:49:42 PM PDT 24
Peak memory 242160 kb
Host smart-27d180b2-bac5-441a-b3f1-ff4be0d2ecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564529896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.1564529896
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.3500065244
Short name T433
Test name
Test status
Simulation time 387756587 ps
CPU time 4.6 seconds
Started Aug 11 06:49:43 PM PDT 24
Finished Aug 11 06:49:47 PM PDT 24
Peak memory 242260 kb
Host smart-d734187c-26dd-4002-b855-420b30986736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500065244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.3500065244
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.1193719125
Short name T770
Test name
Test status
Simulation time 172967003 ps
CPU time 3.71 seconds
Started Aug 11 06:49:42 PM PDT 24
Finished Aug 11 06:49:45 PM PDT 24
Peak memory 242016 kb
Host smart-f4190994-43e4-4027-a8e6-6067153568d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193719125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.1193719125
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.95190366
Short name T548
Test name
Test status
Simulation time 285171594 ps
CPU time 8.49 seconds
Started Aug 11 06:49:42 PM PDT 24
Finished Aug 11 06:49:50 PM PDT 24
Peak memory 241984 kb
Host smart-7327ba6c-2fe5-42f3-84d3-8d87f7e9e1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95190366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.95190366
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.3367599835
Short name T419
Test name
Test status
Simulation time 186298558 ps
CPU time 3.63 seconds
Started Aug 11 06:49:42 PM PDT 24
Finished Aug 11 06:49:46 PM PDT 24
Peak memory 242184 kb
Host smart-70f321ab-aa5c-481d-a1cc-2f55decb7cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367599835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.3367599835
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.3358322495
Short name T353
Test name
Test status
Simulation time 1159270497 ps
CPU time 12.93 seconds
Started Aug 11 06:49:43 PM PDT 24
Finished Aug 11 06:49:56 PM PDT 24
Peak memory 242488 kb
Host smart-16ce5f31-bfa9-4908-a8c9-b9ee1dcc91b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358322495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3358322495
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.3493120966
Short name T703
Test name
Test status
Simulation time 309029330902 ps
CPU time 2402.7 seconds
Started Aug 11 06:49:43 PM PDT 24
Finished Aug 11 07:29:46 PM PDT 24
Peak memory 509956 kb
Host smart-7253e3e4-17d1-4a8e-84b5-4b5e60d1609c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493120966 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.3493120966
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.2675690046
Short name T788
Test name
Test status
Simulation time 247287041 ps
CPU time 4.12 seconds
Started Aug 11 06:49:43 PM PDT 24
Finished Aug 11 06:49:47 PM PDT 24
Peak memory 242260 kb
Host smart-6092f120-9588-48b3-bb87-61399c14e1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675690046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2675690046
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.827882150
Short name T1100
Test name
Test status
Simulation time 1608334293 ps
CPU time 5.72 seconds
Started Aug 11 06:49:47 PM PDT 24
Finished Aug 11 06:49:52 PM PDT 24
Peak memory 241940 kb
Host smart-f309a453-e57b-4ea0-a24f-b69b681ec579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827882150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.827882150
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.1956846232
Short name T295
Test name
Test status
Simulation time 1533286459408 ps
CPU time 2801.55 seconds
Started Aug 11 06:49:42 PM PDT 24
Finished Aug 11 07:36:24 PM PDT 24
Peak memory 620772 kb
Host smart-84337e63-2bff-4504-bef4-7b58e84d8387
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956846232 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.1956846232
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.742090036
Short name T951
Test name
Test status
Simulation time 390615998 ps
CPU time 3.24 seconds
Started Aug 11 06:49:42 PM PDT 24
Finished Aug 11 06:49:46 PM PDT 24
Peak memory 242424 kb
Host smart-7d9754d4-187a-447b-bc0c-8c3dc9b47b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742090036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.742090036
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.2065793130
Short name T673
Test name
Test status
Simulation time 1058510209 ps
CPU time 12.77 seconds
Started Aug 11 06:49:42 PM PDT 24
Finished Aug 11 06:49:55 PM PDT 24
Peak memory 241880 kb
Host smart-a8b4abb9-3836-4aad-8b62-1f490808e446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065793130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.2065793130
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.1178892779
Short name T993
Test name
Test status
Simulation time 1407257535024 ps
CPU time 3597.09 seconds
Started Aug 11 06:49:43 PM PDT 24
Finished Aug 11 07:49:40 PM PDT 24
Peak memory 596196 kb
Host smart-cc21182e-2000-463d-89fd-009ad34e7592
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178892779 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.1178892779
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.2147645379
Short name T547
Test name
Test status
Simulation time 1797132566 ps
CPU time 5.1 seconds
Started Aug 11 06:49:42 PM PDT 24
Finished Aug 11 06:49:47 PM PDT 24
Peak memory 242300 kb
Host smart-1fffeed4-2dad-4a56-b7d2-4445939f9e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147645379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.2147645379
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.1383591263
Short name T624
Test name
Test status
Simulation time 143624809 ps
CPU time 4.96 seconds
Started Aug 11 06:49:47 PM PDT 24
Finished Aug 11 06:49:52 PM PDT 24
Peak memory 241972 kb
Host smart-e5075a59-100c-4195-8ced-831266c6f08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383591263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1383591263
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.1679929954
Short name T254
Test name
Test status
Simulation time 666091018899 ps
CPU time 1125.57 seconds
Started Aug 11 06:49:42 PM PDT 24
Finished Aug 11 07:08:28 PM PDT 24
Peak memory 369660 kb
Host smart-b0f21fb2-a3ec-4384-84b0-2636d2fb748d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679929954 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.1679929954
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.795339265
Short name T597
Test name
Test status
Simulation time 1539840009 ps
CPU time 11.45 seconds
Started Aug 11 06:49:46 PM PDT 24
Finished Aug 11 06:49:57 PM PDT 24
Peak memory 241816 kb
Host smart-34694261-76a3-48f3-8017-392bb839df86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795339265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.795339265
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.3651975065
Short name T341
Test name
Test status
Simulation time 129895948681 ps
CPU time 1045.17 seconds
Started Aug 11 06:49:42 PM PDT 24
Finished Aug 11 07:07:08 PM PDT 24
Peak memory 258532 kb
Host smart-964e45fd-21d1-4440-a7c9-cb6677e763fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651975065 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.3651975065
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.3136696035
Short name T212
Test name
Test status
Simulation time 275084267 ps
CPU time 3.94 seconds
Started Aug 11 06:49:45 PM PDT 24
Finished Aug 11 06:49:49 PM PDT 24
Peak memory 242316 kb
Host smart-72b81c38-38a5-4764-a197-bbcf85655b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136696035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.3136696035
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.2263347111
Short name T704
Test name
Test status
Simulation time 2693397104 ps
CPU time 8.22 seconds
Started Aug 11 06:49:41 PM PDT 24
Finished Aug 11 06:49:50 PM PDT 24
Peak memory 242000 kb
Host smart-581357b4-c496-4d7f-a438-9acb66a8c9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263347111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.2263347111
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.3059945579
Short name T545
Test name
Test status
Simulation time 55299226 ps
CPU time 1.72 seconds
Started Aug 11 06:46:28 PM PDT 24
Finished Aug 11 06:46:30 PM PDT 24
Peak memory 240676 kb
Host smart-a5ae25e0-3855-4b3d-9575-d12039fbb8f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059945579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.3059945579
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.3705453368
Short name T705
Test name
Test status
Simulation time 16312268662 ps
CPU time 89.92 seconds
Started Aug 11 06:46:25 PM PDT 24
Finished Aug 11 06:47:55 PM PDT 24
Peak memory 248724 kb
Host smart-e6c991c5-f2a6-4ced-a57e-947968a92c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705453368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.3705453368
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.1701750138
Short name T901
Test name
Test status
Simulation time 890900081 ps
CPU time 19.38 seconds
Started Aug 11 06:46:25 PM PDT 24
Finished Aug 11 06:46:45 PM PDT 24
Peak memory 248572 kb
Host smart-72f2c514-c338-492a-bae6-6140da1891c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701750138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.1701750138
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.3385616344
Short name T491
Test name
Test status
Simulation time 1814892914 ps
CPU time 29.23 seconds
Started Aug 11 06:46:25 PM PDT 24
Finished Aug 11 06:46:55 PM PDT 24
Peak memory 244396 kb
Host smart-ff1ff926-97cf-4c9e-a5fc-57be9f20049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385616344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.3385616344
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.2053265764
Short name T1088
Test name
Test status
Simulation time 1415326188 ps
CPU time 19.08 seconds
Started Aug 11 06:46:24 PM PDT 24
Finished Aug 11 06:46:44 PM PDT 24
Peak memory 241912 kb
Host smart-8ac86b93-6fe1-43da-8252-d77cd12d9b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053265764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.2053265764
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.558899612
Short name T129
Test name
Test status
Simulation time 293353972 ps
CPU time 4.88 seconds
Started Aug 11 06:46:24 PM PDT 24
Finished Aug 11 06:46:29 PM PDT 24
Peak memory 242316 kb
Host smart-ff8ba81e-1fd6-4e2a-b76e-f0e475454bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558899612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.558899612
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.4058484505
Short name T838
Test name
Test status
Simulation time 1016836174 ps
CPU time 33.21 seconds
Started Aug 11 06:46:26 PM PDT 24
Finished Aug 11 06:47:00 PM PDT 24
Peak memory 246668 kb
Host smart-fb40050b-eb08-4985-97f3-5f5b232ad942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058484505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.4058484505
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.1282694622
Short name T759
Test name
Test status
Simulation time 2367526874 ps
CPU time 31.54 seconds
Started Aug 11 06:46:28 PM PDT 24
Finished Aug 11 06:47:00 PM PDT 24
Peak memory 242312 kb
Host smart-84a0a250-e484-4644-b4e7-62f6e9523ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282694622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.1282694622
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.3821637703
Short name T900
Test name
Test status
Simulation time 722947776 ps
CPU time 9.79 seconds
Started Aug 11 06:46:23 PM PDT 24
Finished Aug 11 06:46:33 PM PDT 24
Peak memory 241864 kb
Host smart-3c2084bf-a1d7-4aa2-869b-98ae4683a862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821637703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.3821637703
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.2404646443
Short name T222
Test name
Test status
Simulation time 7053944167 ps
CPU time 23.58 seconds
Started Aug 11 06:46:23 PM PDT 24
Finished Aug 11 06:46:47 PM PDT 24
Peak memory 242220 kb
Host smart-e11ed2b4-f4e7-455d-aabb-6eb3b156e901
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2404646443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.2404646443
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.2652383589
Short name T762
Test name
Test status
Simulation time 311412600 ps
CPU time 10.08 seconds
Started Aug 11 06:46:28 PM PDT 24
Finished Aug 11 06:46:39 PM PDT 24
Peak memory 241808 kb
Host smart-85e458ff-192e-4385-90a9-c89ebfd5d445
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652383589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.2652383589
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.718729301
Short name T567
Test name
Test status
Simulation time 453561871 ps
CPU time 3.01 seconds
Started Aug 11 06:46:24 PM PDT 24
Finished Aug 11 06:46:27 PM PDT 24
Peak memory 242232 kb
Host smart-6eeea6ba-2d04-4fca-8a62-5a07fa3691bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718729301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.718729301
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.4020666582
Short name T746
Test name
Test status
Simulation time 21848367004 ps
CPU time 157.98 seconds
Started Aug 11 06:46:27 PM PDT 24
Finished Aug 11 06:49:06 PM PDT 24
Peak memory 246308 kb
Host smart-ca45b343-4357-40da-8b75-8c874e09925e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020666582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
4020666582
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.1564210587
Short name T861
Test name
Test status
Simulation time 188248907590 ps
CPU time 343.51 seconds
Started Aug 11 06:46:28 PM PDT 24
Finished Aug 11 06:52:11 PM PDT 24
Peak memory 257016 kb
Host smart-e0d0205a-f5e1-4016-a62b-19384e03cb60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564210587 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.1564210587
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.3940998981
Short name T500
Test name
Test status
Simulation time 5254192582 ps
CPU time 35.62 seconds
Started Aug 11 06:46:27 PM PDT 24
Finished Aug 11 06:47:03 PM PDT 24
Peak memory 242460 kb
Host smart-1c960870-f69a-47c4-b858-88fd598756de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940998981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.3940998981
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.3053593086
Short name T72
Test name
Test status
Simulation time 448958947 ps
CPU time 3.83 seconds
Started Aug 11 06:49:47 PM PDT 24
Finished Aug 11 06:49:51 PM PDT 24
Peak memory 241964 kb
Host smart-36988efb-e27f-4a28-8a58-bcac4eff2d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053593086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.3053593086
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.274798521
Short name T694
Test name
Test status
Simulation time 209305098 ps
CPU time 10.07 seconds
Started Aug 11 06:49:47 PM PDT 24
Finished Aug 11 06:49:57 PM PDT 24
Peak memory 241996 kb
Host smart-696c2a5a-13f1-4e8b-a49d-7ebb05786387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274798521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.274798521
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.3631294454
Short name T240
Test name
Test status
Simulation time 104670274126 ps
CPU time 2198.74 seconds
Started Aug 11 06:49:43 PM PDT 24
Finished Aug 11 07:26:22 PM PDT 24
Peak memory 278548 kb
Host smart-de8477c8-751b-4d5f-9e9d-52fa81d55d30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631294454 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.3631294454
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.1596513885
Short name T664
Test name
Test status
Simulation time 223125226 ps
CPU time 3.05 seconds
Started Aug 11 06:49:43 PM PDT 24
Finished Aug 11 06:49:46 PM PDT 24
Peak memory 242092 kb
Host smart-236e6b8b-c9d0-451f-a735-03999b4f26a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596513885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.1596513885
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.2820324744
Short name T888
Test name
Test status
Simulation time 151957789 ps
CPU time 3.8 seconds
Started Aug 11 06:49:44 PM PDT 24
Finished Aug 11 06:49:48 PM PDT 24
Peak memory 241892 kb
Host smart-798475f6-4e37-46c0-840b-fc6a9e943b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820324744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.2820324744
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.1558163481
Short name T345
Test name
Test status
Simulation time 66065734907 ps
CPU time 1267.05 seconds
Started Aug 11 06:49:43 PM PDT 24
Finished Aug 11 07:10:51 PM PDT 24
Peak memory 264540 kb
Host smart-ef903b74-8666-4119-aaa2-ff5f7c70a10e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558163481 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.1558163481
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.4133991984
Short name T469
Test name
Test status
Simulation time 305091901 ps
CPU time 4.31 seconds
Started Aug 11 06:49:41 PM PDT 24
Finished Aug 11 06:49:45 PM PDT 24
Peak memory 242264 kb
Host smart-1465434d-7a00-4e80-94b1-ca6aca7745ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133991984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.4133991984
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.4184020606
Short name T1087
Test name
Test status
Simulation time 1948119256 ps
CPU time 5.16 seconds
Started Aug 11 06:49:47 PM PDT 24
Finished Aug 11 06:49:52 PM PDT 24
Peak memory 242392 kb
Host smart-a5c28a67-7a64-4a88-8a27-e68a6e56a90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184020606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.4184020606
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.2790064999
Short name T406
Test name
Test status
Simulation time 225179542841 ps
CPU time 458.71 seconds
Started Aug 11 06:49:47 PM PDT 24
Finished Aug 11 06:57:26 PM PDT 24
Peak memory 335756 kb
Host smart-002c0fd3-e9c6-4d18-8d4e-781831b80d3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790064999 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.2790064999
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.1907524385
Short name T667
Test name
Test status
Simulation time 1858652582 ps
CPU time 4.28 seconds
Started Aug 11 06:49:49 PM PDT 24
Finished Aug 11 06:49:53 PM PDT 24
Peak memory 242232 kb
Host smart-f7863217-d4f1-41e2-9135-d087bf7cdf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907524385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.1907524385
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.3071125150
Short name T860
Test name
Test status
Simulation time 316005386 ps
CPU time 19.12 seconds
Started Aug 11 06:49:49 PM PDT 24
Finished Aug 11 06:50:08 PM PDT 24
Peak memory 242336 kb
Host smart-4c4de3cd-85e6-4ebf-b005-fa82363a5bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071125150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.3071125150
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.431802247
Short name T253
Test name
Test status
Simulation time 73743585133 ps
CPU time 1042.07 seconds
Started Aug 11 06:49:48 PM PDT 24
Finished Aug 11 07:07:10 PM PDT 24
Peak memory 304056 kb
Host smart-cb68a0ed-e357-4fe6-b740-c577247d5bc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431802247 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.431802247
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.2447782932
Short name T1133
Test name
Test status
Simulation time 474656131 ps
CPU time 6.11 seconds
Started Aug 11 06:49:47 PM PDT 24
Finished Aug 11 06:49:53 PM PDT 24
Peak memory 241968 kb
Host smart-4934dd67-b287-4996-82b0-cc4249dc1407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447782932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.2447782932
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.2471565890
Short name T830
Test name
Test status
Simulation time 39135148346 ps
CPU time 956.57 seconds
Started Aug 11 06:49:52 PM PDT 24
Finished Aug 11 07:05:48 PM PDT 24
Peak memory 368304 kb
Host smart-e704951c-8b27-4045-9881-ecdb23cb6ada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471565890 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.2471565890
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.3764400068
Short name T103
Test name
Test status
Simulation time 338078929 ps
CPU time 4.93 seconds
Started Aug 11 06:49:50 PM PDT 24
Finished Aug 11 06:49:55 PM PDT 24
Peak memory 242088 kb
Host smart-2b28807a-aa02-459a-a026-b83c4bb8b1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764400068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3764400068
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.3131624788
Short name T172
Test name
Test status
Simulation time 353097947 ps
CPU time 7.9 seconds
Started Aug 11 06:49:45 PM PDT 24
Finished Aug 11 06:49:53 PM PDT 24
Peak memory 242380 kb
Host smart-38005afc-180b-4563-930a-ebeb8b888381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131624788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3131624788
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.2501512438
Short name T343
Test name
Test status
Simulation time 11813379577 ps
CPU time 293.98 seconds
Started Aug 11 06:49:50 PM PDT 24
Finished Aug 11 06:54:44 PM PDT 24
Peak memory 281020 kb
Host smart-aefa0cfc-a659-43a8-aec5-b9af09b01517
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501512438 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.2501512438
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.2355596280
Short name T784
Test name
Test status
Simulation time 195818105 ps
CPU time 3.72 seconds
Started Aug 11 06:49:49 PM PDT 24
Finished Aug 11 06:49:53 PM PDT 24
Peak memory 241944 kb
Host smart-4e7b051a-3fda-426c-9094-9bd29880e441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355596280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.2355596280
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.3760591583
Short name T102
Test name
Test status
Simulation time 98034068 ps
CPU time 2.96 seconds
Started Aug 11 06:49:52 PM PDT 24
Finished Aug 11 06:49:55 PM PDT 24
Peak memory 242328 kb
Host smart-3db4f01c-fe45-43a4-a1ff-79f95521df59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760591583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3760591583
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.3961048360
Short name T887
Test name
Test status
Simulation time 60915626004 ps
CPU time 1038.26 seconds
Started Aug 11 06:49:47 PM PDT 24
Finished Aug 11 07:07:06 PM PDT 24
Peak memory 322964 kb
Host smart-3f554af0-0dcd-4182-a9e5-62fefa3fcd3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961048360 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.3961048360
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.923536796
Short name T125
Test name
Test status
Simulation time 2296445826 ps
CPU time 6.73 seconds
Started Aug 11 06:49:47 PM PDT 24
Finished Aug 11 06:49:54 PM PDT 24
Peak memory 242008 kb
Host smart-0bbe36d1-5ea9-4a2d-9fa5-3134a9c3dfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923536796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.923536796
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.2012412198
Short name T147
Test name
Test status
Simulation time 362379814 ps
CPU time 11.34 seconds
Started Aug 11 06:49:49 PM PDT 24
Finished Aug 11 06:50:00 PM PDT 24
Peak memory 241940 kb
Host smart-d06103f5-416b-4ab9-b9bd-99178a25f65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012412198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2012412198
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.1847950640
Short name T51
Test name
Test status
Simulation time 522238254 ps
CPU time 3.97 seconds
Started Aug 11 06:49:48 PM PDT 24
Finished Aug 11 06:49:52 PM PDT 24
Peak memory 241956 kb
Host smart-510f65a5-7c97-4315-b48a-7fdb3dde5e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847950640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.1847950640
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.856837417
Short name T354
Test name
Test status
Simulation time 8305286774 ps
CPU time 17.59 seconds
Started Aug 11 06:49:48 PM PDT 24
Finished Aug 11 06:50:06 PM PDT 24
Peak memory 241944 kb
Host smart-c9bb45e1-a986-4957-99bc-e8839396ff55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856837417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.856837417
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.3842416701
Short name T82
Test name
Test status
Simulation time 246574653 ps
CPU time 3.62 seconds
Started Aug 11 06:49:48 PM PDT 24
Finished Aug 11 06:49:52 PM PDT 24
Peak memory 242104 kb
Host smart-158e863f-3839-4bc1-8a66-e5f2835de7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842416701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.3842416701
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.3663434503
Short name T314
Test name
Test status
Simulation time 793221587 ps
CPU time 6.06 seconds
Started Aug 11 06:49:47 PM PDT 24
Finished Aug 11 06:49:53 PM PDT 24
Peak memory 242236 kb
Host smart-db2ec9e3-74ff-4444-b831-69b72c49b5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663434503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.3663434503
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.3441250646
Short name T587
Test name
Test status
Simulation time 32640850641 ps
CPU time 937.42 seconds
Started Aug 11 06:49:49 PM PDT 24
Finished Aug 11 07:05:27 PM PDT 24
Peak memory 304484 kb
Host smart-667ff2c1-8bc0-48da-8605-30d0d1a22ce5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441250646 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.3441250646
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.3479876872
Short name T1055
Test name
Test status
Simulation time 774089785 ps
CPU time 2.12 seconds
Started Aug 11 06:46:38 PM PDT 24
Finished Aug 11 06:46:40 PM PDT 24
Peak memory 240928 kb
Host smart-db8610e2-3907-407c-abbd-7bb972aa2b6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479876872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.3479876872
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.2593889502
Short name T807
Test name
Test status
Simulation time 625437633 ps
CPU time 10.09 seconds
Started Aug 11 06:46:28 PM PDT 24
Finished Aug 11 06:46:38 PM PDT 24
Peak memory 242060 kb
Host smart-9bc4dcac-2e20-4a93-83be-f98b41a501fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593889502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.2593889502
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.4035563350
Short name T1151
Test name
Test status
Simulation time 2315969144 ps
CPU time 22.14 seconds
Started Aug 11 06:46:34 PM PDT 24
Finished Aug 11 06:46:56 PM PDT 24
Peak memory 242532 kb
Host smart-3fdd659f-ae06-426c-9888-084a23c53d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035563350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.4035563350
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.835711940
Short name T361
Test name
Test status
Simulation time 175506869 ps
CPU time 9.27 seconds
Started Aug 11 06:46:31 PM PDT 24
Finished Aug 11 06:46:41 PM PDT 24
Peak memory 242004 kb
Host smart-28e08ac9-a010-41c3-bbad-d32f1a9fefdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835711940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.835711940
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.3740694368
Short name T526
Test name
Test status
Simulation time 1148364329 ps
CPU time 9.59 seconds
Started Aug 11 06:46:33 PM PDT 24
Finished Aug 11 06:46:42 PM PDT 24
Peak memory 242480 kb
Host smart-c98bf8d8-d3ff-4448-96e8-43faff907aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740694368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.3740694368
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.2188197666
Short name T676
Test name
Test status
Simulation time 523656703 ps
CPU time 3.61 seconds
Started Aug 11 06:46:27 PM PDT 24
Finished Aug 11 06:46:31 PM PDT 24
Peak memory 242272 kb
Host smart-4cf364b4-65fe-49a5-b502-e5420d9377c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188197666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.2188197666
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.486774405
Short name T438
Test name
Test status
Simulation time 1281098861 ps
CPU time 25.81 seconds
Started Aug 11 06:46:32 PM PDT 24
Finished Aug 11 06:46:58 PM PDT 24
Peak memory 248600 kb
Host smart-b45b5bae-ea05-4750-8dc3-34692b5f0d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486774405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.486774405
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.2732004422
Short name T563
Test name
Test status
Simulation time 9580165898 ps
CPU time 36.81 seconds
Started Aug 11 06:46:34 PM PDT 24
Finished Aug 11 06:47:11 PM PDT 24
Peak memory 243516 kb
Host smart-a0c19e70-7b2c-428c-af99-598c3268292f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732004422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.2732004422
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.3184122906
Short name T631
Test name
Test status
Simulation time 517830101 ps
CPU time 13.38 seconds
Started Aug 11 06:46:34 PM PDT 24
Finished Aug 11 06:46:47 PM PDT 24
Peak memory 241840 kb
Host smart-f0809d9e-fa74-41ec-8563-2fd014d819c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184122906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3184122906
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.1164104591
Short name T682
Test name
Test status
Simulation time 3027719929 ps
CPU time 24.96 seconds
Started Aug 11 06:46:31 PM PDT 24
Finished Aug 11 06:46:56 PM PDT 24
Peak memory 242028 kb
Host smart-4e361d21-83b5-436c-b027-98373785f4a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1164104591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.1164104591
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.2482680104
Short name T924
Test name
Test status
Simulation time 3182136461 ps
CPU time 7.95 seconds
Started Aug 11 06:46:33 PM PDT 24
Finished Aug 11 06:46:41 PM PDT 24
Peak memory 242088 kb
Host smart-9308609c-8aaa-46a5-b7bf-af192b2c77c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2482680104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2482680104
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.3740766250
Short name T198
Test name
Test status
Simulation time 1164790720 ps
CPU time 8.12 seconds
Started Aug 11 06:46:32 PM PDT 24
Finished Aug 11 06:46:40 PM PDT 24
Peak memory 242084 kb
Host smart-e319635e-b31b-4329-be82-41bb0dfdc0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740766250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.3740766250
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.348930177
Short name T758
Test name
Test status
Simulation time 283392006705 ps
CPU time 2143.32 seconds
Started Aug 11 06:46:37 PM PDT 24
Finished Aug 11 07:22:21 PM PDT 24
Peak memory 390284 kb
Host smart-0fa56a31-cea5-43f3-a4e5-ba1fd7efd513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348930177 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.348930177
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.687194706
Short name T875
Test name
Test status
Simulation time 453750846 ps
CPU time 8.82 seconds
Started Aug 11 06:46:39 PM PDT 24
Finished Aug 11 06:46:47 PM PDT 24
Peak memory 241984 kb
Host smart-db8e75eb-8734-4d26-8f4c-8ee62fdb76f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687194706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.687194706
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.978209597
Short name T186
Test name
Test status
Simulation time 141054776 ps
CPU time 3.6 seconds
Started Aug 11 06:49:46 PM PDT 24
Finished Aug 11 06:49:50 PM PDT 24
Peak memory 242136 kb
Host smart-643782e1-4a7d-4fce-9a06-d933e7f754f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978209597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.978209597
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.2285654114
Short name T983
Test name
Test status
Simulation time 791860829 ps
CPU time 9.44 seconds
Started Aug 11 06:49:56 PM PDT 24
Finished Aug 11 06:50:06 PM PDT 24
Peak memory 242320 kb
Host smart-854cac07-d94d-4fdc-b6e4-591b9b98639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285654114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.2285654114
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.449759223
Short name T842
Test name
Test status
Simulation time 130800499 ps
CPU time 3.69 seconds
Started Aug 11 06:49:55 PM PDT 24
Finished Aug 11 06:49:59 PM PDT 24
Peak memory 242072 kb
Host smart-b87ee39f-a8c2-475e-a1a1-f1655513627a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449759223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.449759223
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.850451416
Short name T954
Test name
Test status
Simulation time 299300673 ps
CPU time 4.97 seconds
Started Aug 11 06:49:56 PM PDT 24
Finished Aug 11 06:50:01 PM PDT 24
Peak memory 242332 kb
Host smart-5e2b8381-f586-4cfb-8fb5-3f1178f2798f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850451416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.850451416
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2248273807
Short name T287
Test name
Test status
Simulation time 1515163085008 ps
CPU time 3146.9 seconds
Started Aug 11 06:49:59 PM PDT 24
Finished Aug 11 07:42:27 PM PDT 24
Peak memory 515748 kb
Host smart-8011d2ce-62ac-4ee2-9bcb-ee6475095fec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248273807 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.2248273807
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.2219785227
Short name T1008
Test name
Test status
Simulation time 1683641982 ps
CPU time 4.77 seconds
Started Aug 11 06:49:59 PM PDT 24
Finished Aug 11 06:50:03 PM PDT 24
Peak memory 242204 kb
Host smart-c8e17e0e-5ec3-4936-b386-37e4d7b3ba6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219785227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.2219785227
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.410093221
Short name T1093
Test name
Test status
Simulation time 722609293 ps
CPU time 7.61 seconds
Started Aug 11 06:49:56 PM PDT 24
Finished Aug 11 06:50:04 PM PDT 24
Peak memory 242372 kb
Host smart-1c146c8f-c12d-4982-ab12-b11325aaf70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410093221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.410093221
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.3371126159
Short name T1105
Test name
Test status
Simulation time 2115471724 ps
CPU time 5.26 seconds
Started Aug 11 06:49:56 PM PDT 24
Finished Aug 11 06:50:01 PM PDT 24
Peak memory 242084 kb
Host smart-034dba80-cc10-480f-8dc4-f4bf7870901a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371126159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.3371126159
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.3826032529
Short name T472
Test name
Test status
Simulation time 863868018 ps
CPU time 9.58 seconds
Started Aug 11 06:50:02 PM PDT 24
Finished Aug 11 06:50:12 PM PDT 24
Peak memory 242024 kb
Host smart-4eb21259-e0fa-44d5-8eb4-dd4c159cbf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826032529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.3826032529
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.2584896951
Short name T230
Test name
Test status
Simulation time 314964563 ps
CPU time 3.95 seconds
Started Aug 11 06:49:58 PM PDT 24
Finished Aug 11 06:50:02 PM PDT 24
Peak memory 241828 kb
Host smart-1455d8b4-0e51-48af-baed-5bf2e8b898c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584896951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.2584896951
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.1369216726
Short name T496
Test name
Test status
Simulation time 304981524 ps
CPU time 5.24 seconds
Started Aug 11 06:49:59 PM PDT 24
Finished Aug 11 06:50:04 PM PDT 24
Peak memory 241976 kb
Host smart-1fc26707-d7f9-4d28-a193-c48406d77f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369216726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1369216726
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.758282954
Short name T1113
Test name
Test status
Simulation time 45469761405 ps
CPU time 828.76 seconds
Started Aug 11 06:49:54 PM PDT 24
Finished Aug 11 07:03:43 PM PDT 24
Peak memory 321004 kb
Host smart-547ebd40-0f02-4529-9f0d-04ee96711973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758282954 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.758282954
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.1849997822
Short name T1058
Test name
Test status
Simulation time 147905958 ps
CPU time 3.86 seconds
Started Aug 11 06:49:56 PM PDT 24
Finished Aug 11 06:50:00 PM PDT 24
Peak memory 242328 kb
Host smart-74734a39-1e24-412f-9dfd-2f0e4b73c761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849997822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.1849997822
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.3677622595
Short name T1175
Test name
Test status
Simulation time 266462115 ps
CPU time 7.63 seconds
Started Aug 11 06:49:56 PM PDT 24
Finished Aug 11 06:50:04 PM PDT 24
Peak memory 241868 kb
Host smart-e394d409-d0e7-4e0e-8949-342cc7eda894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677622595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.3677622595
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.2454577090
Short name T751
Test name
Test status
Simulation time 322386344 ps
CPU time 4.52 seconds
Started Aug 11 06:49:57 PM PDT 24
Finished Aug 11 06:50:02 PM PDT 24
Peak memory 242600 kb
Host smart-f293d46f-b158-447b-83dc-768df553305a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454577090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.2454577090
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.451778343
Short name T719
Test name
Test status
Simulation time 261132450 ps
CPU time 6.49 seconds
Started Aug 11 06:49:56 PM PDT 24
Finished Aug 11 06:50:03 PM PDT 24
Peak memory 241980 kb
Host smart-f22e2463-4713-4687-9b84-930c0e1b6e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451778343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.451778343
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.1592269355
Short name T152
Test name
Test status
Simulation time 55058235604 ps
CPU time 1601.27 seconds
Started Aug 11 06:50:02 PM PDT 24
Finished Aug 11 07:16:44 PM PDT 24
Peak memory 380200 kb
Host smart-6bd056a9-c8f9-420c-abc5-9b7c6da47c5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592269355 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.1592269355
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.3881647513
Short name T817
Test name
Test status
Simulation time 309750373 ps
CPU time 3.97 seconds
Started Aug 11 06:49:57 PM PDT 24
Finished Aug 11 06:50:01 PM PDT 24
Peak memory 242344 kb
Host smart-2aebd5ee-70b3-4751-9d3e-577d619cdb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881647513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3881647513
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.2863463196
Short name T593
Test name
Test status
Simulation time 363898555 ps
CPU time 7.58 seconds
Started Aug 11 06:49:57 PM PDT 24
Finished Aug 11 06:50:04 PM PDT 24
Peak memory 241904 kb
Host smart-d627ec1b-b4c6-4b32-b022-f3a9fb3aa9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863463196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.2863463196
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.1696616844
Short name T943
Test name
Test status
Simulation time 860366333239 ps
CPU time 1676.94 seconds
Started Aug 11 06:49:55 PM PDT 24
Finished Aug 11 07:17:52 PM PDT 24
Peak memory 264140 kb
Host smart-8bf36fef-10a2-43a9-8ae2-b71dec631230
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696616844 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.1696616844
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.1108760685
Short name T800
Test name
Test status
Simulation time 590328362 ps
CPU time 3.91 seconds
Started Aug 11 06:49:55 PM PDT 24
Finished Aug 11 06:49:59 PM PDT 24
Peak memory 242308 kb
Host smart-b4af8873-316f-443f-a40d-2109885bb465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108760685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.1108760685
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.1130302596
Short name T1071
Test name
Test status
Simulation time 245468817 ps
CPU time 6.26 seconds
Started Aug 11 06:49:59 PM PDT 24
Finished Aug 11 06:50:05 PM PDT 24
Peak memory 242244 kb
Host smart-c428eaaa-d75c-428a-b7d9-7728e7880cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130302596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1130302596
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.3729623326
Short name T342
Test name
Test status
Simulation time 99158284768 ps
CPU time 1569.16 seconds
Started Aug 11 06:49:56 PM PDT 24
Finished Aug 11 07:16:06 PM PDT 24
Peak memory 255468 kb
Host smart-de4c2e8b-964b-4eae-82ed-7113a7fa1f57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729623326 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.3729623326
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.294597584
Short name T865
Test name
Test status
Simulation time 1830447437 ps
CPU time 4.38 seconds
Started Aug 11 06:50:02 PM PDT 24
Finished Aug 11 06:50:07 PM PDT 24
Peak memory 241996 kb
Host smart-1e0cbcb7-a6a8-4dd6-9abf-3a71618598ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294597584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.294597584
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.1435924134
Short name T15
Test name
Test status
Simulation time 402379309670 ps
CPU time 3038.37 seconds
Started Aug 11 06:49:55 PM PDT 24
Finished Aug 11 07:40:34 PM PDT 24
Peak memory 430428 kb
Host smart-4abdd37b-9b9f-4f2a-84a9-f589d68ac8b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435924134 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.1435924134
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.3379992891
Short name T795
Test name
Test status
Simulation time 69132233 ps
CPU time 2.09 seconds
Started Aug 11 06:46:42 PM PDT 24
Finished Aug 11 06:46:44 PM PDT 24
Peak memory 240580 kb
Host smart-4daf1557-8ab9-420e-bb56-76a90f11bd1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379992891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.3379992891
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.4130577979
Short name T543
Test name
Test status
Simulation time 1561190438 ps
CPU time 18.57 seconds
Started Aug 11 06:46:40 PM PDT 24
Finished Aug 11 06:46:59 PM PDT 24
Peak memory 242384 kb
Host smart-28b1183c-6fa1-40b3-b47f-d02c266859e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130577979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.4130577979
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.1858161608
Short name T1178
Test name
Test status
Simulation time 1873245770 ps
CPU time 4.87 seconds
Started Aug 11 06:46:48 PM PDT 24
Finished Aug 11 06:46:53 PM PDT 24
Peak memory 242320 kb
Host smart-9f88ae86-4532-4d28-a582-5567eac5f0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858161608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.1858161608
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.3096864165
Short name T1104
Test name
Test status
Simulation time 689512640 ps
CPU time 8.12 seconds
Started Aug 11 06:46:41 PM PDT 24
Finished Aug 11 06:46:49 PM PDT 24
Peak memory 242036 kb
Host smart-4e6ea3fa-3428-4bd6-bcdf-677bb2c9ee50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096864165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.3096864165
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.1791481786
Short name T706
Test name
Test status
Simulation time 2586835782 ps
CPU time 32.32 seconds
Started Aug 11 06:46:38 PM PDT 24
Finished Aug 11 06:47:11 PM PDT 24
Peak memory 242404 kb
Host smart-c81e0292-8c89-4042-803c-c125ce72c24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791481786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.1791481786
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.3483727929
Short name T225
Test name
Test status
Simulation time 155160842 ps
CPU time 3.86 seconds
Started Aug 11 06:46:38 PM PDT 24
Finished Aug 11 06:46:42 PM PDT 24
Peak memory 242128 kb
Host smart-f3d442ff-7610-4cd2-9b7b-79b2818dfd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483727929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.3483727929
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.2309863173
Short name T740
Test name
Test status
Simulation time 4961771690 ps
CPU time 34.45 seconds
Started Aug 11 06:46:42 PM PDT 24
Finished Aug 11 06:47:16 PM PDT 24
Peak memory 256884 kb
Host smart-fd885267-475b-4353-9476-6438fc3f6c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309863173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.2309863173
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.2118372967
Short name T399
Test name
Test status
Simulation time 764878376 ps
CPU time 34.66 seconds
Started Aug 11 06:46:50 PM PDT 24
Finished Aug 11 06:47:25 PM PDT 24
Peak memory 242392 kb
Host smart-036f8288-85ad-4753-aec7-025475752e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118372967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2118372967
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.936327361
Short name T711
Test name
Test status
Simulation time 217054020 ps
CPU time 3.12 seconds
Started Aug 11 06:46:38 PM PDT 24
Finished Aug 11 06:46:41 PM PDT 24
Peak memory 241852 kb
Host smart-f66a47d0-bccb-4ad6-be02-4b3c73b2459d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936327361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.936327361
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.3210767970
Short name T387
Test name
Test status
Simulation time 345413461 ps
CPU time 10.05 seconds
Started Aug 11 06:46:45 PM PDT 24
Finished Aug 11 06:46:55 PM PDT 24
Peak memory 241968 kb
Host smart-01ad4b9b-861c-41ba-85ad-c4dd17421a84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3210767970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.3210767970
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.2917827105
Short name T285
Test name
Test status
Simulation time 1322910048 ps
CPU time 11.51 seconds
Started Aug 11 06:46:38 PM PDT 24
Finished Aug 11 06:46:50 PM PDT 24
Peak memory 242096 kb
Host smart-3efdd1c1-b8df-4a30-b1a7-4de52a127cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917827105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.2917827105
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.333795704
Short name T1130
Test name
Test status
Simulation time 105746308135 ps
CPU time 345.62 seconds
Started Aug 11 06:46:42 PM PDT 24
Finished Aug 11 06:52:28 PM PDT 24
Peak memory 297700 kb
Host smart-f68177de-9766-4c23-8d85-b36356c10da6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333795704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.333795704
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.23292700
Short name T283
Test name
Test status
Simulation time 3079925597 ps
CPU time 51.49 seconds
Started Aug 11 06:46:44 PM PDT 24
Finished Aug 11 06:47:35 PM PDT 24
Peak memory 248940 kb
Host smart-3e80da79-4e14-4ccc-8be8-8a8756be6772
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23292700 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.23292700
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.2561246480
Short name T914
Test name
Test status
Simulation time 345529587 ps
CPU time 5.75 seconds
Started Aug 11 06:46:45 PM PDT 24
Finished Aug 11 06:46:51 PM PDT 24
Peak memory 242428 kb
Host smart-cbcfa590-f1bc-435e-aab1-f8e00546a1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561246480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.2561246480
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.1355492998
Short name T58
Test name
Test status
Simulation time 128763803 ps
CPU time 4.96 seconds
Started Aug 11 06:49:55 PM PDT 24
Finished Aug 11 06:50:00 PM PDT 24
Peak memory 242472 kb
Host smart-1a9cb564-55a3-4ad0-b1d1-c59f19de3008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355492998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.1355492998
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.1311521527
Short name T246
Test name
Test status
Simulation time 132194763 ps
CPU time 6.06 seconds
Started Aug 11 06:49:57 PM PDT 24
Finished Aug 11 06:50:03 PM PDT 24
Peak memory 241776 kb
Host smart-fe7920b2-979b-466b-8c12-8da6ab4a2356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311521527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.1311521527
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.687217890
Short name T532
Test name
Test status
Simulation time 368158128 ps
CPU time 3.2 seconds
Started Aug 11 06:49:59 PM PDT 24
Finished Aug 11 06:50:02 PM PDT 24
Peak memory 241828 kb
Host smart-ef91f59b-7cd5-407f-a5a5-639ed604d776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687217890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.687217890
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.3113574899
Short name T108
Test name
Test status
Simulation time 1658213042 ps
CPU time 4.14 seconds
Started Aug 11 06:50:00 PM PDT 24
Finished Aug 11 06:50:04 PM PDT 24
Peak memory 247016 kb
Host smart-5fa2b50d-9669-4112-8692-09904cd0c42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113574899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.3113574899
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.821239556
Short name T899
Test name
Test status
Simulation time 431838874443 ps
CPU time 793.32 seconds
Started Aug 11 06:49:59 PM PDT 24
Finished Aug 11 07:03:13 PM PDT 24
Peak memory 269588 kb
Host smart-a60ff41a-305d-4515-b69f-c1db79aaedfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821239556 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.821239556
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.3585500058
Short name T162
Test name
Test status
Simulation time 135278535 ps
CPU time 3.7 seconds
Started Aug 11 06:50:01 PM PDT 24
Finished Aug 11 06:50:04 PM PDT 24
Peak memory 242376 kb
Host smart-87fd7ff4-dc72-49a4-a4d0-53260631ce72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585500058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.3585500058
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.3800069233
Short name T506
Test name
Test status
Simulation time 258120832 ps
CPU time 5.78 seconds
Started Aug 11 06:50:01 PM PDT 24
Finished Aug 11 06:50:07 PM PDT 24
Peak memory 241912 kb
Host smart-b6a3c301-7c77-4ded-8d79-3fef37526114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800069233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.3800069233
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.2980520059
Short name T560
Test name
Test status
Simulation time 81131700630 ps
CPU time 662.39 seconds
Started Aug 11 06:49:59 PM PDT 24
Finished Aug 11 07:01:01 PM PDT 24
Peak memory 334252 kb
Host smart-d9533493-610d-4fe2-9705-1f0452f87e04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980520059 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.2980520059
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.1135288572
Short name T605
Test name
Test status
Simulation time 125008345 ps
CPU time 4.86 seconds
Started Aug 11 06:49:59 PM PDT 24
Finished Aug 11 06:50:04 PM PDT 24
Peak memory 242572 kb
Host smart-38669d62-b2ff-40d5-a43c-2a1d896d9ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135288572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.1135288572
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.3462518289
Short name T982
Test name
Test status
Simulation time 3384304384 ps
CPU time 8.74 seconds
Started Aug 11 06:50:00 PM PDT 24
Finished Aug 11 06:50:08 PM PDT 24
Peak memory 242332 kb
Host smart-a0c9fa01-c9ea-421c-aac5-d9a51dce0c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462518289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3462518289
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.1896335853
Short name T194
Test name
Test status
Simulation time 214039798 ps
CPU time 4.84 seconds
Started Aug 11 06:50:03 PM PDT 24
Finished Aug 11 06:50:08 PM PDT 24
Peak memory 242020 kb
Host smart-26bdb9a4-50c8-4dc2-80fb-f21db3abd81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896335853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.1896335853
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.770075407
Short name T355
Test name
Test status
Simulation time 8821182813 ps
CPU time 17.2 seconds
Started Aug 11 06:50:02 PM PDT 24
Finished Aug 11 06:50:19 PM PDT 24
Peak memory 242200 kb
Host smart-c1da1130-80b4-4494-8eb6-ff7d6bbb05ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770075407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.770075407
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.3484447016
Short name T1064
Test name
Test status
Simulation time 225966005691 ps
CPU time 1179.51 seconds
Started Aug 11 06:50:03 PM PDT 24
Finished Aug 11 07:09:42 PM PDT 24
Peak memory 289780 kb
Host smart-40b3df26-b159-4072-812d-d595e124d0fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484447016 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.3484447016
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.2125576182
Short name T742
Test name
Test status
Simulation time 600309221 ps
CPU time 4.77 seconds
Started Aug 11 06:50:01 PM PDT 24
Finished Aug 11 06:50:06 PM PDT 24
Peak memory 242392 kb
Host smart-de40cb92-0116-440d-ba37-a05416568bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125576182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2125576182
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.1879384691
Short name T931
Test name
Test status
Simulation time 170273613761 ps
CPU time 1972.31 seconds
Started Aug 11 06:50:02 PM PDT 24
Finished Aug 11 07:22:55 PM PDT 24
Peak memory 330652 kb
Host smart-b0dcfb4e-d292-43ef-87d1-c53fae73ad1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879384691 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.1879384691
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.1719258090
Short name T698
Test name
Test status
Simulation time 152672758 ps
CPU time 4.4 seconds
Started Aug 11 06:50:01 PM PDT 24
Finished Aug 11 06:50:05 PM PDT 24
Peak memory 242120 kb
Host smart-dc83332a-23da-4936-9a40-c9fb697d62fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719258090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.1719258090
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.3011822475
Short name T456
Test name
Test status
Simulation time 1712154457 ps
CPU time 12.81 seconds
Started Aug 11 06:50:00 PM PDT 24
Finished Aug 11 06:50:13 PM PDT 24
Peak memory 242164 kb
Host smart-67892fe7-8f49-4632-8b47-df018ffe6381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011822475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.3011822475
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.3622861494
Short name T443
Test name
Test status
Simulation time 246491951 ps
CPU time 5.07 seconds
Started Aug 11 06:50:01 PM PDT 24
Finished Aug 11 06:50:06 PM PDT 24
Peak memory 242208 kb
Host smart-e6a7f004-dffd-43fe-9c8c-2431e2961aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622861494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.3622861494
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.6277526
Short name T1165
Test name
Test status
Simulation time 416609914 ps
CPU time 7.64 seconds
Started Aug 11 06:50:00 PM PDT 24
Finished Aug 11 06:50:08 PM PDT 24
Peak memory 242236 kb
Host smart-97501178-ab2f-4148-957b-97dff3a8936e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6277526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.6277526
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.1519980652
Short name T615
Test name
Test status
Simulation time 438524160 ps
CPU time 4.51 seconds
Started Aug 11 06:50:01 PM PDT 24
Finished Aug 11 06:50:06 PM PDT 24
Peak memory 242044 kb
Host smart-04b15b7a-189a-4216-ae76-39812b8e3200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519980652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.1519980652
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.2668450520
Short name T1031
Test name
Test status
Simulation time 1244760254 ps
CPU time 4.04 seconds
Started Aug 11 06:49:58 PM PDT 24
Finished Aug 11 06:50:03 PM PDT 24
Peak memory 241948 kb
Host smart-4a9f73bf-f27a-49b7-acec-c6db2cbf585d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668450520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.2668450520
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.2994943922
Short name T870
Test name
Test status
Simulation time 326781478 ps
CPU time 4.62 seconds
Started Aug 11 06:50:08 PM PDT 24
Finished Aug 11 06:50:13 PM PDT 24
Peak memory 241964 kb
Host smart-9c65f0eb-d954-481d-b45e-69ac6a266226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994943922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.2994943922
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.3101365034
Short name T478
Test name
Test status
Simulation time 288741914 ps
CPU time 6.19 seconds
Started Aug 11 06:50:05 PM PDT 24
Finished Aug 11 06:50:12 PM PDT 24
Peak memory 241924 kb
Host smart-80b76749-6c7a-4d1c-b84a-e18da43c83cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101365034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.3101365034
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.2195262327
Short name T131
Test name
Test status
Simulation time 566961252162 ps
CPU time 1542.17 seconds
Started Aug 11 06:50:09 PM PDT 24
Finished Aug 11 07:15:52 PM PDT 24
Peak memory 313776 kb
Host smart-725584a7-69af-4558-8de1-bef6e0b407bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195262327 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.2195262327
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.1122129545
Short name T473
Test name
Test status
Simulation time 86091489 ps
CPU time 1.86 seconds
Started Aug 11 06:46:55 PM PDT 24
Finished Aug 11 06:46:57 PM PDT 24
Peak memory 240524 kb
Host smart-383c6a7b-f866-4ea2-a070-831e1f4168d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122129545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.1122129545
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.3339419672
Short name T635
Test name
Test status
Simulation time 1086047014 ps
CPU time 21.57 seconds
Started Aug 11 06:46:49 PM PDT 24
Finished Aug 11 06:47:11 PM PDT 24
Peak memory 242468 kb
Host smart-78021b08-c219-44bc-b2fe-f7a059149a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339419672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.3339419672
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.2592276574
Short name T66
Test name
Test status
Simulation time 1367373329 ps
CPU time 26.62 seconds
Started Aug 11 06:46:47 PM PDT 24
Finished Aug 11 06:47:14 PM PDT 24
Peak memory 248432 kb
Host smart-99614334-0471-44cf-8a75-8960f123da53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592276574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2592276574
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.426121518
Short name T821
Test name
Test status
Simulation time 1304135666 ps
CPU time 22.96 seconds
Started Aug 11 06:46:48 PM PDT 24
Finished Aug 11 06:47:11 PM PDT 24
Peak memory 242336 kb
Host smart-97b2f03e-8402-4934-85b2-be53e357b1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426121518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.426121518
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.3125766336
Short name T941
Test name
Test status
Simulation time 2220106719 ps
CPU time 29.04 seconds
Started Aug 11 06:46:47 PM PDT 24
Finished Aug 11 06:47:16 PM PDT 24
Peak memory 242232 kb
Host smart-c94010d1-7af1-4d01-8d9b-b2d8ba80ad51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125766336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.3125766336
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.252121014
Short name T418
Test name
Test status
Simulation time 2737266255 ps
CPU time 5.86 seconds
Started Aug 11 06:46:47 PM PDT 24
Finished Aug 11 06:46:53 PM PDT 24
Peak memory 242264 kb
Host smart-9683a4ae-6d4d-41d6-84db-815e47d4e61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252121014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.252121014
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.3628677055
Short name T527
Test name
Test status
Simulation time 384048009 ps
CPU time 5.69 seconds
Started Aug 11 06:46:48 PM PDT 24
Finished Aug 11 06:46:54 PM PDT 24
Peak memory 242068 kb
Host smart-751b5da8-f89c-483c-9824-0eac287901f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628677055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.3628677055
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.2736245853
Short name T621
Test name
Test status
Simulation time 574719295 ps
CPU time 22.19 seconds
Started Aug 11 06:46:51 PM PDT 24
Finished Aug 11 06:47:14 PM PDT 24
Peak memory 241972 kb
Host smart-ac3fec3a-1fc7-4fb4-a666-3b19f1459ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736245853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2736245853
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.1861795073
Short name T854
Test name
Test status
Simulation time 376359950 ps
CPU time 8.63 seconds
Started Aug 11 06:46:50 PM PDT 24
Finished Aug 11 06:46:59 PM PDT 24
Peak memory 241840 kb
Host smart-4843b034-4df6-4e58-9cb9-4550c8a661c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861795073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.1861795073
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.650912039
Short name T550
Test name
Test status
Simulation time 7268335543 ps
CPU time 22.28 seconds
Started Aug 11 06:46:52 PM PDT 24
Finished Aug 11 06:47:14 PM PDT 24
Peak memory 242252 kb
Host smart-6e095ef9-b373-4733-8d53-2c3d1a55b252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=650912039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.650912039
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.1421712471
Short name T375
Test name
Test status
Simulation time 1164480700 ps
CPU time 10.82 seconds
Started Aug 11 06:46:51 PM PDT 24
Finished Aug 11 06:47:02 PM PDT 24
Peak memory 242360 kb
Host smart-c5d4165b-3bce-4fcb-8ea7-42862e75534d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1421712471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.1421712471
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.4055861738
Short name T235
Test name
Test status
Simulation time 328959423 ps
CPU time 7.14 seconds
Started Aug 11 06:46:49 PM PDT 24
Finished Aug 11 06:46:56 PM PDT 24
Peak memory 242372 kb
Host smart-b52e2bb8-cc7a-4db8-83a8-d0319b04521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055861738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.4055861738
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.1718794134
Short name T259
Test name
Test status
Simulation time 3724136150 ps
CPU time 81.76 seconds
Started Aug 11 06:46:53 PM PDT 24
Finished Aug 11 06:48:15 PM PDT 24
Peak memory 248800 kb
Host smart-a03e4b32-9a36-4d00-9e55-b8937db3937a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718794134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
1718794134
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.1143210869
Short name T938
Test name
Test status
Simulation time 147204677847 ps
CPU time 1111.08 seconds
Started Aug 11 06:46:53 PM PDT 24
Finished Aug 11 07:05:24 PM PDT 24
Peak memory 265940 kb
Host smart-4fb70db7-186c-43a2-bedf-99b8442bbc5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143210869 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.1143210869
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.1342743394
Short name T509
Test name
Test status
Simulation time 1434852823 ps
CPU time 15.67 seconds
Started Aug 11 06:46:51 PM PDT 24
Finished Aug 11 06:47:07 PM PDT 24
Peak memory 248612 kb
Host smart-afd904ae-62a7-44b5-8f24-5648f9c3ed52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342743394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.1342743394
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.1774142908
Short name T30
Test name
Test status
Simulation time 504872227 ps
CPU time 4.25 seconds
Started Aug 11 06:50:06 PM PDT 24
Finished Aug 11 06:50:10 PM PDT 24
Peak memory 242224 kb
Host smart-881ad5ea-96b5-4e09-8552-727af8917b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774142908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.1774142908
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.3905200718
Short name T968
Test name
Test status
Simulation time 520839863 ps
CPU time 16.21 seconds
Started Aug 11 06:50:06 PM PDT 24
Finished Aug 11 06:50:22 PM PDT 24
Peak memory 242128 kb
Host smart-984e1e0d-ea69-4c6e-b788-a9179d20c8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905200718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3905200718
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.2800977967
Short name T590
Test name
Test status
Simulation time 284049997 ps
CPU time 4.38 seconds
Started Aug 11 06:50:10 PM PDT 24
Finished Aug 11 06:50:15 PM PDT 24
Peak memory 241948 kb
Host smart-c81e7844-cd2d-47fc-95a0-367ca88211f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800977967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2800977967
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.3674753006
Short name T684
Test name
Test status
Simulation time 279580603 ps
CPU time 5.15 seconds
Started Aug 11 06:50:06 PM PDT 24
Finished Aug 11 06:50:11 PM PDT 24
Peak memory 242404 kb
Host smart-c34e38eb-9f3d-4376-a4c2-ca98c799c57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674753006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.3674753006
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.2564471967
Short name T185
Test name
Test status
Simulation time 304155599 ps
CPU time 4.77 seconds
Started Aug 11 06:50:08 PM PDT 24
Finished Aug 11 06:50:13 PM PDT 24
Peak memory 241976 kb
Host smart-3cd6b231-1044-4870-b2a1-207db6babcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564471967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2564471967
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.3052267243
Short name T581
Test name
Test status
Simulation time 242944257 ps
CPU time 3.78 seconds
Started Aug 11 06:50:08 PM PDT 24
Finished Aug 11 06:50:12 PM PDT 24
Peak memory 241976 kb
Host smart-3d518314-3332-4ccd-b98c-1024c432d276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052267243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3052267243
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.3483155342
Short name T659
Test name
Test status
Simulation time 116238702 ps
CPU time 3.09 seconds
Started Aug 11 06:50:09 PM PDT 24
Finished Aug 11 06:50:12 PM PDT 24
Peak memory 242200 kb
Host smart-aa0118bc-372a-4cae-9b1b-b53c4970c9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483155342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.3483155342
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.3252095106
Short name T1024
Test name
Test status
Simulation time 1169161926 ps
CPU time 9.34 seconds
Started Aug 11 06:50:06 PM PDT 24
Finished Aug 11 06:50:15 PM PDT 24
Peak memory 242448 kb
Host smart-1d0ef113-2472-4946-9600-265d94be6409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252095106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.3252095106
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.3449114595
Short name T1107
Test name
Test status
Simulation time 95315214635 ps
CPU time 2487.6 seconds
Started Aug 11 06:50:07 PM PDT 24
Finished Aug 11 07:31:35 PM PDT 24
Peak memory 330444 kb
Host smart-268bea45-7aaf-4a2a-a44f-1502951fb472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449114595 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.3449114595
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.1263112532
Short name T827
Test name
Test status
Simulation time 160515377 ps
CPU time 4.2 seconds
Started Aug 11 06:50:05 PM PDT 24
Finished Aug 11 06:50:09 PM PDT 24
Peak memory 241932 kb
Host smart-07e3f417-9dfc-4efa-ac75-18788f88e24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263112532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.1263112532
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.3884059101
Short name T882
Test name
Test status
Simulation time 142510337 ps
CPU time 3.84 seconds
Started Aug 11 06:50:10 PM PDT 24
Finished Aug 11 06:50:14 PM PDT 24
Peak memory 242388 kb
Host smart-5aa461b7-27fc-4ec5-be53-27d6258849d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884059101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.3884059101
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2896144926
Short name T286
Test name
Test status
Simulation time 1214082907472 ps
CPU time 1603.33 seconds
Started Aug 11 06:50:12 PM PDT 24
Finished Aug 11 07:16:56 PM PDT 24
Peak memory 352724 kb
Host smart-b47e2e65-6fc0-42db-ab41-48e968ea69ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896144926 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.2896144926
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.4080125287
Short name T99
Test name
Test status
Simulation time 160233085 ps
CPU time 3.62 seconds
Started Aug 11 06:50:09 PM PDT 24
Finished Aug 11 06:50:13 PM PDT 24
Peak memory 242228 kb
Host smart-27bfe7b7-db62-47c4-b9c8-a2f1f071d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080125287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.4080125287
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.1269123376
Short name T499
Test name
Test status
Simulation time 5656477417 ps
CPU time 29.75 seconds
Started Aug 11 06:50:10 PM PDT 24
Finished Aug 11 06:50:40 PM PDT 24
Peak memory 242044 kb
Host smart-b1da0df8-d27b-4372-be83-acd281422a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269123376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.1269123376
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.2150582775
Short name T1156
Test name
Test status
Simulation time 208669782 ps
CPU time 3.48 seconds
Started Aug 11 06:50:10 PM PDT 24
Finished Aug 11 06:50:14 PM PDT 24
Peak memory 242200 kb
Host smart-e17d644f-28c2-491e-be7d-0e361423ebe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150582775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2150582775
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.1794739953
Short name T570
Test name
Test status
Simulation time 453447380 ps
CPU time 12.73 seconds
Started Aug 11 06:50:13 PM PDT 24
Finished Aug 11 06:50:26 PM PDT 24
Peak memory 241964 kb
Host smart-3a118494-a739-4e13-b631-0bc7191b5d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794739953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.1794739953
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.3115386112
Short name T518
Test name
Test status
Simulation time 63397606003 ps
CPU time 1856.42 seconds
Started Aug 11 06:50:11 PM PDT 24
Finished Aug 11 07:21:08 PM PDT 24
Peak memory 631548 kb
Host smart-14e57afb-86bb-4b13-b8b3-a812a62e3f11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115386112 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.3115386112
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.1648646536
Short name T23
Test name
Test status
Simulation time 455181736 ps
CPU time 3.87 seconds
Started Aug 11 06:50:09 PM PDT 24
Finished Aug 11 06:50:13 PM PDT 24
Peak memory 241996 kb
Host smart-1d482447-b5fc-4d3b-b5d6-53e50b7e0057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648646536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.1648646536
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.1623696739
Short name T174
Test name
Test status
Simulation time 7165757210 ps
CPU time 13.76 seconds
Started Aug 11 06:50:13 PM PDT 24
Finished Aug 11 06:50:27 PM PDT 24
Peak memory 242220 kb
Host smart-093dd042-278a-4a64-96c1-ec4529effde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623696739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.1623696739
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3901745993
Short name T243
Test name
Test status
Simulation time 148873233709 ps
CPU time 2030.48 seconds
Started Aug 11 06:50:13 PM PDT 24
Finished Aug 11 07:24:04 PM PDT 24
Peak memory 304132 kb
Host smart-c7ca16c2-3185-40ca-a8d8-7ca92bf049bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901745993 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.3901745993
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.2850049226
Short name T1103
Test name
Test status
Simulation time 2046007838 ps
CPU time 5.2 seconds
Started Aug 11 06:50:19 PM PDT 24
Finished Aug 11 06:50:25 PM PDT 24
Peak memory 242236 kb
Host smart-feab7bfc-8dee-4a01-91eb-7a7f09e0a6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850049226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.2850049226
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.2893008091
Short name T459
Test name
Test status
Simulation time 207784456 ps
CPU time 5.31 seconds
Started Aug 11 06:50:12 PM PDT 24
Finished Aug 11 06:50:17 PM PDT 24
Peak memory 242220 kb
Host smart-5fdb1ac9-6b99-45ea-90f1-3bf55d4563ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893008091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.2893008091
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.767381552
Short name T1038
Test name
Test status
Simulation time 298425476 ps
CPU time 4.31 seconds
Started Aug 11 06:50:12 PM PDT 24
Finished Aug 11 06:50:17 PM PDT 24
Peak memory 242172 kb
Host smart-4aa8fddd-a137-4953-af93-b0d30369d974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767381552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.767381552
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.368220025
Short name T920
Test name
Test status
Simulation time 199997022 ps
CPU time 5.01 seconds
Started Aug 11 06:50:10 PM PDT 24
Finished Aug 11 06:50:15 PM PDT 24
Peak memory 241852 kb
Host smart-3c23ca45-caf9-4d15-9922-9070cfc033fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368220025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.368220025
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.633930932
Short name T181
Test name
Test status
Simulation time 68546762914 ps
CPU time 1241.49 seconds
Started Aug 11 06:50:10 PM PDT 24
Finished Aug 11 07:10:51 PM PDT 24
Peak memory 314312 kb
Host smart-2192ae41-c0cb-447b-9e25-73070f96a1cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633930932 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.633930932
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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