Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	12	0	0.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
flash_addr_req_during_flash_data_req	2	2	0	0.00	100	1	1	2
flash_addr_req_during_lc_esc	2	2	0	0.00	100	1	1	0
flash_addr_req_during_otbn_req	2	2	0	0.00	100	1	1	2
flash_addr_req_during_otp_idle	2	2	0	0.00	100	1	1	2
flash_addr_req_during_sram_0_req	2	2	0	0.00	100	1	1	2
flash_addr_req_during_sram_1_req	2	2	0	0.00	100	1	1	2

Summary for Variable flash_addr_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for flash_addr_req_during_flash_data_req

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable flash_addr_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	2	0	0.00

User Defined Bins for flash_addr_req_during_lc_esc

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
lc_esc_off	0	1	1
lc_esc_on	0	1	1

---

Summary for Variable flash_addr_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for flash_addr_req_during_otbn_req

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable flash_addr_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for flash_addr_req_during_otp_idle

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable flash_addr_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for flash_addr_req_during_sram_0_req

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable flash_addr_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for flash_addr_req_during_sram_1_req

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2