Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	1	3	75.00
Crosses	4	2	2	50.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
keymgr_rd_en	2	0	2	100.00	100	1	1	2
secret2_lock	2	1	1	50.00	100	1	1	2

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
keymgr_output_conditions	4	2	2	50.00	100	1	1	0

Summary for Variable keymgr_rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for keymgr_rd_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44

1

T1

1

T7

1

T11

1

auto[1]

26

1

T3

1

T8

1

T14

1

---

Summary for Variable secret2_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for secret2_lock

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70

1

T1

1

T3

1

T7

1

---

Summary for Cross keymgr_output_conditions

Samples crossed: keymgr_rd_en secret2_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for keymgr_output_conditions

Element holes

keymgr_rd_en	secret2_lock	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

keymgr_rd_en

secret2_lock

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

44

1

T1

1

T7

1

T11

1

auto[1]

auto[0]

26

1

T3

1

T8

1

T14

1