Summary for Variable flash_index
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
2 | 
0 | 
2 | 
100.00 | 
User Defined Bins for flash_index
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| il | 
0 | 
Illegal | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| flash_addr_key | 
5100 | 
1 | 
 | 
 | 
T3 | 
1 | 
 | 
T5 | 
16 | 
 | 
T6 | 
12 | 
| flash_data_key | 
5106 | 
1 | 
 | 
 | 
T3 | 
1 | 
 | 
T5 | 
12 | 
 | 
T6 | 
13 | 
Summary for Variable secret1_lock
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for secret1_lock
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4841 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
28 | 
 | 
T6 | 
25 | 
| auto[1] | 
5365 | 
1 | 
 | 
 | 
T11 | 
16 | 
 | 
T26 | 
8 | 
 | 
T27 | 
8 | 
Summary for Cross flash_req_lock_cross
Samples crossed: flash_index secret1_lock
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for flash_req_lock_cross
Bins
| flash_index | secret1_lock | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| flash_addr_key | 
auto[0] | 
2432 | 
1 | 
 | 
 | 
T3 | 
1 | 
 | 
T5 | 
16 | 
 | 
T6 | 
12 | 
| flash_addr_key | 
auto[1] | 
2668 | 
1 | 
 | 
 | 
T11 | 
8 | 
 | 
T26 | 
4 | 
 | 
T27 | 
4 | 
| flash_data_key | 
auto[0] | 
2409 | 
1 | 
 | 
 | 
T3 | 
1 | 
 | 
T5 | 
12 | 
 | 
T6 | 
13 | 
| flash_data_key | 
auto[1] | 
2697 | 
1 | 
 | 
 | 
T11 | 
8 | 
 | 
T26 | 
4 | 
 | 
T27 | 
4 |