Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	44296	1			T2	756		T4	128		T7	73
access_err	50751	1			T2	359		T3	13		T5	140
write_blank_err	348	1			T2	2		T5	1		T14	4
ecc_uncorr_err	51857	1			T2	155		T4	405		T5	500
ecc_corr_err	1448	1			T2	3		T4	12		T103	5
no_err	73053	1			T2	547		T3	17		T4	30

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	607	1			T2	2		T5	8		T14	2
secret2	21825	1			T2	283		T3	5		T4	4
secret1	23602	1			T2	80		T3	6		T4	146
secret0	27130	1			T2	410		T4	8		T7	73
hw_cfg1	26071	1			T2	71		T3	7		T4	72
hw_cfg0	23752	1			T2	65		T3	3		T4	70
rot_creator_auth_state	16791	1			T2	93		T3	5		T4	66
rot_creator_auth_codesign	18791	1			T2	97		T5	64		T9	5
owner_sw_cfg	17216	1			T2	94		T4	1		T5	40
creator_sw_cfg	16753	1			T2	88		T3	2		T4	128
vendor_test	29215	1			T2	539		T3	2		T4	80

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2802	1			T258	192		T134	11		T326	119
fsm_err	secret1	2281	1			T9	432		T213	34		T327	347
fsm_err	secret0	5212	1			T2	320		T7	73		T95	172
fsm_err	hw_cfg1	2248	1			T251	86		T328	279		T249	516
fsm_err	hw_cfg0	4306	1			T10	8		T203	393		T329	141
fsm_err	rot_creator_auth_state	2977	1			T99	123		T330	574		T28	110
fsm_err	rot_creator_auth_codesign	4193	1			T331	108		T241	125		T263	31
fsm_err	owner_sw_cfg	2890	1			T252	497		T315	550		T332	226
fsm_err	creator_sw_cfg	2277	1			T4	59		T6	205		T18	438
fsm_err	vendor_test	15110	1			T2	436		T4	69		T173	372
access_err	life_cycle	607	1			T2	2		T5	8		T14	2
access_err	secret2	8695	1			T2	67		T5	27		T9	5
access_err	secret1	5742	1			T2	40		T3	6		T5	31
access_err	secret0	4604	1			T2	57		T5	1		T38	3
access_err	hw_cfg1	1175	1			T2	7		T3	2		T5	5
access_err	hw_cfg0	2031	1			T2	1		T3	3		T5	8
access_err	rot_creator_auth_state	4519	1			T2	46		T3	1		T5	8
access_err	rot_creator_auth_codesign	6286	1			T2	52		T5	25		T9	3
access_err	owner_sw_cfg	5178	1			T2	20		T5	7		T9	4
access_err	creator_sw_cfg	6134	1			T2	30		T3	1		T5	9
access_err	vendor_test	5780	1			T2	37		T5	11		T9	1
write_blank_err	secret2	13	1			T2	2		T323	1		T333	1
write_blank_err	secret1	23	1			T14	1		T226	1		T71	2
write_blank_err	secret0	34	1			T183	1		T71	1		T103	2
write_blank_err	hw_cfg1	45	1			T71	1		T103	2		T122	2
write_blank_err	hw_cfg0	26	1			T5	1		T13	1		T227	1
write_blank_err	rot_creator_auth_state	119	1			T14	3		T183	1		T226	2
write_blank_err	rot_creator_auth_codesign	48	1			T183	2		T71	1		T103	2
write_blank_err	owner_sw_cfg	13	1			T183	1		T227	2		T103	1
write_blank_err	creator_sw_cfg	10	1			T71	1		T122	2		T244	2
write_blank_err	vendor_test	17	1			T71	1		T103	1		T234	1
ecc_uncorr_err	secret2	5644	1			T2	155		T323	618		T333	640
ecc_uncorr_err	secret1	8871	1			T4	142		T14	561		T226	673
ecc_uncorr_err	secret0	10788	1			T183	418		T71	534		T103	549
ecc_uncorr_err	hw_cfg1	13780	1			T4	69		T71	316		T122	627
ecc_uncorr_err	hw_cfg0	7266	1			T4	67		T5	500		T13	92
ecc_uncorr_err	rot_creator_auth_state	2041	1			T4	66		T103	292		T204	289
ecc_uncorr_err	rot_creator_auth_codesign	763	1			T134	18		T200	2		T334	23
ecc_uncorr_err	owner_sw_cfg	1144	1			T334	26		T181	3		T335	60
ecc_uncorr_err	creator_sw_cfg	1560	1			T4	61		T134	4		T135	104
ecc_corr_err	secret2	75	1			T2	3		T4	1		T45	2
ecc_corr_err	secret1	75	1			T4	1		T64	1		T45	1
ecc_corr_err	secret0	134	1			T103	1		T64	3		T45	1
ecc_corr_err	hw_cfg1	293	1			T4	2		T103	4		T64	3
ecc_corr_err	hw_cfg0	257	1			T4	1		T64	2		T45	14
ecc_corr_err	rot_creator_auth_state	124	1			T64	3		T45	5		T122	2
ecc_corr_err	rot_creator_auth_codesign	176	1			T64	5		T45	3		T72	4
ecc_corr_err	owner_sw_cfg	177	1			T4	1		T45	7		T133	3
ecc_corr_err	creator_sw_cfg	137	1			T4	6		T64	1		T72	2
no_err	secret2	4596	1			T2	56		T3	5		T4	3
no_err	secret1	6610	1			T2	40		T4	3		T5	16
no_err	secret0	6358	1			T2	33		T4	8		T5	20
no_err	hw_cfg1	8530	1			T2	64		T3	5		T4	1
no_err	hw_cfg0	9866	1			T2	64		T4	2		T5	24
no_err	rot_creator_auth_state	7011	1			T2	47		T3	4		T5	18
no_err	rot_creator_auth_codesign	7325	1			T2	45		T5	39		T9	2
no_err	owner_sw_cfg	7814	1			T2	74		T5	33		T9	1
no_err	creator_sw_cfg	6635	1			T2	58		T3	1		T4	2
no_err	vendor_test	8308	1			T2	66		T3	2		T4	11

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded